1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2021 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include "dpaa2_sparser.h" 30 #include <fsl_qbman_debug.h> 31 32 #define DRIVER_LOOPBACK_MODE "drv_loopback" 33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 34 #define DRIVER_TX_CONF "drv_tx_conf" 35 #define DRIVER_ERROR_QUEUE "drv_err_queue" 36 #define CHECK_INTERVAL 100 /* 100ms */ 37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 38 39 /* Supported Rx offloads */ 40 static uint64_t dev_rx_offloads_sup = 41 DEV_RX_OFFLOAD_CHECKSUM | 42 DEV_RX_OFFLOAD_SCTP_CKSUM | 43 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 44 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 45 DEV_RX_OFFLOAD_VLAN_STRIP | 46 DEV_RX_OFFLOAD_VLAN_FILTER | 47 DEV_RX_OFFLOAD_JUMBO_FRAME | 48 DEV_RX_OFFLOAD_TIMESTAMP; 49 50 /* Rx offloads which cannot be disabled */ 51 static uint64_t dev_rx_offloads_nodis = 52 DEV_RX_OFFLOAD_RSS_HASH | 53 DEV_RX_OFFLOAD_SCATTER; 54 55 /* Supported Tx offloads */ 56 static uint64_t dev_tx_offloads_sup = 57 DEV_TX_OFFLOAD_VLAN_INSERT | 58 DEV_TX_OFFLOAD_IPV4_CKSUM | 59 DEV_TX_OFFLOAD_UDP_CKSUM | 60 DEV_TX_OFFLOAD_TCP_CKSUM | 61 DEV_TX_OFFLOAD_SCTP_CKSUM | 62 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 63 DEV_TX_OFFLOAD_MT_LOCKFREE | 64 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 DEV_TX_OFFLOAD_MULTI_SEGS; 69 70 /* enable timestamp in mbuf */ 71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 72 uint64_t dpaa2_timestamp_rx_dynflag; 73 int dpaa2_timestamp_dynfield_offset = -1; 74 75 /* Enable error queue */ 76 bool dpaa2_enable_err_queue; 77 78 struct rte_dpaa2_xstats_name_off { 79 char name[RTE_ETH_XSTATS_NAME_SIZE]; 80 uint8_t page_id; /* dpni statistics page id */ 81 uint8_t stats_id; /* stats id in the given page */ 82 }; 83 84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 85 {"ingress_multicast_frames", 0, 2}, 86 {"ingress_multicast_bytes", 0, 3}, 87 {"ingress_broadcast_frames", 0, 4}, 88 {"ingress_broadcast_bytes", 0, 5}, 89 {"egress_multicast_frames", 1, 2}, 90 {"egress_multicast_bytes", 1, 3}, 91 {"egress_broadcast_frames", 1, 4}, 92 {"egress_broadcast_bytes", 1, 5}, 93 {"ingress_filtered_frames", 2, 0}, 94 {"ingress_discarded_frames", 2, 1}, 95 {"ingress_nobuffer_discards", 2, 2}, 96 {"egress_discarded_frames", 2, 3}, 97 {"egress_confirmed_frames", 2, 4}, 98 {"cgr_reject_frames", 4, 0}, 99 {"cgr_reject_bytes", 4, 1}, 100 }; 101 102 static const enum rte_filter_op dpaa2_supported_filter_ops[] = { 103 RTE_ETH_FILTER_GET 104 }; 105 106 static struct rte_dpaa2_driver rte_dpaa2_pmd; 107 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 108 int wait_to_complete); 109 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 110 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 111 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 112 113 static int 114 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 115 { 116 int ret; 117 struct dpaa2_dev_priv *priv = dev->data->dev_private; 118 struct fsl_mc_io *dpni = dev->process_private; 119 120 PMD_INIT_FUNC_TRACE(); 121 122 if (dpni == NULL) { 123 DPAA2_PMD_ERR("dpni is NULL"); 124 return -1; 125 } 126 127 if (on) 128 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 129 vlan_id, 0, 0, 0); 130 else 131 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 132 priv->token, vlan_id); 133 134 if (ret < 0) 135 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 136 ret, vlan_id, priv->hw_id); 137 138 return ret; 139 } 140 141 static int 142 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 143 { 144 struct dpaa2_dev_priv *priv = dev->data->dev_private; 145 struct fsl_mc_io *dpni = dev->process_private; 146 int ret = 0; 147 148 PMD_INIT_FUNC_TRACE(); 149 150 if (mask & ETH_VLAN_FILTER_MASK) { 151 /* VLAN Filter not avaialble */ 152 if (!priv->max_vlan_filters) { 153 DPAA2_PMD_INFO("VLAN filter not available"); 154 return -ENOTSUP; 155 } 156 157 if (dev->data->dev_conf.rxmode.offloads & 158 DEV_RX_OFFLOAD_VLAN_FILTER) 159 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 160 priv->token, true); 161 else 162 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 163 priv->token, false); 164 if (ret < 0) 165 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 166 } 167 168 return ret; 169 } 170 171 static int 172 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 173 enum rte_vlan_type vlan_type __rte_unused, 174 uint16_t tpid) 175 { 176 struct dpaa2_dev_priv *priv = dev->data->dev_private; 177 struct fsl_mc_io *dpni = dev->process_private; 178 int ret = -ENOTSUP; 179 180 PMD_INIT_FUNC_TRACE(); 181 182 /* nothing to be done for standard vlan tpids */ 183 if (tpid == 0x8100 || tpid == 0x88A8) 184 return 0; 185 186 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 187 priv->token, tpid); 188 if (ret < 0) 189 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 190 /* if already configured tpids, remove them first */ 191 if (ret == -EBUSY) { 192 struct dpni_custom_tpid_cfg tpid_list = {0}; 193 194 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 195 priv->token, &tpid_list); 196 if (ret < 0) 197 goto fail; 198 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 199 priv->token, tpid_list.tpid1); 200 if (ret < 0) 201 goto fail; 202 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 203 priv->token, tpid); 204 } 205 fail: 206 return ret; 207 } 208 209 static int 210 dpaa2_fw_version_get(struct rte_eth_dev *dev, 211 char *fw_version, 212 size_t fw_size) 213 { 214 int ret; 215 struct fsl_mc_io *dpni = dev->process_private; 216 struct mc_soc_version mc_plat_info = {0}; 217 struct mc_version mc_ver_info = {0}; 218 219 PMD_INIT_FUNC_TRACE(); 220 221 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 222 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 223 224 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 225 DPAA2_PMD_WARN("\tmc_get_version failed"); 226 227 ret = snprintf(fw_version, fw_size, 228 "%x-%d.%d.%d", 229 mc_plat_info.svr, 230 mc_ver_info.major, 231 mc_ver_info.minor, 232 mc_ver_info.revision); 233 234 ret += 1; /* add the size of '\0' */ 235 if (fw_size < (uint32_t)ret) 236 return ret; 237 else 238 return 0; 239 } 240 241 static int 242 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 243 { 244 struct dpaa2_dev_priv *priv = dev->data->dev_private; 245 246 PMD_INIT_FUNC_TRACE(); 247 248 dev_info->max_mac_addrs = priv->max_mac_filters; 249 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 250 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 251 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 252 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 253 dev_info->rx_offload_capa = dev_rx_offloads_sup | 254 dev_rx_offloads_nodis; 255 dev_info->tx_offload_capa = dev_tx_offloads_sup | 256 dev_tx_offloads_nodis; 257 dev_info->speed_capa = ETH_LINK_SPEED_1G | 258 ETH_LINK_SPEED_2_5G | 259 ETH_LINK_SPEED_10G; 260 261 dev_info->max_hash_mac_addrs = 0; 262 dev_info->max_vfs = 0; 263 dev_info->max_vmdq_pools = ETH_16_POOLS; 264 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 265 266 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 267 /* same is rx size for best perf */ 268 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 269 270 dev_info->default_rxportconf.nb_queues = 1; 271 dev_info->default_txportconf.nb_queues = 1; 272 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 273 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 274 275 if (dpaa2_svr_family == SVR_LX2160A) { 276 dev_info->speed_capa |= ETH_LINK_SPEED_25G | 277 ETH_LINK_SPEED_40G | 278 ETH_LINK_SPEED_50G | 279 ETH_LINK_SPEED_100G; 280 } 281 282 return 0; 283 } 284 285 static int 286 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 287 __rte_unused uint16_t queue_id, 288 struct rte_eth_burst_mode *mode) 289 { 290 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 291 int ret = -EINVAL; 292 unsigned int i; 293 const struct burst_info { 294 uint64_t flags; 295 const char *output; 296 } rx_offload_map[] = { 297 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 298 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 299 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 300 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 301 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 302 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 303 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 304 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 305 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}, 306 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"} 307 }; 308 309 /* Update Rx offload info */ 310 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 311 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 312 snprintf(mode->info, sizeof(mode->info), "%s", 313 rx_offload_map[i].output); 314 ret = 0; 315 break; 316 } 317 } 318 return ret; 319 } 320 321 static int 322 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 323 __rte_unused uint16_t queue_id, 324 struct rte_eth_burst_mode *mode) 325 { 326 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 327 int ret = -EINVAL; 328 unsigned int i; 329 const struct burst_info { 330 uint64_t flags; 331 const char *output; 332 } tx_offload_map[] = { 333 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 334 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 335 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 336 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 337 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 338 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 339 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 340 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 341 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 342 }; 343 344 /* Update Tx offload info */ 345 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 346 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 347 snprintf(mode->info, sizeof(mode->info), "%s", 348 tx_offload_map[i].output); 349 ret = 0; 350 break; 351 } 352 } 353 return ret; 354 } 355 356 static int 357 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 358 { 359 struct dpaa2_dev_priv *priv = dev->data->dev_private; 360 uint16_t dist_idx; 361 uint32_t vq_id; 362 uint8_t num_rxqueue_per_tc; 363 struct dpaa2_queue *mc_q, *mcq; 364 uint32_t tot_queues; 365 int i; 366 struct dpaa2_queue *dpaa2_q; 367 368 PMD_INIT_FUNC_TRACE(); 369 370 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 371 if (priv->flags & DPAA2_TX_CONF_ENABLE) 372 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 373 else 374 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 375 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 376 RTE_CACHE_LINE_SIZE); 377 if (!mc_q) { 378 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 379 return -1; 380 } 381 382 for (i = 0; i < priv->nb_rx_queues; i++) { 383 mc_q->eth_data = dev->data; 384 priv->rx_vq[i] = mc_q++; 385 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 386 dpaa2_q->q_storage = rte_malloc("dq_storage", 387 sizeof(struct queue_storage_info_t), 388 RTE_CACHE_LINE_SIZE); 389 if (!dpaa2_q->q_storage) 390 goto fail; 391 392 memset(dpaa2_q->q_storage, 0, 393 sizeof(struct queue_storage_info_t)); 394 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 395 goto fail; 396 } 397 398 if (dpaa2_enable_err_queue) { 399 priv->rx_err_vq = rte_zmalloc("dpni_rx_err", 400 sizeof(struct dpaa2_queue), 0); 401 402 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 403 dpaa2_q->q_storage = rte_malloc("err_dq_storage", 404 sizeof(struct queue_storage_info_t) * 405 RTE_MAX_LCORE, 406 RTE_CACHE_LINE_SIZE); 407 if (!dpaa2_q->q_storage) 408 goto fail; 409 410 memset(dpaa2_q->q_storage, 0, 411 sizeof(struct queue_storage_info_t)); 412 for (i = 0; i < RTE_MAX_LCORE; i++) 413 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i])) 414 goto fail; 415 } 416 417 for (i = 0; i < priv->nb_tx_queues; i++) { 418 mc_q->eth_data = dev->data; 419 mc_q->flow_id = 0xffff; 420 priv->tx_vq[i] = mc_q++; 421 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 422 dpaa2_q->cscn = rte_malloc(NULL, 423 sizeof(struct qbman_result), 16); 424 if (!dpaa2_q->cscn) 425 goto fail_tx; 426 } 427 428 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 429 /*Setup tx confirmation queues*/ 430 for (i = 0; i < priv->nb_tx_queues; i++) { 431 mc_q->eth_data = dev->data; 432 mc_q->tc_index = i; 433 mc_q->flow_id = 0; 434 priv->tx_conf_vq[i] = mc_q++; 435 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 436 dpaa2_q->q_storage = 437 rte_malloc("dq_storage", 438 sizeof(struct queue_storage_info_t), 439 RTE_CACHE_LINE_SIZE); 440 if (!dpaa2_q->q_storage) 441 goto fail_tx_conf; 442 443 memset(dpaa2_q->q_storage, 0, 444 sizeof(struct queue_storage_info_t)); 445 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 446 goto fail_tx_conf; 447 } 448 } 449 450 vq_id = 0; 451 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 452 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 453 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 454 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 455 vq_id++; 456 } 457 458 return 0; 459 fail_tx_conf: 460 i -= 1; 461 while (i >= 0) { 462 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 463 rte_free(dpaa2_q->q_storage); 464 priv->tx_conf_vq[i--] = NULL; 465 } 466 i = priv->nb_tx_queues; 467 fail_tx: 468 i -= 1; 469 while (i >= 0) { 470 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 471 rte_free(dpaa2_q->cscn); 472 priv->tx_vq[i--] = NULL; 473 } 474 i = priv->nb_rx_queues; 475 fail: 476 i -= 1; 477 mc_q = priv->rx_vq[0]; 478 while (i >= 0) { 479 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 480 dpaa2_free_dq_storage(dpaa2_q->q_storage); 481 rte_free(dpaa2_q->q_storage); 482 priv->rx_vq[i--] = NULL; 483 } 484 485 if (dpaa2_enable_err_queue) { 486 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 487 if (dpaa2_q->q_storage) 488 dpaa2_free_dq_storage(dpaa2_q->q_storage); 489 rte_free(dpaa2_q->q_storage); 490 } 491 492 rte_free(mc_q); 493 return -1; 494 } 495 496 static void 497 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 498 { 499 struct dpaa2_dev_priv *priv = dev->data->dev_private; 500 struct dpaa2_queue *dpaa2_q; 501 int i; 502 503 PMD_INIT_FUNC_TRACE(); 504 505 /* Queue allocation base */ 506 if (priv->rx_vq[0]) { 507 /* cleaning up queue storage */ 508 for (i = 0; i < priv->nb_rx_queues; i++) { 509 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 510 if (dpaa2_q->q_storage) 511 rte_free(dpaa2_q->q_storage); 512 } 513 /* cleanup tx queue cscn */ 514 for (i = 0; i < priv->nb_tx_queues; i++) { 515 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 516 rte_free(dpaa2_q->cscn); 517 } 518 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 519 /* cleanup tx conf queue storage */ 520 for (i = 0; i < priv->nb_tx_queues; i++) { 521 dpaa2_q = (struct dpaa2_queue *) 522 priv->tx_conf_vq[i]; 523 rte_free(dpaa2_q->q_storage); 524 } 525 } 526 /*free memory for all queues (RX+TX) */ 527 rte_free(priv->rx_vq[0]); 528 priv->rx_vq[0] = NULL; 529 } 530 } 531 532 static int 533 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 534 { 535 struct dpaa2_dev_priv *priv = dev->data->dev_private; 536 struct fsl_mc_io *dpni = dev->process_private; 537 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 538 uint64_t rx_offloads = eth_conf->rxmode.offloads; 539 uint64_t tx_offloads = eth_conf->txmode.offloads; 540 int rx_l3_csum_offload = false; 541 int rx_l4_csum_offload = false; 542 int tx_l3_csum_offload = false; 543 int tx_l4_csum_offload = false; 544 int ret, tc_index; 545 546 PMD_INIT_FUNC_TRACE(); 547 548 /* Rx offloads which are enabled by default */ 549 if (dev_rx_offloads_nodis & ~rx_offloads) { 550 DPAA2_PMD_INFO( 551 "Some of rx offloads enabled by default - requested 0x%" PRIx64 552 " fixed are 0x%" PRIx64, 553 rx_offloads, dev_rx_offloads_nodis); 554 } 555 556 /* Tx offloads which are enabled by default */ 557 if (dev_tx_offloads_nodis & ~tx_offloads) { 558 DPAA2_PMD_INFO( 559 "Some of tx offloads enabled by default - requested 0x%" PRIx64 560 " fixed are 0x%" PRIx64, 561 tx_offloads, dev_tx_offloads_nodis); 562 } 563 564 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 565 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 566 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 567 priv->token, eth_conf->rxmode.max_rx_pkt_len 568 - RTE_ETHER_CRC_LEN); 569 if (ret) { 570 DPAA2_PMD_ERR( 571 "Unable to set mtu. check config"); 572 return ret; 573 } 574 dev->data->mtu = 575 dev->data->dev_conf.rxmode.max_rx_pkt_len - 576 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - 577 VLAN_TAG_SIZE; 578 } else { 579 return -1; 580 } 581 } 582 583 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 584 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 585 ret = dpaa2_setup_flow_dist(dev, 586 eth_conf->rx_adv_conf.rss_conf.rss_hf, 587 tc_index); 588 if (ret) { 589 DPAA2_PMD_ERR( 590 "Unable to set flow distribution on tc%d." 591 "Check queue config", tc_index); 592 return ret; 593 } 594 } 595 } 596 597 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 598 rx_l3_csum_offload = true; 599 600 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 601 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || 602 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) 603 rx_l4_csum_offload = true; 604 605 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 606 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 607 if (ret) { 608 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 609 return ret; 610 } 611 612 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 613 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 614 if (ret) { 615 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 616 return ret; 617 } 618 619 #if !defined(RTE_LIBRTE_IEEE1588) 620 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) 621 #endif 622 { 623 ret = rte_mbuf_dyn_rx_timestamp_register( 624 &dpaa2_timestamp_dynfield_offset, 625 &dpaa2_timestamp_rx_dynflag); 626 if (ret != 0) { 627 DPAA2_PMD_ERR("Error to register timestamp field/flag"); 628 return -rte_errno; 629 } 630 dpaa2_enable_ts[dev->data->port_id] = true; 631 } 632 633 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 634 tx_l3_csum_offload = true; 635 636 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 637 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 638 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 639 tx_l4_csum_offload = true; 640 641 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 642 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 643 if (ret) { 644 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 645 return ret; 646 } 647 648 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 649 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 650 if (ret) { 651 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 652 return ret; 653 } 654 655 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 656 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 657 * to 0 for LS2 in the hardware thus disabling data/annotation 658 * stashing. For LX2 this is fixed in hardware and thus hash result and 659 * parse results can be received in FD using this option. 660 */ 661 if (dpaa2_svr_family == SVR_LX2160A) { 662 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 663 DPNI_FLCTYPE_HASH, true); 664 if (ret) { 665 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 666 return ret; 667 } 668 } 669 670 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 671 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 672 673 dpaa2_tm_init(dev); 674 675 return 0; 676 } 677 678 /* Function to setup RX flow information. It contains traffic class ID, 679 * flow ID, destination configuration etc. 680 */ 681 static int 682 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 683 uint16_t rx_queue_id, 684 uint16_t nb_rx_desc, 685 unsigned int socket_id __rte_unused, 686 const struct rte_eth_rxconf *rx_conf, 687 struct rte_mempool *mb_pool) 688 { 689 struct dpaa2_dev_priv *priv = dev->data->dev_private; 690 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 691 struct dpaa2_queue *dpaa2_q; 692 struct dpni_queue cfg; 693 uint8_t options = 0; 694 uint8_t flow_id; 695 uint32_t bpid; 696 int i, ret; 697 698 PMD_INIT_FUNC_TRACE(); 699 700 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 701 dev, rx_queue_id, mb_pool, rx_conf); 702 703 /* Rx deferred start is not supported */ 704 if (rx_conf->rx_deferred_start) { 705 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 706 (void *)dev); 707 return -EINVAL; 708 } 709 710 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 711 bpid = mempool_to_bpid(mb_pool); 712 ret = dpaa2_attach_bp_list(priv, 713 rte_dpaa2_bpid_info[bpid].bp_list); 714 if (ret) 715 return ret; 716 } 717 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 718 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 719 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 720 dpaa2_q->nb_desc = UINT16_MAX; 721 dpaa2_q->offloads = rx_conf->offloads; 722 723 /*Get the flow id from given VQ id*/ 724 flow_id = dpaa2_q->flow_id; 725 memset(&cfg, 0, sizeof(struct dpni_queue)); 726 727 options = options | DPNI_QUEUE_OPT_USER_CTX; 728 cfg.user_context = (size_t)(dpaa2_q); 729 730 /* check if a private cgr available. */ 731 for (i = 0; i < priv->max_cgs; i++) { 732 if (!priv->cgid_in_use[i]) { 733 priv->cgid_in_use[i] = 1; 734 break; 735 } 736 } 737 738 if (i < priv->max_cgs) { 739 options |= DPNI_QUEUE_OPT_SET_CGID; 740 cfg.cgid = i; 741 dpaa2_q->cgid = cfg.cgid; 742 } else { 743 dpaa2_q->cgid = 0xff; 744 } 745 746 /*if ls2088 or rev2 device, enable the stashing */ 747 748 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 749 options |= DPNI_QUEUE_OPT_FLC; 750 cfg.flc.stash_control = true; 751 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 752 /* 00 00 00 - last 6 bit represent annotation, context stashing, 753 * data stashing setting 01 01 00 (0x14) 754 * (in following order ->DS AS CS) 755 * to enable 1 line data, 1 line annotation. 756 * For LX2, this setting should be 01 00 00 (0x10) 757 */ 758 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 759 cfg.flc.value |= 0x10; 760 else 761 cfg.flc.value |= 0x14; 762 } 763 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 764 dpaa2_q->tc_index, flow_id, options, &cfg); 765 if (ret) { 766 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 767 return -1; 768 } 769 770 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 771 struct dpni_taildrop taildrop; 772 773 taildrop.enable = 1; 774 dpaa2_q->nb_desc = nb_rx_desc; 775 /* Private CGR will use tail drop length as nb_rx_desc. 776 * for rest cases we can use standard byte based tail drop. 777 * There is no HW restriction, but number of CGRs are limited, 778 * hence this restriction is placed. 779 */ 780 if (dpaa2_q->cgid != 0xff) { 781 /*enabling per rx queue congestion control */ 782 taildrop.threshold = nb_rx_desc; 783 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 784 taildrop.oal = 0; 785 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 786 rx_queue_id); 787 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 788 DPNI_CP_CONGESTION_GROUP, 789 DPNI_QUEUE_RX, 790 dpaa2_q->tc_index, 791 dpaa2_q->cgid, &taildrop); 792 } else { 793 /*enabling per rx queue congestion control */ 794 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 795 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 796 taildrop.oal = CONG_RX_OAL; 797 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 798 rx_queue_id); 799 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 800 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 801 dpaa2_q->tc_index, flow_id, 802 &taildrop); 803 } 804 if (ret) { 805 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 806 ret); 807 return -1; 808 } 809 } else { /* Disable tail Drop */ 810 struct dpni_taildrop taildrop = {0}; 811 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 812 813 taildrop.enable = 0; 814 if (dpaa2_q->cgid != 0xff) { 815 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 816 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 817 dpaa2_q->tc_index, 818 dpaa2_q->cgid, &taildrop); 819 } else { 820 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 821 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 822 dpaa2_q->tc_index, flow_id, &taildrop); 823 } 824 if (ret) { 825 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 826 ret); 827 return -1; 828 } 829 } 830 831 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 832 return 0; 833 } 834 835 static int 836 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 837 uint16_t tx_queue_id, 838 uint16_t nb_tx_desc, 839 unsigned int socket_id __rte_unused, 840 const struct rte_eth_txconf *tx_conf) 841 { 842 struct dpaa2_dev_priv *priv = dev->data->dev_private; 843 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 844 priv->tx_vq[tx_queue_id]; 845 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 846 priv->tx_conf_vq[tx_queue_id]; 847 struct fsl_mc_io *dpni = dev->process_private; 848 struct dpni_queue tx_conf_cfg; 849 struct dpni_queue tx_flow_cfg; 850 uint8_t options = 0, flow_id; 851 struct dpni_queue_id qid; 852 uint32_t tc_id; 853 int ret; 854 855 PMD_INIT_FUNC_TRACE(); 856 857 /* Tx deferred start is not supported */ 858 if (tx_conf->tx_deferred_start) { 859 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 860 (void *)dev); 861 return -EINVAL; 862 } 863 864 dpaa2_q->nb_desc = UINT16_MAX; 865 dpaa2_q->offloads = tx_conf->offloads; 866 867 /* Return if queue already configured */ 868 if (dpaa2_q->flow_id != 0xffff) { 869 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 870 return 0; 871 } 872 873 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 874 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 875 876 tc_id = tx_queue_id; 877 flow_id = 0; 878 879 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 880 tc_id, flow_id, options, &tx_flow_cfg); 881 if (ret) { 882 DPAA2_PMD_ERR("Error in setting the tx flow: " 883 "tc_id=%d, flow=%d err=%d", 884 tc_id, flow_id, ret); 885 return -1; 886 } 887 888 dpaa2_q->flow_id = flow_id; 889 890 if (tx_queue_id == 0) { 891 /*Set tx-conf and error configuration*/ 892 if (priv->flags & DPAA2_TX_CONF_ENABLE) 893 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 894 priv->token, 895 DPNI_CONF_AFFINE); 896 else 897 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 898 priv->token, 899 DPNI_CONF_DISABLE); 900 if (ret) { 901 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 902 "err=%d", ret); 903 return -1; 904 } 905 } 906 dpaa2_q->tc_index = tc_id; 907 908 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 909 DPNI_QUEUE_TX, dpaa2_q->tc_index, 910 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 911 if (ret) { 912 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 913 return -1; 914 } 915 dpaa2_q->fqid = qid.fqid; 916 917 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 918 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 919 920 dpaa2_q->nb_desc = nb_tx_desc; 921 922 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 923 cong_notif_cfg.threshold_entry = nb_tx_desc; 924 /* Notify that the queue is not congested when the data in 925 * the queue is below this thershold.(90% of value) 926 */ 927 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; 928 cong_notif_cfg.message_ctx = 0; 929 cong_notif_cfg.message_iova = 930 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 931 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 932 cong_notif_cfg.notification_mode = 933 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 934 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 935 DPNI_CONG_OPT_COHERENT_WRITE; 936 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 937 938 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 939 priv->token, 940 DPNI_QUEUE_TX, 941 tc_id, 942 &cong_notif_cfg); 943 if (ret) { 944 DPAA2_PMD_ERR( 945 "Error in setting tx congestion notification: " 946 "err=%d", ret); 947 return -ret; 948 } 949 } 950 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 951 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 952 953 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 954 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 955 options = options | DPNI_QUEUE_OPT_USER_CTX; 956 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 957 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 958 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 959 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 960 if (ret) { 961 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 962 "tc_index=%d, flow=%d err=%d", 963 dpaa2_tx_conf_q->tc_index, 964 dpaa2_tx_conf_q->flow_id, ret); 965 return -1; 966 } 967 968 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 969 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 970 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 971 if (ret) { 972 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 973 return -1; 974 } 975 dpaa2_tx_conf_q->fqid = qid.fqid; 976 } 977 return 0; 978 } 979 980 static void 981 dpaa2_dev_rx_queue_release(void *q __rte_unused) 982 { 983 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q; 984 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 985 struct fsl_mc_io *dpni = 986 (struct fsl_mc_io *)priv->eth_dev->process_private; 987 uint8_t options = 0; 988 int ret; 989 struct dpni_queue cfg; 990 991 memset(&cfg, 0, sizeof(struct dpni_queue)); 992 PMD_INIT_FUNC_TRACE(); 993 if (dpaa2_q->cgid != 0xff) { 994 options = DPNI_QUEUE_OPT_CLEAR_CGID; 995 cfg.cgid = dpaa2_q->cgid; 996 997 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 998 DPNI_QUEUE_RX, 999 dpaa2_q->tc_index, dpaa2_q->flow_id, 1000 options, &cfg); 1001 if (ret) 1002 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 1003 dpaa2_q->fqid, ret); 1004 priv->cgid_in_use[dpaa2_q->cgid] = 0; 1005 dpaa2_q->cgid = 0xff; 1006 } 1007 } 1008 1009 static void 1010 dpaa2_dev_tx_queue_release(void *q __rte_unused) 1011 { 1012 PMD_INIT_FUNC_TRACE(); 1013 } 1014 1015 static uint32_t 1016 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1017 { 1018 int32_t ret; 1019 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1020 struct dpaa2_queue *dpaa2_q; 1021 struct qbman_swp *swp; 1022 struct qbman_fq_query_np_rslt state; 1023 uint32_t frame_cnt = 0; 1024 1025 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 1026 ret = dpaa2_affine_qbman_swp(); 1027 if (ret) { 1028 DPAA2_PMD_ERR( 1029 "Failed to allocate IO portal, tid: %d\n", 1030 rte_gettid()); 1031 return -EINVAL; 1032 } 1033 } 1034 swp = DPAA2_PER_LCORE_PORTAL; 1035 1036 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 1037 1038 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 1039 frame_cnt = qbman_fq_state_frame_count(&state); 1040 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u", 1041 rx_queue_id, frame_cnt); 1042 } 1043 return frame_cnt; 1044 } 1045 1046 static const uint32_t * 1047 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 1048 { 1049 static const uint32_t ptypes[] = { 1050 /*todo -= add more types */ 1051 RTE_PTYPE_L2_ETHER, 1052 RTE_PTYPE_L3_IPV4, 1053 RTE_PTYPE_L3_IPV4_EXT, 1054 RTE_PTYPE_L3_IPV6, 1055 RTE_PTYPE_L3_IPV6_EXT, 1056 RTE_PTYPE_L4_TCP, 1057 RTE_PTYPE_L4_UDP, 1058 RTE_PTYPE_L4_SCTP, 1059 RTE_PTYPE_L4_ICMP, 1060 RTE_PTYPE_UNKNOWN 1061 }; 1062 1063 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1064 dev->rx_pkt_burst == dpaa2_dev_rx || 1065 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 1066 return ptypes; 1067 return NULL; 1068 } 1069 1070 /** 1071 * Dpaa2 link Interrupt handler 1072 * 1073 * @param param 1074 * The address of parameter (struct rte_eth_dev *) regsitered before. 1075 * 1076 * @return 1077 * void 1078 */ 1079 static void 1080 dpaa2_interrupt_handler(void *param) 1081 { 1082 struct rte_eth_dev *dev = param; 1083 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1084 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1085 int ret; 1086 int irq_index = DPNI_IRQ_INDEX; 1087 unsigned int status = 0, clear = 0; 1088 1089 PMD_INIT_FUNC_TRACE(); 1090 1091 if (dpni == NULL) { 1092 DPAA2_PMD_ERR("dpni is NULL"); 1093 return; 1094 } 1095 1096 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1097 irq_index, &status); 1098 if (unlikely(ret)) { 1099 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1100 clear = 0xffffffff; 1101 goto out; 1102 } 1103 1104 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1105 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1106 dpaa2_dev_link_update(dev, 0); 1107 /* calling all the apps registered for link status event */ 1108 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1109 } 1110 out: 1111 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1112 irq_index, clear); 1113 if (unlikely(ret)) 1114 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1115 } 1116 1117 static int 1118 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1119 { 1120 int err = 0; 1121 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1122 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1123 int irq_index = DPNI_IRQ_INDEX; 1124 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1125 1126 PMD_INIT_FUNC_TRACE(); 1127 1128 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1129 irq_index, mask); 1130 if (err < 0) { 1131 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1132 strerror(-err)); 1133 return err; 1134 } 1135 1136 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1137 irq_index, enable); 1138 if (err < 0) 1139 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1140 strerror(-err)); 1141 1142 return err; 1143 } 1144 1145 static int 1146 dpaa2_dev_start(struct rte_eth_dev *dev) 1147 { 1148 struct rte_device *rdev = dev->device; 1149 struct rte_dpaa2_device *dpaa2_dev; 1150 struct rte_eth_dev_data *data = dev->data; 1151 struct dpaa2_dev_priv *priv = data->dev_private; 1152 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1153 struct dpni_queue cfg; 1154 struct dpni_error_cfg err_cfg; 1155 uint16_t qdid; 1156 struct dpni_queue_id qid; 1157 struct dpaa2_queue *dpaa2_q; 1158 int ret, i; 1159 struct rte_intr_handle *intr_handle; 1160 1161 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1162 intr_handle = &dpaa2_dev->intr_handle; 1163 1164 PMD_INIT_FUNC_TRACE(); 1165 1166 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1167 if (ret) { 1168 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1169 priv->hw_id, ret); 1170 return ret; 1171 } 1172 1173 /* Power up the phy. Needed to make the link go UP */ 1174 dpaa2_dev_set_link_up(dev); 1175 1176 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 1177 DPNI_QUEUE_TX, &qdid); 1178 if (ret) { 1179 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 1180 return ret; 1181 } 1182 priv->qdid = qdid; 1183 1184 for (i = 0; i < data->nb_rx_queues; i++) { 1185 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1186 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1187 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1188 dpaa2_q->flow_id, &cfg, &qid); 1189 if (ret) { 1190 DPAA2_PMD_ERR("Error in getting flow information: " 1191 "err=%d", ret); 1192 return ret; 1193 } 1194 dpaa2_q->fqid = qid.fqid; 1195 } 1196 1197 if (dpaa2_enable_err_queue) { 1198 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1199 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); 1200 if (ret) { 1201 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", 1202 ret); 1203 return ret; 1204 } 1205 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 1206 dpaa2_q->fqid = qid.fqid; 1207 dpaa2_q->eth_data = dev->data; 1208 1209 err_cfg.errors = DPNI_ERROR_DISC; 1210 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; 1211 } else { 1212 /* checksum errors, send them to normal path 1213 * and set it in annotation 1214 */ 1215 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1216 1217 /* if packet with parse error are not to be dropped */ 1218 err_cfg.errors |= DPNI_ERROR_PHE; 1219 1220 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1221 } 1222 err_cfg.set_frame_annotation = true; 1223 1224 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1225 priv->token, &err_cfg); 1226 if (ret) { 1227 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1228 ret); 1229 return ret; 1230 } 1231 1232 /* if the interrupts were configured on this devices*/ 1233 if (intr_handle && (intr_handle->fd) && 1234 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1235 /* Registering LSC interrupt handler */ 1236 rte_intr_callback_register(intr_handle, 1237 dpaa2_interrupt_handler, 1238 (void *)dev); 1239 1240 /* enable vfio intr/eventfd mapping 1241 * Interrupt index 0 is required, so we can not use 1242 * rte_intr_enable. 1243 */ 1244 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1245 1246 /* enable dpni_irqs */ 1247 dpaa2_eth_setup_irqs(dev, 1); 1248 } 1249 1250 /* Change the tx burst function if ordered queues are used */ 1251 if (priv->en_ordered) 1252 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1253 1254 return 0; 1255 } 1256 1257 /** 1258 * This routine disables all traffic on the adapter by issuing a 1259 * global reset on the MAC. 1260 */ 1261 static int 1262 dpaa2_dev_stop(struct rte_eth_dev *dev) 1263 { 1264 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1265 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1266 int ret; 1267 struct rte_eth_link link; 1268 struct rte_intr_handle *intr_handle = dev->intr_handle; 1269 1270 PMD_INIT_FUNC_TRACE(); 1271 1272 /* reset interrupt callback */ 1273 if (intr_handle && (intr_handle->fd) && 1274 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1275 /*disable dpni irqs */ 1276 dpaa2_eth_setup_irqs(dev, 0); 1277 1278 /* disable vfio intr before callback unregister */ 1279 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1280 1281 /* Unregistering LSC interrupt handler */ 1282 rte_intr_callback_unregister(intr_handle, 1283 dpaa2_interrupt_handler, 1284 (void *)dev); 1285 } 1286 1287 dpaa2_dev_set_link_down(dev); 1288 1289 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1290 if (ret) { 1291 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1292 ret, priv->hw_id); 1293 return ret; 1294 } 1295 1296 /* clear the recorded link status */ 1297 memset(&link, 0, sizeof(link)); 1298 rte_eth_linkstatus_set(dev, &link); 1299 1300 return 0; 1301 } 1302 1303 static int 1304 dpaa2_dev_close(struct rte_eth_dev *dev) 1305 { 1306 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1307 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1308 int i, ret; 1309 struct rte_eth_link link; 1310 1311 PMD_INIT_FUNC_TRACE(); 1312 1313 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1314 return 0; 1315 1316 if (!dpni) { 1317 DPAA2_PMD_WARN("Already closed or not started"); 1318 return -1; 1319 } 1320 1321 dpaa2_tm_deinit(dev); 1322 dpaa2_flow_clean(dev); 1323 /* Clean the device first */ 1324 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1325 if (ret) { 1326 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1327 return -1; 1328 } 1329 1330 memset(&link, 0, sizeof(link)); 1331 rte_eth_linkstatus_set(dev, &link); 1332 1333 /* Free private queues memory */ 1334 dpaa2_free_rx_tx_queues(dev); 1335 /* Close the device at underlying layer*/ 1336 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1337 if (ret) { 1338 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1339 ret); 1340 } 1341 1342 /* Free the allocated memory for ethernet private data and dpni*/ 1343 priv->hw = NULL; 1344 dev->process_private = NULL; 1345 rte_free(dpni); 1346 1347 for (i = 0; i < MAX_TCS; i++) 1348 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1349 1350 if (priv->extract.qos_extract_param) 1351 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1352 1353 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1354 return 0; 1355 } 1356 1357 static int 1358 dpaa2_dev_promiscuous_enable( 1359 struct rte_eth_dev *dev) 1360 { 1361 int ret; 1362 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1363 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1364 1365 PMD_INIT_FUNC_TRACE(); 1366 1367 if (dpni == NULL) { 1368 DPAA2_PMD_ERR("dpni is NULL"); 1369 return -ENODEV; 1370 } 1371 1372 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1373 if (ret < 0) 1374 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1375 1376 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1377 if (ret < 0) 1378 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1379 1380 return ret; 1381 } 1382 1383 static int 1384 dpaa2_dev_promiscuous_disable( 1385 struct rte_eth_dev *dev) 1386 { 1387 int ret; 1388 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1389 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1390 1391 PMD_INIT_FUNC_TRACE(); 1392 1393 if (dpni == NULL) { 1394 DPAA2_PMD_ERR("dpni is NULL"); 1395 return -ENODEV; 1396 } 1397 1398 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1399 if (ret < 0) 1400 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1401 1402 if (dev->data->all_multicast == 0) { 1403 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1404 priv->token, false); 1405 if (ret < 0) 1406 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1407 ret); 1408 } 1409 1410 return ret; 1411 } 1412 1413 static int 1414 dpaa2_dev_allmulticast_enable( 1415 struct rte_eth_dev *dev) 1416 { 1417 int ret; 1418 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1419 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1420 1421 PMD_INIT_FUNC_TRACE(); 1422 1423 if (dpni == NULL) { 1424 DPAA2_PMD_ERR("dpni is NULL"); 1425 return -ENODEV; 1426 } 1427 1428 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1429 if (ret < 0) 1430 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1431 1432 return ret; 1433 } 1434 1435 static int 1436 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1437 { 1438 int ret; 1439 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1440 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1441 1442 PMD_INIT_FUNC_TRACE(); 1443 1444 if (dpni == NULL) { 1445 DPAA2_PMD_ERR("dpni is NULL"); 1446 return -ENODEV; 1447 } 1448 1449 /* must remain on for all promiscuous */ 1450 if (dev->data->promiscuous == 1) 1451 return 0; 1452 1453 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1454 if (ret < 0) 1455 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1456 1457 return ret; 1458 } 1459 1460 static int 1461 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1462 { 1463 int ret; 1464 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1465 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1466 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1467 + VLAN_TAG_SIZE; 1468 1469 PMD_INIT_FUNC_TRACE(); 1470 1471 if (dpni == NULL) { 1472 DPAA2_PMD_ERR("dpni is NULL"); 1473 return -EINVAL; 1474 } 1475 1476 /* check that mtu is within the allowed range */ 1477 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1478 return -EINVAL; 1479 1480 if (frame_size > DPAA2_ETH_MAX_LEN) 1481 dev->data->dev_conf.rxmode.offloads |= 1482 DEV_RX_OFFLOAD_JUMBO_FRAME; 1483 else 1484 dev->data->dev_conf.rxmode.offloads &= 1485 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1486 1487 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1488 1489 /* Set the Max Rx frame length as 'mtu' + 1490 * Maximum Ethernet header length 1491 */ 1492 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1493 frame_size - RTE_ETHER_CRC_LEN); 1494 if (ret) { 1495 DPAA2_PMD_ERR("Setting the max frame length failed"); 1496 return -1; 1497 } 1498 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1499 return 0; 1500 } 1501 1502 static int 1503 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1504 struct rte_ether_addr *addr, 1505 __rte_unused uint32_t index, 1506 __rte_unused uint32_t pool) 1507 { 1508 int ret; 1509 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1510 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1511 1512 PMD_INIT_FUNC_TRACE(); 1513 1514 if (dpni == NULL) { 1515 DPAA2_PMD_ERR("dpni is NULL"); 1516 return -1; 1517 } 1518 1519 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1520 addr->addr_bytes, 0, 0, 0); 1521 if (ret) 1522 DPAA2_PMD_ERR( 1523 "error: Adding the MAC ADDR failed: err = %d", ret); 1524 return 0; 1525 } 1526 1527 static void 1528 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1529 uint32_t index) 1530 { 1531 int ret; 1532 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1533 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1534 struct rte_eth_dev_data *data = dev->data; 1535 struct rte_ether_addr *macaddr; 1536 1537 PMD_INIT_FUNC_TRACE(); 1538 1539 macaddr = &data->mac_addrs[index]; 1540 1541 if (dpni == NULL) { 1542 DPAA2_PMD_ERR("dpni is NULL"); 1543 return; 1544 } 1545 1546 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1547 priv->token, macaddr->addr_bytes); 1548 if (ret) 1549 DPAA2_PMD_ERR( 1550 "error: Removing the MAC ADDR failed: err = %d", ret); 1551 } 1552 1553 static int 1554 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1555 struct rte_ether_addr *addr) 1556 { 1557 int ret; 1558 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1559 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1560 1561 PMD_INIT_FUNC_TRACE(); 1562 1563 if (dpni == NULL) { 1564 DPAA2_PMD_ERR("dpni is NULL"); 1565 return -EINVAL; 1566 } 1567 1568 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1569 priv->token, addr->addr_bytes); 1570 1571 if (ret) 1572 DPAA2_PMD_ERR( 1573 "error: Setting the MAC ADDR failed %d", ret); 1574 1575 return ret; 1576 } 1577 1578 static 1579 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1580 struct rte_eth_stats *stats) 1581 { 1582 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1583 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1584 int32_t retcode; 1585 uint8_t page0 = 0, page1 = 1, page2 = 2; 1586 union dpni_statistics value; 1587 int i; 1588 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1589 1590 memset(&value, 0, sizeof(union dpni_statistics)); 1591 1592 PMD_INIT_FUNC_TRACE(); 1593 1594 if (!dpni) { 1595 DPAA2_PMD_ERR("dpni is NULL"); 1596 return -EINVAL; 1597 } 1598 1599 if (!stats) { 1600 DPAA2_PMD_ERR("stats is NULL"); 1601 return -EINVAL; 1602 } 1603 1604 /*Get Counters from page_0*/ 1605 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1606 page0, 0, &value); 1607 if (retcode) 1608 goto err; 1609 1610 stats->ipackets = value.page_0.ingress_all_frames; 1611 stats->ibytes = value.page_0.ingress_all_bytes; 1612 1613 /*Get Counters from page_1*/ 1614 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1615 page1, 0, &value); 1616 if (retcode) 1617 goto err; 1618 1619 stats->opackets = value.page_1.egress_all_frames; 1620 stats->obytes = value.page_1.egress_all_bytes; 1621 1622 /*Get Counters from page_2*/ 1623 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1624 page2, 0, &value); 1625 if (retcode) 1626 goto err; 1627 1628 /* Ingress drop frame count due to configured rules */ 1629 stats->ierrors = value.page_2.ingress_filtered_frames; 1630 /* Ingress drop frame count due to error */ 1631 stats->ierrors += value.page_2.ingress_discarded_frames; 1632 1633 stats->oerrors = value.page_2.egress_discarded_frames; 1634 stats->imissed = value.page_2.ingress_nobuffer_discards; 1635 1636 /* Fill in per queue stats */ 1637 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1638 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1639 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1640 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1641 if (dpaa2_rxq) 1642 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1643 if (dpaa2_txq) 1644 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1645 1646 /* Byte counting is not implemented */ 1647 stats->q_ibytes[i] = 0; 1648 stats->q_obytes[i] = 0; 1649 } 1650 1651 return 0; 1652 1653 err: 1654 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1655 return retcode; 1656 }; 1657 1658 static int 1659 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1660 unsigned int n) 1661 { 1662 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1663 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1664 int32_t retcode; 1665 union dpni_statistics value[5] = {}; 1666 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1667 1668 if (n < num) 1669 return num; 1670 1671 if (xstats == NULL) 1672 return 0; 1673 1674 /* Get Counters from page_0*/ 1675 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1676 0, 0, &value[0]); 1677 if (retcode) 1678 goto err; 1679 1680 /* Get Counters from page_1*/ 1681 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1682 1, 0, &value[1]); 1683 if (retcode) 1684 goto err; 1685 1686 /* Get Counters from page_2*/ 1687 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1688 2, 0, &value[2]); 1689 if (retcode) 1690 goto err; 1691 1692 for (i = 0; i < priv->max_cgs; i++) { 1693 if (!priv->cgid_in_use[i]) { 1694 /* Get Counters from page_4*/ 1695 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1696 priv->token, 1697 4, 0, &value[4]); 1698 if (retcode) 1699 goto err; 1700 break; 1701 } 1702 } 1703 1704 for (i = 0; i < num; i++) { 1705 xstats[i].id = i; 1706 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1707 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1708 } 1709 return i; 1710 err: 1711 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1712 return retcode; 1713 } 1714 1715 static int 1716 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1717 struct rte_eth_xstat_name *xstats_names, 1718 unsigned int limit) 1719 { 1720 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1721 1722 if (limit < stat_cnt) 1723 return stat_cnt; 1724 1725 if (xstats_names != NULL) 1726 for (i = 0; i < stat_cnt; i++) 1727 strlcpy(xstats_names[i].name, 1728 dpaa2_xstats_strings[i].name, 1729 sizeof(xstats_names[i].name)); 1730 1731 return stat_cnt; 1732 } 1733 1734 static int 1735 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1736 uint64_t *values, unsigned int n) 1737 { 1738 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1739 uint64_t values_copy[stat_cnt]; 1740 1741 if (!ids) { 1742 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1743 struct fsl_mc_io *dpni = 1744 (struct fsl_mc_io *)dev->process_private; 1745 int32_t retcode; 1746 union dpni_statistics value[5] = {}; 1747 1748 if (n < stat_cnt) 1749 return stat_cnt; 1750 1751 if (!values) 1752 return 0; 1753 1754 /* Get Counters from page_0*/ 1755 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1756 0, 0, &value[0]); 1757 if (retcode) 1758 return 0; 1759 1760 /* Get Counters from page_1*/ 1761 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1762 1, 0, &value[1]); 1763 if (retcode) 1764 return 0; 1765 1766 /* Get Counters from page_2*/ 1767 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1768 2, 0, &value[2]); 1769 if (retcode) 1770 return 0; 1771 1772 /* Get Counters from page_4*/ 1773 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1774 4, 0, &value[4]); 1775 if (retcode) 1776 return 0; 1777 1778 for (i = 0; i < stat_cnt; i++) { 1779 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1780 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1781 } 1782 return stat_cnt; 1783 } 1784 1785 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1786 1787 for (i = 0; i < n; i++) { 1788 if (ids[i] >= stat_cnt) { 1789 DPAA2_PMD_ERR("xstats id value isn't valid"); 1790 return -1; 1791 } 1792 values[i] = values_copy[ids[i]]; 1793 } 1794 return n; 1795 } 1796 1797 static int 1798 dpaa2_xstats_get_names_by_id( 1799 struct rte_eth_dev *dev, 1800 struct rte_eth_xstat_name *xstats_names, 1801 const uint64_t *ids, 1802 unsigned int limit) 1803 { 1804 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1805 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1806 1807 if (!ids) 1808 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1809 1810 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1811 1812 for (i = 0; i < limit; i++) { 1813 if (ids[i] >= stat_cnt) { 1814 DPAA2_PMD_ERR("xstats id value isn't valid"); 1815 return -1; 1816 } 1817 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1818 } 1819 return limit; 1820 } 1821 1822 static int 1823 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1824 { 1825 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1826 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1827 int retcode; 1828 int i; 1829 struct dpaa2_queue *dpaa2_q; 1830 1831 PMD_INIT_FUNC_TRACE(); 1832 1833 if (dpni == NULL) { 1834 DPAA2_PMD_ERR("dpni is NULL"); 1835 return -EINVAL; 1836 } 1837 1838 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1839 if (retcode) 1840 goto error; 1841 1842 /* Reset the per queue stats in dpaa2_queue structure */ 1843 for (i = 0; i < priv->nb_rx_queues; i++) { 1844 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1845 if (dpaa2_q) 1846 dpaa2_q->rx_pkts = 0; 1847 } 1848 1849 for (i = 0; i < priv->nb_tx_queues; i++) { 1850 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1851 if (dpaa2_q) 1852 dpaa2_q->tx_pkts = 0; 1853 } 1854 1855 return 0; 1856 1857 error: 1858 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1859 return retcode; 1860 }; 1861 1862 /* return 0 means link status changed, -1 means not changed */ 1863 static int 1864 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1865 int wait_to_complete) 1866 { 1867 int ret; 1868 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1869 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1870 struct rte_eth_link link; 1871 struct dpni_link_state state = {0}; 1872 uint8_t count; 1873 1874 if (dpni == NULL) { 1875 DPAA2_PMD_ERR("dpni is NULL"); 1876 return 0; 1877 } 1878 1879 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 1880 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, 1881 &state); 1882 if (ret < 0) { 1883 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1884 return -1; 1885 } 1886 if (state.up == ETH_LINK_DOWN && 1887 wait_to_complete) 1888 rte_delay_ms(CHECK_INTERVAL); 1889 else 1890 break; 1891 } 1892 1893 memset(&link, 0, sizeof(struct rte_eth_link)); 1894 link.link_status = state.up; 1895 link.link_speed = state.rate; 1896 1897 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1898 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1899 else 1900 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1901 1902 ret = rte_eth_linkstatus_set(dev, &link); 1903 if (ret == -1) 1904 DPAA2_PMD_DEBUG("No change in status"); 1905 else 1906 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1907 link.link_status ? "Up" : "Down"); 1908 1909 return ret; 1910 } 1911 1912 /** 1913 * Toggle the DPNI to enable, if not already enabled. 1914 * This is not strictly PHY up/down - it is more of logical toggling. 1915 */ 1916 static int 1917 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1918 { 1919 int ret = -EINVAL; 1920 struct dpaa2_dev_priv *priv; 1921 struct fsl_mc_io *dpni; 1922 int en = 0; 1923 struct dpni_link_state state = {0}; 1924 1925 priv = dev->data->dev_private; 1926 dpni = (struct fsl_mc_io *)dev->process_private; 1927 1928 if (dpni == NULL) { 1929 DPAA2_PMD_ERR("dpni is NULL"); 1930 return ret; 1931 } 1932 1933 /* Check if DPNI is currently enabled */ 1934 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1935 if (ret) { 1936 /* Unable to obtain dpni status; Not continuing */ 1937 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1938 return -EINVAL; 1939 } 1940 1941 /* Enable link if not already enabled */ 1942 if (!en) { 1943 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1944 if (ret) { 1945 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1946 return -EINVAL; 1947 } 1948 } 1949 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1950 if (ret < 0) { 1951 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1952 return -1; 1953 } 1954 1955 /* changing tx burst function to start enqueues */ 1956 dev->tx_pkt_burst = dpaa2_dev_tx; 1957 dev->data->dev_link.link_status = state.up; 1958 dev->data->dev_link.link_speed = state.rate; 1959 1960 if (state.up) 1961 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1962 else 1963 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1964 return ret; 1965 } 1966 1967 /** 1968 * Toggle the DPNI to disable, if not already disabled. 1969 * This is not strictly PHY up/down - it is more of logical toggling. 1970 */ 1971 static int 1972 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1973 { 1974 int ret = -EINVAL; 1975 struct dpaa2_dev_priv *priv; 1976 struct fsl_mc_io *dpni; 1977 int dpni_enabled = 0; 1978 int retries = 10; 1979 1980 PMD_INIT_FUNC_TRACE(); 1981 1982 priv = dev->data->dev_private; 1983 dpni = (struct fsl_mc_io *)dev->process_private; 1984 1985 if (dpni == NULL) { 1986 DPAA2_PMD_ERR("Device has not yet been configured"); 1987 return ret; 1988 } 1989 1990 /*changing tx burst function to avoid any more enqueues */ 1991 dev->tx_pkt_burst = dummy_dev_tx; 1992 1993 /* Loop while dpni_disable() attempts to drain the egress FQs 1994 * and confirm them back to us. 1995 */ 1996 do { 1997 ret = dpni_disable(dpni, 0, priv->token); 1998 if (ret) { 1999 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 2000 return ret; 2001 } 2002 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 2003 if (ret) { 2004 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 2005 return ret; 2006 } 2007 if (dpni_enabled) 2008 /* Allow the MC some slack */ 2009 rte_delay_us(100 * 1000); 2010 } while (dpni_enabled && --retries); 2011 2012 if (!retries) { 2013 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 2014 /* todo- we may have to manually cleanup queues. 2015 */ 2016 } else { 2017 DPAA2_PMD_INFO("Port %d Link DOWN successful", 2018 dev->data->port_id); 2019 } 2020 2021 dev->data->dev_link.link_status = 0; 2022 2023 return ret; 2024 } 2025 2026 static int 2027 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2028 { 2029 int ret = -EINVAL; 2030 struct dpaa2_dev_priv *priv; 2031 struct fsl_mc_io *dpni; 2032 struct dpni_link_state state = {0}; 2033 2034 PMD_INIT_FUNC_TRACE(); 2035 2036 priv = dev->data->dev_private; 2037 dpni = (struct fsl_mc_io *)dev->process_private; 2038 2039 if (dpni == NULL || fc_conf == NULL) { 2040 DPAA2_PMD_ERR("device not configured"); 2041 return ret; 2042 } 2043 2044 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2045 if (ret) { 2046 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 2047 return ret; 2048 } 2049 2050 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 2051 if (state.options & DPNI_LINK_OPT_PAUSE) { 2052 /* DPNI_LINK_OPT_PAUSE set 2053 * if ASYM_PAUSE not set, 2054 * RX Side flow control (handle received Pause frame) 2055 * TX side flow control (send Pause frame) 2056 * if ASYM_PAUSE set, 2057 * RX Side flow control (handle received Pause frame) 2058 * No TX side flow control (send Pause frame disabled) 2059 */ 2060 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 2061 fc_conf->mode = RTE_FC_FULL; 2062 else 2063 fc_conf->mode = RTE_FC_RX_PAUSE; 2064 } else { 2065 /* DPNI_LINK_OPT_PAUSE not set 2066 * if ASYM_PAUSE set, 2067 * TX side flow control (send Pause frame) 2068 * No RX side flow control (No action on pause frame rx) 2069 * if ASYM_PAUSE not set, 2070 * Flow control disabled 2071 */ 2072 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 2073 fc_conf->mode = RTE_FC_TX_PAUSE; 2074 else 2075 fc_conf->mode = RTE_FC_NONE; 2076 } 2077 2078 return ret; 2079 } 2080 2081 static int 2082 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2083 { 2084 int ret = -EINVAL; 2085 struct dpaa2_dev_priv *priv; 2086 struct fsl_mc_io *dpni; 2087 struct dpni_link_state state = {0}; 2088 struct dpni_link_cfg cfg = {0}; 2089 2090 PMD_INIT_FUNC_TRACE(); 2091 2092 priv = dev->data->dev_private; 2093 dpni = (struct fsl_mc_io *)dev->process_private; 2094 2095 if (dpni == NULL) { 2096 DPAA2_PMD_ERR("dpni is NULL"); 2097 return ret; 2098 } 2099 2100 /* It is necessary to obtain the current state before setting fc_conf 2101 * as MC would return error in case rate, autoneg or duplex values are 2102 * different. 2103 */ 2104 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2105 if (ret) { 2106 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2107 return -1; 2108 } 2109 2110 /* Disable link before setting configuration */ 2111 dpaa2_dev_set_link_down(dev); 2112 2113 /* Based on fc_conf, update cfg */ 2114 cfg.rate = state.rate; 2115 cfg.options = state.options; 2116 2117 /* update cfg with fc_conf */ 2118 switch (fc_conf->mode) { 2119 case RTE_FC_FULL: 2120 /* Full flow control; 2121 * OPT_PAUSE set, ASYM_PAUSE not set 2122 */ 2123 cfg.options |= DPNI_LINK_OPT_PAUSE; 2124 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2125 break; 2126 case RTE_FC_TX_PAUSE: 2127 /* Enable RX flow control 2128 * OPT_PAUSE not set; 2129 * ASYM_PAUSE set; 2130 */ 2131 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2132 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2133 break; 2134 case RTE_FC_RX_PAUSE: 2135 /* Enable TX Flow control 2136 * OPT_PAUSE set 2137 * ASYM_PAUSE set 2138 */ 2139 cfg.options |= DPNI_LINK_OPT_PAUSE; 2140 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2141 break; 2142 case RTE_FC_NONE: 2143 /* Disable Flow control 2144 * OPT_PAUSE not set 2145 * ASYM_PAUSE not set 2146 */ 2147 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2148 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2149 break; 2150 default: 2151 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2152 fc_conf->mode); 2153 return -1; 2154 } 2155 2156 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2157 if (ret) 2158 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2159 ret); 2160 2161 /* Enable link */ 2162 dpaa2_dev_set_link_up(dev); 2163 2164 return ret; 2165 } 2166 2167 static int 2168 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2169 struct rte_eth_rss_conf *rss_conf) 2170 { 2171 struct rte_eth_dev_data *data = dev->data; 2172 struct dpaa2_dev_priv *priv = data->dev_private; 2173 struct rte_eth_conf *eth_conf = &data->dev_conf; 2174 int ret, tc_index; 2175 2176 PMD_INIT_FUNC_TRACE(); 2177 2178 if (rss_conf->rss_hf) { 2179 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2180 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2181 tc_index); 2182 if (ret) { 2183 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2184 tc_index); 2185 return ret; 2186 } 2187 } 2188 } else { 2189 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2190 ret = dpaa2_remove_flow_dist(dev, tc_index); 2191 if (ret) { 2192 DPAA2_PMD_ERR( 2193 "Unable to remove flow dist on tc%d", 2194 tc_index); 2195 return ret; 2196 } 2197 } 2198 } 2199 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2200 return 0; 2201 } 2202 2203 static int 2204 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2205 struct rte_eth_rss_conf *rss_conf) 2206 { 2207 struct rte_eth_dev_data *data = dev->data; 2208 struct rte_eth_conf *eth_conf = &data->dev_conf; 2209 2210 /* dpaa2 does not support rss_key, so length should be 0*/ 2211 rss_conf->rss_key_len = 0; 2212 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2213 return 0; 2214 } 2215 2216 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2217 int eth_rx_queue_id, 2218 struct dpaa2_dpcon_dev *dpcon, 2219 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2220 { 2221 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2222 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2223 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2224 uint8_t flow_id = dpaa2_ethq->flow_id; 2225 struct dpni_queue cfg; 2226 uint8_t options, priority; 2227 int ret; 2228 2229 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2230 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2231 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2232 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2233 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2234 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2235 else 2236 return -EINVAL; 2237 2238 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2239 (dpcon->num_priorities - 1); 2240 2241 memset(&cfg, 0, sizeof(struct dpni_queue)); 2242 options = DPNI_QUEUE_OPT_DEST; 2243 cfg.destination.type = DPNI_DEST_DPCON; 2244 cfg.destination.id = dpcon->dpcon_id; 2245 cfg.destination.priority = priority; 2246 2247 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2248 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2249 cfg.destination.hold_active = 1; 2250 } 2251 2252 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2253 !eth_priv->en_ordered) { 2254 struct opr_cfg ocfg; 2255 2256 /* Restoration window size = 256 frames */ 2257 ocfg.oprrws = 3; 2258 /* Restoration window size = 512 frames for LX2 */ 2259 if (dpaa2_svr_family == SVR_LX2160A) 2260 ocfg.oprrws = 4; 2261 /* Auto advance NESN window enabled */ 2262 ocfg.oa = 1; 2263 /* Late arrival window size disabled */ 2264 ocfg.olws = 0; 2265 /* ORL resource exhaustaion advance NESN disabled */ 2266 ocfg.oeane = 0; 2267 /* Loose ordering enabled */ 2268 ocfg.oloe = 1; 2269 eth_priv->en_loose_ordered = 1; 2270 /* Strict ordering enabled if explicitly set */ 2271 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2272 ocfg.oloe = 0; 2273 eth_priv->en_loose_ordered = 0; 2274 } 2275 2276 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2277 dpaa2_ethq->tc_index, flow_id, 2278 OPR_OPT_CREATE, &ocfg); 2279 if (ret) { 2280 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2281 return ret; 2282 } 2283 2284 eth_priv->en_ordered = 1; 2285 } 2286 2287 options |= DPNI_QUEUE_OPT_USER_CTX; 2288 cfg.user_context = (size_t)(dpaa2_ethq); 2289 2290 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2291 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2292 if (ret) { 2293 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2294 return ret; 2295 } 2296 2297 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2298 2299 return 0; 2300 } 2301 2302 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2303 int eth_rx_queue_id) 2304 { 2305 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2306 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2307 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2308 uint8_t flow_id = dpaa2_ethq->flow_id; 2309 struct dpni_queue cfg; 2310 uint8_t options; 2311 int ret; 2312 2313 memset(&cfg, 0, sizeof(struct dpni_queue)); 2314 options = DPNI_QUEUE_OPT_DEST; 2315 cfg.destination.type = DPNI_DEST_NONE; 2316 2317 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2318 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2319 if (ret) 2320 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2321 2322 return ret; 2323 } 2324 2325 static inline int 2326 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op) 2327 { 2328 unsigned int i; 2329 2330 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) { 2331 if (dpaa2_supported_filter_ops[i] == filter_op) 2332 return 0; 2333 } 2334 return -ENOTSUP; 2335 } 2336 2337 static int 2338 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev, 2339 enum rte_filter_type filter_type, 2340 enum rte_filter_op filter_op, 2341 void *arg) 2342 { 2343 int ret = 0; 2344 2345 if (!dev) 2346 return -ENODEV; 2347 2348 switch (filter_type) { 2349 case RTE_ETH_FILTER_GENERIC: 2350 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) { 2351 ret = -ENOTSUP; 2352 break; 2353 } 2354 *(const void **)arg = &dpaa2_flow_ops; 2355 dpaa2_filter_type |= filter_type; 2356 break; 2357 default: 2358 RTE_LOG(ERR, PMD, "Filter type (%d) not supported", 2359 filter_type); 2360 ret = -ENOTSUP; 2361 break; 2362 } 2363 return ret; 2364 } 2365 2366 static void 2367 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2368 struct rte_eth_rxq_info *qinfo) 2369 { 2370 struct dpaa2_queue *rxq; 2371 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2372 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2373 uint16_t max_frame_length; 2374 2375 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2376 2377 qinfo->mp = rxq->mb_pool; 2378 qinfo->scattered_rx = dev->data->scattered_rx; 2379 qinfo->nb_desc = rxq->nb_desc; 2380 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 2381 &max_frame_length) == 0) 2382 qinfo->rx_buf_size = max_frame_length; 2383 2384 qinfo->conf.rx_free_thresh = 1; 2385 qinfo->conf.rx_drop_en = 1; 2386 qinfo->conf.rx_deferred_start = 0; 2387 qinfo->conf.offloads = rxq->offloads; 2388 } 2389 2390 static void 2391 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2392 struct rte_eth_txq_info *qinfo) 2393 { 2394 struct dpaa2_queue *txq; 2395 2396 txq = dev->data->tx_queues[queue_id]; 2397 2398 qinfo->nb_desc = txq->nb_desc; 2399 qinfo->conf.tx_thresh.pthresh = 0; 2400 qinfo->conf.tx_thresh.hthresh = 0; 2401 qinfo->conf.tx_thresh.wthresh = 0; 2402 2403 qinfo->conf.tx_free_thresh = 0; 2404 qinfo->conf.tx_rs_thresh = 0; 2405 qinfo->conf.offloads = txq->offloads; 2406 qinfo->conf.tx_deferred_start = 0; 2407 } 2408 2409 static int 2410 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2411 { 2412 *(const void **)ops = &dpaa2_tm_ops; 2413 2414 return 0; 2415 } 2416 2417 static struct eth_dev_ops dpaa2_ethdev_ops = { 2418 .dev_configure = dpaa2_eth_dev_configure, 2419 .dev_start = dpaa2_dev_start, 2420 .dev_stop = dpaa2_dev_stop, 2421 .dev_close = dpaa2_dev_close, 2422 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2423 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2424 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2425 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2426 .dev_set_link_up = dpaa2_dev_set_link_up, 2427 .dev_set_link_down = dpaa2_dev_set_link_down, 2428 .link_update = dpaa2_dev_link_update, 2429 .stats_get = dpaa2_dev_stats_get, 2430 .xstats_get = dpaa2_dev_xstats_get, 2431 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2432 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2433 .xstats_get_names = dpaa2_xstats_get_names, 2434 .stats_reset = dpaa2_dev_stats_reset, 2435 .xstats_reset = dpaa2_dev_stats_reset, 2436 .fw_version_get = dpaa2_fw_version_get, 2437 .dev_infos_get = dpaa2_dev_info_get, 2438 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2439 .mtu_set = dpaa2_dev_mtu_set, 2440 .vlan_filter_set = dpaa2_vlan_filter_set, 2441 .vlan_offload_set = dpaa2_vlan_offload_set, 2442 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2443 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2444 .rx_queue_release = dpaa2_dev_rx_queue_release, 2445 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2446 .tx_queue_release = dpaa2_dev_tx_queue_release, 2447 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2448 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2449 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2450 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2451 .mac_addr_add = dpaa2_dev_add_mac_addr, 2452 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2453 .mac_addr_set = dpaa2_dev_set_mac_addr, 2454 .rss_hash_update = dpaa2_dev_rss_hash_update, 2455 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2456 .filter_ctrl = dpaa2_dev_flow_ctrl, 2457 .rxq_info_get = dpaa2_rxq_info_get, 2458 .txq_info_get = dpaa2_txq_info_get, 2459 .tm_ops_get = dpaa2_tm_ops_get, 2460 #if defined(RTE_LIBRTE_IEEE1588) 2461 .timesync_enable = dpaa2_timesync_enable, 2462 .timesync_disable = dpaa2_timesync_disable, 2463 .timesync_read_time = dpaa2_timesync_read_time, 2464 .timesync_write_time = dpaa2_timesync_write_time, 2465 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2466 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2467 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2468 #endif 2469 }; 2470 2471 /* Populate the mac address from physically available (u-boot/firmware) and/or 2472 * one set by higher layers like MC (restool) etc. 2473 * Returns the table of MAC entries (multiple entries) 2474 */ 2475 static int 2476 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2477 struct rte_ether_addr *mac_entry) 2478 { 2479 int ret; 2480 struct rte_ether_addr phy_mac, prime_mac; 2481 2482 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2483 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2484 2485 /* Get the physical device MAC address */ 2486 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2487 phy_mac.addr_bytes); 2488 if (ret) { 2489 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2490 goto cleanup; 2491 } 2492 2493 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2494 prime_mac.addr_bytes); 2495 if (ret) { 2496 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2497 goto cleanup; 2498 } 2499 2500 /* Now that both MAC have been obtained, do: 2501 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2502 * and return phy 2503 * If empty_mac(phy), return prime. 2504 * if both are empty, create random MAC, set as prime and return 2505 */ 2506 if (!rte_is_zero_ether_addr(&phy_mac)) { 2507 /* If the addresses are not same, overwrite prime */ 2508 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2509 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2510 priv->token, 2511 phy_mac.addr_bytes); 2512 if (ret) { 2513 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2514 ret); 2515 goto cleanup; 2516 } 2517 memcpy(&prime_mac, &phy_mac, 2518 sizeof(struct rte_ether_addr)); 2519 } 2520 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2521 /* In case phys and prime, both are zero, create random MAC */ 2522 rte_eth_random_addr(prime_mac.addr_bytes); 2523 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2524 priv->token, 2525 prime_mac.addr_bytes); 2526 if (ret) { 2527 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2528 goto cleanup; 2529 } 2530 } 2531 2532 /* prime_mac the final MAC address */ 2533 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2534 return 0; 2535 2536 cleanup: 2537 return -1; 2538 } 2539 2540 static int 2541 check_devargs_handler(__rte_unused const char *key, const char *value, 2542 __rte_unused void *opaque) 2543 { 2544 if (strcmp(value, "1")) 2545 return -1; 2546 2547 return 0; 2548 } 2549 2550 static int 2551 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2552 { 2553 struct rte_kvargs *kvlist; 2554 2555 if (!devargs) 2556 return 0; 2557 2558 kvlist = rte_kvargs_parse(devargs->args, NULL); 2559 if (!kvlist) 2560 return 0; 2561 2562 if (!rte_kvargs_count(kvlist, key)) { 2563 rte_kvargs_free(kvlist); 2564 return 0; 2565 } 2566 2567 if (rte_kvargs_process(kvlist, key, 2568 check_devargs_handler, NULL) < 0) { 2569 rte_kvargs_free(kvlist); 2570 return 0; 2571 } 2572 rte_kvargs_free(kvlist); 2573 2574 return 1; 2575 } 2576 2577 static int 2578 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2579 { 2580 struct rte_device *dev = eth_dev->device; 2581 struct rte_dpaa2_device *dpaa2_dev; 2582 struct fsl_mc_io *dpni_dev; 2583 struct dpni_attr attr; 2584 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2585 struct dpni_buffer_layout layout; 2586 int ret, hw_id, i; 2587 2588 PMD_INIT_FUNC_TRACE(); 2589 2590 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2591 if (!dpni_dev) { 2592 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2593 return -1; 2594 } 2595 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2596 eth_dev->process_private = (void *)dpni_dev; 2597 2598 /* For secondary processes, the primary has done all the work */ 2599 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2600 /* In case of secondary, only burst and ops API need to be 2601 * plugged. 2602 */ 2603 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2604 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2605 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2606 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2607 else if (dpaa2_get_devargs(dev->devargs, 2608 DRIVER_NO_PREFETCH_MODE)) 2609 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2610 else 2611 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2612 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2613 return 0; 2614 } 2615 2616 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2617 2618 hw_id = dpaa2_dev->object_id; 2619 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2620 if (ret) { 2621 DPAA2_PMD_ERR( 2622 "Failure in opening dpni@%d with err code %d", 2623 hw_id, ret); 2624 rte_free(dpni_dev); 2625 return -1; 2626 } 2627 2628 /* Clean the device first */ 2629 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2630 if (ret) { 2631 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2632 hw_id, ret); 2633 goto init_err; 2634 } 2635 2636 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2637 if (ret) { 2638 DPAA2_PMD_ERR( 2639 "Failure in get dpni@%d attribute, err code %d", 2640 hw_id, ret); 2641 goto init_err; 2642 } 2643 2644 priv->num_rx_tc = attr.num_rx_tcs; 2645 priv->qos_entries = attr.qos_entries; 2646 priv->fs_entries = attr.fs_entries; 2647 priv->dist_queues = attr.num_queues; 2648 2649 /* only if the custom CG is enabled */ 2650 if (attr.options & DPNI_OPT_CUSTOM_CG) 2651 priv->max_cgs = attr.num_cgs; 2652 else 2653 priv->max_cgs = 0; 2654 2655 for (i = 0; i < priv->max_cgs; i++) 2656 priv->cgid_in_use[i] = 0; 2657 2658 for (i = 0; i < attr.num_rx_tcs; i++) 2659 priv->nb_rx_queues += attr.num_queues; 2660 2661 /* Using number of TX queues as number of TX TCs */ 2662 priv->nb_tx_queues = attr.num_tx_tcs; 2663 2664 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2665 priv->num_rx_tc, priv->nb_rx_queues, 2666 priv->nb_tx_queues, priv->max_cgs); 2667 2668 priv->hw = dpni_dev; 2669 priv->hw_id = hw_id; 2670 priv->options = attr.options; 2671 priv->max_mac_filters = attr.mac_filter_entries; 2672 priv->max_vlan_filters = attr.vlan_filter_entries; 2673 priv->flags = 0; 2674 #if defined(RTE_LIBRTE_IEEE1588) 2675 printf("DPDK IEEE1588 is enabled\n"); 2676 priv->flags |= DPAA2_TX_CONF_ENABLE; 2677 #endif 2678 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ 2679 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { 2680 priv->flags |= DPAA2_TX_CONF_ENABLE; 2681 DPAA2_PMD_INFO("TX_CONF Enabled"); 2682 } 2683 2684 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { 2685 dpaa2_enable_err_queue = 1; 2686 DPAA2_PMD_INFO("Enable error queue"); 2687 } 2688 2689 /* Allocate memory for hardware structure for queues */ 2690 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2691 if (ret) { 2692 DPAA2_PMD_ERR("Queue allocation Failed"); 2693 goto init_err; 2694 } 2695 2696 /* Allocate memory for storing MAC addresses. 2697 * Table of mac_filter_entries size is allocated so that RTE ether lib 2698 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2699 */ 2700 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2701 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2702 if (eth_dev->data->mac_addrs == NULL) { 2703 DPAA2_PMD_ERR( 2704 "Failed to allocate %d bytes needed to store MAC addresses", 2705 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2706 ret = -ENOMEM; 2707 goto init_err; 2708 } 2709 2710 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2711 if (ret) { 2712 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2713 rte_free(eth_dev->data->mac_addrs); 2714 eth_dev->data->mac_addrs = NULL; 2715 goto init_err; 2716 } 2717 2718 /* ... tx buffer layout ... */ 2719 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2720 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2721 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2722 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2723 layout.pass_timestamp = true; 2724 } else { 2725 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2726 } 2727 layout.pass_frame_status = 1; 2728 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2729 DPNI_QUEUE_TX, &layout); 2730 if (ret) { 2731 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2732 goto init_err; 2733 } 2734 2735 /* ... tx-conf and error buffer layout ... */ 2736 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2737 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2738 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2739 layout.pass_timestamp = true; 2740 } 2741 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2742 layout.pass_frame_status = 1; 2743 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2744 DPNI_QUEUE_TX_CONFIRM, &layout); 2745 if (ret) { 2746 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2747 ret); 2748 goto init_err; 2749 } 2750 2751 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2752 2753 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2754 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2755 DPAA2_PMD_INFO("Loopback mode"); 2756 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2757 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2758 DPAA2_PMD_INFO("No Prefetch mode"); 2759 } else { 2760 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2761 } 2762 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2763 2764 /*Init fields w.r.t. classficaition*/ 2765 memset(&priv->extract.qos_key_extract, 0, 2766 sizeof(struct dpaa2_key_extract)); 2767 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2768 if (!priv->extract.qos_extract_param) { 2769 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2770 " classificaiton ", ret); 2771 goto init_err; 2772 } 2773 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2774 IP_ADDRESS_OFFSET_INVALID; 2775 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2776 IP_ADDRESS_OFFSET_INVALID; 2777 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2778 IP_ADDRESS_OFFSET_INVALID; 2779 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2780 IP_ADDRESS_OFFSET_INVALID; 2781 2782 for (i = 0; i < MAX_TCS; i++) { 2783 memset(&priv->extract.tc_key_extract[i], 0, 2784 sizeof(struct dpaa2_key_extract)); 2785 priv->extract.tc_extract_param[i] = 2786 (size_t)rte_malloc(NULL, 256, 64); 2787 if (!priv->extract.tc_extract_param[i]) { 2788 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2789 ret); 2790 goto init_err; 2791 } 2792 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2793 IP_ADDRESS_OFFSET_INVALID; 2794 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2795 IP_ADDRESS_OFFSET_INVALID; 2796 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2797 IP_ADDRESS_OFFSET_INVALID; 2798 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2799 IP_ADDRESS_OFFSET_INVALID; 2800 } 2801 2802 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2803 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2804 + VLAN_TAG_SIZE); 2805 if (ret) { 2806 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2807 goto init_err; 2808 } 2809 2810 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2811 * with external entity to receive byte code for software sequence 2812 * and same will be offload to the H/W using MC interface. 2813 * Currently it is assumed that DPAA2 driver has byte code by some 2814 * mean and same if offloaded to H/W. 2815 */ 2816 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2817 WRIOP_SS_INITIALIZER(priv); 2818 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2819 if (ret < 0) { 2820 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2821 ret); 2822 return ret; 2823 } 2824 2825 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2826 DPNI_SS_INGRESS); 2827 if (ret < 0) { 2828 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2829 ret); 2830 return ret; 2831 } 2832 } 2833 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2834 return 0; 2835 init_err: 2836 dpaa2_dev_close(eth_dev); 2837 2838 return ret; 2839 } 2840 2841 static int 2842 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2843 struct rte_dpaa2_device *dpaa2_dev) 2844 { 2845 struct rte_eth_dev *eth_dev; 2846 struct dpaa2_dev_priv *dev_priv; 2847 int diag; 2848 2849 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2850 RTE_PKTMBUF_HEADROOM) { 2851 DPAA2_PMD_ERR( 2852 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2853 RTE_PKTMBUF_HEADROOM, 2854 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2855 2856 return -1; 2857 } 2858 2859 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2860 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2861 if (!eth_dev) 2862 return -ENODEV; 2863 dev_priv = rte_zmalloc("ethdev private structure", 2864 sizeof(struct dpaa2_dev_priv), 2865 RTE_CACHE_LINE_SIZE); 2866 if (dev_priv == NULL) { 2867 DPAA2_PMD_CRIT( 2868 "Unable to allocate memory for private data"); 2869 rte_eth_dev_release_port(eth_dev); 2870 return -ENOMEM; 2871 } 2872 eth_dev->data->dev_private = (void *)dev_priv; 2873 /* Store a pointer to eth_dev in dev_private */ 2874 dev_priv->eth_dev = eth_dev; 2875 } else { 2876 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2877 if (!eth_dev) { 2878 DPAA2_PMD_DEBUG("returning enodev"); 2879 return -ENODEV; 2880 } 2881 } 2882 2883 eth_dev->device = &dpaa2_dev->device; 2884 2885 dpaa2_dev->eth_dev = eth_dev; 2886 eth_dev->data->rx_mbuf_alloc_failed = 0; 2887 2888 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2889 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2890 2891 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2892 2893 /* Invoke PMD device initialization function */ 2894 diag = dpaa2_dev_init(eth_dev); 2895 if (diag == 0) { 2896 rte_eth_dev_probing_finish(eth_dev); 2897 return 0; 2898 } 2899 2900 rte_eth_dev_release_port(eth_dev); 2901 return diag; 2902 } 2903 2904 static int 2905 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2906 { 2907 struct rte_eth_dev *eth_dev; 2908 int ret; 2909 2910 eth_dev = dpaa2_dev->eth_dev; 2911 dpaa2_dev_close(eth_dev); 2912 ret = rte_eth_dev_release_port(eth_dev); 2913 2914 return ret; 2915 } 2916 2917 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2918 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2919 .drv_type = DPAA2_ETH, 2920 .probe = rte_dpaa2_probe, 2921 .remove = rte_dpaa2_remove, 2922 }; 2923 2924 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2925 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, 2926 DRIVER_LOOPBACK_MODE "=<int> " 2927 DRIVER_NO_PREFETCH_MODE "=<int>" 2928 DRIVER_TX_CONF "=<int>" 2929 DRIVER_ERROR_QUEUE "=<int>"); 2930 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE); 2931