1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2021 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include "dpaa2_sparser.h" 30 #include <fsl_qbman_debug.h> 31 32 #define DRIVER_LOOPBACK_MODE "drv_loopback" 33 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 34 #define DRIVER_TX_CONF "drv_tx_conf" 35 #define DRIVER_ERROR_QUEUE "drv_err_queue" 36 #define CHECK_INTERVAL 100 /* 100ms */ 37 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 38 39 /* Supported Rx offloads */ 40 static uint64_t dev_rx_offloads_sup = 41 DEV_RX_OFFLOAD_CHECKSUM | 42 DEV_RX_OFFLOAD_SCTP_CKSUM | 43 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 44 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 45 DEV_RX_OFFLOAD_VLAN_STRIP | 46 DEV_RX_OFFLOAD_VLAN_FILTER | 47 DEV_RX_OFFLOAD_JUMBO_FRAME | 48 DEV_RX_OFFLOAD_TIMESTAMP; 49 50 /* Rx offloads which cannot be disabled */ 51 static uint64_t dev_rx_offloads_nodis = 52 DEV_RX_OFFLOAD_RSS_HASH | 53 DEV_RX_OFFLOAD_SCATTER; 54 55 /* Supported Tx offloads */ 56 static uint64_t dev_tx_offloads_sup = 57 DEV_TX_OFFLOAD_VLAN_INSERT | 58 DEV_TX_OFFLOAD_IPV4_CKSUM | 59 DEV_TX_OFFLOAD_UDP_CKSUM | 60 DEV_TX_OFFLOAD_TCP_CKSUM | 61 DEV_TX_OFFLOAD_SCTP_CKSUM | 62 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 63 DEV_TX_OFFLOAD_MT_LOCKFREE | 64 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 DEV_TX_OFFLOAD_MULTI_SEGS; 69 70 /* enable timestamp in mbuf */ 71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 72 uint64_t dpaa2_timestamp_rx_dynflag; 73 int dpaa2_timestamp_dynfield_offset = -1; 74 75 /* Enable error queue */ 76 bool dpaa2_enable_err_queue; 77 78 struct rte_dpaa2_xstats_name_off { 79 char name[RTE_ETH_XSTATS_NAME_SIZE]; 80 uint8_t page_id; /* dpni statistics page id */ 81 uint8_t stats_id; /* stats id in the given page */ 82 }; 83 84 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 85 {"ingress_multicast_frames", 0, 2}, 86 {"ingress_multicast_bytes", 0, 3}, 87 {"ingress_broadcast_frames", 0, 4}, 88 {"ingress_broadcast_bytes", 0, 5}, 89 {"egress_multicast_frames", 1, 2}, 90 {"egress_multicast_bytes", 1, 3}, 91 {"egress_broadcast_frames", 1, 4}, 92 {"egress_broadcast_bytes", 1, 5}, 93 {"ingress_filtered_frames", 2, 0}, 94 {"ingress_discarded_frames", 2, 1}, 95 {"ingress_nobuffer_discards", 2, 2}, 96 {"egress_discarded_frames", 2, 3}, 97 {"egress_confirmed_frames", 2, 4}, 98 {"cgr_reject_frames", 4, 0}, 99 {"cgr_reject_bytes", 4, 1}, 100 }; 101 102 static struct rte_dpaa2_driver rte_dpaa2_pmd; 103 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 104 int wait_to_complete); 105 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 106 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 107 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 108 109 static int 110 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 111 { 112 int ret; 113 struct dpaa2_dev_priv *priv = dev->data->dev_private; 114 struct fsl_mc_io *dpni = dev->process_private; 115 116 PMD_INIT_FUNC_TRACE(); 117 118 if (dpni == NULL) { 119 DPAA2_PMD_ERR("dpni is NULL"); 120 return -1; 121 } 122 123 if (on) 124 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 125 vlan_id, 0, 0, 0); 126 else 127 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 128 priv->token, vlan_id); 129 130 if (ret < 0) 131 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 132 ret, vlan_id, priv->hw_id); 133 134 return ret; 135 } 136 137 static int 138 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 139 { 140 struct dpaa2_dev_priv *priv = dev->data->dev_private; 141 struct fsl_mc_io *dpni = dev->process_private; 142 int ret = 0; 143 144 PMD_INIT_FUNC_TRACE(); 145 146 if (mask & ETH_VLAN_FILTER_MASK) { 147 /* VLAN Filter not avaialble */ 148 if (!priv->max_vlan_filters) { 149 DPAA2_PMD_INFO("VLAN filter not available"); 150 return -ENOTSUP; 151 } 152 153 if (dev->data->dev_conf.rxmode.offloads & 154 DEV_RX_OFFLOAD_VLAN_FILTER) 155 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 156 priv->token, true); 157 else 158 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 159 priv->token, false); 160 if (ret < 0) 161 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 162 } 163 164 return ret; 165 } 166 167 static int 168 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 169 enum rte_vlan_type vlan_type __rte_unused, 170 uint16_t tpid) 171 { 172 struct dpaa2_dev_priv *priv = dev->data->dev_private; 173 struct fsl_mc_io *dpni = dev->process_private; 174 int ret = -ENOTSUP; 175 176 PMD_INIT_FUNC_TRACE(); 177 178 /* nothing to be done for standard vlan tpids */ 179 if (tpid == 0x8100 || tpid == 0x88A8) 180 return 0; 181 182 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 183 priv->token, tpid); 184 if (ret < 0) 185 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 186 /* if already configured tpids, remove them first */ 187 if (ret == -EBUSY) { 188 struct dpni_custom_tpid_cfg tpid_list = {0}; 189 190 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 191 priv->token, &tpid_list); 192 if (ret < 0) 193 goto fail; 194 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 195 priv->token, tpid_list.tpid1); 196 if (ret < 0) 197 goto fail; 198 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 199 priv->token, tpid); 200 } 201 fail: 202 return ret; 203 } 204 205 static int 206 dpaa2_fw_version_get(struct rte_eth_dev *dev, 207 char *fw_version, 208 size_t fw_size) 209 { 210 int ret; 211 struct fsl_mc_io *dpni = dev->process_private; 212 struct mc_soc_version mc_plat_info = {0}; 213 struct mc_version mc_ver_info = {0}; 214 215 PMD_INIT_FUNC_TRACE(); 216 217 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 218 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 219 220 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 221 DPAA2_PMD_WARN("\tmc_get_version failed"); 222 223 ret = snprintf(fw_version, fw_size, 224 "%x-%d.%d.%d", 225 mc_plat_info.svr, 226 mc_ver_info.major, 227 mc_ver_info.minor, 228 mc_ver_info.revision); 229 230 ret += 1; /* add the size of '\0' */ 231 if (fw_size < (uint32_t)ret) 232 return ret; 233 else 234 return 0; 235 } 236 237 static int 238 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 239 { 240 struct dpaa2_dev_priv *priv = dev->data->dev_private; 241 242 PMD_INIT_FUNC_TRACE(); 243 244 dev_info->max_mac_addrs = priv->max_mac_filters; 245 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 246 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 247 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 248 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 249 dev_info->rx_offload_capa = dev_rx_offloads_sup | 250 dev_rx_offloads_nodis; 251 dev_info->tx_offload_capa = dev_tx_offloads_sup | 252 dev_tx_offloads_nodis; 253 dev_info->speed_capa = ETH_LINK_SPEED_1G | 254 ETH_LINK_SPEED_2_5G | 255 ETH_LINK_SPEED_10G; 256 257 dev_info->max_hash_mac_addrs = 0; 258 dev_info->max_vfs = 0; 259 dev_info->max_vmdq_pools = ETH_16_POOLS; 260 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 261 262 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 263 /* same is rx size for best perf */ 264 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 265 266 dev_info->default_rxportconf.nb_queues = 1; 267 dev_info->default_txportconf.nb_queues = 1; 268 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 269 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 270 271 if (dpaa2_svr_family == SVR_LX2160A) { 272 dev_info->speed_capa |= ETH_LINK_SPEED_25G | 273 ETH_LINK_SPEED_40G | 274 ETH_LINK_SPEED_50G | 275 ETH_LINK_SPEED_100G; 276 } 277 278 return 0; 279 } 280 281 static int 282 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 283 __rte_unused uint16_t queue_id, 284 struct rte_eth_burst_mode *mode) 285 { 286 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 287 int ret = -EINVAL; 288 unsigned int i; 289 const struct burst_info { 290 uint64_t flags; 291 const char *output; 292 } rx_offload_map[] = { 293 {DEV_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 294 {DEV_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 295 {DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 296 {DEV_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 297 {DEV_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 298 {DEV_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 299 {DEV_RX_OFFLOAD_JUMBO_FRAME, " Jumbo frame,"}, 300 {DEV_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 301 {DEV_RX_OFFLOAD_RSS_HASH, " RSS,"}, 302 {DEV_RX_OFFLOAD_SCATTER, " Scattered,"} 303 }; 304 305 /* Update Rx offload info */ 306 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 307 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 308 snprintf(mode->info, sizeof(mode->info), "%s", 309 rx_offload_map[i].output); 310 ret = 0; 311 break; 312 } 313 } 314 return ret; 315 } 316 317 static int 318 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 319 __rte_unused uint16_t queue_id, 320 struct rte_eth_burst_mode *mode) 321 { 322 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 323 int ret = -EINVAL; 324 unsigned int i; 325 const struct burst_info { 326 uint64_t flags; 327 const char *output; 328 } tx_offload_map[] = { 329 {DEV_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 330 {DEV_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 331 {DEV_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 332 {DEV_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 333 {DEV_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 334 {DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 335 {DEV_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 336 {DEV_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 337 {DEV_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 338 }; 339 340 /* Update Tx offload info */ 341 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 342 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 343 snprintf(mode->info, sizeof(mode->info), "%s", 344 tx_offload_map[i].output); 345 ret = 0; 346 break; 347 } 348 } 349 return ret; 350 } 351 352 static int 353 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 354 { 355 struct dpaa2_dev_priv *priv = dev->data->dev_private; 356 uint16_t dist_idx; 357 uint32_t vq_id; 358 uint8_t num_rxqueue_per_tc; 359 struct dpaa2_queue *mc_q, *mcq; 360 uint32_t tot_queues; 361 int i; 362 struct dpaa2_queue *dpaa2_q; 363 364 PMD_INIT_FUNC_TRACE(); 365 366 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 367 if (priv->flags & DPAA2_TX_CONF_ENABLE) 368 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 369 else 370 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 371 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 372 RTE_CACHE_LINE_SIZE); 373 if (!mc_q) { 374 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 375 return -1; 376 } 377 378 for (i = 0; i < priv->nb_rx_queues; i++) { 379 mc_q->eth_data = dev->data; 380 priv->rx_vq[i] = mc_q++; 381 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 382 dpaa2_q->q_storage = rte_malloc("dq_storage", 383 sizeof(struct queue_storage_info_t), 384 RTE_CACHE_LINE_SIZE); 385 if (!dpaa2_q->q_storage) 386 goto fail; 387 388 memset(dpaa2_q->q_storage, 0, 389 sizeof(struct queue_storage_info_t)); 390 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 391 goto fail; 392 } 393 394 if (dpaa2_enable_err_queue) { 395 priv->rx_err_vq = rte_zmalloc("dpni_rx_err", 396 sizeof(struct dpaa2_queue), 0); 397 398 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 399 dpaa2_q->q_storage = rte_malloc("err_dq_storage", 400 sizeof(struct queue_storage_info_t) * 401 RTE_MAX_LCORE, 402 RTE_CACHE_LINE_SIZE); 403 if (!dpaa2_q->q_storage) 404 goto fail; 405 406 memset(dpaa2_q->q_storage, 0, 407 sizeof(struct queue_storage_info_t)); 408 for (i = 0; i < RTE_MAX_LCORE; i++) 409 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i])) 410 goto fail; 411 } 412 413 for (i = 0; i < priv->nb_tx_queues; i++) { 414 mc_q->eth_data = dev->data; 415 mc_q->flow_id = 0xffff; 416 priv->tx_vq[i] = mc_q++; 417 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 418 dpaa2_q->cscn = rte_malloc(NULL, 419 sizeof(struct qbman_result), 16); 420 if (!dpaa2_q->cscn) 421 goto fail_tx; 422 } 423 424 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 425 /*Setup tx confirmation queues*/ 426 for (i = 0; i < priv->nb_tx_queues; i++) { 427 mc_q->eth_data = dev->data; 428 mc_q->tc_index = i; 429 mc_q->flow_id = 0; 430 priv->tx_conf_vq[i] = mc_q++; 431 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 432 dpaa2_q->q_storage = 433 rte_malloc("dq_storage", 434 sizeof(struct queue_storage_info_t), 435 RTE_CACHE_LINE_SIZE); 436 if (!dpaa2_q->q_storage) 437 goto fail_tx_conf; 438 439 memset(dpaa2_q->q_storage, 0, 440 sizeof(struct queue_storage_info_t)); 441 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 442 goto fail_tx_conf; 443 } 444 } 445 446 vq_id = 0; 447 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 448 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 449 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 450 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 451 vq_id++; 452 } 453 454 return 0; 455 fail_tx_conf: 456 i -= 1; 457 while (i >= 0) { 458 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 459 rte_free(dpaa2_q->q_storage); 460 priv->tx_conf_vq[i--] = NULL; 461 } 462 i = priv->nb_tx_queues; 463 fail_tx: 464 i -= 1; 465 while (i >= 0) { 466 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 467 rte_free(dpaa2_q->cscn); 468 priv->tx_vq[i--] = NULL; 469 } 470 i = priv->nb_rx_queues; 471 fail: 472 i -= 1; 473 mc_q = priv->rx_vq[0]; 474 while (i >= 0) { 475 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 476 dpaa2_free_dq_storage(dpaa2_q->q_storage); 477 rte_free(dpaa2_q->q_storage); 478 priv->rx_vq[i--] = NULL; 479 } 480 481 if (dpaa2_enable_err_queue) { 482 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 483 if (dpaa2_q->q_storage) 484 dpaa2_free_dq_storage(dpaa2_q->q_storage); 485 rte_free(dpaa2_q->q_storage); 486 } 487 488 rte_free(mc_q); 489 return -1; 490 } 491 492 static void 493 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 494 { 495 struct dpaa2_dev_priv *priv = dev->data->dev_private; 496 struct dpaa2_queue *dpaa2_q; 497 int i; 498 499 PMD_INIT_FUNC_TRACE(); 500 501 /* Queue allocation base */ 502 if (priv->rx_vq[0]) { 503 /* cleaning up queue storage */ 504 for (i = 0; i < priv->nb_rx_queues; i++) { 505 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 506 if (dpaa2_q->q_storage) 507 rte_free(dpaa2_q->q_storage); 508 } 509 /* cleanup tx queue cscn */ 510 for (i = 0; i < priv->nb_tx_queues; i++) { 511 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 512 rte_free(dpaa2_q->cscn); 513 } 514 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 515 /* cleanup tx conf queue storage */ 516 for (i = 0; i < priv->nb_tx_queues; i++) { 517 dpaa2_q = (struct dpaa2_queue *) 518 priv->tx_conf_vq[i]; 519 rte_free(dpaa2_q->q_storage); 520 } 521 } 522 /*free memory for all queues (RX+TX) */ 523 rte_free(priv->rx_vq[0]); 524 priv->rx_vq[0] = NULL; 525 } 526 } 527 528 static int 529 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 530 { 531 struct dpaa2_dev_priv *priv = dev->data->dev_private; 532 struct fsl_mc_io *dpni = dev->process_private; 533 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 534 uint64_t rx_offloads = eth_conf->rxmode.offloads; 535 uint64_t tx_offloads = eth_conf->txmode.offloads; 536 int rx_l3_csum_offload = false; 537 int rx_l4_csum_offload = false; 538 int tx_l3_csum_offload = false; 539 int tx_l4_csum_offload = false; 540 int ret, tc_index; 541 542 PMD_INIT_FUNC_TRACE(); 543 544 /* Rx offloads which are enabled by default */ 545 if (dev_rx_offloads_nodis & ~rx_offloads) { 546 DPAA2_PMD_INFO( 547 "Some of rx offloads enabled by default - requested 0x%" PRIx64 548 " fixed are 0x%" PRIx64, 549 rx_offloads, dev_rx_offloads_nodis); 550 } 551 552 /* Tx offloads which are enabled by default */ 553 if (dev_tx_offloads_nodis & ~tx_offloads) { 554 DPAA2_PMD_INFO( 555 "Some of tx offloads enabled by default - requested 0x%" PRIx64 556 " fixed are 0x%" PRIx64, 557 tx_offloads, dev_tx_offloads_nodis); 558 } 559 560 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 561 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 562 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 563 priv->token, eth_conf->rxmode.max_rx_pkt_len 564 - RTE_ETHER_CRC_LEN); 565 if (ret) { 566 DPAA2_PMD_ERR( 567 "Unable to set mtu. check config"); 568 return ret; 569 } 570 dev->data->mtu = 571 dev->data->dev_conf.rxmode.max_rx_pkt_len - 572 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - 573 VLAN_TAG_SIZE; 574 } else { 575 return -1; 576 } 577 } 578 579 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 580 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 581 ret = dpaa2_setup_flow_dist(dev, 582 eth_conf->rx_adv_conf.rss_conf.rss_hf, 583 tc_index); 584 if (ret) { 585 DPAA2_PMD_ERR( 586 "Unable to set flow distribution on tc%d." 587 "Check queue config", tc_index); 588 return ret; 589 } 590 } 591 } 592 593 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 594 rx_l3_csum_offload = true; 595 596 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 597 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM) || 598 (rx_offloads & DEV_RX_OFFLOAD_SCTP_CKSUM)) 599 rx_l4_csum_offload = true; 600 601 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 602 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 603 if (ret) { 604 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 605 return ret; 606 } 607 608 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 609 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 610 if (ret) { 611 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 612 return ret; 613 } 614 615 #if !defined(RTE_LIBRTE_IEEE1588) 616 if (rx_offloads & DEV_RX_OFFLOAD_TIMESTAMP) 617 #endif 618 { 619 ret = rte_mbuf_dyn_rx_timestamp_register( 620 &dpaa2_timestamp_dynfield_offset, 621 &dpaa2_timestamp_rx_dynflag); 622 if (ret != 0) { 623 DPAA2_PMD_ERR("Error to register timestamp field/flag"); 624 return -rte_errno; 625 } 626 dpaa2_enable_ts[dev->data->port_id] = true; 627 } 628 629 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 630 tx_l3_csum_offload = true; 631 632 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 633 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 634 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 635 tx_l4_csum_offload = true; 636 637 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 638 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 639 if (ret) { 640 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 641 return ret; 642 } 643 644 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 645 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 646 if (ret) { 647 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 648 return ret; 649 } 650 651 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 652 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 653 * to 0 for LS2 in the hardware thus disabling data/annotation 654 * stashing. For LX2 this is fixed in hardware and thus hash result and 655 * parse results can be received in FD using this option. 656 */ 657 if (dpaa2_svr_family == SVR_LX2160A) { 658 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 659 DPNI_FLCTYPE_HASH, true); 660 if (ret) { 661 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 662 return ret; 663 } 664 } 665 666 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 667 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 668 669 dpaa2_tm_init(dev); 670 671 return 0; 672 } 673 674 /* Function to setup RX flow information. It contains traffic class ID, 675 * flow ID, destination configuration etc. 676 */ 677 static int 678 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 679 uint16_t rx_queue_id, 680 uint16_t nb_rx_desc, 681 unsigned int socket_id __rte_unused, 682 const struct rte_eth_rxconf *rx_conf, 683 struct rte_mempool *mb_pool) 684 { 685 struct dpaa2_dev_priv *priv = dev->data->dev_private; 686 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 687 struct dpaa2_queue *dpaa2_q; 688 struct dpni_queue cfg; 689 uint8_t options = 0; 690 uint8_t flow_id; 691 uint32_t bpid; 692 int i, ret; 693 694 PMD_INIT_FUNC_TRACE(); 695 696 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 697 dev, rx_queue_id, mb_pool, rx_conf); 698 699 /* Rx deferred start is not supported */ 700 if (rx_conf->rx_deferred_start) { 701 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 702 (void *)dev); 703 return -EINVAL; 704 } 705 706 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 707 bpid = mempool_to_bpid(mb_pool); 708 ret = dpaa2_attach_bp_list(priv, 709 rte_dpaa2_bpid_info[bpid].bp_list); 710 if (ret) 711 return ret; 712 } 713 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 714 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 715 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 716 dpaa2_q->nb_desc = UINT16_MAX; 717 dpaa2_q->offloads = rx_conf->offloads; 718 719 /*Get the flow id from given VQ id*/ 720 flow_id = dpaa2_q->flow_id; 721 memset(&cfg, 0, sizeof(struct dpni_queue)); 722 723 options = options | DPNI_QUEUE_OPT_USER_CTX; 724 cfg.user_context = (size_t)(dpaa2_q); 725 726 /* check if a private cgr available. */ 727 for (i = 0; i < priv->max_cgs; i++) { 728 if (!priv->cgid_in_use[i]) { 729 priv->cgid_in_use[i] = 1; 730 break; 731 } 732 } 733 734 if (i < priv->max_cgs) { 735 options |= DPNI_QUEUE_OPT_SET_CGID; 736 cfg.cgid = i; 737 dpaa2_q->cgid = cfg.cgid; 738 } else { 739 dpaa2_q->cgid = 0xff; 740 } 741 742 /*if ls2088 or rev2 device, enable the stashing */ 743 744 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 745 options |= DPNI_QUEUE_OPT_FLC; 746 cfg.flc.stash_control = true; 747 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 748 /* 00 00 00 - last 6 bit represent annotation, context stashing, 749 * data stashing setting 01 01 00 (0x14) 750 * (in following order ->DS AS CS) 751 * to enable 1 line data, 1 line annotation. 752 * For LX2, this setting should be 01 00 00 (0x10) 753 */ 754 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 755 cfg.flc.value |= 0x10; 756 else 757 cfg.flc.value |= 0x14; 758 } 759 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 760 dpaa2_q->tc_index, flow_id, options, &cfg); 761 if (ret) { 762 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 763 return -1; 764 } 765 766 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 767 struct dpni_taildrop taildrop; 768 769 taildrop.enable = 1; 770 dpaa2_q->nb_desc = nb_rx_desc; 771 /* Private CGR will use tail drop length as nb_rx_desc. 772 * for rest cases we can use standard byte based tail drop. 773 * There is no HW restriction, but number of CGRs are limited, 774 * hence this restriction is placed. 775 */ 776 if (dpaa2_q->cgid != 0xff) { 777 /*enabling per rx queue congestion control */ 778 taildrop.threshold = nb_rx_desc; 779 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 780 taildrop.oal = 0; 781 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 782 rx_queue_id); 783 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 784 DPNI_CP_CONGESTION_GROUP, 785 DPNI_QUEUE_RX, 786 dpaa2_q->tc_index, 787 dpaa2_q->cgid, &taildrop); 788 } else { 789 /*enabling per rx queue congestion control */ 790 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 791 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 792 taildrop.oal = CONG_RX_OAL; 793 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 794 rx_queue_id); 795 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 796 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 797 dpaa2_q->tc_index, flow_id, 798 &taildrop); 799 } 800 if (ret) { 801 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 802 ret); 803 return -1; 804 } 805 } else { /* Disable tail Drop */ 806 struct dpni_taildrop taildrop = {0}; 807 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 808 809 taildrop.enable = 0; 810 if (dpaa2_q->cgid != 0xff) { 811 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 812 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 813 dpaa2_q->tc_index, 814 dpaa2_q->cgid, &taildrop); 815 } else { 816 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 817 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 818 dpaa2_q->tc_index, flow_id, &taildrop); 819 } 820 if (ret) { 821 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 822 ret); 823 return -1; 824 } 825 } 826 827 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 828 return 0; 829 } 830 831 static int 832 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 833 uint16_t tx_queue_id, 834 uint16_t nb_tx_desc, 835 unsigned int socket_id __rte_unused, 836 const struct rte_eth_txconf *tx_conf) 837 { 838 struct dpaa2_dev_priv *priv = dev->data->dev_private; 839 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 840 priv->tx_vq[tx_queue_id]; 841 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 842 priv->tx_conf_vq[tx_queue_id]; 843 struct fsl_mc_io *dpni = dev->process_private; 844 struct dpni_queue tx_conf_cfg; 845 struct dpni_queue tx_flow_cfg; 846 uint8_t options = 0, flow_id; 847 struct dpni_queue_id qid; 848 uint32_t tc_id; 849 int ret; 850 851 PMD_INIT_FUNC_TRACE(); 852 853 /* Tx deferred start is not supported */ 854 if (tx_conf->tx_deferred_start) { 855 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 856 (void *)dev); 857 return -EINVAL; 858 } 859 860 dpaa2_q->nb_desc = UINT16_MAX; 861 dpaa2_q->offloads = tx_conf->offloads; 862 863 /* Return if queue already configured */ 864 if (dpaa2_q->flow_id != 0xffff) { 865 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 866 return 0; 867 } 868 869 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 870 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 871 872 tc_id = tx_queue_id; 873 flow_id = 0; 874 875 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 876 tc_id, flow_id, options, &tx_flow_cfg); 877 if (ret) { 878 DPAA2_PMD_ERR("Error in setting the tx flow: " 879 "tc_id=%d, flow=%d err=%d", 880 tc_id, flow_id, ret); 881 return -1; 882 } 883 884 dpaa2_q->flow_id = flow_id; 885 886 if (tx_queue_id == 0) { 887 /*Set tx-conf and error configuration*/ 888 if (priv->flags & DPAA2_TX_CONF_ENABLE) 889 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 890 priv->token, 891 DPNI_CONF_AFFINE); 892 else 893 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 894 priv->token, 895 DPNI_CONF_DISABLE); 896 if (ret) { 897 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 898 "err=%d", ret); 899 return -1; 900 } 901 } 902 dpaa2_q->tc_index = tc_id; 903 904 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 905 DPNI_QUEUE_TX, dpaa2_q->tc_index, 906 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 907 if (ret) { 908 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 909 return -1; 910 } 911 dpaa2_q->fqid = qid.fqid; 912 913 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 914 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 915 916 dpaa2_q->nb_desc = nb_tx_desc; 917 918 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 919 cong_notif_cfg.threshold_entry = nb_tx_desc; 920 /* Notify that the queue is not congested when the data in 921 * the queue is below this thershold.(90% of value) 922 */ 923 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; 924 cong_notif_cfg.message_ctx = 0; 925 cong_notif_cfg.message_iova = 926 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 927 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 928 cong_notif_cfg.notification_mode = 929 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 930 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 931 DPNI_CONG_OPT_COHERENT_WRITE; 932 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 933 934 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 935 priv->token, 936 DPNI_QUEUE_TX, 937 tc_id, 938 &cong_notif_cfg); 939 if (ret) { 940 DPAA2_PMD_ERR( 941 "Error in setting tx congestion notification: " 942 "err=%d", ret); 943 return -ret; 944 } 945 } 946 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 947 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 948 949 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 950 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 951 options = options | DPNI_QUEUE_OPT_USER_CTX; 952 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 953 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 954 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 955 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 956 if (ret) { 957 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 958 "tc_index=%d, flow=%d err=%d", 959 dpaa2_tx_conf_q->tc_index, 960 dpaa2_tx_conf_q->flow_id, ret); 961 return -1; 962 } 963 964 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 965 DPNI_QUEUE_TX_CONFIRM, dpaa2_tx_conf_q->tc_index, 966 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 967 if (ret) { 968 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 969 return -1; 970 } 971 dpaa2_tx_conf_q->fqid = qid.fqid; 972 } 973 return 0; 974 } 975 976 static void 977 dpaa2_dev_rx_queue_release(void *q __rte_unused) 978 { 979 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *)q; 980 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 981 struct fsl_mc_io *dpni = 982 (struct fsl_mc_io *)priv->eth_dev->process_private; 983 uint8_t options = 0; 984 int ret; 985 struct dpni_queue cfg; 986 987 memset(&cfg, 0, sizeof(struct dpni_queue)); 988 PMD_INIT_FUNC_TRACE(); 989 if (dpaa2_q->cgid != 0xff) { 990 options = DPNI_QUEUE_OPT_CLEAR_CGID; 991 cfg.cgid = dpaa2_q->cgid; 992 993 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 994 DPNI_QUEUE_RX, 995 dpaa2_q->tc_index, dpaa2_q->flow_id, 996 options, &cfg); 997 if (ret) 998 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 999 dpaa2_q->fqid, ret); 1000 priv->cgid_in_use[dpaa2_q->cgid] = 0; 1001 dpaa2_q->cgid = 0xff; 1002 } 1003 } 1004 1005 static void 1006 dpaa2_dev_tx_queue_release(void *q __rte_unused) 1007 { 1008 PMD_INIT_FUNC_TRACE(); 1009 } 1010 1011 static uint32_t 1012 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1013 { 1014 int32_t ret; 1015 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1016 struct dpaa2_queue *dpaa2_q; 1017 struct qbman_swp *swp; 1018 struct qbman_fq_query_np_rslt state; 1019 uint32_t frame_cnt = 0; 1020 1021 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 1022 ret = dpaa2_affine_qbman_swp(); 1023 if (ret) { 1024 DPAA2_PMD_ERR( 1025 "Failed to allocate IO portal, tid: %d\n", 1026 rte_gettid()); 1027 return -EINVAL; 1028 } 1029 } 1030 swp = DPAA2_PER_LCORE_PORTAL; 1031 1032 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 1033 1034 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 1035 frame_cnt = qbman_fq_state_frame_count(&state); 1036 DPAA2_PMD_DP_DEBUG("RX frame count for q(%d) is %u", 1037 rx_queue_id, frame_cnt); 1038 } 1039 return frame_cnt; 1040 } 1041 1042 static const uint32_t * 1043 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 1044 { 1045 static const uint32_t ptypes[] = { 1046 /*todo -= add more types */ 1047 RTE_PTYPE_L2_ETHER, 1048 RTE_PTYPE_L3_IPV4, 1049 RTE_PTYPE_L3_IPV4_EXT, 1050 RTE_PTYPE_L3_IPV6, 1051 RTE_PTYPE_L3_IPV6_EXT, 1052 RTE_PTYPE_L4_TCP, 1053 RTE_PTYPE_L4_UDP, 1054 RTE_PTYPE_L4_SCTP, 1055 RTE_PTYPE_L4_ICMP, 1056 RTE_PTYPE_UNKNOWN 1057 }; 1058 1059 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1060 dev->rx_pkt_burst == dpaa2_dev_rx || 1061 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 1062 return ptypes; 1063 return NULL; 1064 } 1065 1066 /** 1067 * Dpaa2 link Interrupt handler 1068 * 1069 * @param param 1070 * The address of parameter (struct rte_eth_dev *) regsitered before. 1071 * 1072 * @return 1073 * void 1074 */ 1075 static void 1076 dpaa2_interrupt_handler(void *param) 1077 { 1078 struct rte_eth_dev *dev = param; 1079 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1080 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1081 int ret; 1082 int irq_index = DPNI_IRQ_INDEX; 1083 unsigned int status = 0, clear = 0; 1084 1085 PMD_INIT_FUNC_TRACE(); 1086 1087 if (dpni == NULL) { 1088 DPAA2_PMD_ERR("dpni is NULL"); 1089 return; 1090 } 1091 1092 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1093 irq_index, &status); 1094 if (unlikely(ret)) { 1095 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1096 clear = 0xffffffff; 1097 goto out; 1098 } 1099 1100 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1101 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1102 dpaa2_dev_link_update(dev, 0); 1103 /* calling all the apps registered for link status event */ 1104 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1105 } 1106 out: 1107 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1108 irq_index, clear); 1109 if (unlikely(ret)) 1110 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1111 } 1112 1113 static int 1114 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1115 { 1116 int err = 0; 1117 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1118 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1119 int irq_index = DPNI_IRQ_INDEX; 1120 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1121 1122 PMD_INIT_FUNC_TRACE(); 1123 1124 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1125 irq_index, mask); 1126 if (err < 0) { 1127 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1128 strerror(-err)); 1129 return err; 1130 } 1131 1132 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1133 irq_index, enable); 1134 if (err < 0) 1135 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1136 strerror(-err)); 1137 1138 return err; 1139 } 1140 1141 static int 1142 dpaa2_dev_start(struct rte_eth_dev *dev) 1143 { 1144 struct rte_device *rdev = dev->device; 1145 struct rte_dpaa2_device *dpaa2_dev; 1146 struct rte_eth_dev_data *data = dev->data; 1147 struct dpaa2_dev_priv *priv = data->dev_private; 1148 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1149 struct dpni_queue cfg; 1150 struct dpni_error_cfg err_cfg; 1151 uint16_t qdid; 1152 struct dpni_queue_id qid; 1153 struct dpaa2_queue *dpaa2_q; 1154 int ret, i; 1155 struct rte_intr_handle *intr_handle; 1156 1157 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1158 intr_handle = &dpaa2_dev->intr_handle; 1159 1160 PMD_INIT_FUNC_TRACE(); 1161 1162 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1163 if (ret) { 1164 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1165 priv->hw_id, ret); 1166 return ret; 1167 } 1168 1169 /* Power up the phy. Needed to make the link go UP */ 1170 dpaa2_dev_set_link_up(dev); 1171 1172 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 1173 DPNI_QUEUE_TX, &qdid); 1174 if (ret) { 1175 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 1176 return ret; 1177 } 1178 priv->qdid = qdid; 1179 1180 for (i = 0; i < data->nb_rx_queues; i++) { 1181 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1182 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1183 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1184 dpaa2_q->flow_id, &cfg, &qid); 1185 if (ret) { 1186 DPAA2_PMD_ERR("Error in getting flow information: " 1187 "err=%d", ret); 1188 return ret; 1189 } 1190 dpaa2_q->fqid = qid.fqid; 1191 } 1192 1193 if (dpaa2_enable_err_queue) { 1194 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1195 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); 1196 if (ret) { 1197 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", 1198 ret); 1199 return ret; 1200 } 1201 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 1202 dpaa2_q->fqid = qid.fqid; 1203 dpaa2_q->eth_data = dev->data; 1204 1205 err_cfg.errors = DPNI_ERROR_DISC; 1206 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; 1207 } else { 1208 /* checksum errors, send them to normal path 1209 * and set it in annotation 1210 */ 1211 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1212 1213 /* if packet with parse error are not to be dropped */ 1214 err_cfg.errors |= DPNI_ERROR_PHE; 1215 1216 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1217 } 1218 err_cfg.set_frame_annotation = true; 1219 1220 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1221 priv->token, &err_cfg); 1222 if (ret) { 1223 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1224 ret); 1225 return ret; 1226 } 1227 1228 /* if the interrupts were configured on this devices*/ 1229 if (intr_handle && (intr_handle->fd) && 1230 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1231 /* Registering LSC interrupt handler */ 1232 rte_intr_callback_register(intr_handle, 1233 dpaa2_interrupt_handler, 1234 (void *)dev); 1235 1236 /* enable vfio intr/eventfd mapping 1237 * Interrupt index 0 is required, so we can not use 1238 * rte_intr_enable. 1239 */ 1240 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1241 1242 /* enable dpni_irqs */ 1243 dpaa2_eth_setup_irqs(dev, 1); 1244 } 1245 1246 /* Change the tx burst function if ordered queues are used */ 1247 if (priv->en_ordered) 1248 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1249 1250 return 0; 1251 } 1252 1253 /** 1254 * This routine disables all traffic on the adapter by issuing a 1255 * global reset on the MAC. 1256 */ 1257 static int 1258 dpaa2_dev_stop(struct rte_eth_dev *dev) 1259 { 1260 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1261 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1262 int ret; 1263 struct rte_eth_link link; 1264 struct rte_intr_handle *intr_handle = dev->intr_handle; 1265 1266 PMD_INIT_FUNC_TRACE(); 1267 1268 /* reset interrupt callback */ 1269 if (intr_handle && (intr_handle->fd) && 1270 (dev->data->dev_conf.intr_conf.lsc != 0)) { 1271 /*disable dpni irqs */ 1272 dpaa2_eth_setup_irqs(dev, 0); 1273 1274 /* disable vfio intr before callback unregister */ 1275 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1276 1277 /* Unregistering LSC interrupt handler */ 1278 rte_intr_callback_unregister(intr_handle, 1279 dpaa2_interrupt_handler, 1280 (void *)dev); 1281 } 1282 1283 dpaa2_dev_set_link_down(dev); 1284 1285 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1286 if (ret) { 1287 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1288 ret, priv->hw_id); 1289 return ret; 1290 } 1291 1292 /* clear the recorded link status */ 1293 memset(&link, 0, sizeof(link)); 1294 rte_eth_linkstatus_set(dev, &link); 1295 1296 return 0; 1297 } 1298 1299 static int 1300 dpaa2_dev_close(struct rte_eth_dev *dev) 1301 { 1302 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1303 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1304 int i, ret; 1305 struct rte_eth_link link; 1306 1307 PMD_INIT_FUNC_TRACE(); 1308 1309 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1310 return 0; 1311 1312 if (!dpni) { 1313 DPAA2_PMD_WARN("Already closed or not started"); 1314 return -1; 1315 } 1316 1317 dpaa2_tm_deinit(dev); 1318 dpaa2_flow_clean(dev); 1319 /* Clean the device first */ 1320 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1321 if (ret) { 1322 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1323 return -1; 1324 } 1325 1326 memset(&link, 0, sizeof(link)); 1327 rte_eth_linkstatus_set(dev, &link); 1328 1329 /* Free private queues memory */ 1330 dpaa2_free_rx_tx_queues(dev); 1331 /* Close the device at underlying layer*/ 1332 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1333 if (ret) { 1334 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1335 ret); 1336 } 1337 1338 /* Free the allocated memory for ethernet private data and dpni*/ 1339 priv->hw = NULL; 1340 dev->process_private = NULL; 1341 rte_free(dpni); 1342 1343 for (i = 0; i < MAX_TCS; i++) 1344 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1345 1346 if (priv->extract.qos_extract_param) 1347 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1348 1349 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1350 return 0; 1351 } 1352 1353 static int 1354 dpaa2_dev_promiscuous_enable( 1355 struct rte_eth_dev *dev) 1356 { 1357 int ret; 1358 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1359 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1360 1361 PMD_INIT_FUNC_TRACE(); 1362 1363 if (dpni == NULL) { 1364 DPAA2_PMD_ERR("dpni is NULL"); 1365 return -ENODEV; 1366 } 1367 1368 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1369 if (ret < 0) 1370 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1371 1372 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1373 if (ret < 0) 1374 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1375 1376 return ret; 1377 } 1378 1379 static int 1380 dpaa2_dev_promiscuous_disable( 1381 struct rte_eth_dev *dev) 1382 { 1383 int ret; 1384 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1385 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1386 1387 PMD_INIT_FUNC_TRACE(); 1388 1389 if (dpni == NULL) { 1390 DPAA2_PMD_ERR("dpni is NULL"); 1391 return -ENODEV; 1392 } 1393 1394 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1395 if (ret < 0) 1396 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1397 1398 if (dev->data->all_multicast == 0) { 1399 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1400 priv->token, false); 1401 if (ret < 0) 1402 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1403 ret); 1404 } 1405 1406 return ret; 1407 } 1408 1409 static int 1410 dpaa2_dev_allmulticast_enable( 1411 struct rte_eth_dev *dev) 1412 { 1413 int ret; 1414 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1415 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1416 1417 PMD_INIT_FUNC_TRACE(); 1418 1419 if (dpni == NULL) { 1420 DPAA2_PMD_ERR("dpni is NULL"); 1421 return -ENODEV; 1422 } 1423 1424 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1425 if (ret < 0) 1426 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1427 1428 return ret; 1429 } 1430 1431 static int 1432 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1433 { 1434 int ret; 1435 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1436 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1437 1438 PMD_INIT_FUNC_TRACE(); 1439 1440 if (dpni == NULL) { 1441 DPAA2_PMD_ERR("dpni is NULL"); 1442 return -ENODEV; 1443 } 1444 1445 /* must remain on for all promiscuous */ 1446 if (dev->data->promiscuous == 1) 1447 return 0; 1448 1449 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1450 if (ret < 0) 1451 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1452 1453 return ret; 1454 } 1455 1456 static int 1457 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1458 { 1459 int ret; 1460 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1461 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1462 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1463 + VLAN_TAG_SIZE; 1464 1465 PMD_INIT_FUNC_TRACE(); 1466 1467 if (dpni == NULL) { 1468 DPAA2_PMD_ERR("dpni is NULL"); 1469 return -EINVAL; 1470 } 1471 1472 /* check that mtu is within the allowed range */ 1473 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1474 return -EINVAL; 1475 1476 if (frame_size > DPAA2_ETH_MAX_LEN) 1477 dev->data->dev_conf.rxmode.offloads |= 1478 DEV_RX_OFFLOAD_JUMBO_FRAME; 1479 else 1480 dev->data->dev_conf.rxmode.offloads &= 1481 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1482 1483 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1484 1485 /* Set the Max Rx frame length as 'mtu' + 1486 * Maximum Ethernet header length 1487 */ 1488 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1489 frame_size - RTE_ETHER_CRC_LEN); 1490 if (ret) { 1491 DPAA2_PMD_ERR("Setting the max frame length failed"); 1492 return -1; 1493 } 1494 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1495 return 0; 1496 } 1497 1498 static int 1499 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1500 struct rte_ether_addr *addr, 1501 __rte_unused uint32_t index, 1502 __rte_unused uint32_t pool) 1503 { 1504 int ret; 1505 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1506 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1507 1508 PMD_INIT_FUNC_TRACE(); 1509 1510 if (dpni == NULL) { 1511 DPAA2_PMD_ERR("dpni is NULL"); 1512 return -1; 1513 } 1514 1515 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1516 addr->addr_bytes, 0, 0, 0); 1517 if (ret) 1518 DPAA2_PMD_ERR( 1519 "error: Adding the MAC ADDR failed: err = %d", ret); 1520 return 0; 1521 } 1522 1523 static void 1524 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1525 uint32_t index) 1526 { 1527 int ret; 1528 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1529 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1530 struct rte_eth_dev_data *data = dev->data; 1531 struct rte_ether_addr *macaddr; 1532 1533 PMD_INIT_FUNC_TRACE(); 1534 1535 macaddr = &data->mac_addrs[index]; 1536 1537 if (dpni == NULL) { 1538 DPAA2_PMD_ERR("dpni is NULL"); 1539 return; 1540 } 1541 1542 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1543 priv->token, macaddr->addr_bytes); 1544 if (ret) 1545 DPAA2_PMD_ERR( 1546 "error: Removing the MAC ADDR failed: err = %d", ret); 1547 } 1548 1549 static int 1550 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1551 struct rte_ether_addr *addr) 1552 { 1553 int ret; 1554 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1555 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1556 1557 PMD_INIT_FUNC_TRACE(); 1558 1559 if (dpni == NULL) { 1560 DPAA2_PMD_ERR("dpni is NULL"); 1561 return -EINVAL; 1562 } 1563 1564 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1565 priv->token, addr->addr_bytes); 1566 1567 if (ret) 1568 DPAA2_PMD_ERR( 1569 "error: Setting the MAC ADDR failed %d", ret); 1570 1571 return ret; 1572 } 1573 1574 static 1575 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1576 struct rte_eth_stats *stats) 1577 { 1578 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1579 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1580 int32_t retcode; 1581 uint8_t page0 = 0, page1 = 1, page2 = 2; 1582 union dpni_statistics value; 1583 int i; 1584 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1585 1586 memset(&value, 0, sizeof(union dpni_statistics)); 1587 1588 PMD_INIT_FUNC_TRACE(); 1589 1590 if (!dpni) { 1591 DPAA2_PMD_ERR("dpni is NULL"); 1592 return -EINVAL; 1593 } 1594 1595 if (!stats) { 1596 DPAA2_PMD_ERR("stats is NULL"); 1597 return -EINVAL; 1598 } 1599 1600 /*Get Counters from page_0*/ 1601 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1602 page0, 0, &value); 1603 if (retcode) 1604 goto err; 1605 1606 stats->ipackets = value.page_0.ingress_all_frames; 1607 stats->ibytes = value.page_0.ingress_all_bytes; 1608 1609 /*Get Counters from page_1*/ 1610 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1611 page1, 0, &value); 1612 if (retcode) 1613 goto err; 1614 1615 stats->opackets = value.page_1.egress_all_frames; 1616 stats->obytes = value.page_1.egress_all_bytes; 1617 1618 /*Get Counters from page_2*/ 1619 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1620 page2, 0, &value); 1621 if (retcode) 1622 goto err; 1623 1624 /* Ingress drop frame count due to configured rules */ 1625 stats->ierrors = value.page_2.ingress_filtered_frames; 1626 /* Ingress drop frame count due to error */ 1627 stats->ierrors += value.page_2.ingress_discarded_frames; 1628 1629 stats->oerrors = value.page_2.egress_discarded_frames; 1630 stats->imissed = value.page_2.ingress_nobuffer_discards; 1631 1632 /* Fill in per queue stats */ 1633 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1634 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1635 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1636 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1637 if (dpaa2_rxq) 1638 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1639 if (dpaa2_txq) 1640 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1641 1642 /* Byte counting is not implemented */ 1643 stats->q_ibytes[i] = 0; 1644 stats->q_obytes[i] = 0; 1645 } 1646 1647 return 0; 1648 1649 err: 1650 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1651 return retcode; 1652 }; 1653 1654 static int 1655 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1656 unsigned int n) 1657 { 1658 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1659 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1660 int32_t retcode; 1661 union dpni_statistics value[5] = {}; 1662 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1663 1664 if (n < num) 1665 return num; 1666 1667 if (xstats == NULL) 1668 return 0; 1669 1670 /* Get Counters from page_0*/ 1671 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1672 0, 0, &value[0]); 1673 if (retcode) 1674 goto err; 1675 1676 /* Get Counters from page_1*/ 1677 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1678 1, 0, &value[1]); 1679 if (retcode) 1680 goto err; 1681 1682 /* Get Counters from page_2*/ 1683 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1684 2, 0, &value[2]); 1685 if (retcode) 1686 goto err; 1687 1688 for (i = 0; i < priv->max_cgs; i++) { 1689 if (!priv->cgid_in_use[i]) { 1690 /* Get Counters from page_4*/ 1691 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1692 priv->token, 1693 4, 0, &value[4]); 1694 if (retcode) 1695 goto err; 1696 break; 1697 } 1698 } 1699 1700 for (i = 0; i < num; i++) { 1701 xstats[i].id = i; 1702 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1703 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1704 } 1705 return i; 1706 err: 1707 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1708 return retcode; 1709 } 1710 1711 static int 1712 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1713 struct rte_eth_xstat_name *xstats_names, 1714 unsigned int limit) 1715 { 1716 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1717 1718 if (limit < stat_cnt) 1719 return stat_cnt; 1720 1721 if (xstats_names != NULL) 1722 for (i = 0; i < stat_cnt; i++) 1723 strlcpy(xstats_names[i].name, 1724 dpaa2_xstats_strings[i].name, 1725 sizeof(xstats_names[i].name)); 1726 1727 return stat_cnt; 1728 } 1729 1730 static int 1731 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1732 uint64_t *values, unsigned int n) 1733 { 1734 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1735 uint64_t values_copy[stat_cnt]; 1736 1737 if (!ids) { 1738 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1739 struct fsl_mc_io *dpni = 1740 (struct fsl_mc_io *)dev->process_private; 1741 int32_t retcode; 1742 union dpni_statistics value[5] = {}; 1743 1744 if (n < stat_cnt) 1745 return stat_cnt; 1746 1747 if (!values) 1748 return 0; 1749 1750 /* Get Counters from page_0*/ 1751 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1752 0, 0, &value[0]); 1753 if (retcode) 1754 return 0; 1755 1756 /* Get Counters from page_1*/ 1757 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1758 1, 0, &value[1]); 1759 if (retcode) 1760 return 0; 1761 1762 /* Get Counters from page_2*/ 1763 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1764 2, 0, &value[2]); 1765 if (retcode) 1766 return 0; 1767 1768 /* Get Counters from page_4*/ 1769 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1770 4, 0, &value[4]); 1771 if (retcode) 1772 return 0; 1773 1774 for (i = 0; i < stat_cnt; i++) { 1775 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1776 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1777 } 1778 return stat_cnt; 1779 } 1780 1781 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1782 1783 for (i = 0; i < n; i++) { 1784 if (ids[i] >= stat_cnt) { 1785 DPAA2_PMD_ERR("xstats id value isn't valid"); 1786 return -1; 1787 } 1788 values[i] = values_copy[ids[i]]; 1789 } 1790 return n; 1791 } 1792 1793 static int 1794 dpaa2_xstats_get_names_by_id( 1795 struct rte_eth_dev *dev, 1796 struct rte_eth_xstat_name *xstats_names, 1797 const uint64_t *ids, 1798 unsigned int limit) 1799 { 1800 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1801 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1802 1803 if (!ids) 1804 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1805 1806 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1807 1808 for (i = 0; i < limit; i++) { 1809 if (ids[i] >= stat_cnt) { 1810 DPAA2_PMD_ERR("xstats id value isn't valid"); 1811 return -1; 1812 } 1813 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1814 } 1815 return limit; 1816 } 1817 1818 static int 1819 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1820 { 1821 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1822 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1823 int retcode; 1824 int i; 1825 struct dpaa2_queue *dpaa2_q; 1826 1827 PMD_INIT_FUNC_TRACE(); 1828 1829 if (dpni == NULL) { 1830 DPAA2_PMD_ERR("dpni is NULL"); 1831 return -EINVAL; 1832 } 1833 1834 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1835 if (retcode) 1836 goto error; 1837 1838 /* Reset the per queue stats in dpaa2_queue structure */ 1839 for (i = 0; i < priv->nb_rx_queues; i++) { 1840 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1841 if (dpaa2_q) 1842 dpaa2_q->rx_pkts = 0; 1843 } 1844 1845 for (i = 0; i < priv->nb_tx_queues; i++) { 1846 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1847 if (dpaa2_q) 1848 dpaa2_q->tx_pkts = 0; 1849 } 1850 1851 return 0; 1852 1853 error: 1854 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1855 return retcode; 1856 }; 1857 1858 /* return 0 means link status changed, -1 means not changed */ 1859 static int 1860 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1861 int wait_to_complete) 1862 { 1863 int ret; 1864 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1865 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1866 struct rte_eth_link link; 1867 struct dpni_link_state state = {0}; 1868 uint8_t count; 1869 1870 if (dpni == NULL) { 1871 DPAA2_PMD_ERR("dpni is NULL"); 1872 return 0; 1873 } 1874 1875 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 1876 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, 1877 &state); 1878 if (ret < 0) { 1879 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1880 return -1; 1881 } 1882 if (state.up == ETH_LINK_DOWN && 1883 wait_to_complete) 1884 rte_delay_ms(CHECK_INTERVAL); 1885 else 1886 break; 1887 } 1888 1889 memset(&link, 0, sizeof(struct rte_eth_link)); 1890 link.link_status = state.up; 1891 link.link_speed = state.rate; 1892 1893 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1894 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1895 else 1896 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1897 1898 ret = rte_eth_linkstatus_set(dev, &link); 1899 if (ret == -1) 1900 DPAA2_PMD_DEBUG("No change in status"); 1901 else 1902 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1903 link.link_status ? "Up" : "Down"); 1904 1905 return ret; 1906 } 1907 1908 /** 1909 * Toggle the DPNI to enable, if not already enabled. 1910 * This is not strictly PHY up/down - it is more of logical toggling. 1911 */ 1912 static int 1913 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1914 { 1915 int ret = -EINVAL; 1916 struct dpaa2_dev_priv *priv; 1917 struct fsl_mc_io *dpni; 1918 int en = 0; 1919 struct dpni_link_state state = {0}; 1920 1921 priv = dev->data->dev_private; 1922 dpni = (struct fsl_mc_io *)dev->process_private; 1923 1924 if (dpni == NULL) { 1925 DPAA2_PMD_ERR("dpni is NULL"); 1926 return ret; 1927 } 1928 1929 /* Check if DPNI is currently enabled */ 1930 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1931 if (ret) { 1932 /* Unable to obtain dpni status; Not continuing */ 1933 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1934 return -EINVAL; 1935 } 1936 1937 /* Enable link if not already enabled */ 1938 if (!en) { 1939 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1940 if (ret) { 1941 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1942 return -EINVAL; 1943 } 1944 } 1945 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1946 if (ret < 0) { 1947 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1948 return -1; 1949 } 1950 1951 /* changing tx burst function to start enqueues */ 1952 dev->tx_pkt_burst = dpaa2_dev_tx; 1953 dev->data->dev_link.link_status = state.up; 1954 dev->data->dev_link.link_speed = state.rate; 1955 1956 if (state.up) 1957 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1958 else 1959 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1960 return ret; 1961 } 1962 1963 /** 1964 * Toggle the DPNI to disable, if not already disabled. 1965 * This is not strictly PHY up/down - it is more of logical toggling. 1966 */ 1967 static int 1968 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1969 { 1970 int ret = -EINVAL; 1971 struct dpaa2_dev_priv *priv; 1972 struct fsl_mc_io *dpni; 1973 int dpni_enabled = 0; 1974 int retries = 10; 1975 1976 PMD_INIT_FUNC_TRACE(); 1977 1978 priv = dev->data->dev_private; 1979 dpni = (struct fsl_mc_io *)dev->process_private; 1980 1981 if (dpni == NULL) { 1982 DPAA2_PMD_ERR("Device has not yet been configured"); 1983 return ret; 1984 } 1985 1986 /*changing tx burst function to avoid any more enqueues */ 1987 dev->tx_pkt_burst = dummy_dev_tx; 1988 1989 /* Loop while dpni_disable() attempts to drain the egress FQs 1990 * and confirm them back to us. 1991 */ 1992 do { 1993 ret = dpni_disable(dpni, 0, priv->token); 1994 if (ret) { 1995 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1996 return ret; 1997 } 1998 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1999 if (ret) { 2000 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 2001 return ret; 2002 } 2003 if (dpni_enabled) 2004 /* Allow the MC some slack */ 2005 rte_delay_us(100 * 1000); 2006 } while (dpni_enabled && --retries); 2007 2008 if (!retries) { 2009 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 2010 /* todo- we may have to manually cleanup queues. 2011 */ 2012 } else { 2013 DPAA2_PMD_INFO("Port %d Link DOWN successful", 2014 dev->data->port_id); 2015 } 2016 2017 dev->data->dev_link.link_status = 0; 2018 2019 return ret; 2020 } 2021 2022 static int 2023 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2024 { 2025 int ret = -EINVAL; 2026 struct dpaa2_dev_priv *priv; 2027 struct fsl_mc_io *dpni; 2028 struct dpni_link_state state = {0}; 2029 2030 PMD_INIT_FUNC_TRACE(); 2031 2032 priv = dev->data->dev_private; 2033 dpni = (struct fsl_mc_io *)dev->process_private; 2034 2035 if (dpni == NULL || fc_conf == NULL) { 2036 DPAA2_PMD_ERR("device not configured"); 2037 return ret; 2038 } 2039 2040 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2041 if (ret) { 2042 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 2043 return ret; 2044 } 2045 2046 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 2047 if (state.options & DPNI_LINK_OPT_PAUSE) { 2048 /* DPNI_LINK_OPT_PAUSE set 2049 * if ASYM_PAUSE not set, 2050 * RX Side flow control (handle received Pause frame) 2051 * TX side flow control (send Pause frame) 2052 * if ASYM_PAUSE set, 2053 * RX Side flow control (handle received Pause frame) 2054 * No TX side flow control (send Pause frame disabled) 2055 */ 2056 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 2057 fc_conf->mode = RTE_FC_FULL; 2058 else 2059 fc_conf->mode = RTE_FC_RX_PAUSE; 2060 } else { 2061 /* DPNI_LINK_OPT_PAUSE not set 2062 * if ASYM_PAUSE set, 2063 * TX side flow control (send Pause frame) 2064 * No RX side flow control (No action on pause frame rx) 2065 * if ASYM_PAUSE not set, 2066 * Flow control disabled 2067 */ 2068 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 2069 fc_conf->mode = RTE_FC_TX_PAUSE; 2070 else 2071 fc_conf->mode = RTE_FC_NONE; 2072 } 2073 2074 return ret; 2075 } 2076 2077 static int 2078 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2079 { 2080 int ret = -EINVAL; 2081 struct dpaa2_dev_priv *priv; 2082 struct fsl_mc_io *dpni; 2083 struct dpni_link_state state = {0}; 2084 struct dpni_link_cfg cfg = {0}; 2085 2086 PMD_INIT_FUNC_TRACE(); 2087 2088 priv = dev->data->dev_private; 2089 dpni = (struct fsl_mc_io *)dev->process_private; 2090 2091 if (dpni == NULL) { 2092 DPAA2_PMD_ERR("dpni is NULL"); 2093 return ret; 2094 } 2095 2096 /* It is necessary to obtain the current state before setting fc_conf 2097 * as MC would return error in case rate, autoneg or duplex values are 2098 * different. 2099 */ 2100 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2101 if (ret) { 2102 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2103 return -1; 2104 } 2105 2106 /* Disable link before setting configuration */ 2107 dpaa2_dev_set_link_down(dev); 2108 2109 /* Based on fc_conf, update cfg */ 2110 cfg.rate = state.rate; 2111 cfg.options = state.options; 2112 2113 /* update cfg with fc_conf */ 2114 switch (fc_conf->mode) { 2115 case RTE_FC_FULL: 2116 /* Full flow control; 2117 * OPT_PAUSE set, ASYM_PAUSE not set 2118 */ 2119 cfg.options |= DPNI_LINK_OPT_PAUSE; 2120 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2121 break; 2122 case RTE_FC_TX_PAUSE: 2123 /* Enable RX flow control 2124 * OPT_PAUSE not set; 2125 * ASYM_PAUSE set; 2126 */ 2127 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2128 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2129 break; 2130 case RTE_FC_RX_PAUSE: 2131 /* Enable TX Flow control 2132 * OPT_PAUSE set 2133 * ASYM_PAUSE set 2134 */ 2135 cfg.options |= DPNI_LINK_OPT_PAUSE; 2136 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2137 break; 2138 case RTE_FC_NONE: 2139 /* Disable Flow control 2140 * OPT_PAUSE not set 2141 * ASYM_PAUSE not set 2142 */ 2143 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2144 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2145 break; 2146 default: 2147 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2148 fc_conf->mode); 2149 return -1; 2150 } 2151 2152 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2153 if (ret) 2154 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2155 ret); 2156 2157 /* Enable link */ 2158 dpaa2_dev_set_link_up(dev); 2159 2160 return ret; 2161 } 2162 2163 static int 2164 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2165 struct rte_eth_rss_conf *rss_conf) 2166 { 2167 struct rte_eth_dev_data *data = dev->data; 2168 struct dpaa2_dev_priv *priv = data->dev_private; 2169 struct rte_eth_conf *eth_conf = &data->dev_conf; 2170 int ret, tc_index; 2171 2172 PMD_INIT_FUNC_TRACE(); 2173 2174 if (rss_conf->rss_hf) { 2175 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2176 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2177 tc_index); 2178 if (ret) { 2179 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2180 tc_index); 2181 return ret; 2182 } 2183 } 2184 } else { 2185 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2186 ret = dpaa2_remove_flow_dist(dev, tc_index); 2187 if (ret) { 2188 DPAA2_PMD_ERR( 2189 "Unable to remove flow dist on tc%d", 2190 tc_index); 2191 return ret; 2192 } 2193 } 2194 } 2195 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2196 return 0; 2197 } 2198 2199 static int 2200 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2201 struct rte_eth_rss_conf *rss_conf) 2202 { 2203 struct rte_eth_dev_data *data = dev->data; 2204 struct rte_eth_conf *eth_conf = &data->dev_conf; 2205 2206 /* dpaa2 does not support rss_key, so length should be 0*/ 2207 rss_conf->rss_key_len = 0; 2208 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2209 return 0; 2210 } 2211 2212 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2213 int eth_rx_queue_id, 2214 struct dpaa2_dpcon_dev *dpcon, 2215 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2216 { 2217 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2218 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2219 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2220 uint8_t flow_id = dpaa2_ethq->flow_id; 2221 struct dpni_queue cfg; 2222 uint8_t options, priority; 2223 int ret; 2224 2225 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2226 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2227 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2228 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2229 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2230 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2231 else 2232 return -EINVAL; 2233 2234 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2235 (dpcon->num_priorities - 1); 2236 2237 memset(&cfg, 0, sizeof(struct dpni_queue)); 2238 options = DPNI_QUEUE_OPT_DEST; 2239 cfg.destination.type = DPNI_DEST_DPCON; 2240 cfg.destination.id = dpcon->dpcon_id; 2241 cfg.destination.priority = priority; 2242 2243 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2244 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2245 cfg.destination.hold_active = 1; 2246 } 2247 2248 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2249 !eth_priv->en_ordered) { 2250 struct opr_cfg ocfg; 2251 2252 /* Restoration window size = 256 frames */ 2253 ocfg.oprrws = 3; 2254 /* Restoration window size = 512 frames for LX2 */ 2255 if (dpaa2_svr_family == SVR_LX2160A) 2256 ocfg.oprrws = 4; 2257 /* Auto advance NESN window enabled */ 2258 ocfg.oa = 1; 2259 /* Late arrival window size disabled */ 2260 ocfg.olws = 0; 2261 /* ORL resource exhaustaion advance NESN disabled */ 2262 ocfg.oeane = 0; 2263 /* Loose ordering enabled */ 2264 ocfg.oloe = 1; 2265 eth_priv->en_loose_ordered = 1; 2266 /* Strict ordering enabled if explicitly set */ 2267 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2268 ocfg.oloe = 0; 2269 eth_priv->en_loose_ordered = 0; 2270 } 2271 2272 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2273 dpaa2_ethq->tc_index, flow_id, 2274 OPR_OPT_CREATE, &ocfg); 2275 if (ret) { 2276 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 2277 return ret; 2278 } 2279 2280 eth_priv->en_ordered = 1; 2281 } 2282 2283 options |= DPNI_QUEUE_OPT_USER_CTX; 2284 cfg.user_context = (size_t)(dpaa2_ethq); 2285 2286 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2287 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2288 if (ret) { 2289 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2290 return ret; 2291 } 2292 2293 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2294 2295 return 0; 2296 } 2297 2298 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2299 int eth_rx_queue_id) 2300 { 2301 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2302 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2303 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2304 uint8_t flow_id = dpaa2_ethq->flow_id; 2305 struct dpni_queue cfg; 2306 uint8_t options; 2307 int ret; 2308 2309 memset(&cfg, 0, sizeof(struct dpni_queue)); 2310 options = DPNI_QUEUE_OPT_DEST; 2311 cfg.destination.type = DPNI_DEST_NONE; 2312 2313 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2314 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2315 if (ret) 2316 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2317 2318 return ret; 2319 } 2320 2321 static int 2322 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev, 2323 const struct rte_flow_ops **ops) 2324 { 2325 if (!dev) 2326 return -ENODEV; 2327 2328 *ops = &dpaa2_flow_ops; 2329 return 0; 2330 } 2331 2332 static void 2333 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2334 struct rte_eth_rxq_info *qinfo) 2335 { 2336 struct dpaa2_queue *rxq; 2337 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2338 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2339 uint16_t max_frame_length; 2340 2341 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2342 2343 qinfo->mp = rxq->mb_pool; 2344 qinfo->scattered_rx = dev->data->scattered_rx; 2345 qinfo->nb_desc = rxq->nb_desc; 2346 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 2347 &max_frame_length) == 0) 2348 qinfo->rx_buf_size = max_frame_length; 2349 2350 qinfo->conf.rx_free_thresh = 1; 2351 qinfo->conf.rx_drop_en = 1; 2352 qinfo->conf.rx_deferred_start = 0; 2353 qinfo->conf.offloads = rxq->offloads; 2354 } 2355 2356 static void 2357 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2358 struct rte_eth_txq_info *qinfo) 2359 { 2360 struct dpaa2_queue *txq; 2361 2362 txq = dev->data->tx_queues[queue_id]; 2363 2364 qinfo->nb_desc = txq->nb_desc; 2365 qinfo->conf.tx_thresh.pthresh = 0; 2366 qinfo->conf.tx_thresh.hthresh = 0; 2367 qinfo->conf.tx_thresh.wthresh = 0; 2368 2369 qinfo->conf.tx_free_thresh = 0; 2370 qinfo->conf.tx_rs_thresh = 0; 2371 qinfo->conf.offloads = txq->offloads; 2372 qinfo->conf.tx_deferred_start = 0; 2373 } 2374 2375 static int 2376 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2377 { 2378 *(const void **)ops = &dpaa2_tm_ops; 2379 2380 return 0; 2381 } 2382 2383 static struct eth_dev_ops dpaa2_ethdev_ops = { 2384 .dev_configure = dpaa2_eth_dev_configure, 2385 .dev_start = dpaa2_dev_start, 2386 .dev_stop = dpaa2_dev_stop, 2387 .dev_close = dpaa2_dev_close, 2388 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2389 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2390 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2391 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2392 .dev_set_link_up = dpaa2_dev_set_link_up, 2393 .dev_set_link_down = dpaa2_dev_set_link_down, 2394 .link_update = dpaa2_dev_link_update, 2395 .stats_get = dpaa2_dev_stats_get, 2396 .xstats_get = dpaa2_dev_xstats_get, 2397 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2398 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2399 .xstats_get_names = dpaa2_xstats_get_names, 2400 .stats_reset = dpaa2_dev_stats_reset, 2401 .xstats_reset = dpaa2_dev_stats_reset, 2402 .fw_version_get = dpaa2_fw_version_get, 2403 .dev_infos_get = dpaa2_dev_info_get, 2404 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2405 .mtu_set = dpaa2_dev_mtu_set, 2406 .vlan_filter_set = dpaa2_vlan_filter_set, 2407 .vlan_offload_set = dpaa2_vlan_offload_set, 2408 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2409 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2410 .rx_queue_release = dpaa2_dev_rx_queue_release, 2411 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2412 .tx_queue_release = dpaa2_dev_tx_queue_release, 2413 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2414 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2415 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2416 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2417 .mac_addr_add = dpaa2_dev_add_mac_addr, 2418 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2419 .mac_addr_set = dpaa2_dev_set_mac_addr, 2420 .rss_hash_update = dpaa2_dev_rss_hash_update, 2421 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2422 .flow_ops_get = dpaa2_dev_flow_ops_get, 2423 .rxq_info_get = dpaa2_rxq_info_get, 2424 .txq_info_get = dpaa2_txq_info_get, 2425 .tm_ops_get = dpaa2_tm_ops_get, 2426 #if defined(RTE_LIBRTE_IEEE1588) 2427 .timesync_enable = dpaa2_timesync_enable, 2428 .timesync_disable = dpaa2_timesync_disable, 2429 .timesync_read_time = dpaa2_timesync_read_time, 2430 .timesync_write_time = dpaa2_timesync_write_time, 2431 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2432 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2433 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2434 #endif 2435 }; 2436 2437 /* Populate the mac address from physically available (u-boot/firmware) and/or 2438 * one set by higher layers like MC (restool) etc. 2439 * Returns the table of MAC entries (multiple entries) 2440 */ 2441 static int 2442 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2443 struct rte_ether_addr *mac_entry) 2444 { 2445 int ret; 2446 struct rte_ether_addr phy_mac, prime_mac; 2447 2448 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2449 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2450 2451 /* Get the physical device MAC address */ 2452 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2453 phy_mac.addr_bytes); 2454 if (ret) { 2455 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2456 goto cleanup; 2457 } 2458 2459 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2460 prime_mac.addr_bytes); 2461 if (ret) { 2462 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2463 goto cleanup; 2464 } 2465 2466 /* Now that both MAC have been obtained, do: 2467 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2468 * and return phy 2469 * If empty_mac(phy), return prime. 2470 * if both are empty, create random MAC, set as prime and return 2471 */ 2472 if (!rte_is_zero_ether_addr(&phy_mac)) { 2473 /* If the addresses are not same, overwrite prime */ 2474 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2475 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2476 priv->token, 2477 phy_mac.addr_bytes); 2478 if (ret) { 2479 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2480 ret); 2481 goto cleanup; 2482 } 2483 memcpy(&prime_mac, &phy_mac, 2484 sizeof(struct rte_ether_addr)); 2485 } 2486 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2487 /* In case phys and prime, both are zero, create random MAC */ 2488 rte_eth_random_addr(prime_mac.addr_bytes); 2489 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2490 priv->token, 2491 prime_mac.addr_bytes); 2492 if (ret) { 2493 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2494 goto cleanup; 2495 } 2496 } 2497 2498 /* prime_mac the final MAC address */ 2499 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2500 return 0; 2501 2502 cleanup: 2503 return -1; 2504 } 2505 2506 static int 2507 check_devargs_handler(__rte_unused const char *key, const char *value, 2508 __rte_unused void *opaque) 2509 { 2510 if (strcmp(value, "1")) 2511 return -1; 2512 2513 return 0; 2514 } 2515 2516 static int 2517 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2518 { 2519 struct rte_kvargs *kvlist; 2520 2521 if (!devargs) 2522 return 0; 2523 2524 kvlist = rte_kvargs_parse(devargs->args, NULL); 2525 if (!kvlist) 2526 return 0; 2527 2528 if (!rte_kvargs_count(kvlist, key)) { 2529 rte_kvargs_free(kvlist); 2530 return 0; 2531 } 2532 2533 if (rte_kvargs_process(kvlist, key, 2534 check_devargs_handler, NULL) < 0) { 2535 rte_kvargs_free(kvlist); 2536 return 0; 2537 } 2538 rte_kvargs_free(kvlist); 2539 2540 return 1; 2541 } 2542 2543 static int 2544 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2545 { 2546 struct rte_device *dev = eth_dev->device; 2547 struct rte_dpaa2_device *dpaa2_dev; 2548 struct fsl_mc_io *dpni_dev; 2549 struct dpni_attr attr; 2550 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2551 struct dpni_buffer_layout layout; 2552 int ret, hw_id, i; 2553 2554 PMD_INIT_FUNC_TRACE(); 2555 2556 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2557 if (!dpni_dev) { 2558 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2559 return -1; 2560 } 2561 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2562 eth_dev->process_private = (void *)dpni_dev; 2563 2564 /* For secondary processes, the primary has done all the work */ 2565 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2566 /* In case of secondary, only burst and ops API need to be 2567 * plugged. 2568 */ 2569 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2570 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2571 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2572 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2573 else if (dpaa2_get_devargs(dev->devargs, 2574 DRIVER_NO_PREFETCH_MODE)) 2575 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2576 else 2577 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2578 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2579 return 0; 2580 } 2581 2582 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2583 2584 hw_id = dpaa2_dev->object_id; 2585 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2586 if (ret) { 2587 DPAA2_PMD_ERR( 2588 "Failure in opening dpni@%d with err code %d", 2589 hw_id, ret); 2590 rte_free(dpni_dev); 2591 return -1; 2592 } 2593 2594 /* Clean the device first */ 2595 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2596 if (ret) { 2597 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2598 hw_id, ret); 2599 goto init_err; 2600 } 2601 2602 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2603 if (ret) { 2604 DPAA2_PMD_ERR( 2605 "Failure in get dpni@%d attribute, err code %d", 2606 hw_id, ret); 2607 goto init_err; 2608 } 2609 2610 priv->num_rx_tc = attr.num_rx_tcs; 2611 priv->qos_entries = attr.qos_entries; 2612 priv->fs_entries = attr.fs_entries; 2613 priv->dist_queues = attr.num_queues; 2614 2615 /* only if the custom CG is enabled */ 2616 if (attr.options & DPNI_OPT_CUSTOM_CG) 2617 priv->max_cgs = attr.num_cgs; 2618 else 2619 priv->max_cgs = 0; 2620 2621 for (i = 0; i < priv->max_cgs; i++) 2622 priv->cgid_in_use[i] = 0; 2623 2624 for (i = 0; i < attr.num_rx_tcs; i++) 2625 priv->nb_rx_queues += attr.num_queues; 2626 2627 /* Using number of TX queues as number of TX TCs */ 2628 priv->nb_tx_queues = attr.num_tx_tcs; 2629 2630 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2631 priv->num_rx_tc, priv->nb_rx_queues, 2632 priv->nb_tx_queues, priv->max_cgs); 2633 2634 priv->hw = dpni_dev; 2635 priv->hw_id = hw_id; 2636 priv->options = attr.options; 2637 priv->max_mac_filters = attr.mac_filter_entries; 2638 priv->max_vlan_filters = attr.vlan_filter_entries; 2639 priv->flags = 0; 2640 #if defined(RTE_LIBRTE_IEEE1588) 2641 printf("DPDK IEEE1588 is enabled\n"); 2642 priv->flags |= DPAA2_TX_CONF_ENABLE; 2643 #endif 2644 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ 2645 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { 2646 priv->flags |= DPAA2_TX_CONF_ENABLE; 2647 DPAA2_PMD_INFO("TX_CONF Enabled"); 2648 } 2649 2650 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { 2651 dpaa2_enable_err_queue = 1; 2652 DPAA2_PMD_INFO("Enable error queue"); 2653 } 2654 2655 /* Allocate memory for hardware structure for queues */ 2656 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2657 if (ret) { 2658 DPAA2_PMD_ERR("Queue allocation Failed"); 2659 goto init_err; 2660 } 2661 2662 /* Allocate memory for storing MAC addresses. 2663 * Table of mac_filter_entries size is allocated so that RTE ether lib 2664 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2665 */ 2666 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2667 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2668 if (eth_dev->data->mac_addrs == NULL) { 2669 DPAA2_PMD_ERR( 2670 "Failed to allocate %d bytes needed to store MAC addresses", 2671 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2672 ret = -ENOMEM; 2673 goto init_err; 2674 } 2675 2676 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2677 if (ret) { 2678 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2679 rte_free(eth_dev->data->mac_addrs); 2680 eth_dev->data->mac_addrs = NULL; 2681 goto init_err; 2682 } 2683 2684 /* ... tx buffer layout ... */ 2685 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2686 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2687 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2688 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2689 layout.pass_timestamp = true; 2690 } else { 2691 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2692 } 2693 layout.pass_frame_status = 1; 2694 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2695 DPNI_QUEUE_TX, &layout); 2696 if (ret) { 2697 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2698 goto init_err; 2699 } 2700 2701 /* ... tx-conf and error buffer layout ... */ 2702 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2703 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2704 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2705 layout.pass_timestamp = true; 2706 } 2707 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2708 layout.pass_frame_status = 1; 2709 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2710 DPNI_QUEUE_TX_CONFIRM, &layout); 2711 if (ret) { 2712 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2713 ret); 2714 goto init_err; 2715 } 2716 2717 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2718 2719 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2720 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2721 DPAA2_PMD_INFO("Loopback mode"); 2722 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2723 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2724 DPAA2_PMD_INFO("No Prefetch mode"); 2725 } else { 2726 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2727 } 2728 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2729 2730 /*Init fields w.r.t. classficaition*/ 2731 memset(&priv->extract.qos_key_extract, 0, 2732 sizeof(struct dpaa2_key_extract)); 2733 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2734 if (!priv->extract.qos_extract_param) { 2735 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2736 " classificaiton ", ret); 2737 goto init_err; 2738 } 2739 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2740 IP_ADDRESS_OFFSET_INVALID; 2741 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2742 IP_ADDRESS_OFFSET_INVALID; 2743 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2744 IP_ADDRESS_OFFSET_INVALID; 2745 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2746 IP_ADDRESS_OFFSET_INVALID; 2747 2748 for (i = 0; i < MAX_TCS; i++) { 2749 memset(&priv->extract.tc_key_extract[i], 0, 2750 sizeof(struct dpaa2_key_extract)); 2751 priv->extract.tc_extract_param[i] = 2752 (size_t)rte_malloc(NULL, 256, 64); 2753 if (!priv->extract.tc_extract_param[i]) { 2754 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2755 ret); 2756 goto init_err; 2757 } 2758 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2759 IP_ADDRESS_OFFSET_INVALID; 2760 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2761 IP_ADDRESS_OFFSET_INVALID; 2762 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2763 IP_ADDRESS_OFFSET_INVALID; 2764 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2765 IP_ADDRESS_OFFSET_INVALID; 2766 } 2767 2768 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2769 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2770 + VLAN_TAG_SIZE); 2771 if (ret) { 2772 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2773 goto init_err; 2774 } 2775 2776 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2777 * with external entity to receive byte code for software sequence 2778 * and same will be offload to the H/W using MC interface. 2779 * Currently it is assumed that DPAA2 driver has byte code by some 2780 * mean and same if offloaded to H/W. 2781 */ 2782 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2783 WRIOP_SS_INITIALIZER(priv); 2784 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2785 if (ret < 0) { 2786 DPAA2_PMD_ERR(" Error(%d) in loading softparser\n", 2787 ret); 2788 return ret; 2789 } 2790 2791 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2792 DPNI_SS_INGRESS); 2793 if (ret < 0) { 2794 DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n", 2795 ret); 2796 return ret; 2797 } 2798 } 2799 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2800 return 0; 2801 init_err: 2802 dpaa2_dev_close(eth_dev); 2803 2804 return ret; 2805 } 2806 2807 static int 2808 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2809 struct rte_dpaa2_device *dpaa2_dev) 2810 { 2811 struct rte_eth_dev *eth_dev; 2812 struct dpaa2_dev_priv *dev_priv; 2813 int diag; 2814 2815 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2816 RTE_PKTMBUF_HEADROOM) { 2817 DPAA2_PMD_ERR( 2818 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2819 RTE_PKTMBUF_HEADROOM, 2820 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2821 2822 return -1; 2823 } 2824 2825 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2826 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2827 if (!eth_dev) 2828 return -ENODEV; 2829 dev_priv = rte_zmalloc("ethdev private structure", 2830 sizeof(struct dpaa2_dev_priv), 2831 RTE_CACHE_LINE_SIZE); 2832 if (dev_priv == NULL) { 2833 DPAA2_PMD_CRIT( 2834 "Unable to allocate memory for private data"); 2835 rte_eth_dev_release_port(eth_dev); 2836 return -ENOMEM; 2837 } 2838 eth_dev->data->dev_private = (void *)dev_priv; 2839 /* Store a pointer to eth_dev in dev_private */ 2840 dev_priv->eth_dev = eth_dev; 2841 } else { 2842 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2843 if (!eth_dev) { 2844 DPAA2_PMD_DEBUG("returning enodev"); 2845 return -ENODEV; 2846 } 2847 } 2848 2849 eth_dev->device = &dpaa2_dev->device; 2850 2851 dpaa2_dev->eth_dev = eth_dev; 2852 eth_dev->data->rx_mbuf_alloc_failed = 0; 2853 2854 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2855 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2856 2857 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2858 2859 /* Invoke PMD device initialization function */ 2860 diag = dpaa2_dev_init(eth_dev); 2861 if (diag == 0) { 2862 rte_eth_dev_probing_finish(eth_dev); 2863 return 0; 2864 } 2865 2866 rte_eth_dev_release_port(eth_dev); 2867 return diag; 2868 } 2869 2870 static int 2871 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2872 { 2873 struct rte_eth_dev *eth_dev; 2874 int ret; 2875 2876 eth_dev = dpaa2_dev->eth_dev; 2877 dpaa2_dev_close(eth_dev); 2878 ret = rte_eth_dev_release_port(eth_dev); 2879 2880 return ret; 2881 } 2882 2883 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2884 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2885 .drv_type = DPAA2_ETH, 2886 .probe = rte_dpaa2_probe, 2887 .remove = rte_dpaa2_remove, 2888 }; 2889 2890 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2891 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, 2892 DRIVER_LOOPBACK_MODE "=<int> " 2893 DRIVER_NO_PREFETCH_MODE "=<int>" 2894 DRIVER_TX_CONF "=<int>" 2895 DRIVER_ERROR_QUEUE "=<int>"); 2896 RTE_LOG_REGISTER(dpaa2_logtype_pmd, pmd.net.dpaa2, NOTICE); 2897