1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 21 #include "dpaa2_pmd_logs.h" 22 #include <fslmc_vfio.h> 23 #include <dpaa2_hw_pvt.h> 24 #include <dpaa2_hw_mempool.h> 25 #include <dpaa2_hw_dpio.h> 26 #include <mc/fsl_dpmng.h> 27 #include "dpaa2_ethdev.h" 28 #include <fsl_qbman_debug.h> 29 30 /* Supported Rx offloads */ 31 static uint64_t dev_rx_offloads_sup = 32 DEV_RX_OFFLOAD_VLAN_STRIP | 33 DEV_RX_OFFLOAD_IPV4_CKSUM | 34 DEV_RX_OFFLOAD_UDP_CKSUM | 35 DEV_RX_OFFLOAD_TCP_CKSUM | 36 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 37 DEV_RX_OFFLOAD_VLAN_FILTER | 38 DEV_RX_OFFLOAD_JUMBO_FRAME; 39 40 /* Rx offloads which cannot be disabled */ 41 static uint64_t dev_rx_offloads_nodis = 42 DEV_RX_OFFLOAD_SCATTER; 43 44 /* Supported Tx offloads */ 45 static uint64_t dev_tx_offloads_sup = 46 DEV_TX_OFFLOAD_VLAN_INSERT | 47 DEV_TX_OFFLOAD_IPV4_CKSUM | 48 DEV_TX_OFFLOAD_UDP_CKSUM | 49 DEV_TX_OFFLOAD_TCP_CKSUM | 50 DEV_TX_OFFLOAD_SCTP_CKSUM | 51 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 52 53 /* Tx offloads which cannot be disabled */ 54 static uint64_t dev_tx_offloads_nodis = 55 DEV_TX_OFFLOAD_MULTI_SEGS | 56 DEV_TX_OFFLOAD_MT_LOCKFREE | 57 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 58 59 /* enable timestamp in mbuf */ 60 enum pmd_dpaa2_ts dpaa2_enable_ts; 61 62 struct rte_dpaa2_xstats_name_off { 63 char name[RTE_ETH_XSTATS_NAME_SIZE]; 64 uint8_t page_id; /* dpni statistics page id */ 65 uint8_t stats_id; /* stats id in the given page */ 66 }; 67 68 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 69 {"ingress_multicast_frames", 0, 2}, 70 {"ingress_multicast_bytes", 0, 3}, 71 {"ingress_broadcast_frames", 0, 4}, 72 {"ingress_broadcast_bytes", 0, 5}, 73 {"egress_multicast_frames", 1, 2}, 74 {"egress_multicast_bytes", 1, 3}, 75 {"egress_broadcast_frames", 1, 4}, 76 {"egress_broadcast_bytes", 1, 5}, 77 {"ingress_filtered_frames", 2, 0}, 78 {"ingress_discarded_frames", 2, 1}, 79 {"ingress_nobuffer_discards", 2, 2}, 80 {"egress_discarded_frames", 2, 3}, 81 {"egress_confirmed_frames", 2, 4}, 82 }; 83 84 static struct rte_dpaa2_driver rte_dpaa2_pmd; 85 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); 86 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 87 int wait_to_complete); 88 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 89 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 90 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 91 92 int dpaa2_logtype_pmd; 93 94 __rte_experimental void 95 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable) 96 { 97 dpaa2_enable_ts = enable; 98 } 99 100 static int 101 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 102 { 103 int ret; 104 struct dpaa2_dev_priv *priv = dev->data->dev_private; 105 struct fsl_mc_io *dpni = priv->hw; 106 107 PMD_INIT_FUNC_TRACE(); 108 109 if (dpni == NULL) { 110 DPAA2_PMD_ERR("dpni is NULL"); 111 return -1; 112 } 113 114 if (on) 115 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, 116 priv->token, vlan_id); 117 else 118 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 119 priv->token, vlan_id); 120 121 if (ret < 0) 122 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 123 ret, vlan_id, priv->hw_id); 124 125 return ret; 126 } 127 128 static int 129 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 130 { 131 struct dpaa2_dev_priv *priv = dev->data->dev_private; 132 struct fsl_mc_io *dpni = priv->hw; 133 int ret; 134 135 PMD_INIT_FUNC_TRACE(); 136 137 if (mask & ETH_VLAN_FILTER_MASK) { 138 /* VLAN Filter not avaialble */ 139 if (!priv->max_vlan_filters) { 140 DPAA2_PMD_INFO("VLAN filter not available"); 141 goto next_mask; 142 } 143 144 if (dev->data->dev_conf.rxmode.offloads & 145 DEV_RX_OFFLOAD_VLAN_FILTER) 146 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 147 priv->token, true); 148 else 149 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 150 priv->token, false); 151 if (ret < 0) 152 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 153 } 154 next_mask: 155 if (mask & ETH_VLAN_EXTEND_MASK) { 156 if (dev->data->dev_conf.rxmode.offloads & 157 DEV_RX_OFFLOAD_VLAN_EXTEND) 158 DPAA2_PMD_INFO("VLAN extend offload not supported"); 159 } 160 161 return 0; 162 } 163 164 static int 165 dpaa2_fw_version_get(struct rte_eth_dev *dev, 166 char *fw_version, 167 size_t fw_size) 168 { 169 int ret; 170 struct dpaa2_dev_priv *priv = dev->data->dev_private; 171 struct fsl_mc_io *dpni = priv->hw; 172 struct mc_soc_version mc_plat_info = {0}; 173 struct mc_version mc_ver_info = {0}; 174 175 PMD_INIT_FUNC_TRACE(); 176 177 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 178 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 179 180 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 181 DPAA2_PMD_WARN("\tmc_get_version failed"); 182 183 ret = snprintf(fw_version, fw_size, 184 "%x-%d.%d.%d", 185 mc_plat_info.svr, 186 mc_ver_info.major, 187 mc_ver_info.minor, 188 mc_ver_info.revision); 189 190 ret += 1; /* add the size of '\0' */ 191 if (fw_size < (uint32_t)ret) 192 return ret; 193 else 194 return 0; 195 } 196 197 static void 198 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 199 { 200 struct dpaa2_dev_priv *priv = dev->data->dev_private; 201 202 PMD_INIT_FUNC_TRACE(); 203 204 dev_info->if_index = priv->hw_id; 205 206 dev_info->max_mac_addrs = priv->max_mac_filters; 207 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 208 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 209 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 210 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 211 dev_info->rx_offload_capa = dev_rx_offloads_sup | 212 dev_rx_offloads_nodis; 213 dev_info->tx_offload_capa = dev_tx_offloads_sup | 214 dev_tx_offloads_nodis; 215 dev_info->speed_capa = ETH_LINK_SPEED_1G | 216 ETH_LINK_SPEED_2_5G | 217 ETH_LINK_SPEED_10G; 218 219 dev_info->max_hash_mac_addrs = 0; 220 dev_info->max_vfs = 0; 221 dev_info->max_vmdq_pools = ETH_16_POOLS; 222 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 223 } 224 225 static int 226 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 227 { 228 struct dpaa2_dev_priv *priv = dev->data->dev_private; 229 uint16_t dist_idx; 230 uint32_t vq_id; 231 struct dpaa2_queue *mc_q, *mcq; 232 uint32_t tot_queues; 233 int i; 234 struct dpaa2_queue *dpaa2_q; 235 236 PMD_INIT_FUNC_TRACE(); 237 238 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 239 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 240 RTE_CACHE_LINE_SIZE); 241 if (!mc_q) { 242 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 243 return -1; 244 } 245 246 for (i = 0; i < priv->nb_rx_queues; i++) { 247 mc_q->eth_data = dev->data; 248 priv->rx_vq[i] = mc_q++; 249 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 250 dpaa2_q->q_storage = rte_malloc("dq_storage", 251 sizeof(struct queue_storage_info_t), 252 RTE_CACHE_LINE_SIZE); 253 if (!dpaa2_q->q_storage) 254 goto fail; 255 256 memset(dpaa2_q->q_storage, 0, 257 sizeof(struct queue_storage_info_t)); 258 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 259 goto fail; 260 } 261 262 for (i = 0; i < priv->nb_tx_queues; i++) { 263 mc_q->eth_data = dev->data; 264 mc_q->flow_id = 0xffff; 265 priv->tx_vq[i] = mc_q++; 266 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 267 dpaa2_q->cscn = rte_malloc(NULL, 268 sizeof(struct qbman_result), 16); 269 if (!dpaa2_q->cscn) 270 goto fail_tx; 271 } 272 273 vq_id = 0; 274 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 275 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 276 mcq->tc_index = DPAA2_DEF_TC; 277 mcq->flow_id = dist_idx; 278 vq_id++; 279 } 280 281 return 0; 282 fail_tx: 283 i -= 1; 284 while (i >= 0) { 285 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 286 rte_free(dpaa2_q->cscn); 287 priv->tx_vq[i--] = NULL; 288 } 289 i = priv->nb_rx_queues; 290 fail: 291 i -= 1; 292 mc_q = priv->rx_vq[0]; 293 while (i >= 0) { 294 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 295 dpaa2_free_dq_storage(dpaa2_q->q_storage); 296 rte_free(dpaa2_q->q_storage); 297 priv->rx_vq[i--] = NULL; 298 } 299 rte_free(mc_q); 300 return -1; 301 } 302 303 static void 304 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 305 { 306 struct dpaa2_dev_priv *priv = dev->data->dev_private; 307 struct dpaa2_queue *dpaa2_q; 308 int i; 309 310 PMD_INIT_FUNC_TRACE(); 311 312 /* Queue allocation base */ 313 if (priv->rx_vq[0]) { 314 /* cleaning up queue storage */ 315 for (i = 0; i < priv->nb_rx_queues; i++) { 316 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 317 if (dpaa2_q->q_storage) 318 rte_free(dpaa2_q->q_storage); 319 } 320 /* cleanup tx queue cscn */ 321 for (i = 0; i < priv->nb_tx_queues; i++) { 322 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 323 rte_free(dpaa2_q->cscn); 324 } 325 /*free memory for all queues (RX+TX) */ 326 rte_free(priv->rx_vq[0]); 327 priv->rx_vq[0] = NULL; 328 } 329 } 330 331 static int 332 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 333 { 334 struct dpaa2_dev_priv *priv = dev->data->dev_private; 335 struct fsl_mc_io *dpni = priv->hw; 336 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 337 uint64_t rx_offloads = eth_conf->rxmode.offloads; 338 uint64_t tx_offloads = eth_conf->txmode.offloads; 339 int rx_l3_csum_offload = false; 340 int rx_l4_csum_offload = false; 341 int tx_l3_csum_offload = false; 342 int tx_l4_csum_offload = false; 343 int ret; 344 345 PMD_INIT_FUNC_TRACE(); 346 347 /* Rx offloads validation */ 348 if (dev_rx_offloads_nodis & ~rx_offloads) { 349 DPAA2_PMD_WARN( 350 "Rx offloads non configurable - requested 0x%" PRIx64 351 " ignored 0x%" PRIx64, 352 rx_offloads, dev_rx_offloads_nodis); 353 } 354 355 /* Tx offloads validation */ 356 if (dev_tx_offloads_nodis & ~tx_offloads) { 357 DPAA2_PMD_WARN( 358 "Tx offloads non configurable - requested 0x%" PRIx64 359 " ignored 0x%" PRIx64, 360 tx_offloads, dev_tx_offloads_nodis); 361 } 362 363 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 364 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 365 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 366 priv->token, eth_conf->rxmode.max_rx_pkt_len); 367 if (ret) { 368 DPAA2_PMD_ERR( 369 "Unable to set mtu. check config"); 370 return ret; 371 } 372 } else { 373 return -1; 374 } 375 } 376 377 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 378 ret = dpaa2_setup_flow_dist(dev, 379 eth_conf->rx_adv_conf.rss_conf.rss_hf); 380 if (ret) { 381 DPAA2_PMD_ERR("Unable to set flow distribution." 382 "Check queue config"); 383 return ret; 384 } 385 } 386 387 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 388 rx_l3_csum_offload = true; 389 390 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 391 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM)) 392 rx_l4_csum_offload = true; 393 394 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 395 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 396 if (ret) { 397 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 398 return ret; 399 } 400 401 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 402 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 403 if (ret) { 404 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 405 return ret; 406 } 407 408 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 409 tx_l3_csum_offload = true; 410 411 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 412 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 413 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 414 tx_l4_csum_offload = true; 415 416 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 417 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 418 if (ret) { 419 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 420 return ret; 421 } 422 423 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 424 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 425 if (ret) { 426 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 427 return ret; 428 } 429 430 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 431 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 432 * to 0 for LS2 in the hardware thus disabling data/annotation 433 * stashing. For LX2 this is fixed in hardware and thus hash result and 434 * parse results can be received in FD using this option. 435 */ 436 if (dpaa2_svr_family == SVR_LX2160A) { 437 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 438 DPNI_FLCTYPE_HASH, true); 439 if (ret) { 440 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 441 return ret; 442 } 443 } 444 445 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 446 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 447 448 /* update the current status */ 449 dpaa2_dev_link_update(dev, 0); 450 451 return 0; 452 } 453 454 /* Function to setup RX flow information. It contains traffic class ID, 455 * flow ID, destination configuration etc. 456 */ 457 static int 458 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 459 uint16_t rx_queue_id, 460 uint16_t nb_rx_desc __rte_unused, 461 unsigned int socket_id __rte_unused, 462 const struct rte_eth_rxconf *rx_conf __rte_unused, 463 struct rte_mempool *mb_pool) 464 { 465 struct dpaa2_dev_priv *priv = dev->data->dev_private; 466 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 467 struct dpaa2_queue *dpaa2_q; 468 struct dpni_queue cfg; 469 uint8_t options = 0; 470 uint8_t flow_id; 471 uint32_t bpid; 472 int ret; 473 474 PMD_INIT_FUNC_TRACE(); 475 476 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 477 dev, rx_queue_id, mb_pool, rx_conf); 478 479 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 480 bpid = mempool_to_bpid(mb_pool); 481 ret = dpaa2_attach_bp_list(priv, 482 rte_dpaa2_bpid_info[bpid].bp_list); 483 if (ret) 484 return ret; 485 } 486 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 487 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 488 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 489 490 /*Get the flow id from given VQ id*/ 491 flow_id = rx_queue_id % priv->nb_rx_queues; 492 memset(&cfg, 0, sizeof(struct dpni_queue)); 493 494 options = options | DPNI_QUEUE_OPT_USER_CTX; 495 cfg.user_context = (size_t)(dpaa2_q); 496 497 /*if ls2088 or rev2 device, enable the stashing */ 498 499 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 500 options |= DPNI_QUEUE_OPT_FLC; 501 cfg.flc.stash_control = true; 502 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 503 /* 00 00 00 - last 6 bit represent annotation, context stashing, 504 * data stashing setting 01 01 00 (0x14) 505 * (in following order ->DS AS CS) 506 * to enable 1 line data, 1 line annotation. 507 * For LX2, this setting should be 01 00 00 (0x10) 508 */ 509 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 510 cfg.flc.value |= 0x10; 511 else 512 cfg.flc.value |= 0x14; 513 } 514 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 515 dpaa2_q->tc_index, flow_id, options, &cfg); 516 if (ret) { 517 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 518 return -1; 519 } 520 521 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 522 struct dpni_taildrop taildrop; 523 524 taildrop.enable = 1; 525 /*enabling per rx queue congestion control */ 526 taildrop.threshold = CONG_THRESHOLD_RX_Q; 527 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 528 taildrop.oal = CONG_RX_OAL; 529 DPAA2_PMD_DEBUG("Enabling Early Drop on queue = %d", 530 rx_queue_id); 531 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 532 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 533 dpaa2_q->tc_index, flow_id, &taildrop); 534 if (ret) { 535 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 536 ret); 537 return -1; 538 } 539 } 540 541 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 542 return 0; 543 } 544 545 static int 546 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 547 uint16_t tx_queue_id, 548 uint16_t nb_tx_desc __rte_unused, 549 unsigned int socket_id __rte_unused, 550 const struct rte_eth_txconf *tx_conf __rte_unused) 551 { 552 struct dpaa2_dev_priv *priv = dev->data->dev_private; 553 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 554 priv->tx_vq[tx_queue_id]; 555 struct fsl_mc_io *dpni = priv->hw; 556 struct dpni_queue tx_conf_cfg; 557 struct dpni_queue tx_flow_cfg; 558 uint8_t options = 0, flow_id; 559 uint32_t tc_id; 560 int ret; 561 562 PMD_INIT_FUNC_TRACE(); 563 564 /* Return if queue already configured */ 565 if (dpaa2_q->flow_id != 0xffff) { 566 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 567 return 0; 568 } 569 570 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 571 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 572 573 tc_id = tx_queue_id; 574 flow_id = 0; 575 576 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 577 tc_id, flow_id, options, &tx_flow_cfg); 578 if (ret) { 579 DPAA2_PMD_ERR("Error in setting the tx flow: " 580 "tc_id=%d, flow=%d err=%d", 581 tc_id, flow_id, ret); 582 return -1; 583 } 584 585 dpaa2_q->flow_id = flow_id; 586 587 if (tx_queue_id == 0) { 588 /*Set tx-conf and error configuration*/ 589 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 590 priv->token, 591 DPNI_CONF_DISABLE); 592 if (ret) { 593 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 594 "err=%d", ret); 595 return -1; 596 } 597 } 598 dpaa2_q->tc_index = tc_id; 599 600 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 601 struct dpni_congestion_notification_cfg cong_notif_cfg; 602 603 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 604 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD; 605 /* Notify that the queue is not congested when the data in 606 * the queue is below this thershold. 607 */ 608 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; 609 cong_notif_cfg.message_ctx = 0; 610 cong_notif_cfg.message_iova = 611 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 612 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 613 cong_notif_cfg.notification_mode = 614 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 615 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 616 DPNI_CONG_OPT_COHERENT_WRITE; 617 618 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 619 priv->token, 620 DPNI_QUEUE_TX, 621 tc_id, 622 &cong_notif_cfg); 623 if (ret) { 624 DPAA2_PMD_ERR( 625 "Error in setting tx congestion notification: " 626 "err=%d", ret); 627 return -ret; 628 } 629 } 630 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 631 return 0; 632 } 633 634 static void 635 dpaa2_dev_rx_queue_release(void *q __rte_unused) 636 { 637 PMD_INIT_FUNC_TRACE(); 638 } 639 640 static void 641 dpaa2_dev_tx_queue_release(void *q __rte_unused) 642 { 643 PMD_INIT_FUNC_TRACE(); 644 } 645 646 static uint32_t 647 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 648 { 649 int32_t ret; 650 struct dpaa2_dev_priv *priv = dev->data->dev_private; 651 struct dpaa2_queue *dpaa2_q; 652 struct qbman_swp *swp; 653 struct qbman_fq_query_np_rslt state; 654 uint32_t frame_cnt = 0; 655 656 PMD_INIT_FUNC_TRACE(); 657 658 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 659 ret = dpaa2_affine_qbman_swp(); 660 if (ret) { 661 DPAA2_PMD_ERR("Failure in affining portal"); 662 return -EINVAL; 663 } 664 } 665 swp = DPAA2_PER_LCORE_PORTAL; 666 667 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 668 669 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 670 frame_cnt = qbman_fq_state_frame_count(&state); 671 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u", 672 rx_queue_id, frame_cnt); 673 } 674 return frame_cnt; 675 } 676 677 static const uint32_t * 678 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 679 { 680 static const uint32_t ptypes[] = { 681 /*todo -= add more types */ 682 RTE_PTYPE_L2_ETHER, 683 RTE_PTYPE_L3_IPV4, 684 RTE_PTYPE_L3_IPV4_EXT, 685 RTE_PTYPE_L3_IPV6, 686 RTE_PTYPE_L3_IPV6_EXT, 687 RTE_PTYPE_L4_TCP, 688 RTE_PTYPE_L4_UDP, 689 RTE_PTYPE_L4_SCTP, 690 RTE_PTYPE_L4_ICMP, 691 RTE_PTYPE_UNKNOWN 692 }; 693 694 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx) 695 return ptypes; 696 return NULL; 697 } 698 699 /** 700 * Dpaa2 link Interrupt handler 701 * 702 * @param param 703 * The address of parameter (struct rte_eth_dev *) regsitered before. 704 * 705 * @return 706 * void 707 */ 708 static void 709 dpaa2_interrupt_handler(void *param) 710 { 711 struct rte_eth_dev *dev = param; 712 struct dpaa2_dev_priv *priv = dev->data->dev_private; 713 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 714 int ret; 715 int irq_index = DPNI_IRQ_INDEX; 716 unsigned int status = 0, clear = 0; 717 718 PMD_INIT_FUNC_TRACE(); 719 720 if (dpni == NULL) { 721 DPAA2_PMD_ERR("dpni is NULL"); 722 return; 723 } 724 725 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 726 irq_index, &status); 727 if (unlikely(ret)) { 728 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 729 clear = 0xffffffff; 730 goto out; 731 } 732 733 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 734 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 735 dpaa2_dev_link_update(dev, 0); 736 /* calling all the apps registered for link status event */ 737 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 738 NULL); 739 } 740 out: 741 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 742 irq_index, clear); 743 if (unlikely(ret)) 744 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 745 } 746 747 static int 748 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 749 { 750 int err = 0; 751 struct dpaa2_dev_priv *priv = dev->data->dev_private; 752 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 753 int irq_index = DPNI_IRQ_INDEX; 754 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 755 756 PMD_INIT_FUNC_TRACE(); 757 758 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 759 irq_index, mask); 760 if (err < 0) { 761 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 762 strerror(-err)); 763 return err; 764 } 765 766 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 767 irq_index, enable); 768 if (err < 0) 769 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 770 strerror(-err)); 771 772 return err; 773 } 774 775 static int 776 dpaa2_dev_start(struct rte_eth_dev *dev) 777 { 778 struct rte_device *rdev = dev->device; 779 struct rte_dpaa2_device *dpaa2_dev; 780 struct rte_eth_dev_data *data = dev->data; 781 struct dpaa2_dev_priv *priv = data->dev_private; 782 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 783 struct dpni_queue cfg; 784 struct dpni_error_cfg err_cfg; 785 uint16_t qdid; 786 struct dpni_queue_id qid; 787 struct dpaa2_queue *dpaa2_q; 788 int ret, i; 789 struct rte_intr_handle *intr_handle; 790 791 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 792 intr_handle = &dpaa2_dev->intr_handle; 793 794 PMD_INIT_FUNC_TRACE(); 795 796 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 797 if (ret) { 798 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 799 priv->hw_id, ret); 800 return ret; 801 } 802 803 /* Power up the phy. Needed to make the link go UP */ 804 dpaa2_dev_set_link_up(dev); 805 806 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 807 DPNI_QUEUE_TX, &qdid); 808 if (ret) { 809 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 810 return ret; 811 } 812 priv->qdid = qdid; 813 814 for (i = 0; i < data->nb_rx_queues; i++) { 815 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 816 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 817 DPNI_QUEUE_RX, dpaa2_q->tc_index, 818 dpaa2_q->flow_id, &cfg, &qid); 819 if (ret) { 820 DPAA2_PMD_ERR("Error in getting flow information: " 821 "err=%d", ret); 822 return ret; 823 } 824 dpaa2_q->fqid = qid.fqid; 825 } 826 827 /*checksum errors, send them to normal path and set it in annotation */ 828 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 829 830 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 831 err_cfg.set_frame_annotation = true; 832 833 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 834 priv->token, &err_cfg); 835 if (ret) { 836 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 837 ret); 838 return ret; 839 } 840 841 /* if the interrupts were configured on this devices*/ 842 if (intr_handle && (intr_handle->fd) && 843 (dev->data->dev_conf.intr_conf.lsc != 0)) { 844 /* Registering LSC interrupt handler */ 845 rte_intr_callback_register(intr_handle, 846 dpaa2_interrupt_handler, 847 (void *)dev); 848 849 /* enable vfio intr/eventfd mapping 850 * Interrupt index 0 is required, so we can not use 851 * rte_intr_enable. 852 */ 853 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 854 855 /* enable dpni_irqs */ 856 dpaa2_eth_setup_irqs(dev, 1); 857 } 858 859 return 0; 860 } 861 862 /** 863 * This routine disables all traffic on the adapter by issuing a 864 * global reset on the MAC. 865 */ 866 static void 867 dpaa2_dev_stop(struct rte_eth_dev *dev) 868 { 869 struct dpaa2_dev_priv *priv = dev->data->dev_private; 870 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 871 int ret; 872 struct rte_eth_link link; 873 struct rte_intr_handle *intr_handle = dev->intr_handle; 874 875 PMD_INIT_FUNC_TRACE(); 876 877 /* reset interrupt callback */ 878 if (intr_handle && (intr_handle->fd) && 879 (dev->data->dev_conf.intr_conf.lsc != 0)) { 880 /*disable dpni irqs */ 881 dpaa2_eth_setup_irqs(dev, 0); 882 883 /* disable vfio intr before callback unregister */ 884 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 885 886 /* Unregistering LSC interrupt handler */ 887 rte_intr_callback_unregister(intr_handle, 888 dpaa2_interrupt_handler, 889 (void *)dev); 890 } 891 892 dpaa2_dev_set_link_down(dev); 893 894 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 895 if (ret) { 896 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 897 ret, priv->hw_id); 898 return; 899 } 900 901 /* clear the recorded link status */ 902 memset(&link, 0, sizeof(link)); 903 rte_eth_linkstatus_set(dev, &link); 904 } 905 906 static void 907 dpaa2_dev_close(struct rte_eth_dev *dev) 908 { 909 struct dpaa2_dev_priv *priv = dev->data->dev_private; 910 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 911 int ret; 912 struct rte_eth_link link; 913 914 PMD_INIT_FUNC_TRACE(); 915 916 /* Clean the device first */ 917 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 918 if (ret) { 919 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 920 return; 921 } 922 923 memset(&link, 0, sizeof(link)); 924 rte_eth_linkstatus_set(dev, &link); 925 } 926 927 static void 928 dpaa2_dev_promiscuous_enable( 929 struct rte_eth_dev *dev) 930 { 931 int ret; 932 struct dpaa2_dev_priv *priv = dev->data->dev_private; 933 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 934 935 PMD_INIT_FUNC_TRACE(); 936 937 if (dpni == NULL) { 938 DPAA2_PMD_ERR("dpni is NULL"); 939 return; 940 } 941 942 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 943 if (ret < 0) 944 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 945 946 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 947 if (ret < 0) 948 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 949 } 950 951 static void 952 dpaa2_dev_promiscuous_disable( 953 struct rte_eth_dev *dev) 954 { 955 int ret; 956 struct dpaa2_dev_priv *priv = dev->data->dev_private; 957 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 958 959 PMD_INIT_FUNC_TRACE(); 960 961 if (dpni == NULL) { 962 DPAA2_PMD_ERR("dpni is NULL"); 963 return; 964 } 965 966 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 967 if (ret < 0) 968 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 969 970 if (dev->data->all_multicast == 0) { 971 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 972 priv->token, false); 973 if (ret < 0) 974 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 975 ret); 976 } 977 } 978 979 static void 980 dpaa2_dev_allmulticast_enable( 981 struct rte_eth_dev *dev) 982 { 983 int ret; 984 struct dpaa2_dev_priv *priv = dev->data->dev_private; 985 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 986 987 PMD_INIT_FUNC_TRACE(); 988 989 if (dpni == NULL) { 990 DPAA2_PMD_ERR("dpni is NULL"); 991 return; 992 } 993 994 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 995 if (ret < 0) 996 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 997 } 998 999 static void 1000 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1001 { 1002 int ret; 1003 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1004 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1005 1006 PMD_INIT_FUNC_TRACE(); 1007 1008 if (dpni == NULL) { 1009 DPAA2_PMD_ERR("dpni is NULL"); 1010 return; 1011 } 1012 1013 /* must remain on for all promiscuous */ 1014 if (dev->data->promiscuous == 1) 1015 return; 1016 1017 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1018 if (ret < 0) 1019 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1020 } 1021 1022 static int 1023 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1024 { 1025 int ret; 1026 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1027 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1028 uint32_t frame_size = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN 1029 + VLAN_TAG_SIZE; 1030 1031 PMD_INIT_FUNC_TRACE(); 1032 1033 if (dpni == NULL) { 1034 DPAA2_PMD_ERR("dpni is NULL"); 1035 return -EINVAL; 1036 } 1037 1038 /* check that mtu is within the allowed range */ 1039 if ((mtu < ETHER_MIN_MTU) || (frame_size > DPAA2_MAX_RX_PKT_LEN)) 1040 return -EINVAL; 1041 1042 if (frame_size > ETHER_MAX_LEN) 1043 dev->data->dev_conf.rxmode.offloads &= 1044 DEV_RX_OFFLOAD_JUMBO_FRAME; 1045 else 1046 dev->data->dev_conf.rxmode.offloads &= 1047 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1048 1049 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1050 1051 /* Set the Max Rx frame length as 'mtu' + 1052 * Maximum Ethernet header length 1053 */ 1054 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1055 frame_size); 1056 if (ret) { 1057 DPAA2_PMD_ERR("Setting the max frame length failed"); 1058 return -1; 1059 } 1060 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1061 return 0; 1062 } 1063 1064 static int 1065 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1066 struct ether_addr *addr, 1067 __rte_unused uint32_t index, 1068 __rte_unused uint32_t pool) 1069 { 1070 int ret; 1071 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1072 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1073 1074 PMD_INIT_FUNC_TRACE(); 1075 1076 if (dpni == NULL) { 1077 DPAA2_PMD_ERR("dpni is NULL"); 1078 return -1; 1079 } 1080 1081 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, 1082 priv->token, addr->addr_bytes); 1083 if (ret) 1084 DPAA2_PMD_ERR( 1085 "error: Adding the MAC ADDR failed: err = %d", ret); 1086 return 0; 1087 } 1088 1089 static void 1090 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1091 uint32_t index) 1092 { 1093 int ret; 1094 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1095 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1096 struct rte_eth_dev_data *data = dev->data; 1097 struct ether_addr *macaddr; 1098 1099 PMD_INIT_FUNC_TRACE(); 1100 1101 macaddr = &data->mac_addrs[index]; 1102 1103 if (dpni == NULL) { 1104 DPAA2_PMD_ERR("dpni is NULL"); 1105 return; 1106 } 1107 1108 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1109 priv->token, macaddr->addr_bytes); 1110 if (ret) 1111 DPAA2_PMD_ERR( 1112 "error: Removing the MAC ADDR failed: err = %d", ret); 1113 } 1114 1115 static int 1116 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1117 struct ether_addr *addr) 1118 { 1119 int ret; 1120 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1121 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1122 1123 PMD_INIT_FUNC_TRACE(); 1124 1125 if (dpni == NULL) { 1126 DPAA2_PMD_ERR("dpni is NULL"); 1127 return -EINVAL; 1128 } 1129 1130 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1131 priv->token, addr->addr_bytes); 1132 1133 if (ret) 1134 DPAA2_PMD_ERR( 1135 "error: Setting the MAC ADDR failed %d", ret); 1136 1137 return ret; 1138 } 1139 1140 static 1141 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1142 struct rte_eth_stats *stats) 1143 { 1144 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1145 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1146 int32_t retcode; 1147 uint8_t page0 = 0, page1 = 1, page2 = 2; 1148 union dpni_statistics value; 1149 int i; 1150 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1151 1152 memset(&value, 0, sizeof(union dpni_statistics)); 1153 1154 PMD_INIT_FUNC_TRACE(); 1155 1156 if (!dpni) { 1157 DPAA2_PMD_ERR("dpni is NULL"); 1158 return -EINVAL; 1159 } 1160 1161 if (!stats) { 1162 DPAA2_PMD_ERR("stats is NULL"); 1163 return -EINVAL; 1164 } 1165 1166 /*Get Counters from page_0*/ 1167 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1168 page0, 0, &value); 1169 if (retcode) 1170 goto err; 1171 1172 stats->ipackets = value.page_0.ingress_all_frames; 1173 stats->ibytes = value.page_0.ingress_all_bytes; 1174 1175 /*Get Counters from page_1*/ 1176 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1177 page1, 0, &value); 1178 if (retcode) 1179 goto err; 1180 1181 stats->opackets = value.page_1.egress_all_frames; 1182 stats->obytes = value.page_1.egress_all_bytes; 1183 1184 /*Get Counters from page_2*/ 1185 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1186 page2, 0, &value); 1187 if (retcode) 1188 goto err; 1189 1190 /* Ingress drop frame count due to configured rules */ 1191 stats->ierrors = value.page_2.ingress_filtered_frames; 1192 /* Ingress drop frame count due to error */ 1193 stats->ierrors += value.page_2.ingress_discarded_frames; 1194 1195 stats->oerrors = value.page_2.egress_discarded_frames; 1196 stats->imissed = value.page_2.ingress_nobuffer_discards; 1197 1198 /* Fill in per queue stats */ 1199 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1200 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1201 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1202 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1203 if (dpaa2_rxq) 1204 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1205 if (dpaa2_txq) 1206 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1207 1208 /* Byte counting is not implemented */ 1209 stats->q_ibytes[i] = 0; 1210 stats->q_obytes[i] = 0; 1211 } 1212 1213 return 0; 1214 1215 err: 1216 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1217 return retcode; 1218 }; 1219 1220 static int 1221 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1222 unsigned int n) 1223 { 1224 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1225 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1226 int32_t retcode; 1227 union dpni_statistics value[3] = {}; 1228 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1229 1230 if (n < num) 1231 return num; 1232 1233 if (xstats == NULL) 1234 return 0; 1235 1236 /* Get Counters from page_0*/ 1237 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1238 0, 0, &value[0]); 1239 if (retcode) 1240 goto err; 1241 1242 /* Get Counters from page_1*/ 1243 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1244 1, 0, &value[1]); 1245 if (retcode) 1246 goto err; 1247 1248 /* Get Counters from page_2*/ 1249 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1250 2, 0, &value[2]); 1251 if (retcode) 1252 goto err; 1253 1254 for (i = 0; i < num; i++) { 1255 xstats[i].id = i; 1256 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1257 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1258 } 1259 return i; 1260 err: 1261 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1262 return retcode; 1263 } 1264 1265 static int 1266 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1267 struct rte_eth_xstat_name *xstats_names, 1268 unsigned int limit) 1269 { 1270 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1271 1272 if (limit < stat_cnt) 1273 return stat_cnt; 1274 1275 if (xstats_names != NULL) 1276 for (i = 0; i < stat_cnt; i++) 1277 snprintf(xstats_names[i].name, 1278 sizeof(xstats_names[i].name), 1279 "%s", 1280 dpaa2_xstats_strings[i].name); 1281 1282 return stat_cnt; 1283 } 1284 1285 static int 1286 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1287 uint64_t *values, unsigned int n) 1288 { 1289 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1290 uint64_t values_copy[stat_cnt]; 1291 1292 if (!ids) { 1293 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1294 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1295 int32_t retcode; 1296 union dpni_statistics value[3] = {}; 1297 1298 if (n < stat_cnt) 1299 return stat_cnt; 1300 1301 if (!values) 1302 return 0; 1303 1304 /* Get Counters from page_0*/ 1305 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1306 0, 0, &value[0]); 1307 if (retcode) 1308 return 0; 1309 1310 /* Get Counters from page_1*/ 1311 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1312 1, 0, &value[1]); 1313 if (retcode) 1314 return 0; 1315 1316 /* Get Counters from page_2*/ 1317 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1318 2, 0, &value[2]); 1319 if (retcode) 1320 return 0; 1321 1322 for (i = 0; i < stat_cnt; i++) { 1323 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1324 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1325 } 1326 return stat_cnt; 1327 } 1328 1329 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1330 1331 for (i = 0; i < n; i++) { 1332 if (ids[i] >= stat_cnt) { 1333 DPAA2_PMD_ERR("xstats id value isn't valid"); 1334 return -1; 1335 } 1336 values[i] = values_copy[ids[i]]; 1337 } 1338 return n; 1339 } 1340 1341 static int 1342 dpaa2_xstats_get_names_by_id( 1343 struct rte_eth_dev *dev, 1344 struct rte_eth_xstat_name *xstats_names, 1345 const uint64_t *ids, 1346 unsigned int limit) 1347 { 1348 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1349 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1350 1351 if (!ids) 1352 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1353 1354 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1355 1356 for (i = 0; i < limit; i++) { 1357 if (ids[i] >= stat_cnt) { 1358 DPAA2_PMD_ERR("xstats id value isn't valid"); 1359 return -1; 1360 } 1361 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1362 } 1363 return limit; 1364 } 1365 1366 static void 1367 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1368 { 1369 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1370 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1371 int32_t retcode; 1372 int i; 1373 struct dpaa2_queue *dpaa2_q; 1374 1375 PMD_INIT_FUNC_TRACE(); 1376 1377 if (dpni == NULL) { 1378 DPAA2_PMD_ERR("dpni is NULL"); 1379 return; 1380 } 1381 1382 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1383 if (retcode) 1384 goto error; 1385 1386 /* Reset the per queue stats in dpaa2_queue structure */ 1387 for (i = 0; i < priv->nb_rx_queues; i++) { 1388 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1389 if (dpaa2_q) 1390 dpaa2_q->rx_pkts = 0; 1391 } 1392 1393 for (i = 0; i < priv->nb_tx_queues; i++) { 1394 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1395 if (dpaa2_q) 1396 dpaa2_q->tx_pkts = 0; 1397 } 1398 1399 return; 1400 1401 error: 1402 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1403 return; 1404 }; 1405 1406 /* return 0 means link status changed, -1 means not changed */ 1407 static int 1408 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1409 int wait_to_complete __rte_unused) 1410 { 1411 int ret; 1412 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1413 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1414 struct rte_eth_link link; 1415 struct dpni_link_state state = {0}; 1416 1417 if (dpni == NULL) { 1418 DPAA2_PMD_ERR("dpni is NULL"); 1419 return 0; 1420 } 1421 1422 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1423 if (ret < 0) { 1424 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1425 return -1; 1426 } 1427 1428 memset(&link, 0, sizeof(struct rte_eth_link)); 1429 link.link_status = state.up; 1430 link.link_speed = state.rate; 1431 1432 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1433 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1434 else 1435 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1436 1437 ret = rte_eth_linkstatus_set(dev, &link); 1438 if (ret == -1) 1439 DPAA2_PMD_DEBUG("No change in status"); 1440 else 1441 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1442 link.link_status ? "Up" : "Down"); 1443 1444 return ret; 1445 } 1446 1447 /** 1448 * Toggle the DPNI to enable, if not already enabled. 1449 * This is not strictly PHY up/down - it is more of logical toggling. 1450 */ 1451 static int 1452 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1453 { 1454 int ret = -EINVAL; 1455 struct dpaa2_dev_priv *priv; 1456 struct fsl_mc_io *dpni; 1457 int en = 0; 1458 struct dpni_link_state state = {0}; 1459 1460 priv = dev->data->dev_private; 1461 dpni = (struct fsl_mc_io *)priv->hw; 1462 1463 if (dpni == NULL) { 1464 DPAA2_PMD_ERR("dpni is NULL"); 1465 return ret; 1466 } 1467 1468 /* Check if DPNI is currently enabled */ 1469 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1470 if (ret) { 1471 /* Unable to obtain dpni status; Not continuing */ 1472 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1473 return -EINVAL; 1474 } 1475 1476 /* Enable link if not already enabled */ 1477 if (!en) { 1478 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1479 if (ret) { 1480 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1481 return -EINVAL; 1482 } 1483 } 1484 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1485 if (ret < 0) { 1486 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1487 return -1; 1488 } 1489 1490 /* changing tx burst function to start enqueues */ 1491 dev->tx_pkt_burst = dpaa2_dev_tx; 1492 dev->data->dev_link.link_status = state.up; 1493 1494 if (state.up) 1495 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1496 else 1497 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1498 return ret; 1499 } 1500 1501 /** 1502 * Toggle the DPNI to disable, if not already disabled. 1503 * This is not strictly PHY up/down - it is more of logical toggling. 1504 */ 1505 static int 1506 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1507 { 1508 int ret = -EINVAL; 1509 struct dpaa2_dev_priv *priv; 1510 struct fsl_mc_io *dpni; 1511 int dpni_enabled = 0; 1512 int retries = 10; 1513 1514 PMD_INIT_FUNC_TRACE(); 1515 1516 priv = dev->data->dev_private; 1517 dpni = (struct fsl_mc_io *)priv->hw; 1518 1519 if (dpni == NULL) { 1520 DPAA2_PMD_ERR("Device has not yet been configured"); 1521 return ret; 1522 } 1523 1524 /*changing tx burst function to avoid any more enqueues */ 1525 dev->tx_pkt_burst = dummy_dev_tx; 1526 1527 /* Loop while dpni_disable() attempts to drain the egress FQs 1528 * and confirm them back to us. 1529 */ 1530 do { 1531 ret = dpni_disable(dpni, 0, priv->token); 1532 if (ret) { 1533 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1534 return ret; 1535 } 1536 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1537 if (ret) { 1538 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1539 return ret; 1540 } 1541 if (dpni_enabled) 1542 /* Allow the MC some slack */ 1543 rte_delay_us(100 * 1000); 1544 } while (dpni_enabled && --retries); 1545 1546 if (!retries) { 1547 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1548 /* todo- we may have to manually cleanup queues. 1549 */ 1550 } else { 1551 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1552 dev->data->port_id); 1553 } 1554 1555 dev->data->dev_link.link_status = 0; 1556 1557 return ret; 1558 } 1559 1560 static int 1561 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1562 { 1563 int ret = -EINVAL; 1564 struct dpaa2_dev_priv *priv; 1565 struct fsl_mc_io *dpni; 1566 struct dpni_link_state state = {0}; 1567 1568 PMD_INIT_FUNC_TRACE(); 1569 1570 priv = dev->data->dev_private; 1571 dpni = (struct fsl_mc_io *)priv->hw; 1572 1573 if (dpni == NULL || fc_conf == NULL) { 1574 DPAA2_PMD_ERR("device not configured"); 1575 return ret; 1576 } 1577 1578 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1579 if (ret) { 1580 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 1581 return ret; 1582 } 1583 1584 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 1585 if (state.options & DPNI_LINK_OPT_PAUSE) { 1586 /* DPNI_LINK_OPT_PAUSE set 1587 * if ASYM_PAUSE not set, 1588 * RX Side flow control (handle received Pause frame) 1589 * TX side flow control (send Pause frame) 1590 * if ASYM_PAUSE set, 1591 * RX Side flow control (handle received Pause frame) 1592 * No TX side flow control (send Pause frame disabled) 1593 */ 1594 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 1595 fc_conf->mode = RTE_FC_FULL; 1596 else 1597 fc_conf->mode = RTE_FC_RX_PAUSE; 1598 } else { 1599 /* DPNI_LINK_OPT_PAUSE not set 1600 * if ASYM_PAUSE set, 1601 * TX side flow control (send Pause frame) 1602 * No RX side flow control (No action on pause frame rx) 1603 * if ASYM_PAUSE not set, 1604 * Flow control disabled 1605 */ 1606 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 1607 fc_conf->mode = RTE_FC_TX_PAUSE; 1608 else 1609 fc_conf->mode = RTE_FC_NONE; 1610 } 1611 1612 return ret; 1613 } 1614 1615 static int 1616 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1617 { 1618 int ret = -EINVAL; 1619 struct dpaa2_dev_priv *priv; 1620 struct fsl_mc_io *dpni; 1621 struct dpni_link_state state = {0}; 1622 struct dpni_link_cfg cfg = {0}; 1623 1624 PMD_INIT_FUNC_TRACE(); 1625 1626 priv = dev->data->dev_private; 1627 dpni = (struct fsl_mc_io *)priv->hw; 1628 1629 if (dpni == NULL) { 1630 DPAA2_PMD_ERR("dpni is NULL"); 1631 return ret; 1632 } 1633 1634 /* It is necessary to obtain the current state before setting fc_conf 1635 * as MC would return error in case rate, autoneg or duplex values are 1636 * different. 1637 */ 1638 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1639 if (ret) { 1640 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 1641 return -1; 1642 } 1643 1644 /* Disable link before setting configuration */ 1645 dpaa2_dev_set_link_down(dev); 1646 1647 /* Based on fc_conf, update cfg */ 1648 cfg.rate = state.rate; 1649 cfg.options = state.options; 1650 1651 /* update cfg with fc_conf */ 1652 switch (fc_conf->mode) { 1653 case RTE_FC_FULL: 1654 /* Full flow control; 1655 * OPT_PAUSE set, ASYM_PAUSE not set 1656 */ 1657 cfg.options |= DPNI_LINK_OPT_PAUSE; 1658 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1659 break; 1660 case RTE_FC_TX_PAUSE: 1661 /* Enable RX flow control 1662 * OPT_PAUSE not set; 1663 * ASYM_PAUSE set; 1664 */ 1665 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1666 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1667 break; 1668 case RTE_FC_RX_PAUSE: 1669 /* Enable TX Flow control 1670 * OPT_PAUSE set 1671 * ASYM_PAUSE set 1672 */ 1673 cfg.options |= DPNI_LINK_OPT_PAUSE; 1674 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1675 break; 1676 case RTE_FC_NONE: 1677 /* Disable Flow control 1678 * OPT_PAUSE not set 1679 * ASYM_PAUSE not set 1680 */ 1681 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1682 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1683 break; 1684 default: 1685 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 1686 fc_conf->mode); 1687 return -1; 1688 } 1689 1690 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 1691 if (ret) 1692 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 1693 ret); 1694 1695 /* Enable link */ 1696 dpaa2_dev_set_link_up(dev); 1697 1698 return ret; 1699 } 1700 1701 static int 1702 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 1703 struct rte_eth_rss_conf *rss_conf) 1704 { 1705 struct rte_eth_dev_data *data = dev->data; 1706 struct rte_eth_conf *eth_conf = &data->dev_conf; 1707 int ret; 1708 1709 PMD_INIT_FUNC_TRACE(); 1710 1711 if (rss_conf->rss_hf) { 1712 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf); 1713 if (ret) { 1714 DPAA2_PMD_ERR("Unable to set flow dist"); 1715 return ret; 1716 } 1717 } else { 1718 ret = dpaa2_remove_flow_dist(dev, 0); 1719 if (ret) { 1720 DPAA2_PMD_ERR("Unable to remove flow dist"); 1721 return ret; 1722 } 1723 } 1724 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1725 return 0; 1726 } 1727 1728 static int 1729 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1730 struct rte_eth_rss_conf *rss_conf) 1731 { 1732 struct rte_eth_dev_data *data = dev->data; 1733 struct rte_eth_conf *eth_conf = &data->dev_conf; 1734 1735 /* dpaa2 does not support rss_key, so length should be 0*/ 1736 rss_conf->rss_key_len = 0; 1737 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1738 return 0; 1739 } 1740 1741 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 1742 int eth_rx_queue_id, 1743 uint16_t dpcon_id, 1744 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1745 { 1746 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 1747 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw; 1748 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 1749 uint8_t flow_id = dpaa2_ethq->flow_id; 1750 struct dpni_queue cfg; 1751 uint8_t options; 1752 int ret; 1753 1754 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 1755 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 1756 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 1757 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 1758 else 1759 return -EINVAL; 1760 1761 memset(&cfg, 0, sizeof(struct dpni_queue)); 1762 options = DPNI_QUEUE_OPT_DEST; 1763 cfg.destination.type = DPNI_DEST_DPCON; 1764 cfg.destination.id = dpcon_id; 1765 cfg.destination.priority = queue_conf->ev.priority; 1766 1767 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 1768 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 1769 cfg.destination.hold_active = 1; 1770 } 1771 1772 options |= DPNI_QUEUE_OPT_USER_CTX; 1773 cfg.user_context = (size_t)(dpaa2_ethq); 1774 1775 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 1776 dpaa2_ethq->tc_index, flow_id, options, &cfg); 1777 if (ret) { 1778 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 1779 return ret; 1780 } 1781 1782 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1783 1784 return 0; 1785 } 1786 1787 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 1788 int eth_rx_queue_id) 1789 { 1790 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 1791 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw; 1792 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 1793 uint8_t flow_id = dpaa2_ethq->flow_id; 1794 struct dpni_queue cfg; 1795 uint8_t options; 1796 int ret; 1797 1798 memset(&cfg, 0, sizeof(struct dpni_queue)); 1799 options = DPNI_QUEUE_OPT_DEST; 1800 cfg.destination.type = DPNI_DEST_NONE; 1801 1802 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 1803 dpaa2_ethq->tc_index, flow_id, options, &cfg); 1804 if (ret) 1805 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 1806 1807 return ret; 1808 } 1809 1810 static struct eth_dev_ops dpaa2_ethdev_ops = { 1811 .dev_configure = dpaa2_eth_dev_configure, 1812 .dev_start = dpaa2_dev_start, 1813 .dev_stop = dpaa2_dev_stop, 1814 .dev_close = dpaa2_dev_close, 1815 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 1816 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 1817 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 1818 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 1819 .dev_set_link_up = dpaa2_dev_set_link_up, 1820 .dev_set_link_down = dpaa2_dev_set_link_down, 1821 .link_update = dpaa2_dev_link_update, 1822 .stats_get = dpaa2_dev_stats_get, 1823 .xstats_get = dpaa2_dev_xstats_get, 1824 .xstats_get_by_id = dpaa2_xstats_get_by_id, 1825 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 1826 .xstats_get_names = dpaa2_xstats_get_names, 1827 .stats_reset = dpaa2_dev_stats_reset, 1828 .xstats_reset = dpaa2_dev_stats_reset, 1829 .fw_version_get = dpaa2_fw_version_get, 1830 .dev_infos_get = dpaa2_dev_info_get, 1831 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 1832 .mtu_set = dpaa2_dev_mtu_set, 1833 .vlan_filter_set = dpaa2_vlan_filter_set, 1834 .vlan_offload_set = dpaa2_vlan_offload_set, 1835 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 1836 .rx_queue_release = dpaa2_dev_rx_queue_release, 1837 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 1838 .tx_queue_release = dpaa2_dev_tx_queue_release, 1839 .rx_queue_count = dpaa2_dev_rx_queue_count, 1840 .flow_ctrl_get = dpaa2_flow_ctrl_get, 1841 .flow_ctrl_set = dpaa2_flow_ctrl_set, 1842 .mac_addr_add = dpaa2_dev_add_mac_addr, 1843 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 1844 .mac_addr_set = dpaa2_dev_set_mac_addr, 1845 .rss_hash_update = dpaa2_dev_rss_hash_update, 1846 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 1847 }; 1848 1849 /* Populate the mac address from physically available (u-boot/firmware) and/or 1850 * one set by higher layers like MC (restool) etc. 1851 * Returns the table of MAC entries (multiple entries) 1852 */ 1853 static int 1854 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 1855 struct ether_addr *mac_entry) 1856 { 1857 int ret; 1858 struct ether_addr phy_mac, prime_mac; 1859 1860 memset(&phy_mac, 0, sizeof(struct ether_addr)); 1861 memset(&prime_mac, 0, sizeof(struct ether_addr)); 1862 1863 /* Get the physical device MAC address */ 1864 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 1865 phy_mac.addr_bytes); 1866 if (ret) { 1867 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 1868 goto cleanup; 1869 } 1870 1871 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 1872 prime_mac.addr_bytes); 1873 if (ret) { 1874 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 1875 goto cleanup; 1876 } 1877 1878 /* Now that both MAC have been obtained, do: 1879 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 1880 * and return phy 1881 * If empty_mac(phy), return prime. 1882 * if both are empty, create random MAC, set as prime and return 1883 */ 1884 if (!is_zero_ether_addr(&phy_mac)) { 1885 /* If the addresses are not same, overwrite prime */ 1886 if (!is_same_ether_addr(&phy_mac, &prime_mac)) { 1887 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 1888 priv->token, 1889 phy_mac.addr_bytes); 1890 if (ret) { 1891 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 1892 ret); 1893 goto cleanup; 1894 } 1895 memcpy(&prime_mac, &phy_mac, sizeof(struct ether_addr)); 1896 } 1897 } else if (is_zero_ether_addr(&prime_mac)) { 1898 /* In case phys and prime, both are zero, create random MAC */ 1899 eth_random_addr(prime_mac.addr_bytes); 1900 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 1901 priv->token, 1902 prime_mac.addr_bytes); 1903 if (ret) { 1904 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 1905 goto cleanup; 1906 } 1907 } 1908 1909 /* prime_mac the final MAC address */ 1910 memcpy(mac_entry, &prime_mac, sizeof(struct ether_addr)); 1911 return 0; 1912 1913 cleanup: 1914 return -1; 1915 } 1916 1917 static int 1918 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 1919 { 1920 struct rte_device *dev = eth_dev->device; 1921 struct rte_dpaa2_device *dpaa2_dev; 1922 struct fsl_mc_io *dpni_dev; 1923 struct dpni_attr attr; 1924 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 1925 struct dpni_buffer_layout layout; 1926 int ret, hw_id; 1927 1928 PMD_INIT_FUNC_TRACE(); 1929 1930 /* For secondary processes, the primary has done all the work */ 1931 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1932 /* In case of secondary, only burst and ops API need to be 1933 * plugged. 1934 */ 1935 eth_dev->dev_ops = &dpaa2_ethdev_ops; 1936 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 1937 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 1938 return 0; 1939 } 1940 1941 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 1942 1943 hw_id = dpaa2_dev->object_id; 1944 1945 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 1946 if (!dpni_dev) { 1947 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 1948 return -1; 1949 } 1950 1951 dpni_dev->regs = rte_mcp_ptr_list[0]; 1952 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 1953 if (ret) { 1954 DPAA2_PMD_ERR( 1955 "Failure in opening dpni@%d with err code %d", 1956 hw_id, ret); 1957 rte_free(dpni_dev); 1958 return -1; 1959 } 1960 1961 /* Clean the device first */ 1962 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 1963 if (ret) { 1964 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 1965 hw_id, ret); 1966 goto init_err; 1967 } 1968 1969 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 1970 if (ret) { 1971 DPAA2_PMD_ERR( 1972 "Failure in get dpni@%d attribute, err code %d", 1973 hw_id, ret); 1974 goto init_err; 1975 } 1976 1977 priv->num_rx_tc = attr.num_rx_tcs; 1978 1979 /* Resetting the "num_rx_queues" to equal number of queues in first TC 1980 * as only one TC is supported on Rx Side. Once Multiple TCs will be 1981 * in use for Rx processing then this will be changed or removed. 1982 */ 1983 priv->nb_rx_queues = attr.num_queues; 1984 1985 /* Using number of TX queues as number of TX TCs */ 1986 priv->nb_tx_queues = attr.num_tx_tcs; 1987 1988 DPAA2_PMD_DEBUG("RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d", 1989 priv->num_rx_tc, priv->nb_rx_queues, 1990 priv->nb_tx_queues); 1991 1992 priv->hw = dpni_dev; 1993 priv->hw_id = hw_id; 1994 priv->options = attr.options; 1995 priv->max_mac_filters = attr.mac_filter_entries; 1996 priv->max_vlan_filters = attr.vlan_filter_entries; 1997 priv->flags = 0; 1998 1999 /* Allocate memory for hardware structure for queues */ 2000 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2001 if (ret) { 2002 DPAA2_PMD_ERR("Queue allocation Failed"); 2003 goto init_err; 2004 } 2005 2006 /* Allocate memory for storing MAC addresses. 2007 * Table of mac_filter_entries size is allocated so that RTE ether lib 2008 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2009 */ 2010 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2011 ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2012 if (eth_dev->data->mac_addrs == NULL) { 2013 DPAA2_PMD_ERR( 2014 "Failed to allocate %d bytes needed to store MAC addresses", 2015 ETHER_ADDR_LEN * attr.mac_filter_entries); 2016 ret = -ENOMEM; 2017 goto init_err; 2018 } 2019 2020 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2021 if (ret) { 2022 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2023 rte_free(eth_dev->data->mac_addrs); 2024 eth_dev->data->mac_addrs = NULL; 2025 goto init_err; 2026 } 2027 2028 /* ... tx buffer layout ... */ 2029 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2030 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2031 layout.pass_frame_status = 1; 2032 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2033 DPNI_QUEUE_TX, &layout); 2034 if (ret) { 2035 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2036 goto init_err; 2037 } 2038 2039 /* ... tx-conf and error buffer layout ... */ 2040 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2041 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2042 layout.pass_frame_status = 1; 2043 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2044 DPNI_QUEUE_TX_CONFIRM, &layout); 2045 if (ret) { 2046 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2047 ret); 2048 goto init_err; 2049 } 2050 2051 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2052 2053 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2054 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2055 2056 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2057 return 0; 2058 init_err: 2059 dpaa2_dev_uninit(eth_dev); 2060 return ret; 2061 } 2062 2063 static int 2064 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev) 2065 { 2066 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2067 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 2068 int ret; 2069 2070 PMD_INIT_FUNC_TRACE(); 2071 2072 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2073 return 0; 2074 2075 if (!dpni) { 2076 DPAA2_PMD_WARN("Already closed or not started"); 2077 return -1; 2078 } 2079 2080 dpaa2_dev_close(eth_dev); 2081 2082 dpaa2_free_rx_tx_queues(eth_dev); 2083 2084 /* Close the device at underlying layer*/ 2085 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 2086 if (ret) { 2087 DPAA2_PMD_ERR( 2088 "Failure closing dpni device with err code %d", 2089 ret); 2090 } 2091 2092 /* Free the allocated memory for ethernet private data and dpni*/ 2093 priv->hw = NULL; 2094 rte_free(dpni); 2095 2096 eth_dev->dev_ops = NULL; 2097 eth_dev->rx_pkt_burst = NULL; 2098 eth_dev->tx_pkt_burst = NULL; 2099 2100 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name); 2101 return 0; 2102 } 2103 2104 static int 2105 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2106 struct rte_dpaa2_device *dpaa2_dev) 2107 { 2108 struct rte_eth_dev *eth_dev; 2109 int diag; 2110 2111 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2112 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2113 if (!eth_dev) 2114 return -ENODEV; 2115 eth_dev->data->dev_private = rte_zmalloc( 2116 "ethdev private structure", 2117 sizeof(struct dpaa2_dev_priv), 2118 RTE_CACHE_LINE_SIZE); 2119 if (eth_dev->data->dev_private == NULL) { 2120 DPAA2_PMD_CRIT( 2121 "Unable to allocate memory for private data"); 2122 rte_eth_dev_release_port(eth_dev); 2123 return -ENOMEM; 2124 } 2125 } else { 2126 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2127 if (!eth_dev) 2128 return -ENODEV; 2129 } 2130 2131 eth_dev->device = &dpaa2_dev->device; 2132 2133 dpaa2_dev->eth_dev = eth_dev; 2134 eth_dev->data->rx_mbuf_alloc_failed = 0; 2135 2136 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2137 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2138 2139 /* Invoke PMD device initialization function */ 2140 diag = dpaa2_dev_init(eth_dev); 2141 if (diag == 0) { 2142 rte_eth_dev_probing_finish(eth_dev); 2143 return 0; 2144 } 2145 2146 rte_eth_dev_release_port(eth_dev); 2147 return diag; 2148 } 2149 2150 static int 2151 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2152 { 2153 struct rte_eth_dev *eth_dev; 2154 2155 eth_dev = dpaa2_dev->eth_dev; 2156 dpaa2_dev_uninit(eth_dev); 2157 2158 rte_eth_dev_release_port(eth_dev); 2159 2160 return 0; 2161 } 2162 2163 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2164 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2165 .drv_type = DPAA2_ETH, 2166 .probe = rte_dpaa2_probe, 2167 .remove = rte_dpaa2_remove, 2168 }; 2169 2170 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2171 2172 RTE_INIT(dpaa2_pmd_init_log) 2173 { 2174 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2"); 2175 if (dpaa2_logtype_pmd >= 0) 2176 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE); 2177 } 2178