1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2021 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <dev_driver.h> 19 #include <bus_fslmc_driver.h> 20 #include <rte_flow_driver.h> 21 #include "rte_dpaa2_mempool.h" 22 23 #include "dpaa2_pmd_logs.h" 24 #include <fslmc_vfio.h> 25 #include <dpaa2_hw_pvt.h> 26 #include <dpaa2_hw_mempool.h> 27 #include <dpaa2_hw_dpio.h> 28 #include <mc/fsl_dpmng.h> 29 #include "dpaa2_ethdev.h" 30 #include "dpaa2_sparser.h" 31 #include <fsl_qbman_debug.h> 32 33 #define DRIVER_LOOPBACK_MODE "drv_loopback" 34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 35 #define DRIVER_TX_CONF "drv_tx_conf" 36 #define DRIVER_ERROR_QUEUE "drv_err_queue" 37 #define CHECK_INTERVAL 100 /* 100ms */ 38 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 39 40 /* Supported Rx offloads */ 41 static uint64_t dev_rx_offloads_sup = 42 RTE_ETH_RX_OFFLOAD_CHECKSUM | 43 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | 44 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 45 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | 46 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 47 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 48 RTE_ETH_RX_OFFLOAD_TIMESTAMP; 49 50 /* Rx offloads which cannot be disabled */ 51 static uint64_t dev_rx_offloads_nodis = 52 RTE_ETH_RX_OFFLOAD_RSS_HASH | 53 RTE_ETH_RX_OFFLOAD_SCATTER; 54 55 /* Supported Tx offloads */ 56 static uint64_t dev_tx_offloads_sup = 57 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 58 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 59 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 60 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 61 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 62 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 63 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 64 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 69 70 /* enable timestamp in mbuf */ 71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 72 uint64_t dpaa2_timestamp_rx_dynflag; 73 int dpaa2_timestamp_dynfield_offset = -1; 74 75 /* Enable error queue */ 76 bool dpaa2_enable_err_queue; 77 78 #define MAX_NB_RX_DESC 11264 79 int total_nb_rx_desc; 80 81 int dpaa2_valid_dev; 82 struct rte_mempool *dpaa2_tx_sg_pool; 83 84 struct rte_dpaa2_xstats_name_off { 85 char name[RTE_ETH_XSTATS_NAME_SIZE]; 86 uint8_t page_id; /* dpni statistics page id */ 87 uint8_t stats_id; /* stats id in the given page */ 88 }; 89 90 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 91 {"ingress_multicast_frames", 0, 2}, 92 {"ingress_multicast_bytes", 0, 3}, 93 {"ingress_broadcast_frames", 0, 4}, 94 {"ingress_broadcast_bytes", 0, 5}, 95 {"egress_multicast_frames", 1, 2}, 96 {"egress_multicast_bytes", 1, 3}, 97 {"egress_broadcast_frames", 1, 4}, 98 {"egress_broadcast_bytes", 1, 5}, 99 {"ingress_filtered_frames", 2, 0}, 100 {"ingress_discarded_frames", 2, 1}, 101 {"ingress_nobuffer_discards", 2, 2}, 102 {"egress_discarded_frames", 2, 3}, 103 {"egress_confirmed_frames", 2, 4}, 104 {"cgr_reject_frames", 4, 0}, 105 {"cgr_reject_bytes", 4, 1}, 106 }; 107 108 static struct rte_dpaa2_driver rte_dpaa2_pmd; 109 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 110 int wait_to_complete); 111 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 112 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 113 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 114 115 static int 116 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 117 { 118 int ret; 119 struct dpaa2_dev_priv *priv = dev->data->dev_private; 120 struct fsl_mc_io *dpni = dev->process_private; 121 122 PMD_INIT_FUNC_TRACE(); 123 124 if (dpni == NULL) { 125 DPAA2_PMD_ERR("dpni is NULL"); 126 return -1; 127 } 128 129 if (on) 130 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 131 vlan_id, 0, 0, 0); 132 else 133 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 134 priv->token, vlan_id); 135 136 if (ret < 0) 137 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 138 ret, vlan_id, priv->hw_id); 139 140 return ret; 141 } 142 143 static int 144 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 145 { 146 struct dpaa2_dev_priv *priv = dev->data->dev_private; 147 struct fsl_mc_io *dpni = dev->process_private; 148 int ret = 0; 149 150 PMD_INIT_FUNC_TRACE(); 151 152 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 153 /* VLAN Filter not available */ 154 if (!priv->max_vlan_filters) { 155 DPAA2_PMD_INFO("VLAN filter not available"); 156 return -ENOTSUP; 157 } 158 159 if (dev->data->dev_conf.rxmode.offloads & 160 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 161 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 162 priv->token, true); 163 else 164 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 165 priv->token, false); 166 if (ret < 0) 167 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 168 } 169 170 return ret; 171 } 172 173 static int 174 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 175 enum rte_vlan_type vlan_type __rte_unused, 176 uint16_t tpid) 177 { 178 struct dpaa2_dev_priv *priv = dev->data->dev_private; 179 struct fsl_mc_io *dpni = dev->process_private; 180 int ret = -ENOTSUP; 181 182 PMD_INIT_FUNC_TRACE(); 183 184 /* nothing to be done for standard vlan tpids */ 185 if (tpid == 0x8100 || tpid == 0x88A8) 186 return 0; 187 188 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 189 priv->token, tpid); 190 if (ret < 0) 191 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 192 /* if already configured tpids, remove them first */ 193 if (ret == -EBUSY) { 194 struct dpni_custom_tpid_cfg tpid_list = {0}; 195 196 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 197 priv->token, &tpid_list); 198 if (ret < 0) 199 goto fail; 200 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 201 priv->token, tpid_list.tpid1); 202 if (ret < 0) 203 goto fail; 204 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 205 priv->token, tpid); 206 } 207 fail: 208 return ret; 209 } 210 211 static int 212 dpaa2_fw_version_get(struct rte_eth_dev *dev, 213 char *fw_version, 214 size_t fw_size) 215 { 216 int ret; 217 struct fsl_mc_io *dpni = dev->process_private; 218 struct mc_soc_version mc_plat_info = {0}; 219 struct mc_version mc_ver_info = {0}; 220 221 PMD_INIT_FUNC_TRACE(); 222 223 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 224 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 225 226 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 227 DPAA2_PMD_WARN("\tmc_get_version failed"); 228 229 ret = snprintf(fw_version, fw_size, 230 "%x-%d.%d.%d", 231 mc_plat_info.svr, 232 mc_ver_info.major, 233 mc_ver_info.minor, 234 mc_ver_info.revision); 235 if (ret < 0) 236 return -EINVAL; 237 238 ret += 1; /* add the size of '\0' */ 239 if (fw_size < (size_t)ret) 240 return ret; 241 else 242 return 0; 243 } 244 245 static int 246 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 247 { 248 struct dpaa2_dev_priv *priv = dev->data->dev_private; 249 250 PMD_INIT_FUNC_TRACE(); 251 252 dev_info->max_mac_addrs = priv->max_mac_filters; 253 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 254 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 255 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 256 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 257 dev_info->rx_offload_capa = dev_rx_offloads_sup | 258 dev_rx_offloads_nodis; 259 dev_info->tx_offload_capa = dev_tx_offloads_sup | 260 dev_tx_offloads_nodis; 261 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | 262 RTE_ETH_LINK_SPEED_2_5G | 263 RTE_ETH_LINK_SPEED_10G; 264 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 265 266 dev_info->max_hash_mac_addrs = 0; 267 dev_info->max_vfs = 0; 268 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 269 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 270 271 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 272 /* same is rx size for best perf */ 273 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 274 275 dev_info->default_rxportconf.nb_queues = 1; 276 dev_info->default_txportconf.nb_queues = 1; 277 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 278 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 279 280 if (dpaa2_svr_family == SVR_LX2160A) { 281 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G | 282 RTE_ETH_LINK_SPEED_40G | 283 RTE_ETH_LINK_SPEED_50G | 284 RTE_ETH_LINK_SPEED_100G; 285 } 286 287 return 0; 288 } 289 290 static int 291 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 292 __rte_unused uint16_t queue_id, 293 struct rte_eth_burst_mode *mode) 294 { 295 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 296 int ret = -EINVAL; 297 unsigned int i; 298 const struct burst_info { 299 uint64_t flags; 300 const char *output; 301 } rx_offload_map[] = { 302 {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 303 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 304 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 305 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 306 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 307 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 308 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 309 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}, 310 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"} 311 }; 312 313 /* Update Rx offload info */ 314 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 315 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 316 snprintf(mode->info, sizeof(mode->info), "%s", 317 rx_offload_map[i].output); 318 ret = 0; 319 break; 320 } 321 } 322 return ret; 323 } 324 325 static int 326 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 327 __rte_unused uint16_t queue_id, 328 struct rte_eth_burst_mode *mode) 329 { 330 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 331 int ret = -EINVAL; 332 unsigned int i; 333 const struct burst_info { 334 uint64_t flags; 335 const char *output; 336 } tx_offload_map[] = { 337 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 338 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 339 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 340 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 341 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 342 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 343 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 344 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 345 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 346 }; 347 348 /* Update Tx offload info */ 349 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 350 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 351 snprintf(mode->info, sizeof(mode->info), "%s", 352 tx_offload_map[i].output); 353 ret = 0; 354 break; 355 } 356 } 357 return ret; 358 } 359 360 static int 361 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 362 { 363 struct dpaa2_dev_priv *priv = dev->data->dev_private; 364 uint16_t dist_idx; 365 uint32_t vq_id; 366 uint8_t num_rxqueue_per_tc; 367 struct dpaa2_queue *mc_q, *mcq; 368 uint32_t tot_queues; 369 int i; 370 struct dpaa2_queue *dpaa2_q; 371 372 PMD_INIT_FUNC_TRACE(); 373 374 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 375 if (priv->flags & DPAA2_TX_CONF_ENABLE) 376 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 377 else 378 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 379 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 380 RTE_CACHE_LINE_SIZE); 381 if (!mc_q) { 382 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 383 return -1; 384 } 385 386 for (i = 0; i < priv->nb_rx_queues; i++) { 387 mc_q->eth_data = dev->data; 388 priv->rx_vq[i] = mc_q++; 389 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 390 dpaa2_q->q_storage = rte_malloc("dq_storage", 391 sizeof(struct queue_storage_info_t), 392 RTE_CACHE_LINE_SIZE); 393 if (!dpaa2_q->q_storage) 394 goto fail; 395 396 memset(dpaa2_q->q_storage, 0, 397 sizeof(struct queue_storage_info_t)); 398 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 399 goto fail; 400 } 401 402 if (dpaa2_enable_err_queue) { 403 priv->rx_err_vq = rte_zmalloc("dpni_rx_err", 404 sizeof(struct dpaa2_queue), 0); 405 if (!priv->rx_err_vq) 406 goto fail; 407 408 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 409 dpaa2_q->q_storage = rte_malloc("err_dq_storage", 410 sizeof(struct queue_storage_info_t) * 411 RTE_MAX_LCORE, 412 RTE_CACHE_LINE_SIZE); 413 if (!dpaa2_q->q_storage) 414 goto fail; 415 416 memset(dpaa2_q->q_storage, 0, 417 sizeof(struct queue_storage_info_t)); 418 for (i = 0; i < RTE_MAX_LCORE; i++) 419 if (dpaa2_alloc_dq_storage(&dpaa2_q->q_storage[i])) 420 goto fail; 421 } 422 423 for (i = 0; i < priv->nb_tx_queues; i++) { 424 mc_q->eth_data = dev->data; 425 mc_q->flow_id = 0xffff; 426 priv->tx_vq[i] = mc_q++; 427 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 428 dpaa2_q->cscn = rte_malloc(NULL, 429 sizeof(struct qbman_result), 16); 430 if (!dpaa2_q->cscn) 431 goto fail_tx; 432 } 433 434 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 435 /*Setup tx confirmation queues*/ 436 for (i = 0; i < priv->nb_tx_queues; i++) { 437 mc_q->eth_data = dev->data; 438 mc_q->tc_index = i; 439 mc_q->flow_id = 0; 440 priv->tx_conf_vq[i] = mc_q++; 441 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 442 dpaa2_q->q_storage = 443 rte_malloc("dq_storage", 444 sizeof(struct queue_storage_info_t), 445 RTE_CACHE_LINE_SIZE); 446 if (!dpaa2_q->q_storage) 447 goto fail_tx_conf; 448 449 memset(dpaa2_q->q_storage, 0, 450 sizeof(struct queue_storage_info_t)); 451 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 452 goto fail_tx_conf; 453 } 454 } 455 456 vq_id = 0; 457 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 458 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 459 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 460 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 461 vq_id++; 462 } 463 464 return 0; 465 fail_tx_conf: 466 i -= 1; 467 while (i >= 0) { 468 dpaa2_q = (struct dpaa2_queue *)priv->tx_conf_vq[i]; 469 rte_free(dpaa2_q->q_storage); 470 priv->tx_conf_vq[i--] = NULL; 471 } 472 i = priv->nb_tx_queues; 473 fail_tx: 474 i -= 1; 475 while (i >= 0) { 476 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 477 rte_free(dpaa2_q->cscn); 478 priv->tx_vq[i--] = NULL; 479 } 480 i = priv->nb_rx_queues; 481 fail: 482 i -= 1; 483 mc_q = priv->rx_vq[0]; 484 while (i >= 0) { 485 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 486 dpaa2_free_dq_storage(dpaa2_q->q_storage); 487 rte_free(dpaa2_q->q_storage); 488 priv->rx_vq[i--] = NULL; 489 } 490 491 if (dpaa2_enable_err_queue) { 492 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 493 if (dpaa2_q->q_storage) 494 dpaa2_free_dq_storage(dpaa2_q->q_storage); 495 rte_free(dpaa2_q->q_storage); 496 } 497 498 rte_free(mc_q); 499 return -1; 500 } 501 502 static void 503 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 504 { 505 struct dpaa2_dev_priv *priv = dev->data->dev_private; 506 struct dpaa2_queue *dpaa2_q; 507 int i; 508 509 PMD_INIT_FUNC_TRACE(); 510 511 /* Queue allocation base */ 512 if (priv->rx_vq[0]) { 513 /* cleaning up queue storage */ 514 for (i = 0; i < priv->nb_rx_queues; i++) { 515 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 516 rte_free(dpaa2_q->q_storage); 517 } 518 /* cleanup tx queue cscn */ 519 for (i = 0; i < priv->nb_tx_queues; i++) { 520 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 521 rte_free(dpaa2_q->cscn); 522 } 523 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 524 /* cleanup tx conf queue storage */ 525 for (i = 0; i < priv->nb_tx_queues; i++) { 526 dpaa2_q = (struct dpaa2_queue *) 527 priv->tx_conf_vq[i]; 528 rte_free(dpaa2_q->q_storage); 529 } 530 } 531 /*free memory for all queues (RX+TX) */ 532 rte_free(priv->rx_vq[0]); 533 priv->rx_vq[0] = NULL; 534 } 535 } 536 537 static int 538 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 539 { 540 struct dpaa2_dev_priv *priv = dev->data->dev_private; 541 struct fsl_mc_io *dpni = dev->process_private; 542 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 543 uint64_t rx_offloads = eth_conf->rxmode.offloads; 544 uint64_t tx_offloads = eth_conf->txmode.offloads; 545 int rx_l3_csum_offload = false; 546 int rx_l4_csum_offload = false; 547 int tx_l3_csum_offload = false; 548 int tx_l4_csum_offload = false; 549 int ret, tc_index; 550 uint32_t max_rx_pktlen; 551 552 PMD_INIT_FUNC_TRACE(); 553 554 /* Rx offloads which are enabled by default */ 555 if (dev_rx_offloads_nodis & ~rx_offloads) { 556 DPAA2_PMD_INFO( 557 "Some of rx offloads enabled by default - requested 0x%" PRIx64 558 " fixed are 0x%" PRIx64, 559 rx_offloads, dev_rx_offloads_nodis); 560 } 561 562 /* Tx offloads which are enabled by default */ 563 if (dev_tx_offloads_nodis & ~tx_offloads) { 564 DPAA2_PMD_INFO( 565 "Some of tx offloads enabled by default - requested 0x%" PRIx64 566 " fixed are 0x%" PRIx64, 567 tx_offloads, dev_tx_offloads_nodis); 568 } 569 570 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 571 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 572 if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) { 573 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 574 priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN); 575 if (ret != 0) { 576 DPAA2_PMD_ERR("Unable to set mtu. check config"); 577 return ret; 578 } 579 DPAA2_PMD_INFO("MTU configured for the device: %d", 580 dev->data->mtu); 581 } else { 582 return -1; 583 } 584 585 if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) { 586 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 587 ret = dpaa2_setup_flow_dist(dev, 588 eth_conf->rx_adv_conf.rss_conf.rss_hf, 589 tc_index); 590 if (ret) { 591 DPAA2_PMD_ERR( 592 "Unable to set flow distribution on tc%d." 593 "Check queue config", tc_index); 594 return ret; 595 } 596 } 597 } 598 599 if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) 600 rx_l3_csum_offload = true; 601 602 if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) || 603 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) || 604 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM)) 605 rx_l4_csum_offload = true; 606 607 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 608 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 609 if (ret) { 610 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 611 return ret; 612 } 613 614 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 615 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 616 if (ret) { 617 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 618 return ret; 619 } 620 621 #if !defined(RTE_LIBRTE_IEEE1588) 622 if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) 623 #endif 624 { 625 ret = rte_mbuf_dyn_rx_timestamp_register( 626 &dpaa2_timestamp_dynfield_offset, 627 &dpaa2_timestamp_rx_dynflag); 628 if (ret != 0) { 629 DPAA2_PMD_ERR("Error to register timestamp field/flag"); 630 return -rte_errno; 631 } 632 dpaa2_enable_ts[dev->data->port_id] = true; 633 } 634 635 if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) 636 tx_l3_csum_offload = true; 637 638 if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) || 639 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) || 640 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)) 641 tx_l4_csum_offload = true; 642 643 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 644 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 645 if (ret) { 646 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 647 return ret; 648 } 649 650 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 651 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 652 if (ret) { 653 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 654 return ret; 655 } 656 657 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 658 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 659 * to 0 for LS2 in the hardware thus disabling data/annotation 660 * stashing. For LX2 this is fixed in hardware and thus hash result and 661 * parse results can be received in FD using this option. 662 */ 663 if (dpaa2_svr_family == SVR_LX2160A) { 664 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 665 DPNI_FLCTYPE_HASH, true); 666 if (ret) { 667 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 668 return ret; 669 } 670 } 671 672 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 673 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK); 674 675 if (eth_conf->lpbk_mode) { 676 ret = dpaa2_dev_recycle_config(dev); 677 if (ret) { 678 DPAA2_PMD_ERR("Error to configure %s to recycle port.", 679 dev->data->name); 680 681 return ret; 682 } 683 } else { 684 /** User may disable loopback mode by calling 685 * "dev_configure" with lpbk_mode cleared. 686 * No matter the port was configured recycle or not, 687 * recycle de-configure is called here. 688 * If port is not recycled, the de-configure will return directly. 689 */ 690 ret = dpaa2_dev_recycle_deconfig(dev); 691 if (ret) { 692 DPAA2_PMD_ERR("Error to de-configure recycle port %s.", 693 dev->data->name); 694 695 return ret; 696 } 697 } 698 699 dpaa2_tm_init(dev); 700 701 return 0; 702 } 703 704 /* Function to setup RX flow information. It contains traffic class ID, 705 * flow ID, destination configuration etc. 706 */ 707 static int 708 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 709 uint16_t rx_queue_id, 710 uint16_t nb_rx_desc, 711 unsigned int socket_id __rte_unused, 712 const struct rte_eth_rxconf *rx_conf, 713 struct rte_mempool *mb_pool) 714 { 715 struct dpaa2_dev_priv *priv = dev->data->dev_private; 716 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 717 struct dpaa2_queue *dpaa2_q; 718 struct dpni_queue cfg; 719 uint8_t options = 0; 720 uint8_t flow_id; 721 uint32_t bpid; 722 int i, ret; 723 724 PMD_INIT_FUNC_TRACE(); 725 726 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 727 dev, rx_queue_id, mb_pool, rx_conf); 728 729 total_nb_rx_desc += nb_rx_desc; 730 if (total_nb_rx_desc > MAX_NB_RX_DESC) { 731 DPAA2_PMD_WARN("Total nb_rx_desc exceeds %d limit. Please use Normal buffers", 732 MAX_NB_RX_DESC); 733 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script"); 734 } 735 736 /* Rx deferred start is not supported */ 737 if (rx_conf->rx_deferred_start) { 738 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 739 (void *)dev); 740 return -EINVAL; 741 } 742 743 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 744 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 745 ret = rte_dpaa2_bpid_info_init(mb_pool); 746 if (ret) 747 return ret; 748 } 749 bpid = mempool_to_bpid(mb_pool); 750 ret = dpaa2_attach_bp_list(priv, dpni, 751 rte_dpaa2_bpid_info[bpid].bp_list); 752 if (ret) 753 return ret; 754 } 755 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 756 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 757 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 758 dpaa2_q->nb_desc = UINT16_MAX; 759 dpaa2_q->offloads = rx_conf->offloads; 760 761 /*Get the flow id from given VQ id*/ 762 flow_id = dpaa2_q->flow_id; 763 memset(&cfg, 0, sizeof(struct dpni_queue)); 764 765 options = options | DPNI_QUEUE_OPT_USER_CTX; 766 cfg.user_context = (size_t)(dpaa2_q); 767 768 /* check if a private cgr available. */ 769 for (i = 0; i < priv->max_cgs; i++) { 770 if (!priv->cgid_in_use[i]) { 771 priv->cgid_in_use[i] = 1; 772 break; 773 } 774 } 775 776 if (i < priv->max_cgs) { 777 options |= DPNI_QUEUE_OPT_SET_CGID; 778 cfg.cgid = i; 779 dpaa2_q->cgid = cfg.cgid; 780 } else { 781 dpaa2_q->cgid = 0xff; 782 } 783 784 /*if ls2088 or rev2 device, enable the stashing */ 785 786 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 787 options |= DPNI_QUEUE_OPT_FLC; 788 cfg.flc.stash_control = true; 789 dpaa2_flc_stashing_clear_all(&cfg.flc.value); 790 if (getenv("DPAA2_DATA_STASHING_OFF")) { 791 dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, 792 &cfg.flc.value); 793 dpaa2_q->data_stashing_off = 1; 794 } else { 795 dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1, 796 &cfg.flc.value); 797 dpaa2_q->data_stashing_off = 0; 798 } 799 if ((dpaa2_svr_family & 0xffff0000) != SVR_LX2160A) { 800 dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 1, 801 &cfg.flc.value); 802 } 803 } 804 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 805 dpaa2_q->tc_index, flow_id, options, &cfg); 806 if (ret) { 807 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 808 return -1; 809 } 810 811 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 812 struct dpni_taildrop taildrop; 813 814 taildrop.enable = 1; 815 dpaa2_q->nb_desc = nb_rx_desc; 816 /* Private CGR will use tail drop length as nb_rx_desc. 817 * for rest cases we can use standard byte based tail drop. 818 * There is no HW restriction, but number of CGRs are limited, 819 * hence this restriction is placed. 820 */ 821 if (dpaa2_q->cgid != 0xff) { 822 /*enabling per rx queue congestion control */ 823 taildrop.threshold = nb_rx_desc; 824 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 825 taildrop.oal = 0; 826 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 827 rx_queue_id); 828 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 829 DPNI_CP_CONGESTION_GROUP, 830 DPNI_QUEUE_RX, 831 dpaa2_q->tc_index, 832 dpaa2_q->cgid, &taildrop); 833 } else { 834 /*enabling per rx queue congestion control */ 835 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 836 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 837 taildrop.oal = CONG_RX_OAL; 838 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 839 rx_queue_id); 840 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 841 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 842 dpaa2_q->tc_index, flow_id, 843 &taildrop); 844 } 845 if (ret) { 846 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 847 ret); 848 return -1; 849 } 850 } else { /* Disable tail Drop */ 851 struct dpni_taildrop taildrop = {0}; 852 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 853 854 taildrop.enable = 0; 855 if (dpaa2_q->cgid != 0xff) { 856 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 857 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 858 dpaa2_q->tc_index, 859 dpaa2_q->cgid, &taildrop); 860 } else { 861 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 862 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 863 dpaa2_q->tc_index, flow_id, &taildrop); 864 } 865 if (ret) { 866 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 867 ret); 868 return -1; 869 } 870 } 871 872 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 873 return 0; 874 } 875 876 static int 877 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 878 uint16_t tx_queue_id, 879 uint16_t nb_tx_desc, 880 unsigned int socket_id __rte_unused, 881 const struct rte_eth_txconf *tx_conf) 882 { 883 struct dpaa2_dev_priv *priv = dev->data->dev_private; 884 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 885 priv->tx_vq[tx_queue_id]; 886 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 887 priv->tx_conf_vq[tx_queue_id]; 888 struct fsl_mc_io *dpni = dev->process_private; 889 struct dpni_queue tx_conf_cfg; 890 struct dpni_queue tx_flow_cfg; 891 uint8_t options = 0, flow_id; 892 uint16_t channel_id; 893 struct dpni_queue_id qid; 894 uint32_t tc_id; 895 int ret; 896 897 PMD_INIT_FUNC_TRACE(); 898 899 /* Tx deferred start is not supported */ 900 if (tx_conf->tx_deferred_start) { 901 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 902 (void *)dev); 903 return -EINVAL; 904 } 905 906 dpaa2_q->nb_desc = UINT16_MAX; 907 dpaa2_q->offloads = tx_conf->offloads; 908 909 /* Return if queue already configured */ 910 if (dpaa2_q->flow_id != 0xffff) { 911 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 912 return 0; 913 } 914 915 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 916 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 917 918 if (tx_queue_id == 0) { 919 /*Set tx-conf and error configuration*/ 920 if (priv->flags & DPAA2_TX_CONF_ENABLE) 921 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 922 priv->token, 923 DPNI_CONF_AFFINE); 924 else 925 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 926 priv->token, 927 DPNI_CONF_DISABLE); 928 if (ret) { 929 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 930 "err=%d", ret); 931 return -1; 932 } 933 } 934 935 tc_id = tx_queue_id % priv->num_tx_tc; 936 channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels; 937 flow_id = 0; 938 939 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 940 ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg); 941 if (ret) { 942 DPAA2_PMD_ERR("Error in setting the tx flow: " 943 "tc_id=%d, flow=%d err=%d", 944 tc_id, flow_id, ret); 945 return -1; 946 } 947 948 dpaa2_q->flow_id = flow_id; 949 950 dpaa2_q->tc_index = tc_id; 951 952 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 953 DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index), 954 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 955 if (ret) { 956 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 957 return -1; 958 } 959 dpaa2_q->fqid = qid.fqid; 960 961 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 962 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 963 964 dpaa2_q->nb_desc = nb_tx_desc; 965 966 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 967 cong_notif_cfg.threshold_entry = nb_tx_desc; 968 /* Notify that the queue is not congested when the data in 969 * the queue is below this threshold.(90% of value) 970 */ 971 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; 972 cong_notif_cfg.message_ctx = 0; 973 cong_notif_cfg.message_iova = 974 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 975 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 976 cong_notif_cfg.notification_mode = 977 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 978 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 979 DPNI_CONG_OPT_COHERENT_WRITE; 980 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 981 982 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 983 priv->token, 984 DPNI_QUEUE_TX, 985 ((channel_id << 8) | tc_id), 986 &cong_notif_cfg); 987 if (ret) { 988 DPAA2_PMD_ERR( 989 "Error in setting tx congestion notification: " 990 "err=%d", ret); 991 return -ret; 992 } 993 } 994 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 995 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 996 997 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 998 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 999 options = options | DPNI_QUEUE_OPT_USER_CTX; 1000 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 1001 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 1002 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index), 1003 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 1004 if (ret) { 1005 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 1006 "tc_index=%d, flow=%d err=%d", 1007 dpaa2_tx_conf_q->tc_index, 1008 dpaa2_tx_conf_q->flow_id, ret); 1009 return -1; 1010 } 1011 1012 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1013 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index), 1014 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 1015 if (ret) { 1016 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 1017 return -1; 1018 } 1019 dpaa2_tx_conf_q->fqid = qid.fqid; 1020 } 1021 return 0; 1022 } 1023 1024 static void 1025 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1026 { 1027 struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id]; 1028 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 1029 struct fsl_mc_io *dpni = 1030 (struct fsl_mc_io *)priv->eth_dev->process_private; 1031 uint8_t options = 0; 1032 int ret; 1033 struct dpni_queue cfg; 1034 1035 memset(&cfg, 0, sizeof(struct dpni_queue)); 1036 PMD_INIT_FUNC_TRACE(); 1037 1038 total_nb_rx_desc -= dpaa2_q->nb_desc; 1039 1040 if (dpaa2_q->cgid != 0xff) { 1041 options = DPNI_QUEUE_OPT_CLEAR_CGID; 1042 cfg.cgid = dpaa2_q->cgid; 1043 1044 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 1045 DPNI_QUEUE_RX, 1046 dpaa2_q->tc_index, dpaa2_q->flow_id, 1047 options, &cfg); 1048 if (ret) 1049 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 1050 dpaa2_q->fqid, ret); 1051 priv->cgid_in_use[dpaa2_q->cgid] = 0; 1052 dpaa2_q->cgid = 0xff; 1053 } 1054 } 1055 1056 static uint32_t 1057 dpaa2_dev_rx_queue_count(void *rx_queue) 1058 { 1059 int32_t ret; 1060 struct dpaa2_queue *dpaa2_q; 1061 struct qbman_swp *swp; 1062 struct qbman_fq_query_np_rslt state; 1063 uint32_t frame_cnt = 0; 1064 1065 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 1066 ret = dpaa2_affine_qbman_swp(); 1067 if (ret) { 1068 DPAA2_PMD_ERR( 1069 "Failed to allocate IO portal, tid: %d", 1070 rte_gettid()); 1071 return -EINVAL; 1072 } 1073 } 1074 swp = DPAA2_PER_LCORE_PORTAL; 1075 1076 dpaa2_q = rx_queue; 1077 1078 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 1079 frame_cnt = qbman_fq_state_frame_count(&state); 1080 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u", 1081 rx_queue, frame_cnt); 1082 } 1083 return frame_cnt; 1084 } 1085 1086 static const uint32_t * 1087 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 1088 { 1089 static const uint32_t ptypes[] = { 1090 /*todo -= add more types */ 1091 RTE_PTYPE_L2_ETHER, 1092 RTE_PTYPE_L3_IPV4, 1093 RTE_PTYPE_L3_IPV4_EXT, 1094 RTE_PTYPE_L3_IPV6, 1095 RTE_PTYPE_L3_IPV6_EXT, 1096 RTE_PTYPE_L4_TCP, 1097 RTE_PTYPE_L4_UDP, 1098 RTE_PTYPE_L4_SCTP, 1099 RTE_PTYPE_L4_ICMP, 1100 }; 1101 1102 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1103 dev->rx_pkt_burst == dpaa2_dev_rx || 1104 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) { 1105 *no_of_elements = RTE_DIM(ptypes); 1106 return ptypes; 1107 } 1108 return NULL; 1109 } 1110 1111 /** 1112 * Dpaa2 link Interrupt handler 1113 * 1114 * @param param 1115 * The address of parameter (struct rte_eth_dev *) registered before. 1116 * 1117 * @return 1118 * void 1119 */ 1120 static void 1121 dpaa2_interrupt_handler(void *param) 1122 { 1123 struct rte_eth_dev *dev = param; 1124 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1125 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1126 int ret; 1127 int irq_index = DPNI_IRQ_INDEX; 1128 unsigned int status = 0, clear = 0; 1129 1130 PMD_INIT_FUNC_TRACE(); 1131 1132 if (dpni == NULL) { 1133 DPAA2_PMD_ERR("dpni is NULL"); 1134 return; 1135 } 1136 1137 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1138 irq_index, &status); 1139 if (unlikely(ret)) { 1140 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1141 clear = 0xffffffff; 1142 goto out; 1143 } 1144 1145 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1146 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1147 dpaa2_dev_link_update(dev, 0); 1148 /* calling all the apps registered for link status event */ 1149 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1150 } 1151 out: 1152 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1153 irq_index, clear); 1154 if (unlikely(ret)) 1155 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1156 } 1157 1158 static int 1159 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1160 { 1161 int err = 0; 1162 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1163 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1164 int irq_index = DPNI_IRQ_INDEX; 1165 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1166 1167 PMD_INIT_FUNC_TRACE(); 1168 1169 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1170 irq_index, mask); 1171 if (err < 0) { 1172 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1173 strerror(-err)); 1174 return err; 1175 } 1176 1177 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1178 irq_index, enable); 1179 if (err < 0) 1180 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1181 strerror(-err)); 1182 1183 return err; 1184 } 1185 1186 static int 1187 dpaa2_dev_start(struct rte_eth_dev *dev) 1188 { 1189 struct rte_device *rdev = dev->device; 1190 struct rte_dpaa2_device *dpaa2_dev; 1191 struct rte_eth_dev_data *data = dev->data; 1192 struct dpaa2_dev_priv *priv = data->dev_private; 1193 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1194 struct dpni_queue cfg; 1195 struct dpni_error_cfg err_cfg; 1196 struct dpni_queue_id qid; 1197 struct dpaa2_queue *dpaa2_q; 1198 int ret, i; 1199 struct rte_intr_handle *intr_handle; 1200 1201 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1202 intr_handle = dpaa2_dev->intr_handle; 1203 1204 PMD_INIT_FUNC_TRACE(); 1205 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1206 if (ret) { 1207 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1208 priv->hw_id, ret); 1209 return ret; 1210 } 1211 1212 /* Power up the phy. Needed to make the link go UP */ 1213 dpaa2_dev_set_link_up(dev); 1214 1215 for (i = 0; i < data->nb_rx_queues; i++) { 1216 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1217 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1218 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1219 dpaa2_q->flow_id, &cfg, &qid); 1220 if (ret) { 1221 DPAA2_PMD_ERR("Error in getting flow information: " 1222 "err=%d", ret); 1223 return ret; 1224 } 1225 dpaa2_q->fqid = qid.fqid; 1226 } 1227 1228 if (dpaa2_enable_err_queue) { 1229 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1230 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); 1231 if (ret) { 1232 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", 1233 ret); 1234 return ret; 1235 } 1236 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 1237 dpaa2_q->fqid = qid.fqid; 1238 dpaa2_q->eth_data = dev->data; 1239 1240 err_cfg.errors = DPNI_ERROR_DISC; 1241 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; 1242 } else { 1243 /* checksum errors, send them to normal path 1244 * and set it in annotation 1245 */ 1246 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1247 1248 /* if packet with parse error are not to be dropped */ 1249 err_cfg.errors |= DPNI_ERROR_PHE; 1250 1251 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1252 } 1253 err_cfg.set_frame_annotation = true; 1254 1255 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1256 priv->token, &err_cfg); 1257 if (ret) { 1258 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1259 ret); 1260 return ret; 1261 } 1262 1263 /* if the interrupts were configured on this devices*/ 1264 if (intr_handle && rte_intr_fd_get(intr_handle) && 1265 dev->data->dev_conf.intr_conf.lsc != 0) { 1266 /* Registering LSC interrupt handler */ 1267 rte_intr_callback_register(intr_handle, 1268 dpaa2_interrupt_handler, 1269 (void *)dev); 1270 1271 /* enable vfio intr/eventfd mapping 1272 * Interrupt index 0 is required, so we can not use 1273 * rte_intr_enable. 1274 */ 1275 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1276 1277 /* enable dpni_irqs */ 1278 dpaa2_eth_setup_irqs(dev, 1); 1279 } 1280 1281 /* Change the tx burst function if ordered queues are used */ 1282 if (priv->en_ordered) 1283 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1284 1285 for (i = 0; i < dev->data->nb_rx_queues; i++) 1286 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1287 for (i = 0; i < dev->data->nb_tx_queues; i++) 1288 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1289 1290 return 0; 1291 } 1292 1293 /** 1294 * This routine disables all traffic on the adapter by issuing a 1295 * global reset on the MAC. 1296 */ 1297 static int 1298 dpaa2_dev_stop(struct rte_eth_dev *dev) 1299 { 1300 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1301 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1302 int ret; 1303 struct rte_eth_link link; 1304 struct rte_device *rdev = dev->device; 1305 struct rte_intr_handle *intr_handle; 1306 struct rte_dpaa2_device *dpaa2_dev; 1307 uint16_t i; 1308 1309 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1310 intr_handle = dpaa2_dev->intr_handle; 1311 1312 PMD_INIT_FUNC_TRACE(); 1313 1314 /* reset interrupt callback */ 1315 if (intr_handle && rte_intr_fd_get(intr_handle) && 1316 dev->data->dev_conf.intr_conf.lsc != 0) { 1317 /*disable dpni irqs */ 1318 dpaa2_eth_setup_irqs(dev, 0); 1319 1320 /* disable vfio intr before callback unregister */ 1321 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1322 1323 /* Unregistering LSC interrupt handler */ 1324 rte_intr_callback_unregister(intr_handle, 1325 dpaa2_interrupt_handler, 1326 (void *)dev); 1327 } 1328 1329 dpaa2_dev_set_link_down(dev); 1330 1331 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1332 if (ret) { 1333 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1334 ret, priv->hw_id); 1335 return ret; 1336 } 1337 1338 /* clear the recorded link status */ 1339 memset(&link, 0, sizeof(link)); 1340 rte_eth_linkstatus_set(dev, &link); 1341 1342 for (i = 0; i < dev->data->nb_rx_queues; i++) 1343 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1344 for (i = 0; i < dev->data->nb_tx_queues; i++) 1345 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1346 1347 return 0; 1348 } 1349 1350 static int 1351 dpaa2_dev_close(struct rte_eth_dev *dev) 1352 { 1353 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1354 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1355 int i, ret; 1356 struct rte_eth_link link; 1357 1358 PMD_INIT_FUNC_TRACE(); 1359 1360 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1361 return 0; 1362 1363 if (!dpni) { 1364 DPAA2_PMD_WARN("Already closed or not started"); 1365 return -1; 1366 } 1367 1368 dpaa2_tm_deinit(dev); 1369 dpaa2_flow_clean(dev); 1370 /* Clean the device first */ 1371 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1372 if (ret) { 1373 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1374 return -1; 1375 } 1376 1377 memset(&link, 0, sizeof(link)); 1378 rte_eth_linkstatus_set(dev, &link); 1379 1380 /* Free private queues memory */ 1381 dpaa2_free_rx_tx_queues(dev); 1382 /* Close the device at underlying layer*/ 1383 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1384 if (ret) { 1385 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1386 ret); 1387 } 1388 1389 /* Free the allocated memory for ethernet private data and dpni*/ 1390 priv->hw = NULL; 1391 dev->process_private = NULL; 1392 rte_free(dpni); 1393 1394 for (i = 0; i < MAX_TCS; i++) 1395 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1396 1397 if (priv->extract.qos_extract_param) 1398 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1399 1400 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1401 return 0; 1402 } 1403 1404 static int 1405 dpaa2_dev_promiscuous_enable( 1406 struct rte_eth_dev *dev) 1407 { 1408 int ret; 1409 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1410 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1411 1412 PMD_INIT_FUNC_TRACE(); 1413 1414 if (dpni == NULL) { 1415 DPAA2_PMD_ERR("dpni is NULL"); 1416 return -ENODEV; 1417 } 1418 1419 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1420 if (ret < 0) 1421 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1422 1423 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1424 if (ret < 0) 1425 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1426 1427 return ret; 1428 } 1429 1430 static int 1431 dpaa2_dev_promiscuous_disable( 1432 struct rte_eth_dev *dev) 1433 { 1434 int ret; 1435 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1436 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1437 1438 PMD_INIT_FUNC_TRACE(); 1439 1440 if (dpni == NULL) { 1441 DPAA2_PMD_ERR("dpni is NULL"); 1442 return -ENODEV; 1443 } 1444 1445 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1446 if (ret < 0) 1447 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1448 1449 if (dev->data->all_multicast == 0) { 1450 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1451 priv->token, false); 1452 if (ret < 0) 1453 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1454 ret); 1455 } 1456 1457 return ret; 1458 } 1459 1460 static int 1461 dpaa2_dev_allmulticast_enable( 1462 struct rte_eth_dev *dev) 1463 { 1464 int ret; 1465 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1466 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1467 1468 PMD_INIT_FUNC_TRACE(); 1469 1470 if (dpni == NULL) { 1471 DPAA2_PMD_ERR("dpni is NULL"); 1472 return -ENODEV; 1473 } 1474 1475 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1476 if (ret < 0) 1477 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1478 1479 return ret; 1480 } 1481 1482 static int 1483 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1484 { 1485 int ret; 1486 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1487 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1488 1489 PMD_INIT_FUNC_TRACE(); 1490 1491 if (dpni == NULL) { 1492 DPAA2_PMD_ERR("dpni is NULL"); 1493 return -ENODEV; 1494 } 1495 1496 /* must remain on for all promiscuous */ 1497 if (dev->data->promiscuous == 1) 1498 return 0; 1499 1500 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1501 if (ret < 0) 1502 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1503 1504 return ret; 1505 } 1506 1507 static int 1508 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1509 { 1510 int ret; 1511 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1512 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1513 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1514 + VLAN_TAG_SIZE; 1515 1516 PMD_INIT_FUNC_TRACE(); 1517 1518 if (dpni == NULL) { 1519 DPAA2_PMD_ERR("dpni is NULL"); 1520 return -EINVAL; 1521 } 1522 1523 /* Set the Max Rx frame length as 'mtu' + 1524 * Maximum Ethernet header length 1525 */ 1526 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1527 frame_size - RTE_ETHER_CRC_LEN); 1528 if (ret) { 1529 DPAA2_PMD_ERR("Setting the max frame length failed"); 1530 return -1; 1531 } 1532 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1533 return 0; 1534 } 1535 1536 static int 1537 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1538 struct rte_ether_addr *addr, 1539 __rte_unused uint32_t index, 1540 __rte_unused uint32_t pool) 1541 { 1542 int ret; 1543 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1544 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1545 1546 PMD_INIT_FUNC_TRACE(); 1547 1548 if (dpni == NULL) { 1549 DPAA2_PMD_ERR("dpni is NULL"); 1550 return -1; 1551 } 1552 1553 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1554 addr->addr_bytes, 0, 0, 0); 1555 if (ret) 1556 DPAA2_PMD_ERR( 1557 "error: Adding the MAC ADDR failed: err = %d", ret); 1558 return 0; 1559 } 1560 1561 static void 1562 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1563 uint32_t index) 1564 { 1565 int ret; 1566 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1567 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1568 struct rte_eth_dev_data *data = dev->data; 1569 struct rte_ether_addr *macaddr; 1570 1571 PMD_INIT_FUNC_TRACE(); 1572 1573 macaddr = &data->mac_addrs[index]; 1574 1575 if (dpni == NULL) { 1576 DPAA2_PMD_ERR("dpni is NULL"); 1577 return; 1578 } 1579 1580 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1581 priv->token, macaddr->addr_bytes); 1582 if (ret) 1583 DPAA2_PMD_ERR( 1584 "error: Removing the MAC ADDR failed: err = %d", ret); 1585 } 1586 1587 static int 1588 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1589 struct rte_ether_addr *addr) 1590 { 1591 int ret; 1592 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1593 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1594 1595 PMD_INIT_FUNC_TRACE(); 1596 1597 if (dpni == NULL) { 1598 DPAA2_PMD_ERR("dpni is NULL"); 1599 return -EINVAL; 1600 } 1601 1602 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1603 priv->token, addr->addr_bytes); 1604 1605 if (ret) 1606 DPAA2_PMD_ERR( 1607 "error: Setting the MAC ADDR failed %d", ret); 1608 1609 return ret; 1610 } 1611 1612 static 1613 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1614 struct rte_eth_stats *stats) 1615 { 1616 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1617 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1618 int32_t retcode; 1619 uint8_t page0 = 0, page1 = 1, page2 = 2; 1620 union dpni_statistics value; 1621 int i; 1622 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1623 1624 memset(&value, 0, sizeof(union dpni_statistics)); 1625 1626 PMD_INIT_FUNC_TRACE(); 1627 1628 if (!dpni) { 1629 DPAA2_PMD_ERR("dpni is NULL"); 1630 return -EINVAL; 1631 } 1632 1633 if (!stats) { 1634 DPAA2_PMD_ERR("stats is NULL"); 1635 return -EINVAL; 1636 } 1637 1638 /*Get Counters from page_0*/ 1639 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1640 page0, 0, &value); 1641 if (retcode) 1642 goto err; 1643 1644 stats->ipackets = value.page_0.ingress_all_frames; 1645 stats->ibytes = value.page_0.ingress_all_bytes; 1646 1647 /*Get Counters from page_1*/ 1648 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1649 page1, 0, &value); 1650 if (retcode) 1651 goto err; 1652 1653 stats->opackets = value.page_1.egress_all_frames; 1654 stats->obytes = value.page_1.egress_all_bytes; 1655 1656 /*Get Counters from page_2*/ 1657 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1658 page2, 0, &value); 1659 if (retcode) 1660 goto err; 1661 1662 /* Ingress drop frame count due to configured rules */ 1663 stats->ierrors = value.page_2.ingress_filtered_frames; 1664 /* Ingress drop frame count due to error */ 1665 stats->ierrors += value.page_2.ingress_discarded_frames; 1666 1667 stats->oerrors = value.page_2.egress_discarded_frames; 1668 stats->imissed = value.page_2.ingress_nobuffer_discards; 1669 1670 /* Fill in per queue stats */ 1671 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1672 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1673 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1674 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1675 if (dpaa2_rxq) 1676 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1677 if (dpaa2_txq) 1678 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1679 1680 /* Byte counting is not implemented */ 1681 stats->q_ibytes[i] = 0; 1682 stats->q_obytes[i] = 0; 1683 } 1684 1685 return 0; 1686 1687 err: 1688 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1689 return retcode; 1690 }; 1691 1692 static int 1693 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1694 unsigned int n) 1695 { 1696 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1697 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1698 int32_t retcode; 1699 union dpni_statistics value[5] = {}; 1700 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1701 1702 if (n < num) 1703 return num; 1704 1705 if (xstats == NULL) 1706 return 0; 1707 1708 /* Get Counters from page_0*/ 1709 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1710 0, 0, &value[0]); 1711 if (retcode) 1712 goto err; 1713 1714 /* Get Counters from page_1*/ 1715 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1716 1, 0, &value[1]); 1717 if (retcode) 1718 goto err; 1719 1720 /* Get Counters from page_2*/ 1721 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1722 2, 0, &value[2]); 1723 if (retcode) 1724 goto err; 1725 1726 for (i = 0; i < priv->max_cgs; i++) { 1727 if (!priv->cgid_in_use[i]) { 1728 /* Get Counters from page_4*/ 1729 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1730 priv->token, 1731 4, 0, &value[4]); 1732 if (retcode) 1733 goto err; 1734 break; 1735 } 1736 } 1737 1738 for (i = 0; i < num; i++) { 1739 xstats[i].id = i; 1740 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1741 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1742 } 1743 return i; 1744 err: 1745 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1746 return retcode; 1747 } 1748 1749 static int 1750 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1751 struct rte_eth_xstat_name *xstats_names, 1752 unsigned int limit) 1753 { 1754 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1755 1756 if (limit < stat_cnt) 1757 return stat_cnt; 1758 1759 if (xstats_names != NULL) 1760 for (i = 0; i < stat_cnt; i++) 1761 strlcpy(xstats_names[i].name, 1762 dpaa2_xstats_strings[i].name, 1763 sizeof(xstats_names[i].name)); 1764 1765 return stat_cnt; 1766 } 1767 1768 static int 1769 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1770 uint64_t *values, unsigned int n) 1771 { 1772 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1773 uint64_t values_copy[stat_cnt]; 1774 1775 if (!ids) { 1776 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1777 struct fsl_mc_io *dpni = 1778 (struct fsl_mc_io *)dev->process_private; 1779 int32_t retcode; 1780 union dpni_statistics value[5] = {}; 1781 1782 if (n < stat_cnt) 1783 return stat_cnt; 1784 1785 if (!values) 1786 return 0; 1787 1788 /* Get Counters from page_0*/ 1789 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1790 0, 0, &value[0]); 1791 if (retcode) 1792 return 0; 1793 1794 /* Get Counters from page_1*/ 1795 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1796 1, 0, &value[1]); 1797 if (retcode) 1798 return 0; 1799 1800 /* Get Counters from page_2*/ 1801 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1802 2, 0, &value[2]); 1803 if (retcode) 1804 return 0; 1805 1806 /* Get Counters from page_4*/ 1807 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1808 4, 0, &value[4]); 1809 if (retcode) 1810 return 0; 1811 1812 for (i = 0; i < stat_cnt; i++) { 1813 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1814 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1815 } 1816 return stat_cnt; 1817 } 1818 1819 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1820 1821 for (i = 0; i < n; i++) { 1822 if (ids[i] >= stat_cnt) { 1823 DPAA2_PMD_ERR("xstats id value isn't valid"); 1824 return -1; 1825 } 1826 values[i] = values_copy[ids[i]]; 1827 } 1828 return n; 1829 } 1830 1831 static int 1832 dpaa2_xstats_get_names_by_id( 1833 struct rte_eth_dev *dev, 1834 const uint64_t *ids, 1835 struct rte_eth_xstat_name *xstats_names, 1836 unsigned int limit) 1837 { 1838 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1839 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1840 1841 if (!ids) 1842 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1843 1844 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1845 1846 for (i = 0; i < limit; i++) { 1847 if (ids[i] >= stat_cnt) { 1848 DPAA2_PMD_ERR("xstats id value isn't valid"); 1849 return -1; 1850 } 1851 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1852 } 1853 return limit; 1854 } 1855 1856 static int 1857 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1858 { 1859 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1860 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1861 int retcode; 1862 int i; 1863 struct dpaa2_queue *dpaa2_q; 1864 1865 PMD_INIT_FUNC_TRACE(); 1866 1867 if (dpni == NULL) { 1868 DPAA2_PMD_ERR("dpni is NULL"); 1869 return -EINVAL; 1870 } 1871 1872 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1873 if (retcode) 1874 goto error; 1875 1876 /* Reset the per queue stats in dpaa2_queue structure */ 1877 for (i = 0; i < priv->nb_rx_queues; i++) { 1878 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1879 if (dpaa2_q) 1880 dpaa2_q->rx_pkts = 0; 1881 } 1882 1883 for (i = 0; i < priv->nb_tx_queues; i++) { 1884 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1885 if (dpaa2_q) 1886 dpaa2_q->tx_pkts = 0; 1887 } 1888 1889 return 0; 1890 1891 error: 1892 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1893 return retcode; 1894 }; 1895 1896 /* return 0 means link status changed, -1 means not changed */ 1897 static int 1898 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1899 int wait_to_complete) 1900 { 1901 int ret; 1902 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1903 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1904 struct rte_eth_link link; 1905 struct dpni_link_state state = {0}; 1906 uint8_t count; 1907 1908 if (dpni == NULL) { 1909 DPAA2_PMD_ERR("dpni is NULL"); 1910 return 0; 1911 } 1912 1913 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 1914 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, 1915 &state); 1916 if (ret < 0) { 1917 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1918 return -1; 1919 } 1920 if (state.up == RTE_ETH_LINK_DOWN && 1921 wait_to_complete) 1922 rte_delay_ms(CHECK_INTERVAL); 1923 else 1924 break; 1925 } 1926 1927 memset(&link, 0, sizeof(struct rte_eth_link)); 1928 link.link_status = state.up; 1929 link.link_speed = state.rate; 1930 1931 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1932 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 1933 else 1934 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1935 1936 ret = rte_eth_linkstatus_set(dev, &link); 1937 if (ret == -1) 1938 DPAA2_PMD_DEBUG("No change in status"); 1939 else 1940 DPAA2_PMD_INFO("Port %d Link is %s", dev->data->port_id, 1941 link.link_status ? "Up" : "Down"); 1942 1943 return ret; 1944 } 1945 1946 /** 1947 * Toggle the DPNI to enable, if not already enabled. 1948 * This is not strictly PHY up/down - it is more of logical toggling. 1949 */ 1950 static int 1951 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1952 { 1953 int ret = -EINVAL; 1954 struct dpaa2_dev_priv *priv; 1955 struct fsl_mc_io *dpni; 1956 int en = 0; 1957 struct dpni_link_state state = {0}; 1958 1959 priv = dev->data->dev_private; 1960 dpni = (struct fsl_mc_io *)dev->process_private; 1961 1962 if (dpni == NULL) { 1963 DPAA2_PMD_ERR("dpni is NULL"); 1964 return ret; 1965 } 1966 1967 /* Check if DPNI is currently enabled */ 1968 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1969 if (ret) { 1970 /* Unable to obtain dpni status; Not continuing */ 1971 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1972 return -EINVAL; 1973 } 1974 1975 /* Enable link if not already enabled */ 1976 if (!en) { 1977 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1978 if (ret) { 1979 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1980 return -EINVAL; 1981 } 1982 } 1983 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1984 if (ret < 0) { 1985 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1986 return -1; 1987 } 1988 1989 /* changing tx burst function to start enqueues */ 1990 dev->tx_pkt_burst = dpaa2_dev_tx; 1991 dev->data->dev_link.link_status = state.up; 1992 dev->data->dev_link.link_speed = state.rate; 1993 1994 if (state.up) 1995 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1996 else 1997 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1998 return ret; 1999 } 2000 2001 /** 2002 * Toggle the DPNI to disable, if not already disabled. 2003 * This is not strictly PHY up/down - it is more of logical toggling. 2004 */ 2005 static int 2006 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 2007 { 2008 int ret = -EINVAL; 2009 struct dpaa2_dev_priv *priv; 2010 struct fsl_mc_io *dpni; 2011 int dpni_enabled = 0; 2012 int retries = 10; 2013 2014 PMD_INIT_FUNC_TRACE(); 2015 2016 priv = dev->data->dev_private; 2017 dpni = (struct fsl_mc_io *)dev->process_private; 2018 2019 if (dpni == NULL) { 2020 DPAA2_PMD_ERR("Device has not yet been configured"); 2021 return ret; 2022 } 2023 2024 /*changing tx burst function to avoid any more enqueues */ 2025 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2026 2027 /* Loop while dpni_disable() attempts to drain the egress FQs 2028 * and confirm them back to us. 2029 */ 2030 do { 2031 ret = dpni_disable(dpni, 0, priv->token); 2032 if (ret) { 2033 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 2034 return ret; 2035 } 2036 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 2037 if (ret) { 2038 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 2039 return ret; 2040 } 2041 if (dpni_enabled) 2042 /* Allow the MC some slack */ 2043 rte_delay_us(100 * 1000); 2044 } while (dpni_enabled && --retries); 2045 2046 if (!retries) { 2047 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 2048 /* todo- we may have to manually cleanup queues. 2049 */ 2050 } else { 2051 DPAA2_PMD_INFO("Port %d Link DOWN successful", 2052 dev->data->port_id); 2053 } 2054 2055 dev->data->dev_link.link_status = 0; 2056 2057 return ret; 2058 } 2059 2060 static int 2061 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2062 { 2063 int ret = -EINVAL; 2064 struct dpaa2_dev_priv *priv; 2065 struct fsl_mc_io *dpni; 2066 struct dpni_link_state state = {0}; 2067 2068 PMD_INIT_FUNC_TRACE(); 2069 2070 priv = dev->data->dev_private; 2071 dpni = (struct fsl_mc_io *)dev->process_private; 2072 2073 if (dpni == NULL || fc_conf == NULL) { 2074 DPAA2_PMD_ERR("device not configured"); 2075 return ret; 2076 } 2077 2078 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2079 if (ret) { 2080 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 2081 return ret; 2082 } 2083 2084 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 2085 if (state.options & DPNI_LINK_OPT_PAUSE) { 2086 /* DPNI_LINK_OPT_PAUSE set 2087 * if ASYM_PAUSE not set, 2088 * RX Side flow control (handle received Pause frame) 2089 * TX side flow control (send Pause frame) 2090 * if ASYM_PAUSE set, 2091 * RX Side flow control (handle received Pause frame) 2092 * No TX side flow control (send Pause frame disabled) 2093 */ 2094 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 2095 fc_conf->mode = RTE_ETH_FC_FULL; 2096 else 2097 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 2098 } else { 2099 /* DPNI_LINK_OPT_PAUSE not set 2100 * if ASYM_PAUSE set, 2101 * TX side flow control (send Pause frame) 2102 * No RX side flow control (No action on pause frame rx) 2103 * if ASYM_PAUSE not set, 2104 * Flow control disabled 2105 */ 2106 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 2107 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2108 else 2109 fc_conf->mode = RTE_ETH_FC_NONE; 2110 } 2111 2112 return ret; 2113 } 2114 2115 static int 2116 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2117 { 2118 int ret = -EINVAL; 2119 struct dpaa2_dev_priv *priv; 2120 struct fsl_mc_io *dpni; 2121 struct dpni_link_state state = {0}; 2122 struct dpni_link_cfg cfg = {0}; 2123 2124 PMD_INIT_FUNC_TRACE(); 2125 2126 priv = dev->data->dev_private; 2127 dpni = (struct fsl_mc_io *)dev->process_private; 2128 2129 if (dpni == NULL) { 2130 DPAA2_PMD_ERR("dpni is NULL"); 2131 return ret; 2132 } 2133 2134 /* It is necessary to obtain the current state before setting fc_conf 2135 * as MC would return error in case rate, autoneg or duplex values are 2136 * different. 2137 */ 2138 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 2139 if (ret) { 2140 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 2141 return -1; 2142 } 2143 2144 /* Disable link before setting configuration */ 2145 dpaa2_dev_set_link_down(dev); 2146 2147 /* Based on fc_conf, update cfg */ 2148 cfg.rate = state.rate; 2149 cfg.options = state.options; 2150 2151 /* update cfg with fc_conf */ 2152 switch (fc_conf->mode) { 2153 case RTE_ETH_FC_FULL: 2154 /* Full flow control; 2155 * OPT_PAUSE set, ASYM_PAUSE not set 2156 */ 2157 cfg.options |= DPNI_LINK_OPT_PAUSE; 2158 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2159 break; 2160 case RTE_ETH_FC_TX_PAUSE: 2161 /* Enable RX flow control 2162 * OPT_PAUSE not set; 2163 * ASYM_PAUSE set; 2164 */ 2165 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2166 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2167 break; 2168 case RTE_ETH_FC_RX_PAUSE: 2169 /* Enable TX Flow control 2170 * OPT_PAUSE set 2171 * ASYM_PAUSE set 2172 */ 2173 cfg.options |= DPNI_LINK_OPT_PAUSE; 2174 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2175 break; 2176 case RTE_ETH_FC_NONE: 2177 /* Disable Flow control 2178 * OPT_PAUSE not set 2179 * ASYM_PAUSE not set 2180 */ 2181 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2182 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2183 break; 2184 default: 2185 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2186 fc_conf->mode); 2187 return -1; 2188 } 2189 2190 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2191 if (ret) 2192 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2193 ret); 2194 2195 /* Enable link */ 2196 dpaa2_dev_set_link_up(dev); 2197 2198 return ret; 2199 } 2200 2201 static int 2202 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2203 struct rte_eth_rss_conf *rss_conf) 2204 { 2205 struct rte_eth_dev_data *data = dev->data; 2206 struct dpaa2_dev_priv *priv = data->dev_private; 2207 struct rte_eth_conf *eth_conf = &data->dev_conf; 2208 int ret, tc_index; 2209 2210 PMD_INIT_FUNC_TRACE(); 2211 2212 if (rss_conf->rss_hf) { 2213 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2214 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2215 tc_index); 2216 if (ret) { 2217 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2218 tc_index); 2219 return ret; 2220 } 2221 } 2222 } else { 2223 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2224 ret = dpaa2_remove_flow_dist(dev, tc_index); 2225 if (ret) { 2226 DPAA2_PMD_ERR( 2227 "Unable to remove flow dist on tc%d", 2228 tc_index); 2229 return ret; 2230 } 2231 } 2232 } 2233 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2234 return 0; 2235 } 2236 2237 static int 2238 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2239 struct rte_eth_rss_conf *rss_conf) 2240 { 2241 struct rte_eth_dev_data *data = dev->data; 2242 struct rte_eth_conf *eth_conf = &data->dev_conf; 2243 2244 /* dpaa2 does not support rss_key, so length should be 0*/ 2245 rss_conf->rss_key_len = 0; 2246 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2247 return 0; 2248 } 2249 2250 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2251 int eth_rx_queue_id, 2252 struct dpaa2_dpcon_dev *dpcon, 2253 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2254 { 2255 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2256 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2257 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2258 uint8_t flow_id = dpaa2_ethq->flow_id; 2259 struct dpni_queue cfg; 2260 uint8_t options, priority; 2261 int ret; 2262 2263 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2264 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2265 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2266 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2267 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2268 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2269 else 2270 return -EINVAL; 2271 2272 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2273 (dpcon->num_priorities - 1); 2274 2275 memset(&cfg, 0, sizeof(struct dpni_queue)); 2276 options = DPNI_QUEUE_OPT_DEST; 2277 cfg.destination.type = DPNI_DEST_DPCON; 2278 cfg.destination.id = dpcon->dpcon_id; 2279 cfg.destination.priority = priority; 2280 2281 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2282 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2283 cfg.destination.hold_active = 1; 2284 } 2285 2286 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2287 !eth_priv->en_ordered) { 2288 struct opr_cfg ocfg; 2289 2290 /* Restoration window size = 256 frames */ 2291 ocfg.oprrws = 3; 2292 /* Restoration window size = 512 frames for LX2 */ 2293 if (dpaa2_svr_family == SVR_LX2160A) 2294 ocfg.oprrws = 4; 2295 /* Auto advance NESN window enabled */ 2296 ocfg.oa = 1; 2297 /* Late arrival window size disabled */ 2298 ocfg.olws = 0; 2299 /* ORL resource exhaustion advance NESN disabled */ 2300 ocfg.oeane = 0; 2301 /* Loose ordering enabled */ 2302 ocfg.oloe = 1; 2303 eth_priv->en_loose_ordered = 1; 2304 /* Strict ordering enabled if explicitly set */ 2305 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2306 ocfg.oloe = 0; 2307 eth_priv->en_loose_ordered = 0; 2308 } 2309 2310 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2311 dpaa2_ethq->tc_index, flow_id, 2312 OPR_OPT_CREATE, &ocfg, 0); 2313 if (ret) { 2314 DPAA2_PMD_ERR("Error setting opr: ret: %d", ret); 2315 return ret; 2316 } 2317 2318 eth_priv->en_ordered = 1; 2319 } 2320 2321 options |= DPNI_QUEUE_OPT_USER_CTX; 2322 cfg.user_context = (size_t)(dpaa2_ethq); 2323 2324 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2325 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2326 if (ret) { 2327 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2328 return ret; 2329 } 2330 2331 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2332 2333 return 0; 2334 } 2335 2336 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2337 int eth_rx_queue_id) 2338 { 2339 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2340 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2341 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2342 uint8_t flow_id = dpaa2_ethq->flow_id; 2343 struct dpni_queue cfg; 2344 uint8_t options; 2345 int ret; 2346 2347 memset(&cfg, 0, sizeof(struct dpni_queue)); 2348 options = DPNI_QUEUE_OPT_DEST; 2349 cfg.destination.type = DPNI_DEST_NONE; 2350 2351 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2352 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2353 if (ret) 2354 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2355 2356 return ret; 2357 } 2358 2359 static int 2360 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev, 2361 const struct rte_flow_ops **ops) 2362 { 2363 if (!dev) 2364 return -ENODEV; 2365 2366 *ops = &dpaa2_flow_ops; 2367 return 0; 2368 } 2369 2370 static void 2371 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2372 struct rte_eth_rxq_info *qinfo) 2373 { 2374 struct dpaa2_queue *rxq; 2375 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2376 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2377 uint16_t max_frame_length; 2378 2379 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2380 2381 qinfo->mp = rxq->mb_pool; 2382 qinfo->scattered_rx = dev->data->scattered_rx; 2383 qinfo->nb_desc = rxq->nb_desc; 2384 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 2385 &max_frame_length) == 0) 2386 qinfo->rx_buf_size = max_frame_length; 2387 2388 qinfo->conf.rx_free_thresh = 1; 2389 qinfo->conf.rx_drop_en = 1; 2390 qinfo->conf.rx_deferred_start = 0; 2391 qinfo->conf.offloads = rxq->offloads; 2392 } 2393 2394 static void 2395 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2396 struct rte_eth_txq_info *qinfo) 2397 { 2398 struct dpaa2_queue *txq; 2399 2400 txq = dev->data->tx_queues[queue_id]; 2401 2402 qinfo->nb_desc = txq->nb_desc; 2403 qinfo->conf.tx_thresh.pthresh = 0; 2404 qinfo->conf.tx_thresh.hthresh = 0; 2405 qinfo->conf.tx_thresh.wthresh = 0; 2406 2407 qinfo->conf.tx_free_thresh = 0; 2408 qinfo->conf.tx_rs_thresh = 0; 2409 qinfo->conf.offloads = txq->offloads; 2410 qinfo->conf.tx_deferred_start = 0; 2411 } 2412 2413 static int 2414 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2415 { 2416 *(const void **)ops = &dpaa2_tm_ops; 2417 2418 return 0; 2419 } 2420 2421 void 2422 rte_pmd_dpaa2_thread_init(void) 2423 { 2424 int ret; 2425 2426 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 2427 ret = dpaa2_affine_qbman_swp(); 2428 if (ret) { 2429 DPAA2_PMD_ERR( 2430 "Failed to allocate IO portal, tid: %d", 2431 rte_gettid()); 2432 return; 2433 } 2434 } 2435 } 2436 2437 static struct eth_dev_ops dpaa2_ethdev_ops = { 2438 .dev_configure = dpaa2_eth_dev_configure, 2439 .dev_start = dpaa2_dev_start, 2440 .dev_stop = dpaa2_dev_stop, 2441 .dev_close = dpaa2_dev_close, 2442 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2443 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2444 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2445 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2446 .dev_set_link_up = dpaa2_dev_set_link_up, 2447 .dev_set_link_down = dpaa2_dev_set_link_down, 2448 .link_update = dpaa2_dev_link_update, 2449 .stats_get = dpaa2_dev_stats_get, 2450 .xstats_get = dpaa2_dev_xstats_get, 2451 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2452 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2453 .xstats_get_names = dpaa2_xstats_get_names, 2454 .stats_reset = dpaa2_dev_stats_reset, 2455 .xstats_reset = dpaa2_dev_stats_reset, 2456 .fw_version_get = dpaa2_fw_version_get, 2457 .dev_infos_get = dpaa2_dev_info_get, 2458 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2459 .mtu_set = dpaa2_dev_mtu_set, 2460 .vlan_filter_set = dpaa2_vlan_filter_set, 2461 .vlan_offload_set = dpaa2_vlan_offload_set, 2462 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2463 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2464 .rx_queue_release = dpaa2_dev_rx_queue_release, 2465 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2466 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2467 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2468 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2469 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2470 .mac_addr_add = dpaa2_dev_add_mac_addr, 2471 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2472 .mac_addr_set = dpaa2_dev_set_mac_addr, 2473 .rss_hash_update = dpaa2_dev_rss_hash_update, 2474 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2475 .flow_ops_get = dpaa2_dev_flow_ops_get, 2476 .rxq_info_get = dpaa2_rxq_info_get, 2477 .txq_info_get = dpaa2_txq_info_get, 2478 .tm_ops_get = dpaa2_tm_ops_get, 2479 #if defined(RTE_LIBRTE_IEEE1588) 2480 .timesync_enable = dpaa2_timesync_enable, 2481 .timesync_disable = dpaa2_timesync_disable, 2482 .timesync_read_time = dpaa2_timesync_read_time, 2483 .timesync_write_time = dpaa2_timesync_write_time, 2484 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2485 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2486 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2487 #endif 2488 }; 2489 2490 /* Populate the mac address from physically available (u-boot/firmware) and/or 2491 * one set by higher layers like MC (restool) etc. 2492 * Returns the table of MAC entries (multiple entries) 2493 */ 2494 static int 2495 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2496 struct rte_ether_addr *mac_entry) 2497 { 2498 int ret; 2499 struct rte_ether_addr phy_mac, prime_mac; 2500 2501 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2502 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2503 2504 /* Get the physical device MAC address */ 2505 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2506 phy_mac.addr_bytes); 2507 if (ret) { 2508 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2509 goto cleanup; 2510 } 2511 2512 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2513 prime_mac.addr_bytes); 2514 if (ret) { 2515 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2516 goto cleanup; 2517 } 2518 2519 /* Now that both MAC have been obtained, do: 2520 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2521 * and return phy 2522 * If empty_mac(phy), return prime. 2523 * if both are empty, create random MAC, set as prime and return 2524 */ 2525 if (!rte_is_zero_ether_addr(&phy_mac)) { 2526 /* If the addresses are not same, overwrite prime */ 2527 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2528 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2529 priv->token, 2530 phy_mac.addr_bytes); 2531 if (ret) { 2532 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2533 ret); 2534 goto cleanup; 2535 } 2536 memcpy(&prime_mac, &phy_mac, 2537 sizeof(struct rte_ether_addr)); 2538 } 2539 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2540 /* In case phys and prime, both are zero, create random MAC */ 2541 rte_eth_random_addr(prime_mac.addr_bytes); 2542 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2543 priv->token, 2544 prime_mac.addr_bytes); 2545 if (ret) { 2546 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2547 goto cleanup; 2548 } 2549 } 2550 2551 /* prime_mac the final MAC address */ 2552 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2553 return 0; 2554 2555 cleanup: 2556 return -1; 2557 } 2558 2559 static int 2560 check_devargs_handler(__rte_unused const char *key, const char *value, 2561 __rte_unused void *opaque) 2562 { 2563 if (strcmp(value, "1")) 2564 return -1; 2565 2566 return 0; 2567 } 2568 2569 static int 2570 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2571 { 2572 struct rte_kvargs *kvlist; 2573 2574 if (!devargs) 2575 return 0; 2576 2577 kvlist = rte_kvargs_parse(devargs->args, NULL); 2578 if (!kvlist) 2579 return 0; 2580 2581 if (!rte_kvargs_count(kvlist, key)) { 2582 rte_kvargs_free(kvlist); 2583 return 0; 2584 } 2585 2586 if (rte_kvargs_process(kvlist, key, 2587 check_devargs_handler, NULL) < 0) { 2588 rte_kvargs_free(kvlist); 2589 return 0; 2590 } 2591 rte_kvargs_free(kvlist); 2592 2593 return 1; 2594 } 2595 2596 static int 2597 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2598 { 2599 struct rte_device *dev = eth_dev->device; 2600 struct rte_dpaa2_device *dpaa2_dev; 2601 struct fsl_mc_io *dpni_dev; 2602 struct dpni_attr attr; 2603 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2604 struct dpni_buffer_layout layout; 2605 int ret, hw_id, i; 2606 2607 PMD_INIT_FUNC_TRACE(); 2608 2609 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2610 if (!dpni_dev) { 2611 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2612 return -1; 2613 } 2614 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2615 eth_dev->process_private = (void *)dpni_dev; 2616 2617 /* For secondary processes, the primary has done all the work */ 2618 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2619 /* In case of secondary, only burst and ops API need to be 2620 * plugged. 2621 */ 2622 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2623 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2624 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2625 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2626 else if (dpaa2_get_devargs(dev->devargs, 2627 DRIVER_NO_PREFETCH_MODE)) 2628 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2629 else 2630 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2631 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2632 return 0; 2633 } 2634 2635 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2636 2637 hw_id = dpaa2_dev->object_id; 2638 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2639 if (ret) { 2640 DPAA2_PMD_ERR( 2641 "Failure in opening dpni@%d with err code %d", 2642 hw_id, ret); 2643 rte_free(dpni_dev); 2644 return -1; 2645 } 2646 2647 if (eth_dev->data->dev_conf.lpbk_mode) 2648 dpaa2_dev_recycle_deconfig(eth_dev); 2649 2650 /* Clean the device first */ 2651 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2652 if (ret) { 2653 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2654 hw_id, ret); 2655 goto init_err; 2656 } 2657 2658 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2659 if (ret) { 2660 DPAA2_PMD_ERR( 2661 "Failure in get dpni@%d attribute, err code %d", 2662 hw_id, ret); 2663 goto init_err; 2664 } 2665 2666 priv->num_rx_tc = attr.num_rx_tcs; 2667 priv->num_tx_tc = attr.num_tx_tcs; 2668 priv->qos_entries = attr.qos_entries; 2669 priv->fs_entries = attr.fs_entries; 2670 priv->dist_queues = attr.num_queues; 2671 priv->num_channels = attr.num_channels; 2672 priv->channel_inuse = 0; 2673 rte_spinlock_init(&priv->lpbk_qp_lock); 2674 2675 /* only if the custom CG is enabled */ 2676 if (attr.options & DPNI_OPT_CUSTOM_CG) 2677 priv->max_cgs = attr.num_cgs; 2678 else 2679 priv->max_cgs = 0; 2680 2681 for (i = 0; i < priv->max_cgs; i++) 2682 priv->cgid_in_use[i] = 0; 2683 2684 for (i = 0; i < attr.num_rx_tcs; i++) 2685 priv->nb_rx_queues += attr.num_queues; 2686 2687 priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels; 2688 2689 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2690 priv->num_rx_tc, priv->nb_rx_queues, 2691 priv->nb_tx_queues, priv->max_cgs); 2692 2693 priv->hw = dpni_dev; 2694 priv->hw_id = hw_id; 2695 priv->options = attr.options; 2696 priv->max_mac_filters = attr.mac_filter_entries; 2697 priv->max_vlan_filters = attr.vlan_filter_entries; 2698 priv->flags = 0; 2699 #if defined(RTE_LIBRTE_IEEE1588) 2700 DPAA2_PMD_INFO("DPDK IEEE1588 is enabled"); 2701 priv->flags |= DPAA2_TX_CONF_ENABLE; 2702 #endif 2703 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ 2704 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { 2705 priv->flags |= DPAA2_TX_CONF_ENABLE; 2706 DPAA2_PMD_INFO("TX_CONF Enabled"); 2707 } 2708 2709 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { 2710 dpaa2_enable_err_queue = 1; 2711 DPAA2_PMD_INFO("Enable error queue"); 2712 } 2713 2714 /* Allocate memory for hardware structure for queues */ 2715 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2716 if (ret) { 2717 DPAA2_PMD_ERR("Queue allocation Failed"); 2718 goto init_err; 2719 } 2720 2721 /* Allocate memory for storing MAC addresses. 2722 * Table of mac_filter_entries size is allocated so that RTE ether lib 2723 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2724 */ 2725 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2726 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2727 if (eth_dev->data->mac_addrs == NULL) { 2728 DPAA2_PMD_ERR( 2729 "Failed to allocate %d bytes needed to store MAC addresses", 2730 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2731 ret = -ENOMEM; 2732 goto init_err; 2733 } 2734 2735 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2736 if (ret) { 2737 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2738 rte_free(eth_dev->data->mac_addrs); 2739 eth_dev->data->mac_addrs = NULL; 2740 goto init_err; 2741 } 2742 2743 /* ... tx buffer layout ... */ 2744 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2745 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2746 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2747 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2748 layout.pass_timestamp = true; 2749 } else { 2750 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2751 } 2752 layout.pass_frame_status = 1; 2753 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2754 DPNI_QUEUE_TX, &layout); 2755 if (ret) { 2756 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2757 goto init_err; 2758 } 2759 2760 /* ... tx-conf and error buffer layout ... */ 2761 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2762 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2763 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2764 layout.pass_timestamp = true; 2765 } 2766 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2767 layout.pass_frame_status = 1; 2768 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2769 DPNI_QUEUE_TX_CONFIRM, &layout); 2770 if (ret) { 2771 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2772 ret); 2773 goto init_err; 2774 } 2775 2776 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2777 2778 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2779 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2780 DPAA2_PMD_INFO("Loopback mode"); 2781 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2782 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2783 DPAA2_PMD_INFO("No Prefetch mode"); 2784 } else { 2785 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2786 } 2787 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2788 2789 /* Init fields w.r.t. classification */ 2790 memset(&priv->extract.qos_key_extract, 0, 2791 sizeof(struct dpaa2_key_extract)); 2792 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2793 if (!priv->extract.qos_extract_param) { 2794 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2795 " classification ", ret); 2796 goto init_err; 2797 } 2798 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2799 IP_ADDRESS_OFFSET_INVALID; 2800 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2801 IP_ADDRESS_OFFSET_INVALID; 2802 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2803 IP_ADDRESS_OFFSET_INVALID; 2804 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2805 IP_ADDRESS_OFFSET_INVALID; 2806 2807 for (i = 0; i < MAX_TCS; i++) { 2808 memset(&priv->extract.tc_key_extract[i], 0, 2809 sizeof(struct dpaa2_key_extract)); 2810 priv->extract.tc_extract_param[i] = 2811 (size_t)rte_malloc(NULL, 256, 64); 2812 if (!priv->extract.tc_extract_param[i]) { 2813 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification", 2814 ret); 2815 goto init_err; 2816 } 2817 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2818 IP_ADDRESS_OFFSET_INVALID; 2819 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2820 IP_ADDRESS_OFFSET_INVALID; 2821 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2822 IP_ADDRESS_OFFSET_INVALID; 2823 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2824 IP_ADDRESS_OFFSET_INVALID; 2825 } 2826 2827 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2828 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2829 + VLAN_TAG_SIZE); 2830 if (ret) { 2831 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2832 goto init_err; 2833 } 2834 2835 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2836 * with external entity to receive byte code for software sequence 2837 * and same will be offload to the H/W using MC interface. 2838 * Currently it is assumed that DPAA2 driver has byte code by some 2839 * mean and same if offloaded to H/W. 2840 */ 2841 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2842 WRIOP_SS_INITIALIZER(priv); 2843 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2844 if (ret < 0) { 2845 DPAA2_PMD_ERR(" Error(%d) in loading softparser", 2846 ret); 2847 return ret; 2848 } 2849 2850 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2851 DPNI_SS_INGRESS); 2852 if (ret < 0) { 2853 DPAA2_PMD_ERR(" Error(%d) in enabling softparser", 2854 ret); 2855 return ret; 2856 } 2857 } 2858 DPAA2_PMD_INFO("%s: netdev created, connected to %s", 2859 eth_dev->data->name, dpaa2_dev->ep_name); 2860 2861 return 0; 2862 init_err: 2863 dpaa2_dev_close(eth_dev); 2864 2865 return ret; 2866 } 2867 2868 int dpaa2_dev_is_dpaa2(struct rte_eth_dev *dev) 2869 { 2870 return dev->device->driver == &rte_dpaa2_pmd.driver; 2871 } 2872 2873 static int 2874 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2875 struct rte_dpaa2_device *dpaa2_dev) 2876 { 2877 struct rte_eth_dev *eth_dev; 2878 struct dpaa2_dev_priv *dev_priv; 2879 int diag; 2880 2881 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2882 RTE_PKTMBUF_HEADROOM) { 2883 DPAA2_PMD_ERR( 2884 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2885 RTE_PKTMBUF_HEADROOM, 2886 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2887 2888 return -1; 2889 } 2890 2891 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2892 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2893 if (!eth_dev) 2894 return -ENODEV; 2895 dev_priv = rte_zmalloc("ethdev private structure", 2896 sizeof(struct dpaa2_dev_priv), 2897 RTE_CACHE_LINE_SIZE); 2898 if (dev_priv == NULL) { 2899 DPAA2_PMD_CRIT( 2900 "Unable to allocate memory for private data"); 2901 rte_eth_dev_release_port(eth_dev); 2902 return -ENOMEM; 2903 } 2904 eth_dev->data->dev_private = (void *)dev_priv; 2905 /* Store a pointer to eth_dev in dev_private */ 2906 dev_priv->eth_dev = eth_dev; 2907 } else { 2908 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2909 if (!eth_dev) { 2910 DPAA2_PMD_DEBUG("returning enodev"); 2911 return -ENODEV; 2912 } 2913 } 2914 2915 eth_dev->device = &dpaa2_dev->device; 2916 2917 dpaa2_dev->eth_dev = eth_dev; 2918 eth_dev->data->rx_mbuf_alloc_failed = 0; 2919 2920 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2921 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2922 2923 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 2924 2925 /* Invoke PMD device initialization function */ 2926 diag = dpaa2_dev_init(eth_dev); 2927 if (diag == 0) { 2928 if (!dpaa2_tx_sg_pool) { 2929 dpaa2_tx_sg_pool = 2930 rte_pktmbuf_pool_create("dpaa2_mbuf_tx_sg_pool", 2931 DPAA2_POOL_SIZE, 2932 DPAA2_POOL_CACHE_SIZE, 0, 2933 DPAA2_MAX_SGS * sizeof(struct qbman_sge), 2934 rte_socket_id()); 2935 if (dpaa2_tx_sg_pool == NULL) { 2936 DPAA2_PMD_ERR("SG pool creation failed"); 2937 return -ENOMEM; 2938 } 2939 } 2940 rte_eth_dev_probing_finish(eth_dev); 2941 dpaa2_valid_dev++; 2942 return 0; 2943 } 2944 2945 rte_eth_dev_release_port(eth_dev); 2946 return diag; 2947 } 2948 2949 static int 2950 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2951 { 2952 struct rte_eth_dev *eth_dev; 2953 int ret; 2954 2955 eth_dev = dpaa2_dev->eth_dev; 2956 dpaa2_dev_close(eth_dev); 2957 dpaa2_valid_dev--; 2958 if (!dpaa2_valid_dev) 2959 rte_mempool_free(dpaa2_tx_sg_pool); 2960 ret = rte_eth_dev_release_port(eth_dev); 2961 2962 return ret; 2963 } 2964 2965 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2966 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2967 .drv_type = DPAA2_ETH, 2968 .probe = rte_dpaa2_probe, 2969 .remove = rte_dpaa2_remove, 2970 }; 2971 2972 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd); 2973 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME, 2974 DRIVER_LOOPBACK_MODE "=<int> " 2975 DRIVER_NO_PREFETCH_MODE "=<int>" 2976 DRIVER_TX_CONF "=<int>" 2977 DRIVER_ERROR_QUEUE "=<int>"); 2978 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE); 2979