1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016-2024 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <dev_driver.h> 19 #include <bus_fslmc_driver.h> 20 #include <rte_flow_driver.h> 21 #include "rte_dpaa2_mempool.h" 22 23 #include "dpaa2_pmd_logs.h" 24 #include <fslmc_vfio.h> 25 #include <dpaa2_hw_pvt.h> 26 #include <dpaa2_hw_mempool.h> 27 #include <dpaa2_hw_dpio.h> 28 #include <mc/fsl_dpmng.h> 29 #include "dpaa2_ethdev.h" 30 #include "dpaa2_sparser.h" 31 #include <fsl_qbman_debug.h> 32 33 #define DRIVER_LOOPBACK_MODE "drv_loopback" 34 #define DRIVER_NO_PREFETCH_MODE "drv_no_prefetch" 35 #define DRIVER_TX_CONF "drv_tx_conf" 36 #define DRIVER_ERROR_QUEUE "drv_err_queue" 37 #define CHECK_INTERVAL 100 /* 100ms */ 38 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 39 40 /* Supported Rx offloads */ 41 static uint64_t dev_rx_offloads_sup = 42 RTE_ETH_RX_OFFLOAD_CHECKSUM | 43 RTE_ETH_RX_OFFLOAD_SCTP_CKSUM | 44 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 45 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | 46 RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 47 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | 48 RTE_ETH_RX_OFFLOAD_TIMESTAMP; 49 50 /* Rx offloads which cannot be disabled */ 51 static uint64_t dev_rx_offloads_nodis = 52 RTE_ETH_RX_OFFLOAD_RSS_HASH | 53 RTE_ETH_RX_OFFLOAD_SCATTER; 54 55 /* Supported Tx offloads */ 56 static uint64_t dev_tx_offloads_sup = 57 RTE_ETH_TX_OFFLOAD_VLAN_INSERT | 58 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 59 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 60 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 61 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 62 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 63 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 64 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 65 66 /* Tx offloads which cannot be disabled */ 67 static uint64_t dev_tx_offloads_nodis = 68 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 69 70 /* enable timestamp in mbuf */ 71 bool dpaa2_enable_ts[RTE_MAX_ETHPORTS]; 72 uint64_t dpaa2_timestamp_rx_dynflag; 73 int dpaa2_timestamp_dynfield_offset = -1; 74 75 /* Enable error queue */ 76 bool dpaa2_enable_err_queue; 77 78 #define MAX_NB_RX_DESC 11264 79 int total_nb_rx_desc; 80 81 int dpaa2_valid_dev; 82 struct rte_mempool *dpaa2_tx_sg_pool; 83 84 struct rte_dpaa2_xstats_name_off { 85 char name[RTE_ETH_XSTATS_NAME_SIZE]; 86 uint8_t page_id; /* dpni statistics page id */ 87 uint8_t stats_id; /* stats id in the given page */ 88 }; 89 90 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 91 {"ingress_multicast_frames", 0, 2}, 92 {"ingress_multicast_bytes", 0, 3}, 93 {"ingress_broadcast_frames", 0, 4}, 94 {"ingress_broadcast_bytes", 0, 5}, 95 {"egress_multicast_frames", 1, 2}, 96 {"egress_multicast_bytes", 1, 3}, 97 {"egress_broadcast_frames", 1, 4}, 98 {"egress_broadcast_bytes", 1, 5}, 99 {"ingress_filtered_frames", 2, 0}, 100 {"ingress_discarded_frames", 2, 1}, 101 {"ingress_nobuffer_discards", 2, 2}, 102 {"egress_discarded_frames", 2, 3}, 103 {"egress_confirmed_frames", 2, 4}, 104 {"cgr_reject_frames", 4, 0}, 105 {"cgr_reject_bytes", 4, 1}, 106 }; 107 108 static struct rte_dpaa2_driver rte_dpaa2_pmd; 109 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 110 int wait_to_complete); 111 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 112 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 113 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 114 115 static int 116 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 117 { 118 int ret; 119 struct dpaa2_dev_priv *priv = dev->data->dev_private; 120 struct fsl_mc_io *dpni = dev->process_private; 121 122 PMD_INIT_FUNC_TRACE(); 123 124 if (dpni == NULL) { 125 DPAA2_PMD_ERR("dpni is NULL"); 126 return -1; 127 } 128 129 if (on) 130 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, priv->token, 131 vlan_id, 0, 0, 0); 132 else 133 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 134 priv->token, vlan_id); 135 136 if (ret < 0) 137 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 138 ret, vlan_id, priv->hw_id); 139 140 return ret; 141 } 142 143 static int 144 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 145 { 146 struct dpaa2_dev_priv *priv = dev->data->dev_private; 147 struct fsl_mc_io *dpni = dev->process_private; 148 int ret = 0; 149 150 PMD_INIT_FUNC_TRACE(); 151 152 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 153 /* VLAN Filter not available */ 154 if (!priv->max_vlan_filters) { 155 DPAA2_PMD_INFO("VLAN filter not available"); 156 return -ENOTSUP; 157 } 158 159 if (dev->data->dev_conf.rxmode.offloads & 160 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 161 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 162 priv->token, true); 163 else 164 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 165 priv->token, false); 166 if (ret < 0) 167 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 168 } 169 170 return ret; 171 } 172 173 static int 174 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 175 enum rte_vlan_type vlan_type __rte_unused, 176 uint16_t tpid) 177 { 178 struct dpaa2_dev_priv *priv = dev->data->dev_private; 179 struct fsl_mc_io *dpni = dev->process_private; 180 int ret = -ENOTSUP; 181 182 PMD_INIT_FUNC_TRACE(); 183 184 /* nothing to be done for standard vlan tpids */ 185 if (tpid == 0x8100 || tpid == 0x88A8) 186 return 0; 187 188 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 189 priv->token, tpid); 190 if (ret < 0) 191 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 192 /* if already configured tpids, remove them first */ 193 if (ret == -EBUSY) { 194 struct dpni_custom_tpid_cfg tpid_list = {0}; 195 196 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 197 priv->token, &tpid_list); 198 if (ret < 0) 199 goto fail; 200 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 201 priv->token, tpid_list.tpid1); 202 if (ret < 0) 203 goto fail; 204 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 205 priv->token, tpid); 206 } 207 fail: 208 return ret; 209 } 210 211 static int 212 dpaa2_fw_version_get(struct rte_eth_dev *dev, 213 char *fw_version, 214 size_t fw_size) 215 { 216 int ret; 217 struct fsl_mc_io *dpni = dev->process_private; 218 struct mc_soc_version mc_plat_info = {0}; 219 struct mc_version mc_ver_info = {0}; 220 221 PMD_INIT_FUNC_TRACE(); 222 223 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 224 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 225 226 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 227 DPAA2_PMD_WARN("\tmc_get_version failed"); 228 229 ret = snprintf(fw_version, fw_size, 230 "%x-%d.%d.%d", 231 mc_plat_info.svr, 232 mc_ver_info.major, 233 mc_ver_info.minor, 234 mc_ver_info.revision); 235 if (ret < 0) 236 return -EINVAL; 237 238 ret += 1; /* add the size of '\0' */ 239 if (fw_size < (size_t)ret) 240 return ret; 241 else 242 return 0; 243 } 244 245 static int 246 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 247 { 248 struct dpaa2_dev_priv *priv = dev->data->dev_private; 249 250 PMD_INIT_FUNC_TRACE(); 251 252 dev_info->max_mac_addrs = priv->max_mac_filters; 253 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 254 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 255 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 256 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 257 dev_info->rx_offload_capa = dev_rx_offloads_sup | 258 dev_rx_offloads_nodis; 259 dev_info->tx_offload_capa = dev_tx_offloads_sup | 260 dev_tx_offloads_nodis; 261 dev_info->speed_capa = RTE_ETH_LINK_SPEED_1G | 262 RTE_ETH_LINK_SPEED_2_5G | 263 RTE_ETH_LINK_SPEED_10G; 264 dev_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 265 266 dev_info->max_hash_mac_addrs = 0; 267 dev_info->max_vfs = 0; 268 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 269 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 270 271 dev_info->default_rxportconf.burst_size = dpaa2_dqrr_size; 272 /* same is rx size for best perf */ 273 dev_info->default_txportconf.burst_size = dpaa2_dqrr_size; 274 275 dev_info->default_rxportconf.nb_queues = 1; 276 dev_info->default_txportconf.nb_queues = 1; 277 dev_info->default_txportconf.ring_size = CONG_ENTER_TX_THRESHOLD; 278 dev_info->default_rxportconf.ring_size = DPAA2_RX_DEFAULT_NBDESC; 279 280 if (dpaa2_svr_family == SVR_LX2160A) { 281 dev_info->speed_capa |= RTE_ETH_LINK_SPEED_25G | 282 RTE_ETH_LINK_SPEED_40G | 283 RTE_ETH_LINK_SPEED_50G | 284 RTE_ETH_LINK_SPEED_100G; 285 } 286 287 return 0; 288 } 289 290 static int 291 dpaa2_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 292 __rte_unused uint16_t queue_id, 293 struct rte_eth_burst_mode *mode) 294 { 295 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 296 int ret = -EINVAL; 297 unsigned int i; 298 const struct burst_info { 299 uint64_t flags; 300 const char *output; 301 } rx_offload_map[] = { 302 {RTE_ETH_RX_OFFLOAD_CHECKSUM, " Checksum,"}, 303 {RTE_ETH_RX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 304 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 305 {RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM, " Outer UDP csum,"}, 306 {RTE_ETH_RX_OFFLOAD_VLAN_STRIP, " VLAN strip,"}, 307 {RTE_ETH_RX_OFFLOAD_VLAN_FILTER, " VLAN filter,"}, 308 {RTE_ETH_RX_OFFLOAD_TIMESTAMP, " Timestamp,"}, 309 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"}, 310 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"} 311 }; 312 313 /* Update Rx offload info */ 314 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 315 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 316 snprintf(mode->info, sizeof(mode->info), "%s", 317 rx_offload_map[i].output); 318 ret = 0; 319 break; 320 } 321 } 322 return ret; 323 } 324 325 static int 326 dpaa2_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 327 __rte_unused uint16_t queue_id, 328 struct rte_eth_burst_mode *mode) 329 { 330 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 331 int ret = -EINVAL; 332 unsigned int i; 333 const struct burst_info { 334 uint64_t flags; 335 const char *output; 336 } tx_offload_map[] = { 337 {RTE_ETH_TX_OFFLOAD_VLAN_INSERT, " VLAN Insert,"}, 338 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 339 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 340 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 341 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 342 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 343 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 344 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 345 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 346 }; 347 348 /* Update Tx offload info */ 349 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 350 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 351 snprintf(mode->info, sizeof(mode->info), "%s", 352 tx_offload_map[i].output); 353 ret = 0; 354 break; 355 } 356 } 357 return ret; 358 } 359 360 static int 361 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 362 { 363 struct dpaa2_dev_priv *priv = dev->data->dev_private; 364 uint16_t dist_idx; 365 uint32_t vq_id; 366 uint8_t num_rxqueue_per_tc; 367 struct dpaa2_queue *mc_q, *mcq; 368 uint32_t tot_queues; 369 int i, ret = 0; 370 struct dpaa2_queue *dpaa2_q; 371 372 PMD_INIT_FUNC_TRACE(); 373 374 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 375 if (priv->flags & DPAA2_TX_CONF_ENABLE) 376 tot_queues = priv->nb_rx_queues + 2 * priv->nb_tx_queues; 377 else 378 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 379 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 380 RTE_CACHE_LINE_SIZE); 381 if (!mc_q) { 382 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 383 return -1; 384 } 385 386 for (i = 0; i < priv->nb_rx_queues; i++) { 387 mc_q->eth_data = dev->data; 388 priv->rx_vq[i] = mc_q++; 389 dpaa2_q = priv->rx_vq[i]; 390 ret = dpaa2_queue_storage_alloc(dpaa2_q, 391 RTE_MAX_LCORE); 392 if (ret) 393 goto fail; 394 } 395 396 if (dpaa2_enable_err_queue) { 397 priv->rx_err_vq = rte_zmalloc("dpni_rx_err", 398 sizeof(struct dpaa2_queue), 0); 399 if (!priv->rx_err_vq) 400 goto fail; 401 402 dpaa2_q = priv->rx_err_vq; 403 ret = dpaa2_queue_storage_alloc(dpaa2_q, 404 RTE_MAX_LCORE); 405 if (ret) 406 goto fail; 407 } 408 409 for (i = 0; i < priv->nb_tx_queues; i++) { 410 mc_q->eth_data = dev->data; 411 mc_q->flow_id = 0xffff; 412 priv->tx_vq[i] = mc_q++; 413 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 414 dpaa2_q->cscn = rte_malloc(NULL, 415 sizeof(struct qbman_result), 16); 416 if (!dpaa2_q->cscn) 417 goto fail_tx; 418 } 419 420 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 421 /*Setup tx confirmation queues*/ 422 for (i = 0; i < priv->nb_tx_queues; i++) { 423 mc_q->eth_data = dev->data; 424 mc_q->tc_index = i; 425 mc_q->flow_id = 0; 426 priv->tx_conf_vq[i] = mc_q++; 427 dpaa2_q = priv->tx_conf_vq[i]; 428 ret = dpaa2_queue_storage_alloc(dpaa2_q, 429 RTE_MAX_LCORE); 430 if (ret) 431 goto fail_tx_conf; 432 } 433 } 434 435 vq_id = 0; 436 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 437 mcq = priv->rx_vq[vq_id]; 438 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 439 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 440 vq_id++; 441 } 442 443 return 0; 444 fail_tx_conf: 445 i -= 1; 446 while (i >= 0) { 447 dpaa2_q = priv->tx_conf_vq[i]; 448 dpaa2_queue_storage_free(dpaa2_q, RTE_MAX_LCORE); 449 priv->tx_conf_vq[i--] = NULL; 450 } 451 i = priv->nb_tx_queues; 452 fail_tx: 453 i -= 1; 454 while (i >= 0) { 455 dpaa2_q = priv->tx_vq[i]; 456 rte_free(dpaa2_q->cscn); 457 priv->tx_vq[i--] = NULL; 458 } 459 i = priv->nb_rx_queues; 460 fail: 461 i -= 1; 462 mc_q = priv->rx_vq[0]; 463 while (i >= 0) { 464 dpaa2_q = priv->rx_vq[i]; 465 dpaa2_queue_storage_free(dpaa2_q, RTE_MAX_LCORE); 466 priv->rx_vq[i--] = NULL; 467 } 468 469 if (dpaa2_enable_err_queue) { 470 dpaa2_q = priv->rx_err_vq; 471 dpaa2_queue_storage_free(dpaa2_q, RTE_MAX_LCORE); 472 } 473 474 rte_free(mc_q); 475 return -1; 476 } 477 478 static void 479 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 480 { 481 struct dpaa2_dev_priv *priv = dev->data->dev_private; 482 struct dpaa2_queue *dpaa2_q; 483 int i; 484 485 PMD_INIT_FUNC_TRACE(); 486 487 /* Queue allocation base */ 488 if (priv->rx_vq[0]) { 489 /* cleaning up queue storage */ 490 for (i = 0; i < priv->nb_rx_queues; i++) { 491 dpaa2_q = priv->rx_vq[i]; 492 dpaa2_queue_storage_free(dpaa2_q, 493 RTE_MAX_LCORE); 494 } 495 /* cleanup tx queue cscn */ 496 for (i = 0; i < priv->nb_tx_queues; i++) { 497 dpaa2_q = priv->tx_vq[i]; 498 rte_free(dpaa2_q->cscn); 499 } 500 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 501 /* cleanup tx conf queue storage */ 502 for (i = 0; i < priv->nb_tx_queues; i++) { 503 dpaa2_q = priv->tx_conf_vq[i]; 504 dpaa2_queue_storage_free(dpaa2_q, 505 RTE_MAX_LCORE); 506 } 507 } 508 /*free memory for all queues (RX+TX) */ 509 rte_free(priv->rx_vq[0]); 510 priv->rx_vq[0] = NULL; 511 } 512 } 513 514 static int 515 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 516 { 517 struct dpaa2_dev_priv *priv = dev->data->dev_private; 518 struct fsl_mc_io *dpni = dev->process_private; 519 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 520 uint64_t rx_offloads = eth_conf->rxmode.offloads; 521 uint64_t tx_offloads = eth_conf->txmode.offloads; 522 int rx_l3_csum_offload = false; 523 int rx_l4_csum_offload = false; 524 int tx_l3_csum_offload = false; 525 int tx_l4_csum_offload = false; 526 int ret, tc_index; 527 uint32_t max_rx_pktlen; 528 #if defined(RTE_LIBRTE_IEEE1588) 529 uint16_t ptp_correction_offset; 530 #endif 531 532 PMD_INIT_FUNC_TRACE(); 533 534 /* Rx offloads which are enabled by default */ 535 if (dev_rx_offloads_nodis & ~rx_offloads) { 536 DPAA2_PMD_INFO( 537 "Some of rx offloads enabled by default - requested 0x%" PRIx64 538 " fixed are 0x%" PRIx64, 539 rx_offloads, dev_rx_offloads_nodis); 540 } 541 542 /* Tx offloads which are enabled by default */ 543 if (dev_tx_offloads_nodis & ~tx_offloads) { 544 DPAA2_PMD_INFO( 545 "Some of tx offloads enabled by default - requested 0x%" PRIx64 546 " fixed are 0x%" PRIx64, 547 tx_offloads, dev_tx_offloads_nodis); 548 } 549 550 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 551 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 552 if (max_rx_pktlen <= DPAA2_MAX_RX_PKT_LEN) { 553 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 554 priv->token, max_rx_pktlen - RTE_ETHER_CRC_LEN); 555 if (ret != 0) { 556 DPAA2_PMD_ERR("Unable to set mtu. check config"); 557 return ret; 558 } 559 DPAA2_PMD_DEBUG("MTU configured for the device: %d", 560 dev->data->mtu); 561 } else { 562 DPAA2_PMD_ERR("Configured mtu %d and calculated max-pkt-len is %d which should be <= %d", 563 eth_conf->rxmode.mtu, max_rx_pktlen, DPAA2_MAX_RX_PKT_LEN); 564 return -1; 565 } 566 567 if (eth_conf->rxmode.mq_mode == RTE_ETH_MQ_RX_RSS) { 568 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 569 ret = dpaa2_setup_flow_dist(dev, 570 eth_conf->rx_adv_conf.rss_conf.rss_hf, 571 tc_index); 572 if (ret) { 573 DPAA2_PMD_ERR( 574 "Unable to set flow distribution on tc%d." 575 "Check queue config", tc_index); 576 return ret; 577 } 578 } 579 } 580 581 if (rx_offloads & RTE_ETH_RX_OFFLOAD_IPV4_CKSUM) 582 rx_l3_csum_offload = true; 583 584 if ((rx_offloads & RTE_ETH_RX_OFFLOAD_UDP_CKSUM) || 585 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_CKSUM) || 586 (rx_offloads & RTE_ETH_RX_OFFLOAD_SCTP_CKSUM)) 587 rx_l4_csum_offload = true; 588 589 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 590 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 591 if (ret) { 592 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 593 return ret; 594 } 595 596 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 597 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 598 if (ret) { 599 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 600 return ret; 601 } 602 603 #if !defined(RTE_LIBRTE_IEEE1588) 604 if (rx_offloads & RTE_ETH_RX_OFFLOAD_TIMESTAMP) 605 #endif 606 { 607 ret = rte_mbuf_dyn_rx_timestamp_register( 608 &dpaa2_timestamp_dynfield_offset, 609 &dpaa2_timestamp_rx_dynflag); 610 if (ret != 0) { 611 DPAA2_PMD_ERR("Error to register timestamp field/flag"); 612 return -rte_errno; 613 } 614 dpaa2_enable_ts[dev->data->port_id] = true; 615 } 616 617 #if defined(RTE_LIBRTE_IEEE1588) 618 /* By default setting ptp correction offset for Ethernet SYNC packets */ 619 ptp_correction_offset = RTE_ETHER_HDR_LEN + 8; 620 rte_pmd_dpaa2_set_one_step_ts(dev->data->port_id, ptp_correction_offset, 0); 621 #endif 622 if (tx_offloads & RTE_ETH_TX_OFFLOAD_IPV4_CKSUM) 623 tx_l3_csum_offload = true; 624 625 if ((tx_offloads & RTE_ETH_TX_OFFLOAD_UDP_CKSUM) || 626 (tx_offloads & RTE_ETH_TX_OFFLOAD_TCP_CKSUM) || 627 (tx_offloads & RTE_ETH_TX_OFFLOAD_SCTP_CKSUM)) 628 tx_l4_csum_offload = true; 629 630 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 631 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 632 if (ret) { 633 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 634 return ret; 635 } 636 637 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 638 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 639 if (ret) { 640 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 641 return ret; 642 } 643 644 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 645 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 646 * to 0 for LS2 in the hardware thus disabling data/annotation 647 * stashing. For LX2 this is fixed in hardware and thus hash result and 648 * parse results can be received in FD using this option. 649 */ 650 if (dpaa2_svr_family == SVR_LX2160A) { 651 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 652 DPNI_FLCTYPE_HASH, true); 653 if (ret) { 654 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 655 return ret; 656 } 657 } 658 659 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 660 dpaa2_vlan_offload_set(dev, RTE_ETH_VLAN_FILTER_MASK); 661 662 if (eth_conf->lpbk_mode) { 663 ret = dpaa2_dev_recycle_config(dev); 664 if (ret) { 665 DPAA2_PMD_ERR("Error to configure %s to recycle port.", 666 dev->data->name); 667 668 return ret; 669 } 670 } else { 671 /** User may disable loopback mode by calling 672 * "dev_configure" with lpbk_mode cleared. 673 * No matter the port was configured recycle or not, 674 * recycle de-configure is called here. 675 * If port is not recycled, the de-configure will return directly. 676 */ 677 ret = dpaa2_dev_recycle_deconfig(dev); 678 if (ret) { 679 DPAA2_PMD_ERR("Error to de-configure recycle port %s.", 680 dev->data->name); 681 682 return ret; 683 } 684 } 685 686 dpaa2_tm_init(dev); 687 688 return 0; 689 } 690 691 /* Function to setup RX flow information. It contains traffic class ID, 692 * flow ID, destination configuration etc. 693 */ 694 static int 695 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 696 uint16_t rx_queue_id, 697 uint16_t nb_rx_desc, 698 unsigned int socket_id __rte_unused, 699 const struct rte_eth_rxconf *rx_conf, 700 struct rte_mempool *mb_pool) 701 { 702 struct dpaa2_dev_priv *priv = dev->data->dev_private; 703 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 704 struct dpaa2_queue *dpaa2_q; 705 struct dpni_queue cfg; 706 uint8_t options = 0; 707 uint8_t flow_id; 708 uint32_t bpid; 709 int i, ret; 710 711 PMD_INIT_FUNC_TRACE(); 712 713 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 714 dev, rx_queue_id, mb_pool, rx_conf); 715 716 total_nb_rx_desc += nb_rx_desc; 717 if (total_nb_rx_desc > MAX_NB_RX_DESC) { 718 DPAA2_PMD_WARN("Total nb_rx_desc exceeds %d limit. Please use Normal buffers", 719 MAX_NB_RX_DESC); 720 DPAA2_PMD_WARN("To use Normal buffers, run 'export DPNI_NORMAL_BUF=1' before running dynamic_dpl.sh script"); 721 } 722 723 /* Rx deferred start is not supported */ 724 if (rx_conf->rx_deferred_start) { 725 DPAA2_PMD_ERR("%p:Rx deferred start not supported", 726 (void *)dev); 727 return -EINVAL; 728 } 729 730 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 731 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 732 ret = rte_dpaa2_bpid_info_init(mb_pool); 733 if (ret) 734 return ret; 735 } 736 bpid = mempool_to_bpid(mb_pool); 737 ret = dpaa2_attach_bp_list(priv, dpni, 738 rte_dpaa2_bpid_info[bpid].bp_list); 739 if (ret) 740 return ret; 741 } 742 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 743 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 744 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 745 dpaa2_q->nb_desc = UINT16_MAX; 746 dpaa2_q->offloads = rx_conf->offloads; 747 748 /*Get the flow id from given VQ id*/ 749 flow_id = dpaa2_q->flow_id; 750 memset(&cfg, 0, sizeof(struct dpni_queue)); 751 752 options = options | DPNI_QUEUE_OPT_USER_CTX; 753 cfg.user_context = (size_t)(dpaa2_q); 754 755 /* check if a private cgr available. */ 756 for (i = 0; i < priv->max_cgs; i++) { 757 if (!priv->cgid_in_use[i]) { 758 priv->cgid_in_use[i] = 1; 759 break; 760 } 761 } 762 763 if (i < priv->max_cgs) { 764 options |= DPNI_QUEUE_OPT_SET_CGID; 765 cfg.cgid = i; 766 dpaa2_q->cgid = cfg.cgid; 767 } else { 768 dpaa2_q->cgid = 0xff; 769 } 770 771 /*if ls2088 or rev2 device, enable the stashing */ 772 773 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 774 options |= DPNI_QUEUE_OPT_FLC; 775 cfg.flc.stash_control = true; 776 dpaa2_flc_stashing_clear_all(&cfg.flc.value); 777 if (getenv("DPAA2_DATA_STASHING_OFF")) { 778 dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 0, 779 &cfg.flc.value); 780 dpaa2_q->data_stashing_off = 1; 781 } else { 782 dpaa2_flc_stashing_set(DPAA2_FLC_DATA_STASHING, 1, 783 &cfg.flc.value); 784 dpaa2_q->data_stashing_off = 0; 785 } 786 if ((dpaa2_svr_family & 0xffff0000) != SVR_LX2160A) { 787 dpaa2_flc_stashing_set(DPAA2_FLC_ANNO_STASHING, 1, 788 &cfg.flc.value); 789 } 790 } 791 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 792 dpaa2_q->tc_index, flow_id, options, &cfg); 793 if (ret) { 794 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 795 return -1; 796 } 797 798 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 799 struct dpni_taildrop taildrop; 800 801 taildrop.enable = 1; 802 dpaa2_q->nb_desc = nb_rx_desc; 803 /* Private CGR will use tail drop length as nb_rx_desc. 804 * for rest cases we can use standard byte based tail drop. 805 * There is no HW restriction, but number of CGRs are limited, 806 * hence this restriction is placed. 807 */ 808 if (dpaa2_q->cgid != 0xff) { 809 /*enabling per rx queue congestion control */ 810 taildrop.threshold = nb_rx_desc; 811 taildrop.units = DPNI_CONGESTION_UNIT_FRAMES; 812 taildrop.oal = 0; 813 DPAA2_PMD_DEBUG("Enabling CG Tail Drop on queue = %d", 814 rx_queue_id); 815 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 816 DPNI_CP_CONGESTION_GROUP, 817 DPNI_QUEUE_RX, 818 dpaa2_q->tc_index, 819 dpaa2_q->cgid, &taildrop); 820 } else { 821 /*enabling per rx queue congestion control */ 822 taildrop.threshold = CONG_THRESHOLD_RX_BYTES_Q; 823 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 824 taildrop.oal = CONG_RX_OAL; 825 DPAA2_PMD_DEBUG("Enabling Byte based Drop on queue= %d", 826 rx_queue_id); 827 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 828 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 829 dpaa2_q->tc_index, flow_id, 830 &taildrop); 831 } 832 if (ret) { 833 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 834 ret); 835 return -1; 836 } 837 } else { /* Disable tail Drop */ 838 struct dpni_taildrop taildrop = {0}; 839 DPAA2_PMD_INFO("Tail drop is disabled on queue"); 840 841 taildrop.enable = 0; 842 if (dpaa2_q->cgid != 0xff) { 843 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 844 DPNI_CP_CONGESTION_GROUP, DPNI_QUEUE_RX, 845 dpaa2_q->tc_index, 846 dpaa2_q->cgid, &taildrop); 847 } else { 848 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 849 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 850 dpaa2_q->tc_index, flow_id, &taildrop); 851 } 852 if (ret) { 853 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 854 ret); 855 return -1; 856 } 857 } 858 859 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 860 return 0; 861 } 862 863 static int 864 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 865 uint16_t tx_queue_id, 866 uint16_t nb_tx_desc, 867 unsigned int socket_id __rte_unused, 868 const struct rte_eth_txconf *tx_conf) 869 { 870 struct dpaa2_dev_priv *priv = dev->data->dev_private; 871 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 872 priv->tx_vq[tx_queue_id]; 873 struct dpaa2_queue *dpaa2_tx_conf_q = (struct dpaa2_queue *) 874 priv->tx_conf_vq[tx_queue_id]; 875 struct fsl_mc_io *dpni = dev->process_private; 876 struct dpni_queue tx_conf_cfg; 877 struct dpni_queue tx_flow_cfg; 878 uint8_t options = 0, flow_id; 879 uint8_t ceetm_ch_idx; 880 uint16_t channel_id; 881 struct dpni_queue_id qid; 882 uint32_t tc_id; 883 int ret; 884 885 PMD_INIT_FUNC_TRACE(); 886 887 /* Tx deferred start is not supported */ 888 if (tx_conf->tx_deferred_start) { 889 DPAA2_PMD_ERR("%p:Tx deferred start not supported", 890 (void *)dev); 891 return -EINVAL; 892 } 893 894 dpaa2_q->nb_desc = UINT16_MAX; 895 dpaa2_q->offloads = tx_conf->offloads; 896 897 /* Return if queue already configured */ 898 if (dpaa2_q->flow_id != 0xffff) { 899 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 900 return 0; 901 } 902 903 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 904 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 905 906 if (!tx_queue_id) { 907 for (ceetm_ch_idx = 0; 908 ceetm_ch_idx <= (priv->num_channels - 1); 909 ceetm_ch_idx++) { 910 /*Set tx-conf and error configuration*/ 911 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 912 ret = dpni_set_tx_confirmation_mode(dpni, 913 CMD_PRI_LOW, priv->token, 914 ceetm_ch_idx, 915 DPNI_CONF_AFFINE); 916 } else { 917 ret = dpni_set_tx_confirmation_mode(dpni, 918 CMD_PRI_LOW, priv->token, 919 ceetm_ch_idx, 920 DPNI_CONF_DISABLE); 921 } 922 if (ret) { 923 DPAA2_PMD_ERR("Error(%d) in tx conf setting", 924 ret); 925 return ret; 926 } 927 } 928 } 929 930 tc_id = tx_queue_id % priv->num_tx_tc; 931 channel_id = (uint8_t)(tx_queue_id / priv->num_tx_tc) % priv->num_channels; 932 flow_id = 0; 933 934 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 935 ((channel_id << 8) | tc_id), flow_id, options, &tx_flow_cfg); 936 if (ret) { 937 DPAA2_PMD_ERR("Error in setting the tx flow: " 938 "tc_id=%d, flow=%d err=%d", 939 tc_id, flow_id, ret); 940 return -1; 941 } 942 943 dpaa2_q->flow_id = flow_id; 944 945 dpaa2_q->tc_index = tc_id; 946 947 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 948 DPNI_QUEUE_TX, ((channel_id << 8) | dpaa2_q->tc_index), 949 dpaa2_q->flow_id, &tx_flow_cfg, &qid); 950 if (ret) { 951 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 952 return -1; 953 } 954 dpaa2_q->fqid = qid.fqid; 955 956 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 957 struct dpni_congestion_notification_cfg cong_notif_cfg = {0}; 958 959 dpaa2_q->nb_desc = nb_tx_desc; 960 961 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 962 cong_notif_cfg.threshold_entry = nb_tx_desc; 963 /* Notify that the queue is not congested when the data in 964 * the queue is below this threshold.(90% of value) 965 */ 966 cong_notif_cfg.threshold_exit = (nb_tx_desc * 9) / 10; 967 cong_notif_cfg.message_ctx = 0; 968 cong_notif_cfg.message_iova = 969 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 970 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 971 cong_notif_cfg.notification_mode = 972 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 973 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 974 DPNI_CONG_OPT_COHERENT_WRITE; 975 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 976 977 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 978 priv->token, 979 DPNI_QUEUE_TX, 980 ((channel_id << 8) | tc_id), 981 &cong_notif_cfg); 982 if (ret) { 983 DPAA2_PMD_ERR( 984 "Error in setting tx congestion notification: " 985 "err=%d", ret); 986 return -ret; 987 } 988 } 989 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 990 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 991 992 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 993 dpaa2_q->tx_conf_queue = dpaa2_tx_conf_q; 994 options = options | DPNI_QUEUE_OPT_USER_CTX; 995 tx_conf_cfg.user_context = (size_t)(dpaa2_q); 996 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 997 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index), 998 dpaa2_tx_conf_q->flow_id, options, &tx_conf_cfg); 999 if (ret) { 1000 DPAA2_PMD_ERR("Error in setting the tx conf flow: " 1001 "tc_index=%d, flow=%d err=%d", 1002 dpaa2_tx_conf_q->tc_index, 1003 dpaa2_tx_conf_q->flow_id, ret); 1004 return -1; 1005 } 1006 1007 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1008 DPNI_QUEUE_TX_CONFIRM, ((channel_id << 8) | dpaa2_tx_conf_q->tc_index), 1009 dpaa2_tx_conf_q->flow_id, &tx_conf_cfg, &qid); 1010 if (ret) { 1011 DPAA2_PMD_ERR("Error in getting LFQID err=%d", ret); 1012 return -1; 1013 } 1014 dpaa2_tx_conf_q->fqid = qid.fqid; 1015 } 1016 return 0; 1017 } 1018 1019 static void 1020 dpaa2_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1021 { 1022 struct dpaa2_queue *dpaa2_q = dev->data->rx_queues[rx_queue_id]; 1023 struct dpaa2_dev_priv *priv = dpaa2_q->eth_data->dev_private; 1024 struct fsl_mc_io *dpni = 1025 (struct fsl_mc_io *)priv->eth_dev->process_private; 1026 uint8_t options = 0; 1027 int ret; 1028 struct dpni_queue cfg; 1029 1030 memset(&cfg, 0, sizeof(struct dpni_queue)); 1031 PMD_INIT_FUNC_TRACE(); 1032 1033 total_nb_rx_desc -= dpaa2_q->nb_desc; 1034 1035 if (dpaa2_q->cgid != 0xff) { 1036 options = DPNI_QUEUE_OPT_CLEAR_CGID; 1037 cfg.cgid = dpaa2_q->cgid; 1038 1039 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, 1040 DPNI_QUEUE_RX, 1041 dpaa2_q->tc_index, dpaa2_q->flow_id, 1042 options, &cfg); 1043 if (ret) 1044 DPAA2_PMD_ERR("Unable to clear CGR from q=%u err=%d", 1045 dpaa2_q->fqid, ret); 1046 priv->cgid_in_use[dpaa2_q->cgid] = 0; 1047 dpaa2_q->cgid = 0xff; 1048 } 1049 } 1050 1051 static uint32_t 1052 dpaa2_dev_rx_queue_count(void *rx_queue) 1053 { 1054 int32_t ret; 1055 struct dpaa2_queue *dpaa2_q; 1056 struct qbman_swp *swp; 1057 struct qbman_fq_query_np_rslt state; 1058 uint32_t frame_cnt = 0; 1059 1060 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 1061 ret = dpaa2_affine_qbman_swp(); 1062 if (ret) { 1063 DPAA2_PMD_ERR( 1064 "Failed to allocate IO portal, tid: %d", 1065 rte_gettid()); 1066 return -EINVAL; 1067 } 1068 } 1069 swp = DPAA2_PER_LCORE_PORTAL; 1070 1071 dpaa2_q = rx_queue; 1072 1073 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 1074 frame_cnt = qbman_fq_state_frame_count(&state); 1075 DPAA2_PMD_DP_DEBUG("RX frame count for q(%p) is %u", 1076 rx_queue, frame_cnt); 1077 } 1078 return frame_cnt; 1079 } 1080 1081 static const uint32_t * 1082 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 1083 { 1084 static const uint32_t ptypes[] = { 1085 /*todo -= add more types */ 1086 RTE_PTYPE_L2_ETHER, 1087 RTE_PTYPE_L3_IPV4, 1088 RTE_PTYPE_L3_IPV4_EXT, 1089 RTE_PTYPE_L3_IPV6, 1090 RTE_PTYPE_L3_IPV6_EXT, 1091 RTE_PTYPE_L4_TCP, 1092 RTE_PTYPE_L4_UDP, 1093 RTE_PTYPE_L4_SCTP, 1094 RTE_PTYPE_L4_ICMP, 1095 }; 1096 1097 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 1098 dev->rx_pkt_burst == dpaa2_dev_rx || 1099 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) { 1100 *no_of_elements = RTE_DIM(ptypes); 1101 return ptypes; 1102 } 1103 return NULL; 1104 } 1105 1106 /** 1107 * Dpaa2 link Interrupt handler 1108 * 1109 * @param param 1110 * The address of parameter (struct rte_eth_dev *) registered before. 1111 * 1112 * @return 1113 * void 1114 */ 1115 static void 1116 dpaa2_interrupt_handler(void *param) 1117 { 1118 struct rte_eth_dev *dev = param; 1119 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1120 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1121 int ret; 1122 int irq_index = DPNI_IRQ_INDEX; 1123 unsigned int status = 0, clear = 0; 1124 1125 PMD_INIT_FUNC_TRACE(); 1126 1127 if (dpni == NULL) { 1128 DPAA2_PMD_ERR("dpni is NULL"); 1129 return; 1130 } 1131 1132 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 1133 irq_index, &status); 1134 if (unlikely(ret)) { 1135 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 1136 clear = 0xffffffff; 1137 goto out; 1138 } 1139 1140 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 1141 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 1142 dpaa2_dev_link_update(dev, 0); 1143 /* calling all the apps registered for link status event */ 1144 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 1145 } 1146 out: 1147 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 1148 irq_index, clear); 1149 if (unlikely(ret)) 1150 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 1151 } 1152 1153 static int 1154 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 1155 { 1156 int err = 0; 1157 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1158 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1159 int irq_index = DPNI_IRQ_INDEX; 1160 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 1161 1162 PMD_INIT_FUNC_TRACE(); 1163 1164 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 1165 irq_index, mask); 1166 if (err < 0) { 1167 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 1168 strerror(-err)); 1169 return err; 1170 } 1171 1172 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 1173 irq_index, enable); 1174 if (err < 0) 1175 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 1176 strerror(-err)); 1177 1178 return err; 1179 } 1180 1181 static int 1182 dpaa2_dev_start(struct rte_eth_dev *dev) 1183 { 1184 struct rte_device *rdev = dev->device; 1185 struct rte_dpaa2_device *dpaa2_dev; 1186 struct rte_eth_dev_data *data = dev->data; 1187 struct dpaa2_dev_priv *priv = data->dev_private; 1188 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1189 struct dpni_queue cfg; 1190 struct dpni_error_cfg err_cfg; 1191 struct dpni_queue_id qid; 1192 struct dpaa2_queue *dpaa2_q; 1193 int ret, i; 1194 struct rte_intr_handle *intr_handle; 1195 1196 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1197 intr_handle = dpaa2_dev->intr_handle; 1198 1199 PMD_INIT_FUNC_TRACE(); 1200 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1201 if (ret) { 1202 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 1203 priv->hw_id, ret); 1204 return ret; 1205 } 1206 1207 /* Power up the phy. Needed to make the link go UP */ 1208 dpaa2_dev_set_link_up(dev); 1209 1210 for (i = 0; i < data->nb_rx_queues; i++) { 1211 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 1212 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1213 DPNI_QUEUE_RX, dpaa2_q->tc_index, 1214 dpaa2_q->flow_id, &cfg, &qid); 1215 if (ret) { 1216 DPAA2_PMD_ERR("Error in getting flow information: " 1217 "err=%d", ret); 1218 return ret; 1219 } 1220 dpaa2_q->fqid = qid.fqid; 1221 } 1222 1223 if (dpaa2_enable_err_queue) { 1224 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 1225 DPNI_QUEUE_RX_ERR, 0, 0, &cfg, &qid); 1226 if (ret) { 1227 DPAA2_PMD_ERR("Error getting rx err flow information: err=%d", 1228 ret); 1229 return ret; 1230 } 1231 dpaa2_q = (struct dpaa2_queue *)priv->rx_err_vq; 1232 dpaa2_q->fqid = qid.fqid; 1233 dpaa2_q->eth_data = dev->data; 1234 1235 err_cfg.errors = DPNI_ERROR_DISC; 1236 err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE; 1237 } else { 1238 /* checksum errors, send them to normal path 1239 * and set it in annotation 1240 */ 1241 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 1242 1243 /* if packet with parse error are not to be dropped */ 1244 err_cfg.errors |= DPNI_ERROR_PHE; 1245 1246 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 1247 } 1248 err_cfg.set_frame_annotation = true; 1249 1250 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 1251 priv->token, &err_cfg); 1252 if (ret) { 1253 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 1254 ret); 1255 return ret; 1256 } 1257 1258 /* if the interrupts were configured on this devices*/ 1259 if (intr_handle && rte_intr_fd_get(intr_handle) && 1260 dev->data->dev_conf.intr_conf.lsc != 0) { 1261 /* Registering LSC interrupt handler */ 1262 rte_intr_callback_register(intr_handle, 1263 dpaa2_interrupt_handler, 1264 (void *)dev); 1265 1266 /* enable vfio intr/eventfd mapping 1267 * Interrupt index 0 is required, so we can not use 1268 * rte_intr_enable. 1269 */ 1270 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 1271 1272 /* enable dpni_irqs */ 1273 dpaa2_eth_setup_irqs(dev, 1); 1274 } 1275 1276 /* Change the tx burst function if ordered queues are used */ 1277 if (priv->en_ordered) 1278 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 1279 1280 for (i = 0; i < dev->data->nb_rx_queues; i++) 1281 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1282 for (i = 0; i < dev->data->nb_tx_queues; i++) 1283 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 1284 1285 return 0; 1286 } 1287 1288 /** 1289 * This routine disables all traffic on the adapter by issuing a 1290 * global reset on the MAC. 1291 */ 1292 static int 1293 dpaa2_dev_stop(struct rte_eth_dev *dev) 1294 { 1295 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1296 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1297 int ret; 1298 struct rte_eth_link link; 1299 struct rte_device *rdev = dev->device; 1300 struct rte_intr_handle *intr_handle; 1301 struct rte_dpaa2_device *dpaa2_dev; 1302 uint16_t i; 1303 1304 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 1305 intr_handle = dpaa2_dev->intr_handle; 1306 1307 PMD_INIT_FUNC_TRACE(); 1308 1309 /* reset interrupt callback */ 1310 if (intr_handle && rte_intr_fd_get(intr_handle) && 1311 dev->data->dev_conf.intr_conf.lsc != 0) { 1312 /*disable dpni irqs */ 1313 dpaa2_eth_setup_irqs(dev, 0); 1314 1315 /* disable vfio intr before callback unregister */ 1316 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 1317 1318 /* Unregistering LSC interrupt handler */ 1319 rte_intr_callback_unregister(intr_handle, 1320 dpaa2_interrupt_handler, 1321 (void *)dev); 1322 } 1323 1324 dpaa2_dev_set_link_down(dev); 1325 1326 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 1327 if (ret) { 1328 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 1329 ret, priv->hw_id); 1330 return ret; 1331 } 1332 1333 /* clear the recorded link status */ 1334 memset(&link, 0, sizeof(link)); 1335 rte_eth_linkstatus_set(dev, &link); 1336 1337 for (i = 0; i < dev->data->nb_rx_queues; i++) 1338 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1339 for (i = 0; i < dev->data->nb_tx_queues; i++) 1340 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 1341 1342 return 0; 1343 } 1344 1345 static int 1346 dpaa2_dev_close(struct rte_eth_dev *dev) 1347 { 1348 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1349 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1350 int i, ret; 1351 struct rte_eth_link link; 1352 1353 PMD_INIT_FUNC_TRACE(); 1354 1355 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1356 return 0; 1357 1358 if (!dpni) { 1359 DPAA2_PMD_WARN("Already closed or not started"); 1360 return -1; 1361 } 1362 1363 dpaa2_tm_deinit(dev); 1364 dpaa2_flow_clean(dev); 1365 /* Clean the device first */ 1366 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 1367 if (ret) { 1368 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 1369 return -1; 1370 } 1371 1372 memset(&link, 0, sizeof(link)); 1373 rte_eth_linkstatus_set(dev, &link); 1374 1375 /* Free private queues memory */ 1376 dpaa2_free_rx_tx_queues(dev); 1377 /* Close the device at underlying layer*/ 1378 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 1379 if (ret) { 1380 DPAA2_PMD_ERR("Failure closing dpni device with err code %d", 1381 ret); 1382 } 1383 1384 /* Free the allocated memory for ethernet private data and dpni*/ 1385 priv->hw = NULL; 1386 dev->process_private = NULL; 1387 rte_free(dpni); 1388 1389 for (i = 0; i < MAX_TCS; i++) 1390 rte_free((void *)(size_t)priv->extract.tc_extract_param[i]); 1391 1392 if (priv->extract.qos_extract_param) 1393 rte_free((void *)(size_t)priv->extract.qos_extract_param); 1394 1395 DPAA2_PMD_INFO("%s: netdev deleted", dev->data->name); 1396 return 0; 1397 } 1398 1399 static int 1400 dpaa2_dev_promiscuous_enable( 1401 struct rte_eth_dev *dev) 1402 { 1403 int ret; 1404 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1405 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1406 1407 PMD_INIT_FUNC_TRACE(); 1408 1409 if (dpni == NULL) { 1410 DPAA2_PMD_ERR("dpni is NULL"); 1411 return -ENODEV; 1412 } 1413 1414 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1415 if (ret < 0) 1416 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1417 1418 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1419 if (ret < 0) 1420 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1421 1422 return ret; 1423 } 1424 1425 static int 1426 dpaa2_dev_promiscuous_disable( 1427 struct rte_eth_dev *dev) 1428 { 1429 int ret; 1430 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1431 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1432 1433 PMD_INIT_FUNC_TRACE(); 1434 1435 if (dpni == NULL) { 1436 DPAA2_PMD_ERR("dpni is NULL"); 1437 return -ENODEV; 1438 } 1439 1440 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1441 if (ret < 0) 1442 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1443 1444 if (dev->data->all_multicast == 0) { 1445 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1446 priv->token, false); 1447 if (ret < 0) 1448 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1449 ret); 1450 } 1451 1452 return ret; 1453 } 1454 1455 static int 1456 dpaa2_dev_allmulticast_enable( 1457 struct rte_eth_dev *dev) 1458 { 1459 int ret; 1460 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1461 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1462 1463 PMD_INIT_FUNC_TRACE(); 1464 1465 if (dpni == NULL) { 1466 DPAA2_PMD_ERR("dpni is NULL"); 1467 return -ENODEV; 1468 } 1469 1470 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1471 if (ret < 0) 1472 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1473 1474 return ret; 1475 } 1476 1477 static int 1478 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1479 { 1480 int ret; 1481 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1482 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1483 1484 PMD_INIT_FUNC_TRACE(); 1485 1486 if (dpni == NULL) { 1487 DPAA2_PMD_ERR("dpni is NULL"); 1488 return -ENODEV; 1489 } 1490 1491 /* must remain on for all promiscuous */ 1492 if (dev->data->promiscuous == 1) 1493 return 0; 1494 1495 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1496 if (ret < 0) 1497 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1498 1499 return ret; 1500 } 1501 1502 static int 1503 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1504 { 1505 int ret; 1506 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1507 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1508 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1509 + VLAN_TAG_SIZE; 1510 1511 PMD_INIT_FUNC_TRACE(); 1512 1513 if (dpni == NULL) { 1514 DPAA2_PMD_ERR("dpni is NULL"); 1515 return -EINVAL; 1516 } 1517 1518 /* Set the Max Rx frame length as 'mtu' + 1519 * Maximum Ethernet header length 1520 */ 1521 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1522 frame_size - RTE_ETHER_CRC_LEN); 1523 if (ret) { 1524 DPAA2_PMD_ERR("Setting the max frame length failed"); 1525 return -1; 1526 } 1527 dev->data->mtu = mtu; 1528 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1529 return 0; 1530 } 1531 1532 static int 1533 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1534 struct rte_ether_addr *addr, 1535 __rte_unused uint32_t index, 1536 __rte_unused uint32_t pool) 1537 { 1538 int ret; 1539 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1540 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1541 1542 PMD_INIT_FUNC_TRACE(); 1543 1544 if (dpni == NULL) { 1545 DPAA2_PMD_ERR("dpni is NULL"); 1546 return -1; 1547 } 1548 1549 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, priv->token, 1550 addr->addr_bytes, 0, 0, 0); 1551 if (ret) 1552 DPAA2_PMD_ERR( 1553 "error: Adding the MAC ADDR failed: err = %d", ret); 1554 return 0; 1555 } 1556 1557 static void 1558 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1559 uint32_t index) 1560 { 1561 int ret; 1562 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1563 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1564 struct rte_eth_dev_data *data = dev->data; 1565 struct rte_ether_addr *macaddr; 1566 1567 PMD_INIT_FUNC_TRACE(); 1568 1569 macaddr = &data->mac_addrs[index]; 1570 1571 if (dpni == NULL) { 1572 DPAA2_PMD_ERR("dpni is NULL"); 1573 return; 1574 } 1575 1576 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1577 priv->token, macaddr->addr_bytes); 1578 if (ret) 1579 DPAA2_PMD_ERR( 1580 "error: Removing the MAC ADDR failed: err = %d", ret); 1581 } 1582 1583 static int 1584 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1585 struct rte_ether_addr *addr) 1586 { 1587 int ret; 1588 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1589 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1590 1591 PMD_INIT_FUNC_TRACE(); 1592 1593 if (dpni == NULL) { 1594 DPAA2_PMD_ERR("dpni is NULL"); 1595 return -EINVAL; 1596 } 1597 1598 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1599 priv->token, addr->addr_bytes); 1600 1601 if (ret) 1602 DPAA2_PMD_ERR( 1603 "error: Setting the MAC ADDR failed %d", ret); 1604 1605 return ret; 1606 } 1607 1608 static 1609 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1610 struct rte_eth_stats *stats) 1611 { 1612 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1613 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1614 int32_t retcode; 1615 uint8_t page0 = 0, page1 = 1, page2 = 2; 1616 union dpni_statistics value; 1617 int i; 1618 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1619 1620 memset(&value, 0, sizeof(union dpni_statistics)); 1621 1622 PMD_INIT_FUNC_TRACE(); 1623 1624 if (!dpni) { 1625 DPAA2_PMD_ERR("dpni is NULL"); 1626 return -EINVAL; 1627 } 1628 1629 if (!stats) { 1630 DPAA2_PMD_ERR("stats is NULL"); 1631 return -EINVAL; 1632 } 1633 1634 /*Get Counters from page_0*/ 1635 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1636 page0, 0, &value); 1637 if (retcode) 1638 goto err; 1639 1640 stats->ipackets = value.page_0.ingress_all_frames; 1641 stats->ibytes = value.page_0.ingress_all_bytes; 1642 1643 /*Get Counters from page_1*/ 1644 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1645 page1, 0, &value); 1646 if (retcode) 1647 goto err; 1648 1649 stats->opackets = value.page_1.egress_all_frames; 1650 stats->obytes = value.page_1.egress_all_bytes; 1651 1652 /*Get Counters from page_2*/ 1653 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1654 page2, 0, &value); 1655 if (retcode) 1656 goto err; 1657 1658 /* Ingress drop frame count due to configured rules */ 1659 stats->ierrors = value.page_2.ingress_filtered_frames; 1660 /* Ingress drop frame count due to error */ 1661 stats->ierrors += value.page_2.ingress_discarded_frames; 1662 1663 stats->oerrors = value.page_2.egress_discarded_frames; 1664 stats->imissed = value.page_2.ingress_nobuffer_discards; 1665 1666 /* Fill in per queue stats */ 1667 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1668 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1669 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1670 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1671 if (dpaa2_rxq) 1672 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1673 if (dpaa2_txq) 1674 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1675 1676 /* Byte counting is not implemented */ 1677 stats->q_ibytes[i] = 0; 1678 stats->q_obytes[i] = 0; 1679 } 1680 1681 return 0; 1682 1683 err: 1684 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1685 return retcode; 1686 }; 1687 1688 static int 1689 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1690 unsigned int n) 1691 { 1692 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1693 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1694 int32_t retcode; 1695 union dpni_statistics value[5] = {}; 1696 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1697 1698 if (n < num) 1699 return num; 1700 1701 if (xstats == NULL) 1702 return 0; 1703 1704 /* Get Counters from page_0*/ 1705 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1706 0, 0, &value[0]); 1707 if (retcode) 1708 goto err; 1709 1710 /* Get Counters from page_1*/ 1711 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1712 1, 0, &value[1]); 1713 if (retcode) 1714 goto err; 1715 1716 /* Get Counters from page_2*/ 1717 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1718 2, 0, &value[2]); 1719 if (retcode) 1720 goto err; 1721 1722 for (i = 0; i < priv->max_cgs; i++) { 1723 if (!priv->cgid_in_use[i]) { 1724 /* Get Counters from page_4*/ 1725 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, 1726 priv->token, 1727 4, 0, &value[4]); 1728 if (retcode) 1729 goto err; 1730 break; 1731 } 1732 } 1733 1734 for (i = 0; i < num; i++) { 1735 xstats[i].id = i; 1736 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1737 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1738 } 1739 return i; 1740 err: 1741 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1742 return retcode; 1743 } 1744 1745 static int 1746 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1747 struct rte_eth_xstat_name *xstats_names, 1748 unsigned int limit) 1749 { 1750 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1751 1752 if (limit < stat_cnt) 1753 return stat_cnt; 1754 1755 if (xstats_names != NULL) 1756 for (i = 0; i < stat_cnt; i++) 1757 strlcpy(xstats_names[i].name, 1758 dpaa2_xstats_strings[i].name, 1759 sizeof(xstats_names[i].name)); 1760 1761 return stat_cnt; 1762 } 1763 1764 static int 1765 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1766 uint64_t *values, unsigned int n) 1767 { 1768 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1769 uint64_t values_copy[stat_cnt]; 1770 1771 if (!ids) { 1772 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1773 struct fsl_mc_io *dpni = 1774 (struct fsl_mc_io *)dev->process_private; 1775 int32_t retcode; 1776 union dpni_statistics value[5] = {}; 1777 1778 if (n < stat_cnt) 1779 return stat_cnt; 1780 1781 if (!values) 1782 return 0; 1783 1784 /* Get Counters from page_0*/ 1785 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1786 0, 0, &value[0]); 1787 if (retcode) 1788 return 0; 1789 1790 /* Get Counters from page_1*/ 1791 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1792 1, 0, &value[1]); 1793 if (retcode) 1794 return 0; 1795 1796 /* Get Counters from page_2*/ 1797 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1798 2, 0, &value[2]); 1799 if (retcode) 1800 return 0; 1801 1802 /* Get Counters from page_4*/ 1803 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1804 4, 0, &value[4]); 1805 if (retcode) 1806 return 0; 1807 1808 for (i = 0; i < stat_cnt; i++) { 1809 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1810 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1811 } 1812 return stat_cnt; 1813 } 1814 1815 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1816 1817 for (i = 0; i < n; i++) { 1818 if (ids[i] >= stat_cnt) { 1819 DPAA2_PMD_ERR("xstats id value isn't valid"); 1820 return -1; 1821 } 1822 values[i] = values_copy[ids[i]]; 1823 } 1824 return n; 1825 } 1826 1827 static int 1828 dpaa2_xstats_get_names_by_id( 1829 struct rte_eth_dev *dev, 1830 const uint64_t *ids, 1831 struct rte_eth_xstat_name *xstats_names, 1832 unsigned int limit) 1833 { 1834 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1835 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1836 1837 if (!ids) 1838 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1839 1840 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1841 1842 for (i = 0; i < limit; i++) { 1843 if (ids[i] >= stat_cnt) { 1844 DPAA2_PMD_ERR("xstats id value isn't valid"); 1845 return -1; 1846 } 1847 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1848 } 1849 return limit; 1850 } 1851 1852 static int 1853 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1854 { 1855 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1856 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1857 int retcode; 1858 int i; 1859 struct dpaa2_queue *dpaa2_q; 1860 1861 PMD_INIT_FUNC_TRACE(); 1862 1863 if (dpni == NULL) { 1864 DPAA2_PMD_ERR("dpni is NULL"); 1865 return -EINVAL; 1866 } 1867 1868 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1869 if (retcode) 1870 goto error; 1871 1872 /* Reset the per queue stats in dpaa2_queue structure */ 1873 for (i = 0; i < priv->nb_rx_queues; i++) { 1874 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1875 if (dpaa2_q) 1876 dpaa2_q->rx_pkts = 0; 1877 } 1878 1879 for (i = 0; i < priv->nb_tx_queues; i++) { 1880 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1881 if (dpaa2_q) 1882 dpaa2_q->tx_pkts = 0; 1883 } 1884 1885 return 0; 1886 1887 error: 1888 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1889 return retcode; 1890 }; 1891 1892 /* return 0 means link status changed, -1 means not changed */ 1893 static int 1894 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1895 int wait_to_complete) 1896 { 1897 int ret; 1898 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1899 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 1900 struct rte_eth_link link; 1901 struct dpni_link_state state = {0}; 1902 uint8_t count; 1903 1904 if (dpni == NULL) { 1905 DPAA2_PMD_ERR("dpni is NULL"); 1906 return 0; 1907 } 1908 1909 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 1910 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, 1911 &state); 1912 if (ret < 0) { 1913 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1914 return -1; 1915 } 1916 if (state.up == RTE_ETH_LINK_DOWN && 1917 wait_to_complete) 1918 rte_delay_ms(CHECK_INTERVAL); 1919 else 1920 break; 1921 } 1922 1923 memset(&link, 0, sizeof(struct rte_eth_link)); 1924 link.link_status = state.up; 1925 link.link_speed = state.rate; 1926 1927 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1928 link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 1929 else 1930 link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1931 1932 ret = rte_eth_linkstatus_set(dev, &link); 1933 if (ret == -1) 1934 DPAA2_PMD_DEBUG("No change in status"); 1935 else 1936 DPAA2_PMD_INFO("Port %d Link is %s", dev->data->port_id, 1937 link.link_status ? "Up" : "Down"); 1938 1939 return ret; 1940 } 1941 1942 /** 1943 * Toggle the DPNI to enable, if not already enabled. 1944 * This is not strictly PHY up/down - it is more of logical toggling. 1945 */ 1946 static int 1947 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1948 { 1949 int ret = -EINVAL; 1950 struct dpaa2_dev_priv *priv; 1951 struct fsl_mc_io *dpni; 1952 int en = 0; 1953 struct dpni_link_state state = {0}; 1954 1955 priv = dev->data->dev_private; 1956 dpni = (struct fsl_mc_io *)dev->process_private; 1957 1958 if (dpni == NULL) { 1959 DPAA2_PMD_ERR("dpni is NULL"); 1960 return ret; 1961 } 1962 1963 /* Check if DPNI is currently enabled */ 1964 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1965 if (ret) { 1966 /* Unable to obtain dpni status; Not continuing */ 1967 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1968 return ret; 1969 } 1970 1971 /* Enable link if not already enabled */ 1972 if (!en) { 1973 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1974 if (ret) { 1975 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1976 return ret; 1977 } 1978 } 1979 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1980 if (ret < 0) { 1981 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1982 return ret; 1983 } 1984 1985 /* changing tx burst function to start enqueues */ 1986 dev->tx_pkt_burst = dpaa2_dev_tx; 1987 dev->data->dev_link.link_status = state.up; 1988 dev->data->dev_link.link_speed = state.rate; 1989 1990 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1991 dev->data->dev_link.link_duplex = RTE_ETH_LINK_HALF_DUPLEX; 1992 else 1993 dev->data->dev_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1994 1995 if (state.up) 1996 DPAA2_PMD_DEBUG("Port %d Link is Up", dev->data->port_id); 1997 else 1998 DPAA2_PMD_DEBUG("Port %d Link is Down", dev->data->port_id); 1999 return ret; 2000 } 2001 2002 /** 2003 * Toggle the DPNI to disable, if not already disabled. 2004 * This is not strictly PHY up/down - it is more of logical toggling. 2005 */ 2006 static int 2007 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 2008 { 2009 int ret = -EINVAL; 2010 struct dpaa2_dev_priv *priv; 2011 struct fsl_mc_io *dpni; 2012 int dpni_enabled = 0; 2013 int retries = 10; 2014 2015 PMD_INIT_FUNC_TRACE(); 2016 2017 priv = dev->data->dev_private; 2018 dpni = (struct fsl_mc_io *)dev->process_private; 2019 2020 if (dpni == NULL) { 2021 DPAA2_PMD_ERR("Device has not yet been configured"); 2022 return ret; 2023 } 2024 2025 /*changing tx burst function to avoid any more enqueues */ 2026 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2027 2028 /* Loop while dpni_disable() attempts to drain the egress FQs 2029 * and confirm them back to us. 2030 */ 2031 do { 2032 ret = dpni_disable(dpni, 0, priv->token); 2033 if (ret) { 2034 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 2035 return ret; 2036 } 2037 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 2038 if (ret) { 2039 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 2040 return ret; 2041 } 2042 if (dpni_enabled) 2043 /* Allow the MC some slack */ 2044 rte_delay_us(100 * 1000); 2045 } while (dpni_enabled && --retries); 2046 2047 if (!retries) { 2048 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 2049 /* todo- we may have to manually cleanup queues. 2050 */ 2051 } else { 2052 DPAA2_PMD_INFO("Port %d Link DOWN successful", 2053 dev->data->port_id); 2054 } 2055 2056 dev->data->dev_link.link_status = 0; 2057 2058 return ret; 2059 } 2060 2061 static int 2062 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2063 { 2064 int ret = -EINVAL; 2065 struct dpaa2_dev_priv *priv; 2066 struct fsl_mc_io *dpni; 2067 struct dpni_link_cfg cfg = {0}; 2068 2069 PMD_INIT_FUNC_TRACE(); 2070 2071 priv = dev->data->dev_private; 2072 dpni = (struct fsl_mc_io *)dev->process_private; 2073 2074 if (dpni == NULL || fc_conf == NULL) { 2075 DPAA2_PMD_ERR("device not configured"); 2076 return ret; 2077 } 2078 2079 ret = dpni_get_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2080 if (ret) { 2081 DPAA2_PMD_ERR("error: dpni_get_link_cfg %d", ret); 2082 return ret; 2083 } 2084 2085 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 2086 if (cfg.options & DPNI_LINK_OPT_PAUSE) { 2087 /* DPNI_LINK_OPT_PAUSE set 2088 * if ASYM_PAUSE not set, 2089 * RX Side flow control (handle received Pause frame) 2090 * TX side flow control (send Pause frame) 2091 * if ASYM_PAUSE set, 2092 * RX Side flow control (handle received Pause frame) 2093 * No TX side flow control (send Pause frame disabled) 2094 */ 2095 if (!(cfg.options & DPNI_LINK_OPT_ASYM_PAUSE)) 2096 fc_conf->mode = RTE_ETH_FC_FULL; 2097 else 2098 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 2099 } else { 2100 /* DPNI_LINK_OPT_PAUSE not set 2101 * if ASYM_PAUSE set, 2102 * TX side flow control (send Pause frame) 2103 * No RX side flow control (No action on pause frame rx) 2104 * if ASYM_PAUSE not set, 2105 * Flow control disabled 2106 */ 2107 if (cfg.options & DPNI_LINK_OPT_ASYM_PAUSE) 2108 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2109 else 2110 fc_conf->mode = RTE_ETH_FC_NONE; 2111 } 2112 2113 return ret; 2114 } 2115 2116 static int 2117 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 2118 { 2119 int ret = -EINVAL; 2120 struct dpaa2_dev_priv *priv; 2121 struct fsl_mc_io *dpni; 2122 struct dpni_link_cfg cfg = {0}; 2123 2124 PMD_INIT_FUNC_TRACE(); 2125 2126 priv = dev->data->dev_private; 2127 dpni = (struct fsl_mc_io *)dev->process_private; 2128 2129 if (dpni == NULL) { 2130 DPAA2_PMD_ERR("dpni is NULL"); 2131 return ret; 2132 } 2133 2134 /* It is necessary to obtain the current cfg before setting fc_conf 2135 * as MC would return error in case rate, autoneg or duplex values are 2136 * different. 2137 */ 2138 ret = dpni_get_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2139 if (ret) { 2140 DPAA2_PMD_ERR("Unable to get link cfg (err=%d)", ret); 2141 return ret; 2142 } 2143 2144 /* Disable link before setting configuration */ 2145 dpaa2_dev_set_link_down(dev); 2146 2147 /* update cfg with fc_conf */ 2148 switch (fc_conf->mode) { 2149 case RTE_ETH_FC_FULL: 2150 /* Full flow control; 2151 * OPT_PAUSE set, ASYM_PAUSE not set 2152 */ 2153 cfg.options |= DPNI_LINK_OPT_PAUSE; 2154 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2155 break; 2156 case RTE_ETH_FC_TX_PAUSE: 2157 /* Enable RX flow control 2158 * OPT_PAUSE not set; 2159 * ASYM_PAUSE set; 2160 */ 2161 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2162 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2163 break; 2164 case RTE_ETH_FC_RX_PAUSE: 2165 /* Enable TX Flow control 2166 * OPT_PAUSE set 2167 * ASYM_PAUSE set 2168 */ 2169 cfg.options |= DPNI_LINK_OPT_PAUSE; 2170 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 2171 break; 2172 case RTE_ETH_FC_NONE: 2173 /* Disable Flow control 2174 * OPT_PAUSE not set 2175 * ASYM_PAUSE not set 2176 */ 2177 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 2178 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 2179 break; 2180 default: 2181 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 2182 fc_conf->mode); 2183 return -EINVAL; 2184 } 2185 2186 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2187 if (ret) 2188 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 2189 ret); 2190 2191 /* Enable link */ 2192 dpaa2_dev_set_link_up(dev); 2193 2194 return ret; 2195 } 2196 2197 static int 2198 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 2199 struct rte_eth_rss_conf *rss_conf) 2200 { 2201 struct rte_eth_dev_data *data = dev->data; 2202 struct dpaa2_dev_priv *priv = data->dev_private; 2203 struct rte_eth_conf *eth_conf = &data->dev_conf; 2204 int ret, tc_index; 2205 2206 PMD_INIT_FUNC_TRACE(); 2207 2208 if (rss_conf->rss_hf) { 2209 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2210 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf, 2211 tc_index); 2212 if (ret) { 2213 DPAA2_PMD_ERR("Unable to set flow dist on tc%d", 2214 tc_index); 2215 return ret; 2216 } 2217 } 2218 } else { 2219 for (tc_index = 0; tc_index < priv->num_rx_tc; tc_index++) { 2220 ret = dpaa2_remove_flow_dist(dev, tc_index); 2221 if (ret) { 2222 DPAA2_PMD_ERR( 2223 "Unable to remove flow dist on tc%d", 2224 tc_index); 2225 return ret; 2226 } 2227 } 2228 } 2229 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 2230 return 0; 2231 } 2232 2233 static int 2234 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 2235 struct rte_eth_rss_conf *rss_conf) 2236 { 2237 struct rte_eth_dev_data *data = dev->data; 2238 struct rte_eth_conf *eth_conf = &data->dev_conf; 2239 2240 /* dpaa2 does not support rss_key, so length should be 0*/ 2241 rss_conf->rss_key_len = 0; 2242 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 2243 return 0; 2244 } 2245 2246 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 2247 int eth_rx_queue_id, 2248 struct dpaa2_dpcon_dev *dpcon, 2249 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 2250 { 2251 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2252 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2253 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2254 uint8_t flow_id = dpaa2_ethq->flow_id; 2255 struct dpni_queue cfg; 2256 uint8_t options, priority; 2257 int ret; 2258 2259 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 2260 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 2261 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 2262 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 2263 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 2264 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 2265 else 2266 return -EINVAL; 2267 2268 priority = (RTE_EVENT_DEV_PRIORITY_LOWEST / queue_conf->ev.priority) * 2269 (dpcon->num_priorities - 1); 2270 2271 memset(&cfg, 0, sizeof(struct dpni_queue)); 2272 options = DPNI_QUEUE_OPT_DEST; 2273 cfg.destination.type = DPNI_DEST_DPCON; 2274 cfg.destination.id = dpcon->dpcon_id; 2275 cfg.destination.priority = priority; 2276 2277 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 2278 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 2279 cfg.destination.hold_active = 1; 2280 } 2281 2282 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 2283 !eth_priv->en_ordered) { 2284 struct opr_cfg ocfg; 2285 2286 /* Restoration window size = 256 frames */ 2287 ocfg.oprrws = 3; 2288 /* Restoration window size = 512 frames for LX2 */ 2289 if (dpaa2_svr_family == SVR_LX2160A) 2290 ocfg.oprrws = 4; 2291 /* Auto advance NESN window enabled */ 2292 ocfg.oa = 1; 2293 /* Late arrival window size disabled */ 2294 ocfg.olws = 0; 2295 /* ORL resource exhaustion advance NESN disabled */ 2296 ocfg.oeane = 0; 2297 /* Loose ordering enabled */ 2298 ocfg.oloe = 1; 2299 eth_priv->en_loose_ordered = 1; 2300 /* Strict ordering enabled if explicitly set */ 2301 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 2302 ocfg.oloe = 0; 2303 eth_priv->en_loose_ordered = 0; 2304 } 2305 2306 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 2307 dpaa2_ethq->tc_index, flow_id, 2308 OPR_OPT_CREATE, &ocfg, 0); 2309 if (ret) { 2310 DPAA2_PMD_ERR("Error setting opr: ret: %d", ret); 2311 return ret; 2312 } 2313 2314 eth_priv->en_ordered = 1; 2315 } 2316 2317 options |= DPNI_QUEUE_OPT_USER_CTX; 2318 cfg.user_context = (size_t)(dpaa2_ethq); 2319 2320 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2321 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2322 if (ret) { 2323 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2324 return ret; 2325 } 2326 2327 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 2328 2329 return 0; 2330 } 2331 2332 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 2333 int eth_rx_queue_id) 2334 { 2335 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 2336 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2337 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 2338 uint8_t flow_id = dpaa2_ethq->flow_id; 2339 struct dpni_queue cfg; 2340 uint8_t options; 2341 int ret; 2342 2343 memset(&cfg, 0, sizeof(struct dpni_queue)); 2344 options = DPNI_QUEUE_OPT_DEST; 2345 cfg.destination.type = DPNI_DEST_NONE; 2346 2347 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 2348 dpaa2_ethq->tc_index, flow_id, options, &cfg); 2349 if (ret) 2350 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 2351 2352 return ret; 2353 } 2354 2355 static int 2356 dpaa2_dev_flow_ops_get(struct rte_eth_dev *dev, 2357 const struct rte_flow_ops **ops) 2358 { 2359 if (!dev) 2360 return -ENODEV; 2361 2362 *ops = &dpaa2_flow_ops; 2363 return 0; 2364 } 2365 2366 static void 2367 dpaa2_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2368 struct rte_eth_rxq_info *qinfo) 2369 { 2370 struct dpaa2_queue *rxq; 2371 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2372 struct fsl_mc_io *dpni = (struct fsl_mc_io *)dev->process_private; 2373 uint16_t max_frame_length; 2374 2375 rxq = (struct dpaa2_queue *)dev->data->rx_queues[queue_id]; 2376 2377 qinfo->mp = rxq->mb_pool; 2378 qinfo->scattered_rx = dev->data->scattered_rx; 2379 qinfo->nb_desc = rxq->nb_desc; 2380 if (dpni_get_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 2381 &max_frame_length) == 0) 2382 qinfo->rx_buf_size = max_frame_length; 2383 2384 qinfo->conf.rx_free_thresh = 1; 2385 qinfo->conf.rx_drop_en = 1; 2386 qinfo->conf.rx_deferred_start = 0; 2387 qinfo->conf.offloads = rxq->offloads; 2388 } 2389 2390 static void 2391 dpaa2_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 2392 struct rte_eth_txq_info *qinfo) 2393 { 2394 struct dpaa2_queue *txq; 2395 2396 txq = dev->data->tx_queues[queue_id]; 2397 2398 qinfo->nb_desc = txq->nb_desc; 2399 qinfo->conf.tx_thresh.pthresh = 0; 2400 qinfo->conf.tx_thresh.hthresh = 0; 2401 qinfo->conf.tx_thresh.wthresh = 0; 2402 2403 qinfo->conf.tx_free_thresh = 0; 2404 qinfo->conf.tx_rs_thresh = 0; 2405 qinfo->conf.offloads = txq->offloads; 2406 qinfo->conf.tx_deferred_start = 0; 2407 } 2408 2409 static int 2410 dpaa2_tm_ops_get(struct rte_eth_dev *dev __rte_unused, void *ops) 2411 { 2412 *(const void **)ops = &dpaa2_tm_ops; 2413 2414 return 0; 2415 } 2416 2417 void 2418 rte_pmd_dpaa2_thread_init(void) 2419 { 2420 int ret; 2421 2422 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 2423 ret = dpaa2_affine_qbman_swp(); 2424 if (ret) { 2425 DPAA2_PMD_ERR( 2426 "Failed to allocate IO portal, tid: %d", 2427 rte_gettid()); 2428 return; 2429 } 2430 } 2431 } 2432 2433 static struct eth_dev_ops dpaa2_ethdev_ops = { 2434 .dev_configure = dpaa2_eth_dev_configure, 2435 .dev_start = dpaa2_dev_start, 2436 .dev_stop = dpaa2_dev_stop, 2437 .dev_close = dpaa2_dev_close, 2438 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 2439 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 2440 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 2441 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 2442 .dev_set_link_up = dpaa2_dev_set_link_up, 2443 .dev_set_link_down = dpaa2_dev_set_link_down, 2444 .link_update = dpaa2_dev_link_update, 2445 .stats_get = dpaa2_dev_stats_get, 2446 .xstats_get = dpaa2_dev_xstats_get, 2447 .xstats_get_by_id = dpaa2_xstats_get_by_id, 2448 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 2449 .xstats_get_names = dpaa2_xstats_get_names, 2450 .stats_reset = dpaa2_dev_stats_reset, 2451 .xstats_reset = dpaa2_dev_stats_reset, 2452 .fw_version_get = dpaa2_fw_version_get, 2453 .dev_infos_get = dpaa2_dev_info_get, 2454 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 2455 .mtu_set = dpaa2_dev_mtu_set, 2456 .vlan_filter_set = dpaa2_vlan_filter_set, 2457 .vlan_offload_set = dpaa2_vlan_offload_set, 2458 .vlan_tpid_set = dpaa2_vlan_tpid_set, 2459 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 2460 .rx_queue_release = dpaa2_dev_rx_queue_release, 2461 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 2462 .rx_burst_mode_get = dpaa2_dev_rx_burst_mode_get, 2463 .tx_burst_mode_get = dpaa2_dev_tx_burst_mode_get, 2464 .flow_ctrl_get = dpaa2_flow_ctrl_get, 2465 .flow_ctrl_set = dpaa2_flow_ctrl_set, 2466 .mac_addr_add = dpaa2_dev_add_mac_addr, 2467 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 2468 .mac_addr_set = dpaa2_dev_set_mac_addr, 2469 .rss_hash_update = dpaa2_dev_rss_hash_update, 2470 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 2471 .flow_ops_get = dpaa2_dev_flow_ops_get, 2472 .rxq_info_get = dpaa2_rxq_info_get, 2473 .txq_info_get = dpaa2_txq_info_get, 2474 .tm_ops_get = dpaa2_tm_ops_get, 2475 #if defined(RTE_LIBRTE_IEEE1588) 2476 .timesync_enable = dpaa2_timesync_enable, 2477 .timesync_disable = dpaa2_timesync_disable, 2478 .timesync_read_time = dpaa2_timesync_read_time, 2479 .timesync_write_time = dpaa2_timesync_write_time, 2480 .timesync_adjust_time = dpaa2_timesync_adjust_time, 2481 .timesync_read_rx_timestamp = dpaa2_timesync_read_rx_timestamp, 2482 .timesync_read_tx_timestamp = dpaa2_timesync_read_tx_timestamp, 2483 #endif 2484 }; 2485 2486 /* Populate the mac address from physically available (u-boot/firmware) and/or 2487 * one set by higher layers like MC (restool) etc. 2488 * Returns the table of MAC entries (multiple entries) 2489 */ 2490 static int 2491 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2492 struct rte_ether_addr *mac_entry) 2493 { 2494 int ret; 2495 struct rte_ether_addr phy_mac, prime_mac; 2496 2497 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2498 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2499 2500 /* Get the physical device MAC address */ 2501 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2502 phy_mac.addr_bytes); 2503 if (ret) { 2504 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2505 goto cleanup; 2506 } 2507 2508 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2509 prime_mac.addr_bytes); 2510 if (ret) { 2511 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2512 goto cleanup; 2513 } 2514 2515 /* Now that both MAC have been obtained, do: 2516 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2517 * and return phy 2518 * If empty_mac(phy), return prime. 2519 * if both are empty, create random MAC, set as prime and return 2520 */ 2521 if (!rte_is_zero_ether_addr(&phy_mac)) { 2522 /* If the addresses are not same, overwrite prime */ 2523 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2524 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2525 priv->token, 2526 phy_mac.addr_bytes); 2527 if (ret) { 2528 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2529 ret); 2530 goto cleanup; 2531 } 2532 memcpy(&prime_mac, &phy_mac, 2533 sizeof(struct rte_ether_addr)); 2534 } 2535 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2536 /* In case phys and prime, both are zero, create random MAC */ 2537 rte_eth_random_addr(prime_mac.addr_bytes); 2538 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2539 priv->token, 2540 prime_mac.addr_bytes); 2541 if (ret) { 2542 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2543 goto cleanup; 2544 } 2545 } 2546 2547 /* prime_mac the final MAC address */ 2548 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2549 return 0; 2550 2551 cleanup: 2552 return -1; 2553 } 2554 2555 static int 2556 check_devargs_handler(__rte_unused const char *key, const char *value, 2557 __rte_unused void *opaque) 2558 { 2559 if (strcmp(value, "1")) 2560 return -1; 2561 2562 return 0; 2563 } 2564 2565 static int 2566 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2567 { 2568 struct rte_kvargs *kvlist; 2569 2570 if (!devargs) 2571 return 0; 2572 2573 kvlist = rte_kvargs_parse(devargs->args, NULL); 2574 if (!kvlist) 2575 return 0; 2576 2577 if (!rte_kvargs_count(kvlist, key)) { 2578 rte_kvargs_free(kvlist); 2579 return 0; 2580 } 2581 2582 if (rte_kvargs_process(kvlist, key, 2583 check_devargs_handler, NULL) < 0) { 2584 rte_kvargs_free(kvlist); 2585 return 0; 2586 } 2587 rte_kvargs_free(kvlist); 2588 2589 return 1; 2590 } 2591 2592 static int 2593 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2594 { 2595 struct rte_device *dev = eth_dev->device; 2596 struct rte_dpaa2_device *dpaa2_dev; 2597 struct fsl_mc_io *dpni_dev; 2598 struct dpni_attr attr; 2599 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2600 struct dpni_buffer_layout layout; 2601 int ret, hw_id, i; 2602 2603 PMD_INIT_FUNC_TRACE(); 2604 2605 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2606 if (!dpni_dev) { 2607 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2608 return -1; 2609 } 2610 dpni_dev->regs = dpaa2_get_mcp_ptr(MC_PORTAL_INDEX); 2611 eth_dev->process_private = (void *)dpni_dev; 2612 2613 /* For secondary processes, the primary has done all the work */ 2614 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2615 /* In case of secondary, only burst and ops API need to be 2616 * plugged. 2617 */ 2618 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2619 eth_dev->rx_queue_count = dpaa2_dev_rx_queue_count; 2620 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2621 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2622 else if (dpaa2_get_devargs(dev->devargs, 2623 DRIVER_NO_PREFETCH_MODE)) 2624 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2625 else 2626 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2627 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2628 return 0; 2629 } 2630 2631 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2632 2633 hw_id = dpaa2_dev->object_id; 2634 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2635 if (ret) { 2636 DPAA2_PMD_ERR( 2637 "Failure in opening dpni@%d with err code %d", 2638 hw_id, ret); 2639 rte_free(dpni_dev); 2640 return -1; 2641 } 2642 2643 if (eth_dev->data->dev_conf.lpbk_mode) 2644 dpaa2_dev_recycle_deconfig(eth_dev); 2645 2646 /* Clean the device first */ 2647 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2648 if (ret) { 2649 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2650 hw_id, ret); 2651 goto init_err; 2652 } 2653 2654 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2655 if (ret) { 2656 DPAA2_PMD_ERR( 2657 "Failure in get dpni@%d attribute, err code %d", 2658 hw_id, ret); 2659 goto init_err; 2660 } 2661 2662 priv->num_rx_tc = attr.num_rx_tcs; 2663 priv->num_tx_tc = attr.num_tx_tcs; 2664 priv->qos_entries = attr.qos_entries; 2665 priv->fs_entries = attr.fs_entries; 2666 priv->dist_queues = attr.num_queues; 2667 priv->num_channels = attr.num_channels; 2668 priv->channel_inuse = 0; 2669 rte_spinlock_init(&priv->lpbk_qp_lock); 2670 2671 /* only if the custom CG is enabled */ 2672 if (attr.options & DPNI_OPT_CUSTOM_CG) 2673 priv->max_cgs = attr.num_cgs; 2674 else 2675 priv->max_cgs = 0; 2676 2677 for (i = 0; i < priv->max_cgs; i++) 2678 priv->cgid_in_use[i] = 0; 2679 2680 for (i = 0; i < attr.num_rx_tcs; i++) 2681 priv->nb_rx_queues += attr.num_queues; 2682 2683 priv->nb_tx_queues = attr.num_tx_tcs * attr.num_channels; 2684 2685 DPAA2_PMD_DEBUG("RX-TC= %d, rx_queues= %d, tx_queues=%d, max_cgs=%d", 2686 priv->num_rx_tc, priv->nb_rx_queues, 2687 priv->nb_tx_queues, priv->max_cgs); 2688 2689 priv->hw = dpni_dev; 2690 priv->hw_id = hw_id; 2691 priv->options = attr.options; 2692 priv->max_mac_filters = attr.mac_filter_entries; 2693 priv->max_vlan_filters = attr.vlan_filter_entries; 2694 priv->flags = 0; 2695 #if defined(RTE_LIBRTE_IEEE1588) 2696 DPAA2_PMD_INFO("DPDK IEEE1588 is enabled"); 2697 priv->flags |= DPAA2_TX_CONF_ENABLE; 2698 #endif 2699 /* Used with ``fslmc:dpni.1,drv_tx_conf=1`` */ 2700 if (dpaa2_get_devargs(dev->devargs, DRIVER_TX_CONF)) { 2701 priv->flags |= DPAA2_TX_CONF_ENABLE; 2702 DPAA2_PMD_INFO("TX_CONF Enabled"); 2703 } 2704 2705 if (dpaa2_get_devargs(dev->devargs, DRIVER_ERROR_QUEUE)) { 2706 dpaa2_enable_err_queue = 1; 2707 DPAA2_PMD_INFO("Enable DMA error checks"); 2708 } 2709 2710 /* Allocate memory for hardware structure for queues */ 2711 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2712 if (ret) { 2713 DPAA2_PMD_ERR("Queue allocation Failed"); 2714 goto init_err; 2715 } 2716 2717 /* Allocate memory for storing MAC addresses. 2718 * Table of mac_filter_entries size is allocated so that RTE ether lib 2719 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2720 */ 2721 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2722 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2723 if (eth_dev->data->mac_addrs == NULL) { 2724 DPAA2_PMD_ERR( 2725 "Failed to allocate %d bytes needed to store MAC addresses", 2726 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2727 ret = -ENOMEM; 2728 goto init_err; 2729 } 2730 2731 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2732 if (ret) { 2733 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2734 rte_free(eth_dev->data->mac_addrs); 2735 eth_dev->data->mac_addrs = NULL; 2736 goto init_err; 2737 } 2738 2739 /* ... tx buffer layout ... */ 2740 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2741 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2742 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS | 2743 DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2744 layout.pass_timestamp = true; 2745 } else { 2746 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2747 } 2748 layout.pass_frame_status = 1; 2749 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2750 DPNI_QUEUE_TX, &layout); 2751 if (ret) { 2752 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2753 goto init_err; 2754 } 2755 2756 /* ... tx-conf and error buffer layout ... */ 2757 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2758 if (priv->flags & DPAA2_TX_CONF_ENABLE) { 2759 layout.options = DPNI_BUF_LAYOUT_OPT_TIMESTAMP; 2760 layout.pass_timestamp = true; 2761 } 2762 layout.options |= DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2763 layout.pass_frame_status = 1; 2764 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2765 DPNI_QUEUE_TX_CONFIRM, &layout); 2766 if (ret) { 2767 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2768 ret); 2769 goto init_err; 2770 } 2771 2772 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2773 2774 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2775 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2776 DPAA2_PMD_INFO("Loopback mode"); 2777 } else if (dpaa2_get_devargs(dev->devargs, DRIVER_NO_PREFETCH_MODE)) { 2778 eth_dev->rx_pkt_burst = dpaa2_dev_rx; 2779 DPAA2_PMD_INFO("No Prefetch mode"); 2780 } else { 2781 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2782 } 2783 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2784 2785 /* Init fields w.r.t. classification */ 2786 memset(&priv->extract.qos_key_extract, 0, 2787 sizeof(struct dpaa2_key_extract)); 2788 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2789 if (!priv->extract.qos_extract_param) { 2790 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2791 " classification ", ret); 2792 goto init_err; 2793 } 2794 priv->extract.qos_key_extract.key_info.ipv4_src_offset = 2795 IP_ADDRESS_OFFSET_INVALID; 2796 priv->extract.qos_key_extract.key_info.ipv4_dst_offset = 2797 IP_ADDRESS_OFFSET_INVALID; 2798 priv->extract.qos_key_extract.key_info.ipv6_src_offset = 2799 IP_ADDRESS_OFFSET_INVALID; 2800 priv->extract.qos_key_extract.key_info.ipv6_dst_offset = 2801 IP_ADDRESS_OFFSET_INVALID; 2802 2803 for (i = 0; i < MAX_TCS; i++) { 2804 memset(&priv->extract.tc_key_extract[i], 0, 2805 sizeof(struct dpaa2_key_extract)); 2806 priv->extract.tc_extract_param[i] = 2807 (size_t)rte_malloc(NULL, 256, 64); 2808 if (!priv->extract.tc_extract_param[i]) { 2809 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classification", 2810 ret); 2811 goto init_err; 2812 } 2813 priv->extract.tc_key_extract[i].key_info.ipv4_src_offset = 2814 IP_ADDRESS_OFFSET_INVALID; 2815 priv->extract.tc_key_extract[i].key_info.ipv4_dst_offset = 2816 IP_ADDRESS_OFFSET_INVALID; 2817 priv->extract.tc_key_extract[i].key_info.ipv6_src_offset = 2818 IP_ADDRESS_OFFSET_INVALID; 2819 priv->extract.tc_key_extract[i].key_info.ipv6_dst_offset = 2820 IP_ADDRESS_OFFSET_INVALID; 2821 } 2822 2823 ret = dpni_set_max_frame_length(dpni_dev, CMD_PRI_LOW, priv->token, 2824 RTE_ETHER_MAX_LEN - RTE_ETHER_CRC_LEN 2825 + VLAN_TAG_SIZE); 2826 if (ret) { 2827 DPAA2_PMD_ERR("Unable to set mtu. check config"); 2828 goto init_err; 2829 } 2830 eth_dev->data->mtu = RTE_ETHER_MTU; 2831 2832 /*TODO To enable soft parser support DPAA2 driver needs to integrate 2833 * with external entity to receive byte code for software sequence 2834 * and same will be offload to the H/W using MC interface. 2835 * Currently it is assumed that DPAA2 driver has byte code by some 2836 * mean and same if offloaded to H/W. 2837 */ 2838 if (getenv("DPAA2_ENABLE_SOFT_PARSER")) { 2839 WRIOP_SS_INITIALIZER(priv); 2840 ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS); 2841 if (ret < 0) { 2842 DPAA2_PMD_ERR(" Error(%d) in loading softparser", 2843 ret); 2844 return ret; 2845 } 2846 2847 ret = dpaa2_eth_enable_wriop_soft_parser(priv, 2848 DPNI_SS_INGRESS); 2849 if (ret < 0) { 2850 DPAA2_PMD_ERR(" Error(%d) in enabling softparser", 2851 ret); 2852 return ret; 2853 } 2854 } 2855 DPAA2_PMD_INFO("%s: netdev created, connected to %s", 2856 eth_dev->data->name, dpaa2_dev->ep_name); 2857 2858 return 0; 2859 init_err: 2860 dpaa2_dev_close(eth_dev); 2861 2862 return ret; 2863 } 2864 2865 int 2866 rte_pmd_dpaa2_dev_is_dpaa2(uint32_t eth_id) 2867 { 2868 struct rte_eth_dev *dev; 2869 2870 if (eth_id >= RTE_MAX_ETHPORTS) 2871 return false; 2872 2873 dev = &rte_eth_devices[eth_id]; 2874 if (!dev->device) 2875 return false; 2876 2877 return dev->device->driver == &rte_dpaa2_pmd.driver; 2878 } 2879 2880 #if defined(RTE_LIBRTE_IEEE1588) 2881 int 2882 rte_pmd_dpaa2_get_one_step_ts(uint16_t port_id, bool mc_query) 2883 { 2884 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 2885 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2886 struct fsl_mc_io *dpni = priv->eth_dev->process_private; 2887 struct dpni_single_step_cfg ptp_cfg; 2888 int err; 2889 2890 if (!mc_query) 2891 return priv->ptp_correction_offset; 2892 2893 err = dpni_get_single_step_cfg(dpni, CMD_PRI_LOW, priv->token, &ptp_cfg); 2894 if (err) { 2895 DPAA2_PMD_ERR("Failed to retrieve onestep configuration"); 2896 return err; 2897 } 2898 2899 if (!ptp_cfg.ptp_onestep_reg_base) { 2900 DPAA2_PMD_ERR("1588 onestep reg not available"); 2901 return -1; 2902 } 2903 2904 priv->ptp_correction_offset = ptp_cfg.offset; 2905 2906 return priv->ptp_correction_offset; 2907 } 2908 2909 int 2910 rte_pmd_dpaa2_set_one_step_ts(uint16_t port_id, uint16_t offset, uint8_t ch_update) 2911 { 2912 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 2913 struct dpaa2_dev_priv *priv = dev->data->dev_private; 2914 struct fsl_mc_io *dpni = dev->process_private; 2915 struct dpni_single_step_cfg cfg; 2916 int err; 2917 2918 cfg.en = 1; 2919 cfg.ch_update = ch_update; 2920 cfg.offset = offset; 2921 cfg.peer_delay = 0; 2922 2923 err = dpni_set_single_step_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 2924 if (err) 2925 return err; 2926 2927 priv->ptp_correction_offset = offset; 2928 2929 return 0; 2930 } 2931 #endif 2932 2933 static int dpaa2_tx_sg_pool_init(void) 2934 { 2935 char name[RTE_MEMZONE_NAMESIZE]; 2936 2937 if (dpaa2_tx_sg_pool) 2938 return 0; 2939 2940 sprintf(name, "dpaa2_mbuf_tx_sg_pool"); 2941 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2942 dpaa2_tx_sg_pool = rte_pktmbuf_pool_create(name, 2943 DPAA2_POOL_SIZE, 2944 DPAA2_POOL_CACHE_SIZE, 0, 2945 DPAA2_MAX_SGS * sizeof(struct qbman_sge), 2946 rte_socket_id()); 2947 if (!dpaa2_tx_sg_pool) { 2948 DPAA2_PMD_ERR("SG pool creation failed"); 2949 return -ENOMEM; 2950 } 2951 } else { 2952 dpaa2_tx_sg_pool = rte_mempool_lookup(name); 2953 if (!dpaa2_tx_sg_pool) { 2954 DPAA2_PMD_ERR("SG pool lookup failed"); 2955 return -ENOMEM; 2956 } 2957 } 2958 2959 return 0; 2960 } 2961 2962 static int 2963 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2964 struct rte_dpaa2_device *dpaa2_dev) 2965 { 2966 struct rte_eth_dev *eth_dev; 2967 struct dpaa2_dev_priv *dev_priv; 2968 int diag; 2969 2970 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2971 RTE_PKTMBUF_HEADROOM) { 2972 DPAA2_PMD_ERR( 2973 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2974 RTE_PKTMBUF_HEADROOM, 2975 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2976 2977 return -1; 2978 } 2979 2980 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2981 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2982 if (!eth_dev) 2983 return -ENODEV; 2984 dev_priv = rte_zmalloc("ethdev private structure", 2985 sizeof(struct dpaa2_dev_priv), 2986 RTE_CACHE_LINE_SIZE); 2987 if (dev_priv == NULL) { 2988 DPAA2_PMD_CRIT( 2989 "Unable to allocate memory for private data"); 2990 rte_eth_dev_release_port(eth_dev); 2991 return -ENOMEM; 2992 } 2993 eth_dev->data->dev_private = (void *)dev_priv; 2994 /* Store a pointer to eth_dev in dev_private */ 2995 dev_priv->eth_dev = eth_dev; 2996 } else { 2997 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2998 if (!eth_dev) { 2999 DPAA2_PMD_DEBUG("returning enodev"); 3000 return -ENODEV; 3001 } 3002 } 3003 3004 eth_dev->device = &dpaa2_dev->device; 3005 3006 dpaa2_dev->eth_dev = eth_dev; 3007 eth_dev->data->rx_mbuf_alloc_failed = 0; 3008 3009 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 3010 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 3011 3012 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 3013 3014 /* Invoke PMD device initialization function */ 3015 diag = dpaa2_dev_init(eth_dev); 3016 if (!diag) { 3017 diag = dpaa2_tx_sg_pool_init(); 3018 if (diag) 3019 return diag; 3020 rte_eth_dev_probing_finish(eth_dev); 3021 dpaa2_valid_dev++; 3022 return 0; 3023 } 3024 3025 rte_eth_dev_release_port(eth_dev); 3026 return diag; 3027 } 3028 3029 static int 3030 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 3031 { 3032 struct rte_eth_dev *eth_dev; 3033 int ret; 3034 3035 eth_dev = dpaa2_dev->eth_dev; 3036 dpaa2_dev_close(eth_dev); 3037 dpaa2_valid_dev--; 3038 if (!dpaa2_valid_dev) 3039 rte_mempool_free(dpaa2_tx_sg_pool); 3040 ret = rte_eth_dev_release_port(eth_dev); 3041 3042 return ret; 3043 } 3044 3045 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 3046 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 3047 .drv_type = DPAA2_ETH, 3048 .probe = rte_dpaa2_probe, 3049 .remove = rte_dpaa2_remove, 3050 }; 3051 3052 RTE_PMD_REGISTER_DPAA2(NET_DPAA2_PMD_DRIVER_NAME, rte_dpaa2_pmd); 3053 RTE_PMD_REGISTER_PARAM_STRING(NET_DPAA2_PMD_DRIVER_NAME, 3054 DRIVER_LOOPBACK_MODE "=<int> " 3055 DRIVER_NO_PREFETCH_MODE "=<int>" 3056 DRIVER_TX_CONF "=<int>" 3057 DRIVER_ERROR_QUEUE "=<int>"); 3058 RTE_LOG_REGISTER_DEFAULT(dpaa2_logtype_pmd, NOTICE); 3059