1 /* * SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2016 NXP 5 * 6 */ 7 8 #include <time.h> 9 #include <net/if.h> 10 11 #include <rte_mbuf.h> 12 #include <rte_ethdev_driver.h> 13 #include <rte_malloc.h> 14 #include <rte_memcpy.h> 15 #include <rte_string_fns.h> 16 #include <rte_cycles.h> 17 #include <rte_kvargs.h> 18 #include <rte_dev.h> 19 #include <rte_fslmc.h> 20 #include <rte_flow_driver.h> 21 22 #include "dpaa2_pmd_logs.h" 23 #include <fslmc_vfio.h> 24 #include <dpaa2_hw_pvt.h> 25 #include <dpaa2_hw_mempool.h> 26 #include <dpaa2_hw_dpio.h> 27 #include <mc/fsl_dpmng.h> 28 #include "dpaa2_ethdev.h" 29 #include <fsl_qbman_debug.h> 30 31 #define DRIVER_LOOPBACK_MODE "drv_loopback" 32 33 /* Supported Rx offloads */ 34 static uint64_t dev_rx_offloads_sup = 35 DEV_RX_OFFLOAD_VLAN_STRIP | 36 DEV_RX_OFFLOAD_IPV4_CKSUM | 37 DEV_RX_OFFLOAD_UDP_CKSUM | 38 DEV_RX_OFFLOAD_TCP_CKSUM | 39 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 40 DEV_RX_OFFLOAD_VLAN_FILTER | 41 DEV_RX_OFFLOAD_JUMBO_FRAME; 42 43 /* Rx offloads which cannot be disabled */ 44 static uint64_t dev_rx_offloads_nodis = 45 DEV_RX_OFFLOAD_SCATTER; 46 47 /* Supported Tx offloads */ 48 static uint64_t dev_tx_offloads_sup = 49 DEV_TX_OFFLOAD_VLAN_INSERT | 50 DEV_TX_OFFLOAD_IPV4_CKSUM | 51 DEV_TX_OFFLOAD_UDP_CKSUM | 52 DEV_TX_OFFLOAD_TCP_CKSUM | 53 DEV_TX_OFFLOAD_SCTP_CKSUM | 54 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM; 55 56 /* Tx offloads which cannot be disabled */ 57 static uint64_t dev_tx_offloads_nodis = 58 DEV_TX_OFFLOAD_MULTI_SEGS | 59 DEV_TX_OFFLOAD_MT_LOCKFREE | 60 DEV_TX_OFFLOAD_MBUF_FAST_FREE; 61 62 /* enable timestamp in mbuf */ 63 enum pmd_dpaa2_ts dpaa2_enable_ts; 64 65 struct rte_dpaa2_xstats_name_off { 66 char name[RTE_ETH_XSTATS_NAME_SIZE]; 67 uint8_t page_id; /* dpni statistics page id */ 68 uint8_t stats_id; /* stats id in the given page */ 69 }; 70 71 static const struct rte_dpaa2_xstats_name_off dpaa2_xstats_strings[] = { 72 {"ingress_multicast_frames", 0, 2}, 73 {"ingress_multicast_bytes", 0, 3}, 74 {"ingress_broadcast_frames", 0, 4}, 75 {"ingress_broadcast_bytes", 0, 5}, 76 {"egress_multicast_frames", 1, 2}, 77 {"egress_multicast_bytes", 1, 3}, 78 {"egress_broadcast_frames", 1, 4}, 79 {"egress_broadcast_bytes", 1, 5}, 80 {"ingress_filtered_frames", 2, 0}, 81 {"ingress_discarded_frames", 2, 1}, 82 {"ingress_nobuffer_discards", 2, 2}, 83 {"egress_discarded_frames", 2, 3}, 84 {"egress_confirmed_frames", 2, 4}, 85 }; 86 87 static const enum rte_filter_op dpaa2_supported_filter_ops[] = { 88 RTE_ETH_FILTER_ADD, 89 RTE_ETH_FILTER_DELETE, 90 RTE_ETH_FILTER_UPDATE, 91 RTE_ETH_FILTER_FLUSH, 92 RTE_ETH_FILTER_GET 93 }; 94 95 static struct rte_dpaa2_driver rte_dpaa2_pmd; 96 static int dpaa2_dev_uninit(struct rte_eth_dev *eth_dev); 97 static int dpaa2_dev_link_update(struct rte_eth_dev *dev, 98 int wait_to_complete); 99 static int dpaa2_dev_set_link_up(struct rte_eth_dev *dev); 100 static int dpaa2_dev_set_link_down(struct rte_eth_dev *dev); 101 static int dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu); 102 103 int dpaa2_logtype_pmd; 104 105 void 106 rte_pmd_dpaa2_set_timestamp(enum pmd_dpaa2_ts enable) 107 { 108 dpaa2_enable_ts = enable; 109 } 110 111 static int 112 dpaa2_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on) 113 { 114 int ret; 115 struct dpaa2_dev_priv *priv = dev->data->dev_private; 116 struct fsl_mc_io *dpni = priv->hw; 117 118 PMD_INIT_FUNC_TRACE(); 119 120 if (dpni == NULL) { 121 DPAA2_PMD_ERR("dpni is NULL"); 122 return -1; 123 } 124 125 if (on) 126 ret = dpni_add_vlan_id(dpni, CMD_PRI_LOW, 127 priv->token, vlan_id); 128 else 129 ret = dpni_remove_vlan_id(dpni, CMD_PRI_LOW, 130 priv->token, vlan_id); 131 132 if (ret < 0) 133 DPAA2_PMD_ERR("ret = %d Unable to add/rem vlan %d hwid =%d", 134 ret, vlan_id, priv->hw_id); 135 136 return ret; 137 } 138 139 static int 140 dpaa2_vlan_offload_set(struct rte_eth_dev *dev, int mask) 141 { 142 struct dpaa2_dev_priv *priv = dev->data->dev_private; 143 struct fsl_mc_io *dpni = priv->hw; 144 int ret; 145 146 PMD_INIT_FUNC_TRACE(); 147 148 if (mask & ETH_VLAN_FILTER_MASK) { 149 /* VLAN Filter not avaialble */ 150 if (!priv->max_vlan_filters) { 151 DPAA2_PMD_INFO("VLAN filter not available"); 152 goto next_mask; 153 } 154 155 if (dev->data->dev_conf.rxmode.offloads & 156 DEV_RX_OFFLOAD_VLAN_FILTER) 157 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 158 priv->token, true); 159 else 160 ret = dpni_enable_vlan_filter(dpni, CMD_PRI_LOW, 161 priv->token, false); 162 if (ret < 0) 163 DPAA2_PMD_INFO("Unable to set vlan filter = %d", ret); 164 } 165 next_mask: 166 if (mask & ETH_VLAN_EXTEND_MASK) { 167 if (dev->data->dev_conf.rxmode.offloads & 168 DEV_RX_OFFLOAD_VLAN_EXTEND) 169 DPAA2_PMD_INFO("VLAN extend offload not supported"); 170 } 171 172 return 0; 173 } 174 175 static int 176 dpaa2_vlan_tpid_set(struct rte_eth_dev *dev, 177 enum rte_vlan_type vlan_type __rte_unused, 178 uint16_t tpid) 179 { 180 struct dpaa2_dev_priv *priv = dev->data->dev_private; 181 struct fsl_mc_io *dpni = priv->hw; 182 int ret = -ENOTSUP; 183 184 PMD_INIT_FUNC_TRACE(); 185 186 /* nothing to be done for standard vlan tpids */ 187 if (tpid == 0x8100 || tpid == 0x88A8) 188 return 0; 189 190 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 191 priv->token, tpid); 192 if (ret < 0) 193 DPAA2_PMD_INFO("Unable to set vlan tpid = %d", ret); 194 /* if already configured tpids, remove them first */ 195 if (ret == -EBUSY) { 196 struct dpni_custom_tpid_cfg tpid_list = {0}; 197 198 ret = dpni_get_custom_tpid(dpni, CMD_PRI_LOW, 199 priv->token, &tpid_list); 200 if (ret < 0) 201 goto fail; 202 ret = dpni_remove_custom_tpid(dpni, CMD_PRI_LOW, 203 priv->token, tpid_list.tpid1); 204 if (ret < 0) 205 goto fail; 206 ret = dpni_add_custom_tpid(dpni, CMD_PRI_LOW, 207 priv->token, tpid); 208 } 209 fail: 210 return ret; 211 } 212 213 static int 214 dpaa2_fw_version_get(struct rte_eth_dev *dev, 215 char *fw_version, 216 size_t fw_size) 217 { 218 int ret; 219 struct dpaa2_dev_priv *priv = dev->data->dev_private; 220 struct fsl_mc_io *dpni = priv->hw; 221 struct mc_soc_version mc_plat_info = {0}; 222 struct mc_version mc_ver_info = {0}; 223 224 PMD_INIT_FUNC_TRACE(); 225 226 if (mc_get_soc_version(dpni, CMD_PRI_LOW, &mc_plat_info)) 227 DPAA2_PMD_WARN("\tmc_get_soc_version failed"); 228 229 if (mc_get_version(dpni, CMD_PRI_LOW, &mc_ver_info)) 230 DPAA2_PMD_WARN("\tmc_get_version failed"); 231 232 ret = snprintf(fw_version, fw_size, 233 "%x-%d.%d.%d", 234 mc_plat_info.svr, 235 mc_ver_info.major, 236 mc_ver_info.minor, 237 mc_ver_info.revision); 238 239 ret += 1; /* add the size of '\0' */ 240 if (fw_size < (uint32_t)ret) 241 return ret; 242 else 243 return 0; 244 } 245 246 static int 247 dpaa2_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info) 248 { 249 struct dpaa2_dev_priv *priv = dev->data->dev_private; 250 251 PMD_INIT_FUNC_TRACE(); 252 253 dev_info->if_index = priv->hw_id; 254 255 dev_info->max_mac_addrs = priv->max_mac_filters; 256 dev_info->max_rx_pktlen = DPAA2_MAX_RX_PKT_LEN; 257 dev_info->min_rx_bufsize = DPAA2_MIN_RX_BUF_SIZE; 258 dev_info->max_rx_queues = (uint16_t)priv->nb_rx_queues; 259 dev_info->max_tx_queues = (uint16_t)priv->nb_tx_queues; 260 dev_info->rx_offload_capa = dev_rx_offloads_sup | 261 dev_rx_offloads_nodis; 262 dev_info->tx_offload_capa = dev_tx_offloads_sup | 263 dev_tx_offloads_nodis; 264 dev_info->speed_capa = ETH_LINK_SPEED_1G | 265 ETH_LINK_SPEED_2_5G | 266 ETH_LINK_SPEED_10G; 267 268 dev_info->max_hash_mac_addrs = 0; 269 dev_info->max_vfs = 0; 270 dev_info->max_vmdq_pools = ETH_16_POOLS; 271 dev_info->flow_type_rss_offloads = DPAA2_RSS_OFFLOAD_ALL; 272 273 return 0; 274 } 275 276 static int 277 dpaa2_alloc_rx_tx_queues(struct rte_eth_dev *dev) 278 { 279 struct dpaa2_dev_priv *priv = dev->data->dev_private; 280 uint16_t dist_idx; 281 uint32_t vq_id; 282 uint8_t num_rxqueue_per_tc; 283 struct dpaa2_queue *mc_q, *mcq; 284 uint32_t tot_queues; 285 int i; 286 struct dpaa2_queue *dpaa2_q; 287 288 PMD_INIT_FUNC_TRACE(); 289 290 num_rxqueue_per_tc = (priv->nb_rx_queues / priv->num_rx_tc); 291 tot_queues = priv->nb_rx_queues + priv->nb_tx_queues; 292 mc_q = rte_malloc(NULL, sizeof(struct dpaa2_queue) * tot_queues, 293 RTE_CACHE_LINE_SIZE); 294 if (!mc_q) { 295 DPAA2_PMD_ERR("Memory allocation failed for rx/tx queues"); 296 return -1; 297 } 298 299 for (i = 0; i < priv->nb_rx_queues; i++) { 300 mc_q->eth_data = dev->data; 301 priv->rx_vq[i] = mc_q++; 302 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 303 dpaa2_q->q_storage = rte_malloc("dq_storage", 304 sizeof(struct queue_storage_info_t), 305 RTE_CACHE_LINE_SIZE); 306 if (!dpaa2_q->q_storage) 307 goto fail; 308 309 memset(dpaa2_q->q_storage, 0, 310 sizeof(struct queue_storage_info_t)); 311 if (dpaa2_alloc_dq_storage(dpaa2_q->q_storage)) 312 goto fail; 313 } 314 315 for (i = 0; i < priv->nb_tx_queues; i++) { 316 mc_q->eth_data = dev->data; 317 mc_q->flow_id = 0xffff; 318 priv->tx_vq[i] = mc_q++; 319 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 320 dpaa2_q->cscn = rte_malloc(NULL, 321 sizeof(struct qbman_result), 16); 322 if (!dpaa2_q->cscn) 323 goto fail_tx; 324 } 325 326 vq_id = 0; 327 for (dist_idx = 0; dist_idx < priv->nb_rx_queues; dist_idx++) { 328 mcq = (struct dpaa2_queue *)priv->rx_vq[vq_id]; 329 mcq->tc_index = dist_idx / num_rxqueue_per_tc; 330 mcq->flow_id = dist_idx % num_rxqueue_per_tc; 331 vq_id++; 332 } 333 334 return 0; 335 fail_tx: 336 i -= 1; 337 while (i >= 0) { 338 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 339 rte_free(dpaa2_q->cscn); 340 priv->tx_vq[i--] = NULL; 341 } 342 i = priv->nb_rx_queues; 343 fail: 344 i -= 1; 345 mc_q = priv->rx_vq[0]; 346 while (i >= 0) { 347 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 348 dpaa2_free_dq_storage(dpaa2_q->q_storage); 349 rte_free(dpaa2_q->q_storage); 350 priv->rx_vq[i--] = NULL; 351 } 352 rte_free(mc_q); 353 return -1; 354 } 355 356 static void 357 dpaa2_free_rx_tx_queues(struct rte_eth_dev *dev) 358 { 359 struct dpaa2_dev_priv *priv = dev->data->dev_private; 360 struct dpaa2_queue *dpaa2_q; 361 int i; 362 363 PMD_INIT_FUNC_TRACE(); 364 365 /* Queue allocation base */ 366 if (priv->rx_vq[0]) { 367 /* cleaning up queue storage */ 368 for (i = 0; i < priv->nb_rx_queues; i++) { 369 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 370 if (dpaa2_q->q_storage) 371 rte_free(dpaa2_q->q_storage); 372 } 373 /* cleanup tx queue cscn */ 374 for (i = 0; i < priv->nb_tx_queues; i++) { 375 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 376 rte_free(dpaa2_q->cscn); 377 } 378 /*free memory for all queues (RX+TX) */ 379 rte_free(priv->rx_vq[0]); 380 priv->rx_vq[0] = NULL; 381 } 382 } 383 384 static int 385 dpaa2_eth_dev_configure(struct rte_eth_dev *dev) 386 { 387 struct dpaa2_dev_priv *priv = dev->data->dev_private; 388 struct fsl_mc_io *dpni = priv->hw; 389 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 390 uint64_t rx_offloads = eth_conf->rxmode.offloads; 391 uint64_t tx_offloads = eth_conf->txmode.offloads; 392 int rx_l3_csum_offload = false; 393 int rx_l4_csum_offload = false; 394 int tx_l3_csum_offload = false; 395 int tx_l4_csum_offload = false; 396 int ret; 397 398 PMD_INIT_FUNC_TRACE(); 399 400 /* Rx offloads validation */ 401 if (dev_rx_offloads_nodis & ~rx_offloads) { 402 DPAA2_PMD_WARN( 403 "Rx offloads non configurable - requested 0x%" PRIx64 404 " ignored 0x%" PRIx64, 405 rx_offloads, dev_rx_offloads_nodis); 406 } 407 408 /* Tx offloads validation */ 409 if (dev_tx_offloads_nodis & ~tx_offloads) { 410 DPAA2_PMD_WARN( 411 "Tx offloads non configurable - requested 0x%" PRIx64 412 " ignored 0x%" PRIx64, 413 tx_offloads, dev_tx_offloads_nodis); 414 } 415 416 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 417 if (eth_conf->rxmode.max_rx_pkt_len <= DPAA2_MAX_RX_PKT_LEN) { 418 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, 419 priv->token, eth_conf->rxmode.max_rx_pkt_len); 420 if (ret) { 421 DPAA2_PMD_ERR( 422 "Unable to set mtu. check config"); 423 return ret; 424 } 425 } else { 426 return -1; 427 } 428 } 429 430 if (eth_conf->rxmode.mq_mode == ETH_MQ_RX_RSS) { 431 ret = dpaa2_setup_flow_dist(dev, 432 eth_conf->rx_adv_conf.rss_conf.rss_hf); 433 if (ret) { 434 DPAA2_PMD_ERR("Unable to set flow distribution." 435 "Check queue config"); 436 return ret; 437 } 438 } 439 440 if (rx_offloads & DEV_RX_OFFLOAD_IPV4_CKSUM) 441 rx_l3_csum_offload = true; 442 443 if ((rx_offloads & DEV_RX_OFFLOAD_UDP_CKSUM) || 444 (rx_offloads & DEV_RX_OFFLOAD_TCP_CKSUM)) 445 rx_l4_csum_offload = true; 446 447 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 448 DPNI_OFF_RX_L3_CSUM, rx_l3_csum_offload); 449 if (ret) { 450 DPAA2_PMD_ERR("Error to set RX l3 csum:Error = %d", ret); 451 return ret; 452 } 453 454 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 455 DPNI_OFF_RX_L4_CSUM, rx_l4_csum_offload); 456 if (ret) { 457 DPAA2_PMD_ERR("Error to get RX l4 csum:Error = %d", ret); 458 return ret; 459 } 460 461 if (tx_offloads & DEV_TX_OFFLOAD_IPV4_CKSUM) 462 tx_l3_csum_offload = true; 463 464 if ((tx_offloads & DEV_TX_OFFLOAD_UDP_CKSUM) || 465 (tx_offloads & DEV_TX_OFFLOAD_TCP_CKSUM) || 466 (tx_offloads & DEV_TX_OFFLOAD_SCTP_CKSUM)) 467 tx_l4_csum_offload = true; 468 469 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 470 DPNI_OFF_TX_L3_CSUM, tx_l3_csum_offload); 471 if (ret) { 472 DPAA2_PMD_ERR("Error to set TX l3 csum:Error = %d", ret); 473 return ret; 474 } 475 476 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 477 DPNI_OFF_TX_L4_CSUM, tx_l4_csum_offload); 478 if (ret) { 479 DPAA2_PMD_ERR("Error to get TX l4 csum:Error = %d", ret); 480 return ret; 481 } 482 483 /* Enabling hash results in FD requires setting DPNI_FLCTYPE_HASH in 484 * dpni_set_offload API. Setting this FLCTYPE for DPNI sets the FD[SC] 485 * to 0 for LS2 in the hardware thus disabling data/annotation 486 * stashing. For LX2 this is fixed in hardware and thus hash result and 487 * parse results can be received in FD using this option. 488 */ 489 if (dpaa2_svr_family == SVR_LX2160A) { 490 ret = dpni_set_offload(dpni, CMD_PRI_LOW, priv->token, 491 DPNI_FLCTYPE_HASH, true); 492 if (ret) { 493 DPAA2_PMD_ERR("Error setting FLCTYPE: Err = %d", ret); 494 return ret; 495 } 496 } 497 498 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 499 dpaa2_vlan_offload_set(dev, ETH_VLAN_FILTER_MASK); 500 501 /* update the current status */ 502 dpaa2_dev_link_update(dev, 0); 503 504 return 0; 505 } 506 507 /* Function to setup RX flow information. It contains traffic class ID, 508 * flow ID, destination configuration etc. 509 */ 510 static int 511 dpaa2_dev_rx_queue_setup(struct rte_eth_dev *dev, 512 uint16_t rx_queue_id, 513 uint16_t nb_rx_desc __rte_unused, 514 unsigned int socket_id __rte_unused, 515 const struct rte_eth_rxconf *rx_conf __rte_unused, 516 struct rte_mempool *mb_pool) 517 { 518 struct dpaa2_dev_priv *priv = dev->data->dev_private; 519 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 520 struct dpaa2_queue *dpaa2_q; 521 struct dpni_queue cfg; 522 uint8_t options = 0; 523 uint8_t flow_id; 524 uint32_t bpid; 525 int ret; 526 527 PMD_INIT_FUNC_TRACE(); 528 529 DPAA2_PMD_DEBUG("dev =%p, queue =%d, pool = %p, conf =%p", 530 dev, rx_queue_id, mb_pool, rx_conf); 531 532 if (!priv->bp_list || priv->bp_list->mp != mb_pool) { 533 bpid = mempool_to_bpid(mb_pool); 534 ret = dpaa2_attach_bp_list(priv, 535 rte_dpaa2_bpid_info[bpid].bp_list); 536 if (ret) 537 return ret; 538 } 539 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 540 dpaa2_q->mb_pool = mb_pool; /**< mbuf pool to populate RX ring. */ 541 dpaa2_q->bp_array = rte_dpaa2_bpid_info; 542 543 /*Get the flow id from given VQ id*/ 544 flow_id = rx_queue_id % priv->nb_rx_queues; 545 memset(&cfg, 0, sizeof(struct dpni_queue)); 546 547 options = options | DPNI_QUEUE_OPT_USER_CTX; 548 cfg.user_context = (size_t)(dpaa2_q); 549 550 /*if ls2088 or rev2 device, enable the stashing */ 551 552 if ((dpaa2_svr_family & 0xffff0000) != SVR_LS2080A) { 553 options |= DPNI_QUEUE_OPT_FLC; 554 cfg.flc.stash_control = true; 555 cfg.flc.value &= 0xFFFFFFFFFFFFFFC0; 556 /* 00 00 00 - last 6 bit represent annotation, context stashing, 557 * data stashing setting 01 01 00 (0x14) 558 * (in following order ->DS AS CS) 559 * to enable 1 line data, 1 line annotation. 560 * For LX2, this setting should be 01 00 00 (0x10) 561 */ 562 if ((dpaa2_svr_family & 0xffff0000) == SVR_LX2160A) 563 cfg.flc.value |= 0x10; 564 else 565 cfg.flc.value |= 0x14; 566 } 567 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_RX, 568 dpaa2_q->tc_index, flow_id, options, &cfg); 569 if (ret) { 570 DPAA2_PMD_ERR("Error in setting the rx flow: = %d", ret); 571 return -1; 572 } 573 574 if (!(priv->flags & DPAA2_RX_TAILDROP_OFF)) { 575 struct dpni_taildrop taildrop; 576 577 taildrop.enable = 1; 578 /*enabling per rx queue congestion control */ 579 taildrop.threshold = CONG_THRESHOLD_RX_Q; 580 taildrop.units = DPNI_CONGESTION_UNIT_BYTES; 581 taildrop.oal = CONG_RX_OAL; 582 DPAA2_PMD_DEBUG("Enabling Early Drop on queue = %d", 583 rx_queue_id); 584 ret = dpni_set_taildrop(dpni, CMD_PRI_LOW, priv->token, 585 DPNI_CP_QUEUE, DPNI_QUEUE_RX, 586 dpaa2_q->tc_index, flow_id, &taildrop); 587 if (ret) { 588 DPAA2_PMD_ERR("Error in setting taildrop. err=(%d)", 589 ret); 590 return -1; 591 } 592 } 593 594 dev->data->rx_queues[rx_queue_id] = dpaa2_q; 595 return 0; 596 } 597 598 static int 599 dpaa2_dev_tx_queue_setup(struct rte_eth_dev *dev, 600 uint16_t tx_queue_id, 601 uint16_t nb_tx_desc __rte_unused, 602 unsigned int socket_id __rte_unused, 603 const struct rte_eth_txconf *tx_conf __rte_unused) 604 { 605 struct dpaa2_dev_priv *priv = dev->data->dev_private; 606 struct dpaa2_queue *dpaa2_q = (struct dpaa2_queue *) 607 priv->tx_vq[tx_queue_id]; 608 struct fsl_mc_io *dpni = priv->hw; 609 struct dpni_queue tx_conf_cfg; 610 struct dpni_queue tx_flow_cfg; 611 uint8_t options = 0, flow_id; 612 uint32_t tc_id; 613 int ret; 614 615 PMD_INIT_FUNC_TRACE(); 616 617 /* Return if queue already configured */ 618 if (dpaa2_q->flow_id != 0xffff) { 619 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 620 return 0; 621 } 622 623 memset(&tx_conf_cfg, 0, sizeof(struct dpni_queue)); 624 memset(&tx_flow_cfg, 0, sizeof(struct dpni_queue)); 625 626 tc_id = tx_queue_id; 627 flow_id = 0; 628 629 ret = dpni_set_queue(dpni, CMD_PRI_LOW, priv->token, DPNI_QUEUE_TX, 630 tc_id, flow_id, options, &tx_flow_cfg); 631 if (ret) { 632 DPAA2_PMD_ERR("Error in setting the tx flow: " 633 "tc_id=%d, flow=%d err=%d", 634 tc_id, flow_id, ret); 635 return -1; 636 } 637 638 dpaa2_q->flow_id = flow_id; 639 640 if (tx_queue_id == 0) { 641 /*Set tx-conf and error configuration*/ 642 ret = dpni_set_tx_confirmation_mode(dpni, CMD_PRI_LOW, 643 priv->token, 644 DPNI_CONF_DISABLE); 645 if (ret) { 646 DPAA2_PMD_ERR("Error in set tx conf mode settings: " 647 "err=%d", ret); 648 return -1; 649 } 650 } 651 dpaa2_q->tc_index = tc_id; 652 653 if (!(priv->flags & DPAA2_TX_CGR_OFF)) { 654 struct dpni_congestion_notification_cfg cong_notif_cfg; 655 656 cong_notif_cfg.units = DPNI_CONGESTION_UNIT_FRAMES; 657 cong_notif_cfg.threshold_entry = CONG_ENTER_TX_THRESHOLD; 658 /* Notify that the queue is not congested when the data in 659 * the queue is below this thershold. 660 */ 661 cong_notif_cfg.threshold_exit = CONG_EXIT_TX_THRESHOLD; 662 cong_notif_cfg.message_ctx = 0; 663 cong_notif_cfg.message_iova = 664 (size_t)DPAA2_VADDR_TO_IOVA(dpaa2_q->cscn); 665 cong_notif_cfg.dest_cfg.dest_type = DPNI_DEST_NONE; 666 cong_notif_cfg.notification_mode = 667 DPNI_CONG_OPT_WRITE_MEM_ON_ENTER | 668 DPNI_CONG_OPT_WRITE_MEM_ON_EXIT | 669 DPNI_CONG_OPT_COHERENT_WRITE; 670 cong_notif_cfg.cg_point = DPNI_CP_QUEUE; 671 672 ret = dpni_set_congestion_notification(dpni, CMD_PRI_LOW, 673 priv->token, 674 DPNI_QUEUE_TX, 675 tc_id, 676 &cong_notif_cfg); 677 if (ret) { 678 DPAA2_PMD_ERR( 679 "Error in setting tx congestion notification: " 680 "err=%d", ret); 681 return -ret; 682 } 683 } 684 dpaa2_q->cb_eqresp_free = dpaa2_dev_free_eqresp_buf; 685 dev->data->tx_queues[tx_queue_id] = dpaa2_q; 686 return 0; 687 } 688 689 static void 690 dpaa2_dev_rx_queue_release(void *q __rte_unused) 691 { 692 PMD_INIT_FUNC_TRACE(); 693 } 694 695 static void 696 dpaa2_dev_tx_queue_release(void *q __rte_unused) 697 { 698 PMD_INIT_FUNC_TRACE(); 699 } 700 701 static uint32_t 702 dpaa2_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id) 703 { 704 int32_t ret; 705 struct dpaa2_dev_priv *priv = dev->data->dev_private; 706 struct dpaa2_queue *dpaa2_q; 707 struct qbman_swp *swp; 708 struct qbman_fq_query_np_rslt state; 709 uint32_t frame_cnt = 0; 710 711 PMD_INIT_FUNC_TRACE(); 712 713 if (unlikely(!DPAA2_PER_LCORE_DPIO)) { 714 ret = dpaa2_affine_qbman_swp(); 715 if (ret) { 716 DPAA2_PMD_ERR("Failure in affining portal"); 717 return -EINVAL; 718 } 719 } 720 swp = DPAA2_PER_LCORE_PORTAL; 721 722 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[rx_queue_id]; 723 724 if (qbman_fq_query_state(swp, dpaa2_q->fqid, &state) == 0) { 725 frame_cnt = qbman_fq_state_frame_count(&state); 726 DPAA2_PMD_DEBUG("RX frame count for q(%d) is %u", 727 rx_queue_id, frame_cnt); 728 } 729 return frame_cnt; 730 } 731 732 static const uint32_t * 733 dpaa2_supported_ptypes_get(struct rte_eth_dev *dev) 734 { 735 static const uint32_t ptypes[] = { 736 /*todo -= add more types */ 737 RTE_PTYPE_L2_ETHER, 738 RTE_PTYPE_L3_IPV4, 739 RTE_PTYPE_L3_IPV4_EXT, 740 RTE_PTYPE_L3_IPV6, 741 RTE_PTYPE_L3_IPV6_EXT, 742 RTE_PTYPE_L4_TCP, 743 RTE_PTYPE_L4_UDP, 744 RTE_PTYPE_L4_SCTP, 745 RTE_PTYPE_L4_ICMP, 746 RTE_PTYPE_UNKNOWN 747 }; 748 749 if (dev->rx_pkt_burst == dpaa2_dev_prefetch_rx || 750 dev->rx_pkt_burst == dpaa2_dev_loopback_rx) 751 return ptypes; 752 return NULL; 753 } 754 755 /** 756 * Dpaa2 link Interrupt handler 757 * 758 * @param param 759 * The address of parameter (struct rte_eth_dev *) regsitered before. 760 * 761 * @return 762 * void 763 */ 764 static void 765 dpaa2_interrupt_handler(void *param) 766 { 767 struct rte_eth_dev *dev = param; 768 struct dpaa2_dev_priv *priv = dev->data->dev_private; 769 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 770 int ret; 771 int irq_index = DPNI_IRQ_INDEX; 772 unsigned int status = 0, clear = 0; 773 774 PMD_INIT_FUNC_TRACE(); 775 776 if (dpni == NULL) { 777 DPAA2_PMD_ERR("dpni is NULL"); 778 return; 779 } 780 781 ret = dpni_get_irq_status(dpni, CMD_PRI_LOW, priv->token, 782 irq_index, &status); 783 if (unlikely(ret)) { 784 DPAA2_PMD_ERR("Can't get irq status (err %d)", ret); 785 clear = 0xffffffff; 786 goto out; 787 } 788 789 if (status & DPNI_IRQ_EVENT_LINK_CHANGED) { 790 clear = DPNI_IRQ_EVENT_LINK_CHANGED; 791 dpaa2_dev_link_update(dev, 0); 792 /* calling all the apps registered for link status event */ 793 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, 794 NULL); 795 } 796 out: 797 ret = dpni_clear_irq_status(dpni, CMD_PRI_LOW, priv->token, 798 irq_index, clear); 799 if (unlikely(ret)) 800 DPAA2_PMD_ERR("Can't clear irq status (err %d)", ret); 801 } 802 803 static int 804 dpaa2_eth_setup_irqs(struct rte_eth_dev *dev, int enable) 805 { 806 int err = 0; 807 struct dpaa2_dev_priv *priv = dev->data->dev_private; 808 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 809 int irq_index = DPNI_IRQ_INDEX; 810 unsigned int mask = DPNI_IRQ_EVENT_LINK_CHANGED; 811 812 PMD_INIT_FUNC_TRACE(); 813 814 err = dpni_set_irq_mask(dpni, CMD_PRI_LOW, priv->token, 815 irq_index, mask); 816 if (err < 0) { 817 DPAA2_PMD_ERR("Error: dpni_set_irq_mask():%d (%s)", err, 818 strerror(-err)); 819 return err; 820 } 821 822 err = dpni_set_irq_enable(dpni, CMD_PRI_LOW, priv->token, 823 irq_index, enable); 824 if (err < 0) 825 DPAA2_PMD_ERR("Error: dpni_set_irq_enable():%d (%s)", err, 826 strerror(-err)); 827 828 return err; 829 } 830 831 static int 832 dpaa2_dev_start(struct rte_eth_dev *dev) 833 { 834 struct rte_device *rdev = dev->device; 835 struct rte_dpaa2_device *dpaa2_dev; 836 struct rte_eth_dev_data *data = dev->data; 837 struct dpaa2_dev_priv *priv = data->dev_private; 838 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 839 struct dpni_queue cfg; 840 struct dpni_error_cfg err_cfg; 841 uint16_t qdid; 842 struct dpni_queue_id qid; 843 struct dpaa2_queue *dpaa2_q; 844 int ret, i; 845 struct rte_intr_handle *intr_handle; 846 847 dpaa2_dev = container_of(rdev, struct rte_dpaa2_device, device); 848 intr_handle = &dpaa2_dev->intr_handle; 849 850 PMD_INIT_FUNC_TRACE(); 851 852 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 853 if (ret) { 854 DPAA2_PMD_ERR("Failure in enabling dpni %d device: err=%d", 855 priv->hw_id, ret); 856 return ret; 857 } 858 859 /* Power up the phy. Needed to make the link go UP */ 860 dpaa2_dev_set_link_up(dev); 861 862 ret = dpni_get_qdid(dpni, CMD_PRI_LOW, priv->token, 863 DPNI_QUEUE_TX, &qdid); 864 if (ret) { 865 DPAA2_PMD_ERR("Error in getting qdid: err=%d", ret); 866 return ret; 867 } 868 priv->qdid = qdid; 869 870 for (i = 0; i < data->nb_rx_queues; i++) { 871 dpaa2_q = (struct dpaa2_queue *)data->rx_queues[i]; 872 ret = dpni_get_queue(dpni, CMD_PRI_LOW, priv->token, 873 DPNI_QUEUE_RX, dpaa2_q->tc_index, 874 dpaa2_q->flow_id, &cfg, &qid); 875 if (ret) { 876 DPAA2_PMD_ERR("Error in getting flow information: " 877 "err=%d", ret); 878 return ret; 879 } 880 dpaa2_q->fqid = qid.fqid; 881 } 882 883 /*checksum errors, send them to normal path and set it in annotation */ 884 err_cfg.errors = DPNI_ERROR_L3CE | DPNI_ERROR_L4CE; 885 err_cfg.errors |= DPNI_ERROR_PHE; 886 887 err_cfg.error_action = DPNI_ERROR_ACTION_CONTINUE; 888 err_cfg.set_frame_annotation = true; 889 890 ret = dpni_set_errors_behavior(dpni, CMD_PRI_LOW, 891 priv->token, &err_cfg); 892 if (ret) { 893 DPAA2_PMD_ERR("Error to dpni_set_errors_behavior: code = %d", 894 ret); 895 return ret; 896 } 897 898 /* if the interrupts were configured on this devices*/ 899 if (intr_handle && (intr_handle->fd) && 900 (dev->data->dev_conf.intr_conf.lsc != 0)) { 901 /* Registering LSC interrupt handler */ 902 rte_intr_callback_register(intr_handle, 903 dpaa2_interrupt_handler, 904 (void *)dev); 905 906 /* enable vfio intr/eventfd mapping 907 * Interrupt index 0 is required, so we can not use 908 * rte_intr_enable. 909 */ 910 rte_dpaa2_intr_enable(intr_handle, DPNI_IRQ_INDEX); 911 912 /* enable dpni_irqs */ 913 dpaa2_eth_setup_irqs(dev, 1); 914 } 915 916 /* Change the tx burst function if ordered queues are used */ 917 if (priv->en_ordered) 918 dev->tx_pkt_burst = dpaa2_dev_tx_ordered; 919 920 return 0; 921 } 922 923 /** 924 * This routine disables all traffic on the adapter by issuing a 925 * global reset on the MAC. 926 */ 927 static void 928 dpaa2_dev_stop(struct rte_eth_dev *dev) 929 { 930 struct dpaa2_dev_priv *priv = dev->data->dev_private; 931 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 932 int ret; 933 struct rte_eth_link link; 934 struct rte_intr_handle *intr_handle = dev->intr_handle; 935 936 PMD_INIT_FUNC_TRACE(); 937 938 /* reset interrupt callback */ 939 if (intr_handle && (intr_handle->fd) && 940 (dev->data->dev_conf.intr_conf.lsc != 0)) { 941 /*disable dpni irqs */ 942 dpaa2_eth_setup_irqs(dev, 0); 943 944 /* disable vfio intr before callback unregister */ 945 rte_dpaa2_intr_disable(intr_handle, DPNI_IRQ_INDEX); 946 947 /* Unregistering LSC interrupt handler */ 948 rte_intr_callback_unregister(intr_handle, 949 dpaa2_interrupt_handler, 950 (void *)dev); 951 } 952 953 dpaa2_dev_set_link_down(dev); 954 955 ret = dpni_disable(dpni, CMD_PRI_LOW, priv->token); 956 if (ret) { 957 DPAA2_PMD_ERR("Failure (ret %d) in disabling dpni %d dev", 958 ret, priv->hw_id); 959 return; 960 } 961 962 /* clear the recorded link status */ 963 memset(&link, 0, sizeof(link)); 964 rte_eth_linkstatus_set(dev, &link); 965 } 966 967 static void 968 dpaa2_dev_close(struct rte_eth_dev *dev) 969 { 970 struct dpaa2_dev_priv *priv = dev->data->dev_private; 971 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 972 int ret; 973 struct rte_eth_link link; 974 975 PMD_INIT_FUNC_TRACE(); 976 977 dpaa2_flow_clean(dev); 978 979 /* Clean the device first */ 980 ret = dpni_reset(dpni, CMD_PRI_LOW, priv->token); 981 if (ret) { 982 DPAA2_PMD_ERR("Failure cleaning dpni device: err=%d", ret); 983 return; 984 } 985 986 memset(&link, 0, sizeof(link)); 987 rte_eth_linkstatus_set(dev, &link); 988 } 989 990 static int 991 dpaa2_dev_promiscuous_enable( 992 struct rte_eth_dev *dev) 993 { 994 int ret; 995 struct dpaa2_dev_priv *priv = dev->data->dev_private; 996 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 997 998 PMD_INIT_FUNC_TRACE(); 999 1000 if (dpni == NULL) { 1001 DPAA2_PMD_ERR("dpni is NULL"); 1002 return -ENODEV; 1003 } 1004 1005 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1006 if (ret < 0) 1007 DPAA2_PMD_ERR("Unable to enable U promisc mode %d", ret); 1008 1009 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1010 if (ret < 0) 1011 DPAA2_PMD_ERR("Unable to enable M promisc mode %d", ret); 1012 1013 return ret; 1014 } 1015 1016 static int 1017 dpaa2_dev_promiscuous_disable( 1018 struct rte_eth_dev *dev) 1019 { 1020 int ret; 1021 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1022 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1023 1024 PMD_INIT_FUNC_TRACE(); 1025 1026 if (dpni == NULL) { 1027 DPAA2_PMD_ERR("dpni is NULL"); 1028 return -ENODEV; 1029 } 1030 1031 ret = dpni_set_unicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1032 if (ret < 0) 1033 DPAA2_PMD_ERR("Unable to disable U promisc mode %d", ret); 1034 1035 if (dev->data->all_multicast == 0) { 1036 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, 1037 priv->token, false); 1038 if (ret < 0) 1039 DPAA2_PMD_ERR("Unable to disable M promisc mode %d", 1040 ret); 1041 } 1042 1043 return ret; 1044 } 1045 1046 static int 1047 dpaa2_dev_allmulticast_enable( 1048 struct rte_eth_dev *dev) 1049 { 1050 int ret; 1051 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1052 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1053 1054 PMD_INIT_FUNC_TRACE(); 1055 1056 if (dpni == NULL) { 1057 DPAA2_PMD_ERR("dpni is NULL"); 1058 return -ENODEV; 1059 } 1060 1061 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, true); 1062 if (ret < 0) 1063 DPAA2_PMD_ERR("Unable to enable multicast mode %d", ret); 1064 1065 return ret; 1066 } 1067 1068 static int 1069 dpaa2_dev_allmulticast_disable(struct rte_eth_dev *dev) 1070 { 1071 int ret; 1072 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1073 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1074 1075 PMD_INIT_FUNC_TRACE(); 1076 1077 if (dpni == NULL) { 1078 DPAA2_PMD_ERR("dpni is NULL"); 1079 return -ENODEV; 1080 } 1081 1082 /* must remain on for all promiscuous */ 1083 if (dev->data->promiscuous == 1) 1084 return 0; 1085 1086 ret = dpni_set_multicast_promisc(dpni, CMD_PRI_LOW, priv->token, false); 1087 if (ret < 0) 1088 DPAA2_PMD_ERR("Unable to disable multicast mode %d", ret); 1089 1090 return ret; 1091 } 1092 1093 static int 1094 dpaa2_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 1095 { 1096 int ret; 1097 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1098 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1099 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 1100 + VLAN_TAG_SIZE; 1101 1102 PMD_INIT_FUNC_TRACE(); 1103 1104 if (dpni == NULL) { 1105 DPAA2_PMD_ERR("dpni is NULL"); 1106 return -EINVAL; 1107 } 1108 1109 /* check that mtu is within the allowed range */ 1110 if (mtu < RTE_ETHER_MIN_MTU || frame_size > DPAA2_MAX_RX_PKT_LEN) 1111 return -EINVAL; 1112 1113 if (frame_size > RTE_ETHER_MAX_LEN) 1114 dev->data->dev_conf.rxmode.offloads &= 1115 DEV_RX_OFFLOAD_JUMBO_FRAME; 1116 else 1117 dev->data->dev_conf.rxmode.offloads &= 1118 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1119 1120 dev->data->dev_conf.rxmode.max_rx_pkt_len = frame_size; 1121 1122 /* Set the Max Rx frame length as 'mtu' + 1123 * Maximum Ethernet header length 1124 */ 1125 ret = dpni_set_max_frame_length(dpni, CMD_PRI_LOW, priv->token, 1126 frame_size); 1127 if (ret) { 1128 DPAA2_PMD_ERR("Setting the max frame length failed"); 1129 return -1; 1130 } 1131 DPAA2_PMD_INFO("MTU configured for the device: %d", mtu); 1132 return 0; 1133 } 1134 1135 static int 1136 dpaa2_dev_add_mac_addr(struct rte_eth_dev *dev, 1137 struct rte_ether_addr *addr, 1138 __rte_unused uint32_t index, 1139 __rte_unused uint32_t pool) 1140 { 1141 int ret; 1142 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1143 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1144 1145 PMD_INIT_FUNC_TRACE(); 1146 1147 if (dpni == NULL) { 1148 DPAA2_PMD_ERR("dpni is NULL"); 1149 return -1; 1150 } 1151 1152 ret = dpni_add_mac_addr(dpni, CMD_PRI_LOW, 1153 priv->token, addr->addr_bytes); 1154 if (ret) 1155 DPAA2_PMD_ERR( 1156 "error: Adding the MAC ADDR failed: err = %d", ret); 1157 return 0; 1158 } 1159 1160 static void 1161 dpaa2_dev_remove_mac_addr(struct rte_eth_dev *dev, 1162 uint32_t index) 1163 { 1164 int ret; 1165 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1166 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1167 struct rte_eth_dev_data *data = dev->data; 1168 struct rte_ether_addr *macaddr; 1169 1170 PMD_INIT_FUNC_TRACE(); 1171 1172 macaddr = &data->mac_addrs[index]; 1173 1174 if (dpni == NULL) { 1175 DPAA2_PMD_ERR("dpni is NULL"); 1176 return; 1177 } 1178 1179 ret = dpni_remove_mac_addr(dpni, CMD_PRI_LOW, 1180 priv->token, macaddr->addr_bytes); 1181 if (ret) 1182 DPAA2_PMD_ERR( 1183 "error: Removing the MAC ADDR failed: err = %d", ret); 1184 } 1185 1186 static int 1187 dpaa2_dev_set_mac_addr(struct rte_eth_dev *dev, 1188 struct rte_ether_addr *addr) 1189 { 1190 int ret; 1191 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1192 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1193 1194 PMD_INIT_FUNC_TRACE(); 1195 1196 if (dpni == NULL) { 1197 DPAA2_PMD_ERR("dpni is NULL"); 1198 return -EINVAL; 1199 } 1200 1201 ret = dpni_set_primary_mac_addr(dpni, CMD_PRI_LOW, 1202 priv->token, addr->addr_bytes); 1203 1204 if (ret) 1205 DPAA2_PMD_ERR( 1206 "error: Setting the MAC ADDR failed %d", ret); 1207 1208 return ret; 1209 } 1210 1211 static 1212 int dpaa2_dev_stats_get(struct rte_eth_dev *dev, 1213 struct rte_eth_stats *stats) 1214 { 1215 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1216 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1217 int32_t retcode; 1218 uint8_t page0 = 0, page1 = 1, page2 = 2; 1219 union dpni_statistics value; 1220 int i; 1221 struct dpaa2_queue *dpaa2_rxq, *dpaa2_txq; 1222 1223 memset(&value, 0, sizeof(union dpni_statistics)); 1224 1225 PMD_INIT_FUNC_TRACE(); 1226 1227 if (!dpni) { 1228 DPAA2_PMD_ERR("dpni is NULL"); 1229 return -EINVAL; 1230 } 1231 1232 if (!stats) { 1233 DPAA2_PMD_ERR("stats is NULL"); 1234 return -EINVAL; 1235 } 1236 1237 /*Get Counters from page_0*/ 1238 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1239 page0, 0, &value); 1240 if (retcode) 1241 goto err; 1242 1243 stats->ipackets = value.page_0.ingress_all_frames; 1244 stats->ibytes = value.page_0.ingress_all_bytes; 1245 1246 /*Get Counters from page_1*/ 1247 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1248 page1, 0, &value); 1249 if (retcode) 1250 goto err; 1251 1252 stats->opackets = value.page_1.egress_all_frames; 1253 stats->obytes = value.page_1.egress_all_bytes; 1254 1255 /*Get Counters from page_2*/ 1256 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1257 page2, 0, &value); 1258 if (retcode) 1259 goto err; 1260 1261 /* Ingress drop frame count due to configured rules */ 1262 stats->ierrors = value.page_2.ingress_filtered_frames; 1263 /* Ingress drop frame count due to error */ 1264 stats->ierrors += value.page_2.ingress_discarded_frames; 1265 1266 stats->oerrors = value.page_2.egress_discarded_frames; 1267 stats->imissed = value.page_2.ingress_nobuffer_discards; 1268 1269 /* Fill in per queue stats */ 1270 for (i = 0; (i < RTE_ETHDEV_QUEUE_STAT_CNTRS) && 1271 (i < priv->nb_rx_queues || i < priv->nb_tx_queues); ++i) { 1272 dpaa2_rxq = (struct dpaa2_queue *)priv->rx_vq[i]; 1273 dpaa2_txq = (struct dpaa2_queue *)priv->tx_vq[i]; 1274 if (dpaa2_rxq) 1275 stats->q_ipackets[i] = dpaa2_rxq->rx_pkts; 1276 if (dpaa2_txq) 1277 stats->q_opackets[i] = dpaa2_txq->tx_pkts; 1278 1279 /* Byte counting is not implemented */ 1280 stats->q_ibytes[i] = 0; 1281 stats->q_obytes[i] = 0; 1282 } 1283 1284 return 0; 1285 1286 err: 1287 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1288 return retcode; 1289 }; 1290 1291 static int 1292 dpaa2_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 1293 unsigned int n) 1294 { 1295 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1296 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1297 int32_t retcode; 1298 union dpni_statistics value[3] = {}; 1299 unsigned int i = 0, num = RTE_DIM(dpaa2_xstats_strings); 1300 1301 if (n < num) 1302 return num; 1303 1304 if (xstats == NULL) 1305 return 0; 1306 1307 /* Get Counters from page_0*/ 1308 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1309 0, 0, &value[0]); 1310 if (retcode) 1311 goto err; 1312 1313 /* Get Counters from page_1*/ 1314 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1315 1, 0, &value[1]); 1316 if (retcode) 1317 goto err; 1318 1319 /* Get Counters from page_2*/ 1320 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1321 2, 0, &value[2]); 1322 if (retcode) 1323 goto err; 1324 1325 for (i = 0; i < num; i++) { 1326 xstats[i].id = i; 1327 xstats[i].value = value[dpaa2_xstats_strings[i].page_id]. 1328 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1329 } 1330 return i; 1331 err: 1332 DPAA2_PMD_ERR("Error in obtaining extended stats (%d)", retcode); 1333 return retcode; 1334 } 1335 1336 static int 1337 dpaa2_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 1338 struct rte_eth_xstat_name *xstats_names, 1339 unsigned int limit) 1340 { 1341 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1342 1343 if (limit < stat_cnt) 1344 return stat_cnt; 1345 1346 if (xstats_names != NULL) 1347 for (i = 0; i < stat_cnt; i++) 1348 strlcpy(xstats_names[i].name, 1349 dpaa2_xstats_strings[i].name, 1350 sizeof(xstats_names[i].name)); 1351 1352 return stat_cnt; 1353 } 1354 1355 static int 1356 dpaa2_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 1357 uint64_t *values, unsigned int n) 1358 { 1359 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1360 uint64_t values_copy[stat_cnt]; 1361 1362 if (!ids) { 1363 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1364 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1365 int32_t retcode; 1366 union dpni_statistics value[3] = {}; 1367 1368 if (n < stat_cnt) 1369 return stat_cnt; 1370 1371 if (!values) 1372 return 0; 1373 1374 /* Get Counters from page_0*/ 1375 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1376 0, 0, &value[0]); 1377 if (retcode) 1378 return 0; 1379 1380 /* Get Counters from page_1*/ 1381 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1382 1, 0, &value[1]); 1383 if (retcode) 1384 return 0; 1385 1386 /* Get Counters from page_2*/ 1387 retcode = dpni_get_statistics(dpni, CMD_PRI_LOW, priv->token, 1388 2, 0, &value[2]); 1389 if (retcode) 1390 return 0; 1391 1392 for (i = 0; i < stat_cnt; i++) { 1393 values[i] = value[dpaa2_xstats_strings[i].page_id]. 1394 raw.counter[dpaa2_xstats_strings[i].stats_id]; 1395 } 1396 return stat_cnt; 1397 } 1398 1399 dpaa2_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 1400 1401 for (i = 0; i < n; i++) { 1402 if (ids[i] >= stat_cnt) { 1403 DPAA2_PMD_ERR("xstats id value isn't valid"); 1404 return -1; 1405 } 1406 values[i] = values_copy[ids[i]]; 1407 } 1408 return n; 1409 } 1410 1411 static int 1412 dpaa2_xstats_get_names_by_id( 1413 struct rte_eth_dev *dev, 1414 struct rte_eth_xstat_name *xstats_names, 1415 const uint64_t *ids, 1416 unsigned int limit) 1417 { 1418 unsigned int i, stat_cnt = RTE_DIM(dpaa2_xstats_strings); 1419 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 1420 1421 if (!ids) 1422 return dpaa2_xstats_get_names(dev, xstats_names, limit); 1423 1424 dpaa2_xstats_get_names(dev, xstats_names_copy, limit); 1425 1426 for (i = 0; i < limit; i++) { 1427 if (ids[i] >= stat_cnt) { 1428 DPAA2_PMD_ERR("xstats id value isn't valid"); 1429 return -1; 1430 } 1431 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 1432 } 1433 return limit; 1434 } 1435 1436 static int 1437 dpaa2_dev_stats_reset(struct rte_eth_dev *dev) 1438 { 1439 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1440 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1441 int retcode; 1442 int i; 1443 struct dpaa2_queue *dpaa2_q; 1444 1445 PMD_INIT_FUNC_TRACE(); 1446 1447 if (dpni == NULL) { 1448 DPAA2_PMD_ERR("dpni is NULL"); 1449 return -EINVAL; 1450 } 1451 1452 retcode = dpni_reset_statistics(dpni, CMD_PRI_LOW, priv->token); 1453 if (retcode) 1454 goto error; 1455 1456 /* Reset the per queue stats in dpaa2_queue structure */ 1457 for (i = 0; i < priv->nb_rx_queues; i++) { 1458 dpaa2_q = (struct dpaa2_queue *)priv->rx_vq[i]; 1459 if (dpaa2_q) 1460 dpaa2_q->rx_pkts = 0; 1461 } 1462 1463 for (i = 0; i < priv->nb_tx_queues; i++) { 1464 dpaa2_q = (struct dpaa2_queue *)priv->tx_vq[i]; 1465 if (dpaa2_q) 1466 dpaa2_q->tx_pkts = 0; 1467 } 1468 1469 return 0; 1470 1471 error: 1472 DPAA2_PMD_ERR("Operation not completed:Error Code = %d", retcode); 1473 return retcode; 1474 }; 1475 1476 /* return 0 means link status changed, -1 means not changed */ 1477 static int 1478 dpaa2_dev_link_update(struct rte_eth_dev *dev, 1479 int wait_to_complete __rte_unused) 1480 { 1481 int ret; 1482 struct dpaa2_dev_priv *priv = dev->data->dev_private; 1483 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 1484 struct rte_eth_link link; 1485 struct dpni_link_state state = {0}; 1486 1487 if (dpni == NULL) { 1488 DPAA2_PMD_ERR("dpni is NULL"); 1489 return 0; 1490 } 1491 1492 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1493 if (ret < 0) { 1494 DPAA2_PMD_DEBUG("error: dpni_get_link_state %d", ret); 1495 return -1; 1496 } 1497 1498 memset(&link, 0, sizeof(struct rte_eth_link)); 1499 link.link_status = state.up; 1500 link.link_speed = state.rate; 1501 1502 if (state.options & DPNI_LINK_OPT_HALF_DUPLEX) 1503 link.link_duplex = ETH_LINK_HALF_DUPLEX; 1504 else 1505 link.link_duplex = ETH_LINK_FULL_DUPLEX; 1506 1507 ret = rte_eth_linkstatus_set(dev, &link); 1508 if (ret == -1) 1509 DPAA2_PMD_DEBUG("No change in status"); 1510 else 1511 DPAA2_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 1512 link.link_status ? "Up" : "Down"); 1513 1514 return ret; 1515 } 1516 1517 /** 1518 * Toggle the DPNI to enable, if not already enabled. 1519 * This is not strictly PHY up/down - it is more of logical toggling. 1520 */ 1521 static int 1522 dpaa2_dev_set_link_up(struct rte_eth_dev *dev) 1523 { 1524 int ret = -EINVAL; 1525 struct dpaa2_dev_priv *priv; 1526 struct fsl_mc_io *dpni; 1527 int en = 0; 1528 struct dpni_link_state state = {0}; 1529 1530 priv = dev->data->dev_private; 1531 dpni = (struct fsl_mc_io *)priv->hw; 1532 1533 if (dpni == NULL) { 1534 DPAA2_PMD_ERR("dpni is NULL"); 1535 return ret; 1536 } 1537 1538 /* Check if DPNI is currently enabled */ 1539 ret = dpni_is_enabled(dpni, CMD_PRI_LOW, priv->token, &en); 1540 if (ret) { 1541 /* Unable to obtain dpni status; Not continuing */ 1542 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1543 return -EINVAL; 1544 } 1545 1546 /* Enable link if not already enabled */ 1547 if (!en) { 1548 ret = dpni_enable(dpni, CMD_PRI_LOW, priv->token); 1549 if (ret) { 1550 DPAA2_PMD_ERR("Interface Link UP failed (%d)", ret); 1551 return -EINVAL; 1552 } 1553 } 1554 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1555 if (ret < 0) { 1556 DPAA2_PMD_DEBUG("Unable to get link state (%d)", ret); 1557 return -1; 1558 } 1559 1560 /* changing tx burst function to start enqueues */ 1561 dev->tx_pkt_burst = dpaa2_dev_tx; 1562 dev->data->dev_link.link_status = state.up; 1563 1564 if (state.up) 1565 DPAA2_PMD_INFO("Port %d Link is Up", dev->data->port_id); 1566 else 1567 DPAA2_PMD_INFO("Port %d Link is Down", dev->data->port_id); 1568 return ret; 1569 } 1570 1571 /** 1572 * Toggle the DPNI to disable, if not already disabled. 1573 * This is not strictly PHY up/down - it is more of logical toggling. 1574 */ 1575 static int 1576 dpaa2_dev_set_link_down(struct rte_eth_dev *dev) 1577 { 1578 int ret = -EINVAL; 1579 struct dpaa2_dev_priv *priv; 1580 struct fsl_mc_io *dpni; 1581 int dpni_enabled = 0; 1582 int retries = 10; 1583 1584 PMD_INIT_FUNC_TRACE(); 1585 1586 priv = dev->data->dev_private; 1587 dpni = (struct fsl_mc_io *)priv->hw; 1588 1589 if (dpni == NULL) { 1590 DPAA2_PMD_ERR("Device has not yet been configured"); 1591 return ret; 1592 } 1593 1594 /*changing tx burst function to avoid any more enqueues */ 1595 dev->tx_pkt_burst = dummy_dev_tx; 1596 1597 /* Loop while dpni_disable() attempts to drain the egress FQs 1598 * and confirm them back to us. 1599 */ 1600 do { 1601 ret = dpni_disable(dpni, 0, priv->token); 1602 if (ret) { 1603 DPAA2_PMD_ERR("dpni disable failed (%d)", ret); 1604 return ret; 1605 } 1606 ret = dpni_is_enabled(dpni, 0, priv->token, &dpni_enabled); 1607 if (ret) { 1608 DPAA2_PMD_ERR("dpni enable check failed (%d)", ret); 1609 return ret; 1610 } 1611 if (dpni_enabled) 1612 /* Allow the MC some slack */ 1613 rte_delay_us(100 * 1000); 1614 } while (dpni_enabled && --retries); 1615 1616 if (!retries) { 1617 DPAA2_PMD_WARN("Retry count exceeded disabling dpni"); 1618 /* todo- we may have to manually cleanup queues. 1619 */ 1620 } else { 1621 DPAA2_PMD_INFO("Port %d Link DOWN successful", 1622 dev->data->port_id); 1623 } 1624 1625 dev->data->dev_link.link_status = 0; 1626 1627 return ret; 1628 } 1629 1630 static int 1631 dpaa2_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1632 { 1633 int ret = -EINVAL; 1634 struct dpaa2_dev_priv *priv; 1635 struct fsl_mc_io *dpni; 1636 struct dpni_link_state state = {0}; 1637 1638 PMD_INIT_FUNC_TRACE(); 1639 1640 priv = dev->data->dev_private; 1641 dpni = (struct fsl_mc_io *)priv->hw; 1642 1643 if (dpni == NULL || fc_conf == NULL) { 1644 DPAA2_PMD_ERR("device not configured"); 1645 return ret; 1646 } 1647 1648 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1649 if (ret) { 1650 DPAA2_PMD_ERR("error: dpni_get_link_state %d", ret); 1651 return ret; 1652 } 1653 1654 memset(fc_conf, 0, sizeof(struct rte_eth_fc_conf)); 1655 if (state.options & DPNI_LINK_OPT_PAUSE) { 1656 /* DPNI_LINK_OPT_PAUSE set 1657 * if ASYM_PAUSE not set, 1658 * RX Side flow control (handle received Pause frame) 1659 * TX side flow control (send Pause frame) 1660 * if ASYM_PAUSE set, 1661 * RX Side flow control (handle received Pause frame) 1662 * No TX side flow control (send Pause frame disabled) 1663 */ 1664 if (!(state.options & DPNI_LINK_OPT_ASYM_PAUSE)) 1665 fc_conf->mode = RTE_FC_FULL; 1666 else 1667 fc_conf->mode = RTE_FC_RX_PAUSE; 1668 } else { 1669 /* DPNI_LINK_OPT_PAUSE not set 1670 * if ASYM_PAUSE set, 1671 * TX side flow control (send Pause frame) 1672 * No RX side flow control (No action on pause frame rx) 1673 * if ASYM_PAUSE not set, 1674 * Flow control disabled 1675 */ 1676 if (state.options & DPNI_LINK_OPT_ASYM_PAUSE) 1677 fc_conf->mode = RTE_FC_TX_PAUSE; 1678 else 1679 fc_conf->mode = RTE_FC_NONE; 1680 } 1681 1682 return ret; 1683 } 1684 1685 static int 1686 dpaa2_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) 1687 { 1688 int ret = -EINVAL; 1689 struct dpaa2_dev_priv *priv; 1690 struct fsl_mc_io *dpni; 1691 struct dpni_link_state state = {0}; 1692 struct dpni_link_cfg cfg = {0}; 1693 1694 PMD_INIT_FUNC_TRACE(); 1695 1696 priv = dev->data->dev_private; 1697 dpni = (struct fsl_mc_io *)priv->hw; 1698 1699 if (dpni == NULL) { 1700 DPAA2_PMD_ERR("dpni is NULL"); 1701 return ret; 1702 } 1703 1704 /* It is necessary to obtain the current state before setting fc_conf 1705 * as MC would return error in case rate, autoneg or duplex values are 1706 * different. 1707 */ 1708 ret = dpni_get_link_state(dpni, CMD_PRI_LOW, priv->token, &state); 1709 if (ret) { 1710 DPAA2_PMD_ERR("Unable to get link state (err=%d)", ret); 1711 return -1; 1712 } 1713 1714 /* Disable link before setting configuration */ 1715 dpaa2_dev_set_link_down(dev); 1716 1717 /* Based on fc_conf, update cfg */ 1718 cfg.rate = state.rate; 1719 cfg.options = state.options; 1720 1721 /* update cfg with fc_conf */ 1722 switch (fc_conf->mode) { 1723 case RTE_FC_FULL: 1724 /* Full flow control; 1725 * OPT_PAUSE set, ASYM_PAUSE not set 1726 */ 1727 cfg.options |= DPNI_LINK_OPT_PAUSE; 1728 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1729 break; 1730 case RTE_FC_TX_PAUSE: 1731 /* Enable RX flow control 1732 * OPT_PAUSE not set; 1733 * ASYM_PAUSE set; 1734 */ 1735 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1736 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1737 break; 1738 case RTE_FC_RX_PAUSE: 1739 /* Enable TX Flow control 1740 * OPT_PAUSE set 1741 * ASYM_PAUSE set 1742 */ 1743 cfg.options |= DPNI_LINK_OPT_PAUSE; 1744 cfg.options |= DPNI_LINK_OPT_ASYM_PAUSE; 1745 break; 1746 case RTE_FC_NONE: 1747 /* Disable Flow control 1748 * OPT_PAUSE not set 1749 * ASYM_PAUSE not set 1750 */ 1751 cfg.options &= ~DPNI_LINK_OPT_PAUSE; 1752 cfg.options &= ~DPNI_LINK_OPT_ASYM_PAUSE; 1753 break; 1754 default: 1755 DPAA2_PMD_ERR("Incorrect Flow control flag (%d)", 1756 fc_conf->mode); 1757 return -1; 1758 } 1759 1760 ret = dpni_set_link_cfg(dpni, CMD_PRI_LOW, priv->token, &cfg); 1761 if (ret) 1762 DPAA2_PMD_ERR("Unable to set Link configuration (err=%d)", 1763 ret); 1764 1765 /* Enable link */ 1766 dpaa2_dev_set_link_up(dev); 1767 1768 return ret; 1769 } 1770 1771 static int 1772 dpaa2_dev_rss_hash_update(struct rte_eth_dev *dev, 1773 struct rte_eth_rss_conf *rss_conf) 1774 { 1775 struct rte_eth_dev_data *data = dev->data; 1776 struct rte_eth_conf *eth_conf = &data->dev_conf; 1777 int ret; 1778 1779 PMD_INIT_FUNC_TRACE(); 1780 1781 if (rss_conf->rss_hf) { 1782 ret = dpaa2_setup_flow_dist(dev, rss_conf->rss_hf); 1783 if (ret) { 1784 DPAA2_PMD_ERR("Unable to set flow dist"); 1785 return ret; 1786 } 1787 } else { 1788 ret = dpaa2_remove_flow_dist(dev, 0); 1789 if (ret) { 1790 DPAA2_PMD_ERR("Unable to remove flow dist"); 1791 return ret; 1792 } 1793 } 1794 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1795 return 0; 1796 } 1797 1798 static int 1799 dpaa2_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1800 struct rte_eth_rss_conf *rss_conf) 1801 { 1802 struct rte_eth_dev_data *data = dev->data; 1803 struct rte_eth_conf *eth_conf = &data->dev_conf; 1804 1805 /* dpaa2 does not support rss_key, so length should be 0*/ 1806 rss_conf->rss_key_len = 0; 1807 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1808 return 0; 1809 } 1810 1811 int dpaa2_eth_eventq_attach(const struct rte_eth_dev *dev, 1812 int eth_rx_queue_id, 1813 uint16_t dpcon_id, 1814 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1815 { 1816 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 1817 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw; 1818 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 1819 uint8_t flow_id = dpaa2_ethq->flow_id; 1820 struct dpni_queue cfg; 1821 uint8_t options; 1822 int ret; 1823 1824 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_PARALLEL) 1825 dpaa2_ethq->cb = dpaa2_dev_process_parallel_event; 1826 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) 1827 dpaa2_ethq->cb = dpaa2_dev_process_atomic_event; 1828 else if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED) 1829 dpaa2_ethq->cb = dpaa2_dev_process_ordered_event; 1830 else 1831 return -EINVAL; 1832 1833 memset(&cfg, 0, sizeof(struct dpni_queue)); 1834 options = DPNI_QUEUE_OPT_DEST; 1835 cfg.destination.type = DPNI_DEST_DPCON; 1836 cfg.destination.id = dpcon_id; 1837 cfg.destination.priority = queue_conf->ev.priority; 1838 1839 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ATOMIC) { 1840 options |= DPNI_QUEUE_OPT_HOLD_ACTIVE; 1841 cfg.destination.hold_active = 1; 1842 } 1843 1844 if (queue_conf->ev.sched_type == RTE_SCHED_TYPE_ORDERED && 1845 !eth_priv->en_ordered) { 1846 struct opr_cfg ocfg; 1847 1848 /* Restoration window size = 256 frames */ 1849 ocfg.oprrws = 3; 1850 /* Restoration window size = 512 frames for LX2 */ 1851 if (dpaa2_svr_family == SVR_LX2160A) 1852 ocfg.oprrws = 4; 1853 /* Auto advance NESN window enabled */ 1854 ocfg.oa = 1; 1855 /* Late arrival window size disabled */ 1856 ocfg.olws = 0; 1857 /* ORL resource exhaustaion advance NESN disabled */ 1858 ocfg.oeane = 0; 1859 /* Loose ordering enabled */ 1860 ocfg.oloe = 1; 1861 eth_priv->en_loose_ordered = 1; 1862 /* Strict ordering enabled if explicitly set */ 1863 if (getenv("DPAA2_STRICT_ORDERING_ENABLE")) { 1864 ocfg.oloe = 0; 1865 eth_priv->en_loose_ordered = 0; 1866 } 1867 1868 ret = dpni_set_opr(dpni, CMD_PRI_LOW, eth_priv->token, 1869 dpaa2_ethq->tc_index, flow_id, 1870 OPR_OPT_CREATE, &ocfg); 1871 if (ret) { 1872 DPAA2_PMD_ERR("Error setting opr: ret: %d\n", ret); 1873 return ret; 1874 } 1875 1876 eth_priv->en_ordered = 1; 1877 } 1878 1879 options |= DPNI_QUEUE_OPT_USER_CTX; 1880 cfg.user_context = (size_t)(dpaa2_ethq); 1881 1882 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 1883 dpaa2_ethq->tc_index, flow_id, options, &cfg); 1884 if (ret) { 1885 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 1886 return ret; 1887 } 1888 1889 memcpy(&dpaa2_ethq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1890 1891 return 0; 1892 } 1893 1894 int dpaa2_eth_eventq_detach(const struct rte_eth_dev *dev, 1895 int eth_rx_queue_id) 1896 { 1897 struct dpaa2_dev_priv *eth_priv = dev->data->dev_private; 1898 struct fsl_mc_io *dpni = (struct fsl_mc_io *)eth_priv->hw; 1899 struct dpaa2_queue *dpaa2_ethq = eth_priv->rx_vq[eth_rx_queue_id]; 1900 uint8_t flow_id = dpaa2_ethq->flow_id; 1901 struct dpni_queue cfg; 1902 uint8_t options; 1903 int ret; 1904 1905 memset(&cfg, 0, sizeof(struct dpni_queue)); 1906 options = DPNI_QUEUE_OPT_DEST; 1907 cfg.destination.type = DPNI_DEST_NONE; 1908 1909 ret = dpni_set_queue(dpni, CMD_PRI_LOW, eth_priv->token, DPNI_QUEUE_RX, 1910 dpaa2_ethq->tc_index, flow_id, options, &cfg); 1911 if (ret) 1912 DPAA2_PMD_ERR("Error in dpni_set_queue: ret: %d", ret); 1913 1914 return ret; 1915 } 1916 1917 static inline int 1918 dpaa2_dev_verify_filter_ops(enum rte_filter_op filter_op) 1919 { 1920 unsigned int i; 1921 1922 for (i = 0; i < RTE_DIM(dpaa2_supported_filter_ops); i++) { 1923 if (dpaa2_supported_filter_ops[i] == filter_op) 1924 return 0; 1925 } 1926 return -ENOTSUP; 1927 } 1928 1929 static int 1930 dpaa2_dev_flow_ctrl(struct rte_eth_dev *dev, 1931 enum rte_filter_type filter_type, 1932 enum rte_filter_op filter_op, 1933 void *arg) 1934 { 1935 int ret = 0; 1936 1937 if (!dev) 1938 return -ENODEV; 1939 1940 switch (filter_type) { 1941 case RTE_ETH_FILTER_GENERIC: 1942 if (dpaa2_dev_verify_filter_ops(filter_op) < 0) { 1943 ret = -ENOTSUP; 1944 break; 1945 } 1946 *(const void **)arg = &dpaa2_flow_ops; 1947 dpaa2_filter_type |= filter_type; 1948 break; 1949 default: 1950 RTE_LOG(ERR, PMD, "Filter type (%d) not supported", 1951 filter_type); 1952 ret = -ENOTSUP; 1953 break; 1954 } 1955 return ret; 1956 } 1957 1958 static struct eth_dev_ops dpaa2_ethdev_ops = { 1959 .dev_configure = dpaa2_eth_dev_configure, 1960 .dev_start = dpaa2_dev_start, 1961 .dev_stop = dpaa2_dev_stop, 1962 .dev_close = dpaa2_dev_close, 1963 .promiscuous_enable = dpaa2_dev_promiscuous_enable, 1964 .promiscuous_disable = dpaa2_dev_promiscuous_disable, 1965 .allmulticast_enable = dpaa2_dev_allmulticast_enable, 1966 .allmulticast_disable = dpaa2_dev_allmulticast_disable, 1967 .dev_set_link_up = dpaa2_dev_set_link_up, 1968 .dev_set_link_down = dpaa2_dev_set_link_down, 1969 .link_update = dpaa2_dev_link_update, 1970 .stats_get = dpaa2_dev_stats_get, 1971 .xstats_get = dpaa2_dev_xstats_get, 1972 .xstats_get_by_id = dpaa2_xstats_get_by_id, 1973 .xstats_get_names_by_id = dpaa2_xstats_get_names_by_id, 1974 .xstats_get_names = dpaa2_xstats_get_names, 1975 .stats_reset = dpaa2_dev_stats_reset, 1976 .xstats_reset = dpaa2_dev_stats_reset, 1977 .fw_version_get = dpaa2_fw_version_get, 1978 .dev_infos_get = dpaa2_dev_info_get, 1979 .dev_supported_ptypes_get = dpaa2_supported_ptypes_get, 1980 .mtu_set = dpaa2_dev_mtu_set, 1981 .vlan_filter_set = dpaa2_vlan_filter_set, 1982 .vlan_offload_set = dpaa2_vlan_offload_set, 1983 .vlan_tpid_set = dpaa2_vlan_tpid_set, 1984 .rx_queue_setup = dpaa2_dev_rx_queue_setup, 1985 .rx_queue_release = dpaa2_dev_rx_queue_release, 1986 .tx_queue_setup = dpaa2_dev_tx_queue_setup, 1987 .tx_queue_release = dpaa2_dev_tx_queue_release, 1988 .rx_queue_count = dpaa2_dev_rx_queue_count, 1989 .flow_ctrl_get = dpaa2_flow_ctrl_get, 1990 .flow_ctrl_set = dpaa2_flow_ctrl_set, 1991 .mac_addr_add = dpaa2_dev_add_mac_addr, 1992 .mac_addr_remove = dpaa2_dev_remove_mac_addr, 1993 .mac_addr_set = dpaa2_dev_set_mac_addr, 1994 .rss_hash_update = dpaa2_dev_rss_hash_update, 1995 .rss_hash_conf_get = dpaa2_dev_rss_hash_conf_get, 1996 .filter_ctrl = dpaa2_dev_flow_ctrl, 1997 }; 1998 1999 /* Populate the mac address from physically available (u-boot/firmware) and/or 2000 * one set by higher layers like MC (restool) etc. 2001 * Returns the table of MAC entries (multiple entries) 2002 */ 2003 static int 2004 populate_mac_addr(struct fsl_mc_io *dpni_dev, struct dpaa2_dev_priv *priv, 2005 struct rte_ether_addr *mac_entry) 2006 { 2007 int ret; 2008 struct rte_ether_addr phy_mac, prime_mac; 2009 2010 memset(&phy_mac, 0, sizeof(struct rte_ether_addr)); 2011 memset(&prime_mac, 0, sizeof(struct rte_ether_addr)); 2012 2013 /* Get the physical device MAC address */ 2014 ret = dpni_get_port_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2015 phy_mac.addr_bytes); 2016 if (ret) { 2017 DPAA2_PMD_ERR("DPNI get physical port MAC failed: %d", ret); 2018 goto cleanup; 2019 } 2020 2021 ret = dpni_get_primary_mac_addr(dpni_dev, CMD_PRI_LOW, priv->token, 2022 prime_mac.addr_bytes); 2023 if (ret) { 2024 DPAA2_PMD_ERR("DPNI get Prime port MAC failed: %d", ret); 2025 goto cleanup; 2026 } 2027 2028 /* Now that both MAC have been obtained, do: 2029 * if not_empty_mac(phy) && phy != Prime, overwrite prime with Phy 2030 * and return phy 2031 * If empty_mac(phy), return prime. 2032 * if both are empty, create random MAC, set as prime and return 2033 */ 2034 if (!rte_is_zero_ether_addr(&phy_mac)) { 2035 /* If the addresses are not same, overwrite prime */ 2036 if (!rte_is_same_ether_addr(&phy_mac, &prime_mac)) { 2037 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2038 priv->token, 2039 phy_mac.addr_bytes); 2040 if (ret) { 2041 DPAA2_PMD_ERR("Unable to set MAC Address: %d", 2042 ret); 2043 goto cleanup; 2044 } 2045 memcpy(&prime_mac, &phy_mac, 2046 sizeof(struct rte_ether_addr)); 2047 } 2048 } else if (rte_is_zero_ether_addr(&prime_mac)) { 2049 /* In case phys and prime, both are zero, create random MAC */ 2050 rte_eth_random_addr(prime_mac.addr_bytes); 2051 ret = dpni_set_primary_mac_addr(dpni_dev, CMD_PRI_LOW, 2052 priv->token, 2053 prime_mac.addr_bytes); 2054 if (ret) { 2055 DPAA2_PMD_ERR("Unable to set MAC Address: %d", ret); 2056 goto cleanup; 2057 } 2058 } 2059 2060 /* prime_mac the final MAC address */ 2061 memcpy(mac_entry, &prime_mac, sizeof(struct rte_ether_addr)); 2062 return 0; 2063 2064 cleanup: 2065 return -1; 2066 } 2067 2068 static int 2069 check_devargs_handler(__rte_unused const char *key, const char *value, 2070 __rte_unused void *opaque) 2071 { 2072 if (strcmp(value, "1")) 2073 return -1; 2074 2075 return 0; 2076 } 2077 2078 static int 2079 dpaa2_get_devargs(struct rte_devargs *devargs, const char *key) 2080 { 2081 struct rte_kvargs *kvlist; 2082 2083 if (!devargs) 2084 return 0; 2085 2086 kvlist = rte_kvargs_parse(devargs->args, NULL); 2087 if (!kvlist) 2088 return 0; 2089 2090 if (!rte_kvargs_count(kvlist, key)) { 2091 rte_kvargs_free(kvlist); 2092 return 0; 2093 } 2094 2095 if (rte_kvargs_process(kvlist, key, 2096 check_devargs_handler, NULL) < 0) { 2097 rte_kvargs_free(kvlist); 2098 return 0; 2099 } 2100 rte_kvargs_free(kvlist); 2101 2102 return 1; 2103 } 2104 2105 static int 2106 dpaa2_dev_init(struct rte_eth_dev *eth_dev) 2107 { 2108 struct rte_device *dev = eth_dev->device; 2109 struct rte_dpaa2_device *dpaa2_dev; 2110 struct fsl_mc_io *dpni_dev; 2111 struct dpni_attr attr; 2112 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2113 struct dpni_buffer_layout layout; 2114 int ret, hw_id, i; 2115 2116 PMD_INIT_FUNC_TRACE(); 2117 2118 /* For secondary processes, the primary has done all the work */ 2119 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2120 /* In case of secondary, only burst and ops API need to be 2121 * plugged. 2122 */ 2123 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2124 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) 2125 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2126 else 2127 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2128 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2129 return 0; 2130 } 2131 2132 dpaa2_dev = container_of(dev, struct rte_dpaa2_device, device); 2133 2134 hw_id = dpaa2_dev->object_id; 2135 2136 dpni_dev = rte_malloc(NULL, sizeof(struct fsl_mc_io), 0); 2137 if (!dpni_dev) { 2138 DPAA2_PMD_ERR("Memory allocation failed for dpni device"); 2139 return -1; 2140 } 2141 2142 dpni_dev->regs = rte_mcp_ptr_list[0]; 2143 ret = dpni_open(dpni_dev, CMD_PRI_LOW, hw_id, &priv->token); 2144 if (ret) { 2145 DPAA2_PMD_ERR( 2146 "Failure in opening dpni@%d with err code %d", 2147 hw_id, ret); 2148 rte_free(dpni_dev); 2149 return -1; 2150 } 2151 2152 /* Clean the device first */ 2153 ret = dpni_reset(dpni_dev, CMD_PRI_LOW, priv->token); 2154 if (ret) { 2155 DPAA2_PMD_ERR("Failure cleaning dpni@%d with err code %d", 2156 hw_id, ret); 2157 goto init_err; 2158 } 2159 2160 ret = dpni_get_attributes(dpni_dev, CMD_PRI_LOW, priv->token, &attr); 2161 if (ret) { 2162 DPAA2_PMD_ERR( 2163 "Failure in get dpni@%d attribute, err code %d", 2164 hw_id, ret); 2165 goto init_err; 2166 } 2167 2168 priv->num_rx_tc = attr.num_rx_tcs; 2169 2170 for (i = 0; i < attr.num_rx_tcs; i++) 2171 priv->nb_rx_queues += attr.num_queues; 2172 2173 /* Using number of TX queues as number of TX TCs */ 2174 priv->nb_tx_queues = attr.num_tx_tcs; 2175 2176 DPAA2_PMD_DEBUG("RX-TC= %d, nb_rx_queues= %d, nb_tx_queues=%d", 2177 priv->num_rx_tc, priv->nb_rx_queues, 2178 priv->nb_tx_queues); 2179 2180 priv->hw = dpni_dev; 2181 priv->hw_id = hw_id; 2182 priv->options = attr.options; 2183 priv->max_mac_filters = attr.mac_filter_entries; 2184 priv->max_vlan_filters = attr.vlan_filter_entries; 2185 priv->flags = 0; 2186 2187 /* Allocate memory for hardware structure for queues */ 2188 ret = dpaa2_alloc_rx_tx_queues(eth_dev); 2189 if (ret) { 2190 DPAA2_PMD_ERR("Queue allocation Failed"); 2191 goto init_err; 2192 } 2193 2194 /* Allocate memory for storing MAC addresses. 2195 * Table of mac_filter_entries size is allocated so that RTE ether lib 2196 * can add MAC entries when rte_eth_dev_mac_addr_add is called. 2197 */ 2198 eth_dev->data->mac_addrs = rte_zmalloc("dpni", 2199 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries, 0); 2200 if (eth_dev->data->mac_addrs == NULL) { 2201 DPAA2_PMD_ERR( 2202 "Failed to allocate %d bytes needed to store MAC addresses", 2203 RTE_ETHER_ADDR_LEN * attr.mac_filter_entries); 2204 ret = -ENOMEM; 2205 goto init_err; 2206 } 2207 2208 ret = populate_mac_addr(dpni_dev, priv, ð_dev->data->mac_addrs[0]); 2209 if (ret) { 2210 DPAA2_PMD_ERR("Unable to fetch MAC Address for device"); 2211 rte_free(eth_dev->data->mac_addrs); 2212 eth_dev->data->mac_addrs = NULL; 2213 goto init_err; 2214 } 2215 2216 /* ... tx buffer layout ... */ 2217 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2218 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2219 layout.pass_frame_status = 1; 2220 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2221 DPNI_QUEUE_TX, &layout); 2222 if (ret) { 2223 DPAA2_PMD_ERR("Error (%d) in setting tx buffer layout", ret); 2224 goto init_err; 2225 } 2226 2227 /* ... tx-conf and error buffer layout ... */ 2228 memset(&layout, 0, sizeof(struct dpni_buffer_layout)); 2229 layout.options = DPNI_BUF_LAYOUT_OPT_FRAME_STATUS; 2230 layout.pass_frame_status = 1; 2231 ret = dpni_set_buffer_layout(dpni_dev, CMD_PRI_LOW, priv->token, 2232 DPNI_QUEUE_TX_CONFIRM, &layout); 2233 if (ret) { 2234 DPAA2_PMD_ERR("Error (%d) in setting tx-conf buffer layout", 2235 ret); 2236 goto init_err; 2237 } 2238 2239 eth_dev->dev_ops = &dpaa2_ethdev_ops; 2240 2241 if (dpaa2_get_devargs(dev->devargs, DRIVER_LOOPBACK_MODE)) { 2242 eth_dev->rx_pkt_burst = dpaa2_dev_loopback_rx; 2243 DPAA2_PMD_INFO("Loopback mode"); 2244 } else { 2245 eth_dev->rx_pkt_burst = dpaa2_dev_prefetch_rx; 2246 } 2247 eth_dev->tx_pkt_burst = dpaa2_dev_tx; 2248 2249 /*Init fields w.r.t. classficaition*/ 2250 memset(&priv->extract.qos_key_cfg, 0, sizeof(struct dpkg_profile_cfg)); 2251 priv->extract.qos_extract_param = (size_t)rte_malloc(NULL, 256, 64); 2252 if (!priv->extract.qos_extract_param) { 2253 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow " 2254 " classificaiton ", ret); 2255 goto init_err; 2256 } 2257 for (i = 0; i < MAX_TCS; i++) { 2258 memset(&priv->extract.fs_key_cfg[i], 0, 2259 sizeof(struct dpkg_profile_cfg)); 2260 priv->extract.fs_extract_param[i] = 2261 (size_t)rte_malloc(NULL, 256, 64); 2262 if (!priv->extract.fs_extract_param[i]) { 2263 DPAA2_PMD_ERR(" Error(%d) in allocation resources for flow classificaiton", 2264 ret); 2265 goto init_err; 2266 } 2267 } 2268 2269 RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name); 2270 return 0; 2271 init_err: 2272 dpaa2_dev_uninit(eth_dev); 2273 return ret; 2274 } 2275 2276 static int 2277 dpaa2_dev_uninit(struct rte_eth_dev *eth_dev) 2278 { 2279 struct dpaa2_dev_priv *priv = eth_dev->data->dev_private; 2280 struct fsl_mc_io *dpni = (struct fsl_mc_io *)priv->hw; 2281 int i, ret; 2282 2283 PMD_INIT_FUNC_TRACE(); 2284 2285 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2286 return 0; 2287 2288 if (!dpni) { 2289 DPAA2_PMD_WARN("Already closed or not started"); 2290 return -1; 2291 } 2292 2293 dpaa2_dev_close(eth_dev); 2294 2295 dpaa2_free_rx_tx_queues(eth_dev); 2296 2297 /* Close the device at underlying layer*/ 2298 ret = dpni_close(dpni, CMD_PRI_LOW, priv->token); 2299 if (ret) { 2300 DPAA2_PMD_ERR( 2301 "Failure closing dpni device with err code %d", 2302 ret); 2303 } 2304 2305 /* Free the allocated memory for ethernet private data and dpni*/ 2306 priv->hw = NULL; 2307 rte_free(dpni); 2308 2309 for (i = 0; i < MAX_TCS; i++) { 2310 if (priv->extract.fs_extract_param[i]) 2311 rte_free((void *)(size_t)priv->extract.fs_extract_param[i]); 2312 } 2313 2314 if (priv->extract.qos_extract_param) 2315 rte_free((void *)(size_t)priv->extract.qos_extract_param); 2316 2317 eth_dev->dev_ops = NULL; 2318 eth_dev->rx_pkt_burst = NULL; 2319 eth_dev->tx_pkt_burst = NULL; 2320 2321 DPAA2_PMD_INFO("%s: netdev deleted", eth_dev->data->name); 2322 return 0; 2323 } 2324 2325 static int 2326 rte_dpaa2_probe(struct rte_dpaa2_driver *dpaa2_drv, 2327 struct rte_dpaa2_device *dpaa2_dev) 2328 { 2329 struct rte_eth_dev *eth_dev; 2330 int diag; 2331 2332 if ((DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > 2333 RTE_PKTMBUF_HEADROOM) { 2334 DPAA2_PMD_ERR( 2335 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA2 Annotation req(%d)", 2336 RTE_PKTMBUF_HEADROOM, 2337 DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE); 2338 2339 return -1; 2340 } 2341 2342 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 2343 eth_dev = rte_eth_dev_allocate(dpaa2_dev->device.name); 2344 if (!eth_dev) 2345 return -ENODEV; 2346 eth_dev->data->dev_private = rte_zmalloc( 2347 "ethdev private structure", 2348 sizeof(struct dpaa2_dev_priv), 2349 RTE_CACHE_LINE_SIZE); 2350 if (eth_dev->data->dev_private == NULL) { 2351 DPAA2_PMD_CRIT( 2352 "Unable to allocate memory for private data"); 2353 rte_eth_dev_release_port(eth_dev); 2354 return -ENOMEM; 2355 } 2356 } else { 2357 eth_dev = rte_eth_dev_attach_secondary(dpaa2_dev->device.name); 2358 if (!eth_dev) 2359 return -ENODEV; 2360 } 2361 2362 eth_dev->device = &dpaa2_dev->device; 2363 2364 dpaa2_dev->eth_dev = eth_dev; 2365 eth_dev->data->rx_mbuf_alloc_failed = 0; 2366 2367 if (dpaa2_drv->drv_flags & RTE_DPAA2_DRV_INTR_LSC) 2368 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2369 2370 /* Invoke PMD device initialization function */ 2371 diag = dpaa2_dev_init(eth_dev); 2372 if (diag == 0) { 2373 rte_eth_dev_probing_finish(eth_dev); 2374 return 0; 2375 } 2376 2377 rte_eth_dev_release_port(eth_dev); 2378 return diag; 2379 } 2380 2381 static int 2382 rte_dpaa2_remove(struct rte_dpaa2_device *dpaa2_dev) 2383 { 2384 struct rte_eth_dev *eth_dev; 2385 2386 eth_dev = dpaa2_dev->eth_dev; 2387 dpaa2_dev_uninit(eth_dev); 2388 2389 rte_eth_dev_release_port(eth_dev); 2390 2391 return 0; 2392 } 2393 2394 static struct rte_dpaa2_driver rte_dpaa2_pmd = { 2395 .drv_flags = RTE_DPAA2_DRV_INTR_LSC | RTE_DPAA2_DRV_IOVA_AS_VA, 2396 .drv_type = DPAA2_ETH, 2397 .probe = rte_dpaa2_probe, 2398 .remove = rte_dpaa2_remove, 2399 }; 2400 2401 RTE_PMD_REGISTER_DPAA2(net_dpaa2, rte_dpaa2_pmd); 2402 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa2, 2403 DRIVER_LOOPBACK_MODE "=<int>"); 2404 RTE_INIT(dpaa2_pmd_init_log) 2405 { 2406 dpaa2_logtype_pmd = rte_log_register("pmd.net.dpaa2"); 2407 if (dpaa2_logtype_pmd >= 0) 2408 rte_log_set_level(dpaa2_logtype_pmd, RTE_LOG_NOTICE); 2409 } 2410