1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017,2020-2024 NXP 5 * 6 */ 7 8 #ifndef __DPDK_RXTX_H__ 9 #define __DPDK_RXTX_H__ 10 11 /* internal offset from where IC is copied to packet buffer*/ 12 #define DEFAULT_ICIOF 32 13 /* IC transfer size */ 14 #define DEFAULT_ICSZ 48 15 16 /* IC offsets from buffer header address */ 17 #define DEFAULT_RX_ICEOF 16 18 #define DEFAULT_TX_ICEOF 16 19 20 /* 21 * Values for the L3R field of the FM Parse Results 22 */ 23 /* L3 Type field: First IP Present IPv4 */ 24 #define DPAA_L3_PARSE_RESULT_IPV4 0x80 25 /* L3 Type field: First IP Present IPv6 */ 26 #define DPAA_L3_PARSE_RESULT_IPV6 0x40 27 /* Values for the L4R field of the FM Parse Results 28 * See $8.8.4.7.20 - L4 HXS - L4 Results from DPAA-Rev2 Reference Manual. 29 */ 30 /* L4 Type field: UDP */ 31 #define DPAA_L4_PARSE_RESULT_UDP 0x40 32 /* L4 Type field: TCP */ 33 #define DPAA_L4_PARSE_RESULT_TCP 0x20 34 35 #define DPAA_MAX_DEQUEUE_NUM_FRAMES 63 36 /** <Maximum number of frames to be dequeued in a single rx call*/ 37 38 /* FD structure masks and offset */ 39 #define DPAA_FD_FORMAT_MASK 0xE0000000 40 #define DPAA_FD_OFFSET_MASK 0x1FF00000 41 #define DPAA_FD_LENGTH_MASK 0xFFFFF 42 #define DPAA_FD_FORMAT_SHIFT 29 43 #define DPAA_FD_OFFSET_SHIFT 20 44 45 /* Parsing mask (Little Endian) - 0x00E044ED00800000 46 * Classification Plan ID 0x00 47 * L4R 0xE0 - 48 * 0x20 - TCP 49 * 0x40 - UDP 50 * 0x60 - IPsec 51 * 0x80 - SCTP 52 * L3R 0xEDC4 (in Big Endian) - 53 * 0x8000 - IPv4 54 * 0x4000 - IPv6 55 * 0x8140 - IPv4 Ext + Frag 56 * 0x8040 - IPv4 Frag 57 * 0x8100 - IPv4 Ext 58 * 0x4140 - IPv6 Ext + Frag 59 * 0x4040 - IPv6 Frag 60 * 0x4100 - IPv6 Ext 61 * L2R 0x8000 (in Big Endian) - 62 * 0x8000 - Ethernet type 63 * ShimR & Logical Port ID 0x0000 64 */ 65 #define DPAA_PARSE_MASK 0x00F044EF00800000 66 #define DPAA_PARSE_VLAN_MASK 0x0000000000700000 67 #define DPAA_PARSE_ESP_MASK 0x0008000000000000 68 69 /* Parsed values (Little Endian) */ 70 #define DPAA_PKT_TYPE_NONE 0x0000000000000000 71 #define DPAA_PKT_TYPE_ETHER 0x0000000000800000 72 #define DPAA_PKT_TYPE_IPV4 \ 73 (0x0000008000000000 | DPAA_PKT_TYPE_ETHER) 74 #define DPAA_PKT_TYPE_IPV6 \ 75 (0x0000004000000000 | DPAA_PKT_TYPE_ETHER) 76 #define DPAA_PKT_TYPE_GRE \ 77 (0x0000002000000000 | DPAA_PKT_TYPE_ETHER) 78 #define DPAA_PKT_TYPE_IPV4_FRAG \ 79 (0x0000400000000000 | DPAA_PKT_TYPE_IPV4) 80 #define DPAA_PKT_TYPE_IPV6_FRAG \ 81 (0x0000400000000000 | DPAA_PKT_TYPE_IPV6) 82 #define DPAA_PKT_TYPE_IPV4_EXT \ 83 (0x0000000100000000 | DPAA_PKT_TYPE_IPV4) 84 #define DPAA_PKT_TYPE_IPV6_EXT \ 85 (0x0000000100000000 | DPAA_PKT_TYPE_IPV6) 86 #define DPAA_PKT_TYPE_IPV4_TCP \ 87 (0x0020000000000000 | DPAA_PKT_TYPE_IPV4) 88 #define DPAA_PKT_TYPE_IPV6_TCP \ 89 (0x0020000000000000 | DPAA_PKT_TYPE_IPV6) 90 #define DPAA_PKT_TYPE_IPV4_UDP \ 91 (0x0040000000000000 | DPAA_PKT_TYPE_IPV4) 92 #define DPAA_PKT_TYPE_IPV6_UDP \ 93 (0x0040000000000000 | DPAA_PKT_TYPE_IPV6) 94 #define DPAA_PKT_TYPE_IPV4_SCTP \ 95 (0x0080000000000000 | DPAA_PKT_TYPE_IPV4) 96 #define DPAA_PKT_TYPE_IPV6_SCTP \ 97 (0x0080000000000000 | DPAA_PKT_TYPE_IPV6) 98 #define DPAA_PKT_TYPE_IPV4_FRAG_TCP \ 99 (0x0020000000000000 | DPAA_PKT_TYPE_IPV4_FRAG) 100 #define DPAA_PKT_TYPE_IPV6_FRAG_TCP \ 101 (0x0020000000000000 | DPAA_PKT_TYPE_IPV6_FRAG) 102 #define DPAA_PKT_TYPE_IPV4_FRAG_UDP \ 103 (0x0040000000000000 | DPAA_PKT_TYPE_IPV4_FRAG) 104 #define DPAA_PKT_TYPE_IPV6_FRAG_UDP \ 105 (0x0040000000000000 | DPAA_PKT_TYPE_IPV6_FRAG) 106 #define DPAA_PKT_TYPE_IPV4_FRAG_SCTP \ 107 (0x0080000000000000 | DPAA_PKT_TYPE_IPV4_FRAG) 108 #define DPAA_PKT_TYPE_IPV6_FRAG_SCTP \ 109 (0x0080000000000000 | DPAA_PKT_TYPE_IPV6_FRAG) 110 #define DPAA_PKT_TYPE_IPV4_EXT_UDP \ 111 (0x0040000000000000 | DPAA_PKT_TYPE_IPV4_EXT) 112 #define DPAA_PKT_TYPE_IPV6_EXT_UDP \ 113 (0x0040000000000000 | DPAA_PKT_TYPE_IPV6_EXT) 114 #define DPAA_PKT_TYPE_IPV4_EXT_TCP \ 115 (0x0020000000000000 | DPAA_PKT_TYPE_IPV4_EXT) 116 #define DPAA_PKT_TYPE_IPV6_EXT_TCP \ 117 (0x0020000000000000 | DPAA_PKT_TYPE_IPV6_EXT) 118 #define DPAA_PKT_TYPE_TUNNEL_4_4 \ 119 (0x0000000800000000 | DPAA_PKT_TYPE_IPV4) 120 #define DPAA_PKT_TYPE_TUNNEL_6_6 \ 121 (0x0000000400000000 | DPAA_PKT_TYPE_IPV6) 122 #define DPAA_PKT_TYPE_TUNNEL_4_6 \ 123 (0x0000000400000000 | DPAA_PKT_TYPE_IPV4) 124 #define DPAA_PKT_TYPE_TUNNEL_6_4 \ 125 (0x0000000800000000 | DPAA_PKT_TYPE_IPV6) 126 #define DPAA_PKT_TYPE_TUNNEL_4_4_UDP \ 127 (0x0040000000000000 | DPAA_PKT_TYPE_TUNNEL_4_4) 128 #define DPAA_PKT_TYPE_TUNNEL_6_6_UDP \ 129 (0x0040000000000000 | DPAA_PKT_TYPE_TUNNEL_6_6) 130 #define DPAA_PKT_TYPE_TUNNEL_4_6_UDP \ 131 (0x0040000000000000 | DPAA_PKT_TYPE_TUNNEL_4_6) 132 #define DPAA_PKT_TYPE_TUNNEL_6_4_UDP \ 133 (0x0040000000000000 | DPAA_PKT_TYPE_TUNNEL_6_4) 134 #define DPAA_PKT_TYPE_TUNNEL_4_4_TCP \ 135 (0x0020000000000000 | DPAA_PKT_TYPE_TUNNEL_4_4) 136 #define DPAA_PKT_TYPE_TUNNEL_6_6_TCP \ 137 (0x0020000000000000 | DPAA_PKT_TYPE_TUNNEL_6_6) 138 #define DPAA_PKT_TYPE_TUNNEL_4_6_TCP \ 139 (0x0020000000000000 | DPAA_PKT_TYPE_TUNNEL_4_6) 140 #define DPAA_PKT_TYPE_TUNNEL_6_4_TCP \ 141 (0x0020000000000000 | DPAA_PKT_TYPE_TUNNEL_6_4) 142 #define DPAA_PKT_TYPE_IPSEC_IPV4 \ 143 (0x0060000000000000 | DPAA_PKT_TYPE_IPV4) 144 #define DPAA_PKT_TYPE_IPSEC_IPV6 \ 145 (0x0060000000000000 | DPAA_PKT_TYPE_IPV6) 146 147 /* Checksum Errors */ 148 #define DPAA_PKT_IP_CSUM_ERR 0x0000400200000000 149 #define DPAA_PKT_L4_CSUM_ERR 0x0010000000000000 150 #define DPAA_PKT_TYPE_IPV4_CSUM_ERR \ 151 (DPAA_PKT_IP_CSUM_ERR | DPAA_PKT_TYPE_IPV4) 152 #define DPAA_PKT_TYPE_IPV6_CSUM_ERR \ 153 (DPAA_PKT_IP_CSUM_ERR | DPAA_PKT_TYPE_IPV6) 154 #define DPAA_PKT_TYPE_IPV4_TCP_CSUM_ERR \ 155 (DPAA_PKT_L4_CSUM_ERR | DPAA_PKT_TYPE_IPV4_TCP) 156 #define DPAA_PKT_TYPE_IPV6_TCP_CSUM_ERR \ 157 (DPAA_PKT_L4_CSUM_ERR | DPAA_PKT_TYPE_IPV6_TCP) 158 #define DPAA_PKT_TYPE_IPV4_UDP_CSUM_ERR \ 159 (DPAA_PKT_L4_CSUM_ERR | DPAA_PKT_TYPE_IPV4_UDP) 160 #define DPAA_PKT_TYPE_IPV6_UDP_CSUM_ERR \ 161 (DPAA_PKT_L4_CSUM_ERR | DPAA_PKT_TYPE_IPV6_UDP) 162 163 #define DPAA_PKT_L3_LEN_SHIFT 7 164 165 enum dpaa_parse_result_l4_type { 166 DPAA_PR_L4_TCP_TYPE = 1, 167 DPAA_PR_L4_UDP_TYPE = 2, 168 DPAA_PR_L4_IPSEC_TYPE = 3, 169 DPAA_PR_L4_SCTP_TYPE = 4, 170 DPAA_PR_L4_DCCP_TYPE = 5 171 }; 172 173 /** 174 * FMan parse result array 175 */ 176 struct __rte_packed_begin dpaa_eth_parse_results_t { 177 uint8_t lpid; /**< Logical port id */ 178 uint8_t shimr; /**< Shim header result */ 179 union __rte_packed_begin { 180 uint16_t l2r; /**< Layer 2 result */ 181 struct __rte_packed_begin { 182 uint16_t unused_1:3; 183 uint16_t ppoe_ppp:1; 184 uint16_t mpls:1; 185 uint16_t llc_snap:1; 186 uint16_t vlan:1; 187 uint16_t ethernet:1; 188 189 uint16_t l2r_err:5; 190 uint16_t eth_frame_type:2; 191 /*00-unicast, 01-multicast, 11-broadcast*/ 192 uint16_t unknown_eth_proto:1; 193 } __rte_packed_end; 194 } __rte_packed_end; 195 union __rte_packed_begin { 196 uint16_t l3r; /**< Layer 3 result */ 197 struct __rte_packed_begin { 198 uint16_t unused_2:1; 199 uint16_t l3_err:1; 200 uint16_t last_ipv6:1; 201 uint16_t last_ipv4:1; 202 uint16_t min_enc:1; 203 uint16_t gre:1; 204 uint16_t first_ipv6:1; 205 uint16_t first_ipv4:1; 206 207 uint16_t unused_3:8; 208 } __rte_packed_end; 209 } __rte_packed_end; 210 union __rte_packed_begin { 211 uint8_t l4r; /**< Layer 4 result */ 212 struct __rte_packed_begin { 213 uint8_t l4cv:1; 214 uint8_t unused_4:1; 215 uint8_t ah:1; 216 uint8_t esp_sum:1; 217 uint8_t l4_info_err:1; 218 uint8_t l4_type:3; 219 } __rte_packed_end; 220 } __rte_packed_end; 221 uint8_t cplan; /**< Classification plan id */ 222 uint16_t nxthdr; /**< Next Header */ 223 uint16_t cksum; /**< Checksum */ 224 uint32_t lcv; /**< LCV */ 225 uint8_t shim_off[3]; /**< Shim offset */ 226 uint8_t eth_off; /**< ETH offset */ 227 uint8_t llc_snap_off; /**< LLC_SNAP offset */ 228 uint8_t vlan_off[2]; /**< VLAN offset */ 229 uint8_t etype_off; /**< ETYPE offset */ 230 uint8_t pppoe_off; /**< PPP offset */ 231 uint8_t mpls_off[2]; /**< MPLS offset */ 232 uint8_t ip_off[2]; /**< IP offset */ 233 uint8_t gre_off; /**< GRE offset */ 234 uint8_t l4_off; /**< Layer 4 offset */ 235 uint8_t nxthdr_off; /**< Parser end point */ 236 } __rte_packed_end; 237 238 /* The structure is the Prepended Data to the Frame which is used by FMAN */ 239 struct annotations_t { 240 uint8_t reserved[DEFAULT_RX_ICEOF]; 241 struct dpaa_eth_parse_results_t parse; /**< Pointer to Parsed result*/ 242 uint64_t timestamp; 243 uint64_t hash; /**< Hash Result */ 244 }; 245 246 #define GET_ANNOTATIONS(_buf) \ 247 (struct annotations_t *)(_buf) 248 249 #define GET_RX_PRS(_buf) \ 250 (struct dpaa_eth_parse_results_t *)((uint8_t *)(_buf) + \ 251 DEFAULT_RX_ICEOF) 252 253 #define GET_TX_PRS(_buf) \ 254 (struct dpaa_eth_parse_results_t *)((uint8_t *)(_buf) + \ 255 DEFAULT_TX_ICEOF) 256 257 uint16_t dpaa_eth_queue_rx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs); 258 259 uint16_t dpaa_eth_queue_tx_slow(void *q, struct rte_mbuf **bufs, 260 uint16_t nb_bufs); 261 uint16_t dpaa_eth_queue_tx(void *q, struct rte_mbuf **bufs, uint16_t nb_bufs); 262 263 void dpaa_eth_tx_conf(void *q); 264 265 uint16_t dpaa_eth_tx_drop_all(void *q __rte_unused, 266 struct rte_mbuf **bufs __rte_unused, 267 uint16_t nb_bufs __rte_unused); 268 269 uint16_t dpaa_free_mbuf(const struct qm_fd *fd); 270 void dpaa_rx_cb(struct qman_fq **fq, 271 struct qm_dqrr_entry **dqrr, void **bufs, int num_bufs); 272 273 void dpaa_rx_cb_prepare(struct qm_dqrr_entry *dq, void **bufs); 274 275 void dpaa_rx_cb_no_prefetch(struct qman_fq **fq, 276 struct qm_dqrr_entry **dqrr, void **bufs, int num_bufs); 277 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 278 void 279 dpaa_force_display_frame_set(int set); 280 #endif 281 282 #endif 283