1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 #include "base/common.h" 6 #include "cxgbe_flow.h" 7 8 #define __CXGBE_FILL_FS(__v, __m, fs, elem, e) \ 9 do { \ 10 if ((fs)->mask.elem && ((fs)->val.elem != (__v))) \ 11 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, \ 12 NULL, "Redefined match item with" \ 13 " different values found"); \ 14 (fs)->val.elem = (__v); \ 15 (fs)->mask.elem = (__m); \ 16 } while (0) 17 18 #define __CXGBE_FILL_FS_MEMCPY(__v, __m, fs, elem) \ 19 do { \ 20 memcpy(&(fs)->val.elem, &(__v), sizeof(__v)); \ 21 memcpy(&(fs)->mask.elem, &(__m), sizeof(__m)); \ 22 } while (0) 23 24 #define CXGBE_FILL_FS(v, m, elem) \ 25 __CXGBE_FILL_FS(v, m, fs, elem, e) 26 27 #define CXGBE_FILL_FS_MEMCPY(v, m, elem) \ 28 __CXGBE_FILL_FS_MEMCPY(v, m, fs, elem) 29 30 static int 31 cxgbe_validate_item(const struct rte_flow_item *i, struct rte_flow_error *e) 32 { 33 /* rte_flow specification does not allow it. */ 34 if (!i->spec && (i->mask || i->last)) 35 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 36 i, "last or mask given without spec"); 37 /* 38 * We don't support it. 39 * Although, we can support values in last as 0's or last == spec. 40 * But this will not provide user with any additional functionality 41 * and will only increase the complexity for us. 42 */ 43 if (i->last) 44 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, 45 i, "last is not supported by chelsio pmd"); 46 return 0; 47 } 48 49 /** 50 * Apart from the 4-tuple IPv4/IPv6 - TCP/UDP information, 51 * there's only 40-bits available to store match fields. 52 * So, to save space, optimize filter spec for some common 53 * known fields that hardware can parse against incoming 54 * packets automatically. 55 */ 56 static void 57 cxgbe_tweak_filter_spec(struct adapter *adap, 58 struct ch_filter_specification *fs) 59 { 60 /* Save 16-bit ethertype field space, by setting corresponding 61 * 1-bit flags in the filter spec for common known ethertypes. 62 * When hardware sees these flags, it automatically infers and 63 * matches incoming packets against the corresponding ethertype. 64 */ 65 if (fs->mask.ethtype == 0xffff) { 66 switch (fs->val.ethtype) { 67 case RTE_ETHER_TYPE_IPV4: 68 if (adap->params.tp.ethertype_shift < 0) { 69 fs->type = FILTER_TYPE_IPV4; 70 fs->val.ethtype = 0; 71 fs->mask.ethtype = 0; 72 } 73 break; 74 case RTE_ETHER_TYPE_IPV6: 75 if (adap->params.tp.ethertype_shift < 0) { 76 fs->type = FILTER_TYPE_IPV6; 77 fs->val.ethtype = 0; 78 fs->mask.ethtype = 0; 79 } 80 break; 81 case RTE_ETHER_TYPE_VLAN: 82 if (adap->params.tp.ethertype_shift < 0 && 83 adap->params.tp.vlan_shift >= 0) { 84 fs->val.ivlan_vld = 1; 85 fs->mask.ivlan_vld = 1; 86 fs->val.ethtype = 0; 87 fs->mask.ethtype = 0; 88 } 89 break; 90 case RTE_ETHER_TYPE_QINQ: 91 if (adap->params.tp.ethertype_shift < 0 && 92 adap->params.tp.vnic_shift >= 0) { 93 fs->val.ovlan_vld = 1; 94 fs->mask.ovlan_vld = 1; 95 fs->val.ethtype = 0; 96 fs->mask.ethtype = 0; 97 } 98 break; 99 default: 100 break; 101 } 102 } 103 } 104 105 static void 106 cxgbe_fill_filter_region(struct adapter *adap, 107 struct ch_filter_specification *fs) 108 { 109 struct tp_params *tp = &adap->params.tp; 110 u64 hash_filter_mask = tp->hash_filter_mask; 111 u64 ntuple_mask = 0; 112 113 fs->cap = 0; 114 115 if (!is_hashfilter(adap)) 116 return; 117 118 if (fs->type) { 119 uint8_t biton[16] = {0xff, 0xff, 0xff, 0xff, 120 0xff, 0xff, 0xff, 0xff, 121 0xff, 0xff, 0xff, 0xff, 122 0xff, 0xff, 0xff, 0xff}; 123 uint8_t bitoff[16] = {0}; 124 125 if (!memcmp(fs->val.lip, bitoff, sizeof(bitoff)) || 126 !memcmp(fs->val.fip, bitoff, sizeof(bitoff)) || 127 memcmp(fs->mask.lip, biton, sizeof(biton)) || 128 memcmp(fs->mask.fip, biton, sizeof(biton))) 129 return; 130 } else { 131 uint32_t biton = 0xffffffff; 132 uint32_t bitoff = 0x0U; 133 134 if (!memcmp(fs->val.lip, &bitoff, sizeof(bitoff)) || 135 !memcmp(fs->val.fip, &bitoff, sizeof(bitoff)) || 136 memcmp(fs->mask.lip, &biton, sizeof(biton)) || 137 memcmp(fs->mask.fip, &biton, sizeof(biton))) 138 return; 139 } 140 141 if (!fs->val.lport || fs->mask.lport != 0xffff) 142 return; 143 if (!fs->val.fport || fs->mask.fport != 0xffff) 144 return; 145 146 if (tp->protocol_shift >= 0) 147 ntuple_mask |= (u64)fs->mask.proto << tp->protocol_shift; 148 if (tp->ethertype_shift >= 0) 149 ntuple_mask |= (u64)fs->mask.ethtype << tp->ethertype_shift; 150 if (tp->port_shift >= 0) 151 ntuple_mask |= (u64)fs->mask.iport << tp->port_shift; 152 if (tp->macmatch_shift >= 0) 153 ntuple_mask |= (u64)fs->mask.macidx << tp->macmatch_shift; 154 if (tp->vlan_shift >= 0 && fs->mask.ivlan_vld) 155 ntuple_mask |= (u64)(F_FT_VLAN_VLD | fs->mask.ivlan) << 156 tp->vlan_shift; 157 if (tp->vnic_shift >= 0) { 158 if (fs->mask.ovlan_vld) 159 ntuple_mask |= (u64)(fs->val.ovlan_vld << 16 | 160 fs->mask.ovlan) << tp->vnic_shift; 161 else if (fs->mask.pfvf_vld) 162 ntuple_mask |= (u64)(fs->mask.pfvf_vld << 16 | 163 fs->mask.pf << 13 | 164 fs->mask.vf) << tp->vnic_shift; 165 } 166 if (tp->tos_shift >= 0) 167 ntuple_mask |= (u64)fs->mask.tos << tp->tos_shift; 168 169 if (ntuple_mask != hash_filter_mask) 170 return; 171 172 fs->cap = 1; /* use hash region */ 173 } 174 175 static int 176 ch_rte_parsetype_eth(const void *dmask, const struct rte_flow_item *item, 177 struct ch_filter_specification *fs, 178 struct rte_flow_error *e) 179 { 180 const struct rte_flow_item_eth *spec = item->spec; 181 const struct rte_flow_item_eth *umask = item->mask; 182 const struct rte_flow_item_eth *mask; 183 184 /* If user has not given any mask, then use chelsio supported mask. */ 185 mask = umask ? umask : (const struct rte_flow_item_eth *)dmask; 186 187 if (!spec) 188 return 0; 189 190 /* we don't support SRC_MAC filtering*/ 191 if (!rte_is_zero_ether_addr(&mask->src)) 192 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, 193 item, 194 "src mac filtering not supported"); 195 196 if (!rte_is_zero_ether_addr(&mask->dst)) { 197 const u8 *addr = (const u8 *)&spec->dst.addr_bytes[0]; 198 const u8 *m = (const u8 *)&mask->dst.addr_bytes[0]; 199 struct rte_flow *flow = (struct rte_flow *)fs->private; 200 struct port_info *pi = (struct port_info *) 201 (flow->dev->data->dev_private); 202 int idx; 203 204 idx = cxgbe_mpstcam_alloc(pi, addr, m); 205 if (idx <= 0) 206 return rte_flow_error_set(e, idx, 207 RTE_FLOW_ERROR_TYPE_ITEM, 208 NULL, "unable to allocate mac" 209 " entry in h/w"); 210 CXGBE_FILL_FS(idx, 0x1ff, macidx); 211 } 212 213 CXGBE_FILL_FS(be16_to_cpu(spec->type), 214 be16_to_cpu(mask->type), ethtype); 215 216 return 0; 217 } 218 219 static int 220 ch_rte_parsetype_port(const void *dmask, const struct rte_flow_item *item, 221 struct ch_filter_specification *fs, 222 struct rte_flow_error *e) 223 { 224 const struct rte_flow_item_phy_port *val = item->spec; 225 const struct rte_flow_item_phy_port *umask = item->mask; 226 const struct rte_flow_item_phy_port *mask; 227 228 mask = umask ? umask : (const struct rte_flow_item_phy_port *)dmask; 229 230 if (!val) 231 return 0; /* Wildcard, match all physical ports */ 232 233 if (val->index > 0x7) 234 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 235 item, 236 "port index upto 0x7 is supported"); 237 238 CXGBE_FILL_FS(val->index, mask->index, iport); 239 240 return 0; 241 } 242 243 static int 244 ch_rte_parsetype_vlan(const void *dmask, const struct rte_flow_item *item, 245 struct ch_filter_specification *fs, 246 struct rte_flow_error *e) 247 { 248 const struct rte_flow_item_vlan *spec = item->spec; 249 const struct rte_flow_item_vlan *umask = item->mask; 250 const struct rte_flow_item_vlan *mask; 251 252 /* If user has not given any mask, then use chelsio supported mask. */ 253 mask = umask ? umask : (const struct rte_flow_item_vlan *)dmask; 254 255 if (!fs->mask.ethtype) 256 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 257 item, 258 "Can't parse VLAN item without knowing ethertype"); 259 260 /* If ethertype is already set and is not VLAN (0x8100) or 261 * QINQ(0x88A8), then don't proceed further. Otherwise, 262 * reset the outer ethertype, so that it can be replaced by 263 * innermost ethertype. Note that hardware will automatically 264 * match against VLAN or QINQ packets, based on 'ivlan_vld' or 265 * 'ovlan_vld' bit set in Chelsio filter spec, respectively. 266 */ 267 if (fs->mask.ethtype) { 268 if (fs->val.ethtype != RTE_ETHER_TYPE_VLAN && 269 fs->val.ethtype != RTE_ETHER_TYPE_QINQ) 270 return rte_flow_error_set(e, EINVAL, 271 RTE_FLOW_ERROR_TYPE_ITEM, 272 item, 273 "Ethertype must be 0x8100 or 0x88a8"); 274 } 275 276 if (fs->val.ethtype == RTE_ETHER_TYPE_QINQ) { 277 CXGBE_FILL_FS(1, 1, ovlan_vld); 278 if (spec) { 279 CXGBE_FILL_FS(be16_to_cpu(spec->tci), 280 be16_to_cpu(mask->tci), ovlan); 281 282 fs->mask.ethtype = 0; 283 fs->val.ethtype = 0; 284 } 285 } else if (fs->val.ethtype == RTE_ETHER_TYPE_VLAN) { 286 CXGBE_FILL_FS(1, 1, ivlan_vld); 287 if (spec) { 288 CXGBE_FILL_FS(be16_to_cpu(spec->tci), 289 be16_to_cpu(mask->tci), ivlan); 290 291 fs->mask.ethtype = 0; 292 fs->val.ethtype = 0; 293 } 294 } 295 296 if (spec) 297 CXGBE_FILL_FS(be16_to_cpu(spec->inner_type), 298 be16_to_cpu(mask->inner_type), ethtype); 299 300 return 0; 301 } 302 303 static int 304 ch_rte_parsetype_pf(const void *dmask __rte_unused, 305 const struct rte_flow_item *item __rte_unused, 306 struct ch_filter_specification *fs, 307 struct rte_flow_error *e __rte_unused) 308 { 309 struct rte_flow *flow = (struct rte_flow *)fs->private; 310 struct rte_eth_dev *dev = flow->dev; 311 struct adapter *adap = ethdev2adap(dev); 312 313 CXGBE_FILL_FS(1, 1, pfvf_vld); 314 315 CXGBE_FILL_FS(adap->pf, 0x7, pf); 316 return 0; 317 } 318 319 static int 320 ch_rte_parsetype_vf(const void *dmask, const struct rte_flow_item *item, 321 struct ch_filter_specification *fs, 322 struct rte_flow_error *e) 323 { 324 const struct rte_flow_item_vf *umask = item->mask; 325 const struct rte_flow_item_vf *val = item->spec; 326 const struct rte_flow_item_vf *mask; 327 328 /* If user has not given any mask, then use chelsio supported mask. */ 329 mask = umask ? umask : (const struct rte_flow_item_vf *)dmask; 330 331 CXGBE_FILL_FS(1, 1, pfvf_vld); 332 333 if (!val) 334 return 0; /* Wildcard, match all Vf */ 335 336 if (val->id > UCHAR_MAX) 337 return rte_flow_error_set(e, EINVAL, 338 RTE_FLOW_ERROR_TYPE_ITEM, 339 item, 340 "VF ID > MAX(255)"); 341 342 CXGBE_FILL_FS(val->id, mask->id, vf); 343 344 return 0; 345 } 346 347 static int 348 ch_rte_parsetype_udp(const void *dmask, const struct rte_flow_item *item, 349 struct ch_filter_specification *fs, 350 struct rte_flow_error *e) 351 { 352 const struct rte_flow_item_udp *val = item->spec; 353 const struct rte_flow_item_udp *umask = item->mask; 354 const struct rte_flow_item_udp *mask; 355 356 mask = umask ? umask : (const struct rte_flow_item_udp *)dmask; 357 358 if (mask->hdr.dgram_len || mask->hdr.dgram_cksum) 359 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, 360 item, 361 "udp: only src/dst port supported"); 362 363 CXGBE_FILL_FS(IPPROTO_UDP, 0xff, proto); 364 if (!val) 365 return 0; 366 CXGBE_FILL_FS(be16_to_cpu(val->hdr.src_port), 367 be16_to_cpu(mask->hdr.src_port), fport); 368 CXGBE_FILL_FS(be16_to_cpu(val->hdr.dst_port), 369 be16_to_cpu(mask->hdr.dst_port), lport); 370 return 0; 371 } 372 373 static int 374 ch_rte_parsetype_tcp(const void *dmask, const struct rte_flow_item *item, 375 struct ch_filter_specification *fs, 376 struct rte_flow_error *e) 377 { 378 const struct rte_flow_item_tcp *val = item->spec; 379 const struct rte_flow_item_tcp *umask = item->mask; 380 const struct rte_flow_item_tcp *mask; 381 382 mask = umask ? umask : (const struct rte_flow_item_tcp *)dmask; 383 384 if (mask->hdr.sent_seq || mask->hdr.recv_ack || mask->hdr.data_off || 385 mask->hdr.tcp_flags || mask->hdr.rx_win || mask->hdr.cksum || 386 mask->hdr.tcp_urp) 387 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, 388 item, 389 "tcp: only src/dst port supported"); 390 391 CXGBE_FILL_FS(IPPROTO_TCP, 0xff, proto); 392 if (!val) 393 return 0; 394 CXGBE_FILL_FS(be16_to_cpu(val->hdr.src_port), 395 be16_to_cpu(mask->hdr.src_port), fport); 396 CXGBE_FILL_FS(be16_to_cpu(val->hdr.dst_port), 397 be16_to_cpu(mask->hdr.dst_port), lport); 398 return 0; 399 } 400 401 static int 402 ch_rte_parsetype_ipv4(const void *dmask, const struct rte_flow_item *item, 403 struct ch_filter_specification *fs, 404 struct rte_flow_error *e) 405 { 406 const struct rte_flow_item_ipv4 *val = item->spec; 407 const struct rte_flow_item_ipv4 *umask = item->mask; 408 const struct rte_flow_item_ipv4 *mask; 409 410 mask = umask ? umask : (const struct rte_flow_item_ipv4 *)dmask; 411 412 if (mask->hdr.time_to_live) 413 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, 414 item, "ttl is not supported"); 415 416 if (fs->mask.ethtype && 417 (fs->val.ethtype != RTE_ETHER_TYPE_IPV4)) 418 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 419 item, 420 "Couldn't find IPv4 ethertype"); 421 fs->type = FILTER_TYPE_IPV4; 422 if (!val) 423 return 0; /* ipv4 wild card */ 424 425 CXGBE_FILL_FS(val->hdr.next_proto_id, mask->hdr.next_proto_id, proto); 426 CXGBE_FILL_FS_MEMCPY(val->hdr.dst_addr, mask->hdr.dst_addr, lip); 427 CXGBE_FILL_FS_MEMCPY(val->hdr.src_addr, mask->hdr.src_addr, fip); 428 CXGBE_FILL_FS(val->hdr.type_of_service, mask->hdr.type_of_service, tos); 429 430 return 0; 431 } 432 433 static int 434 ch_rte_parsetype_ipv6(const void *dmask, const struct rte_flow_item *item, 435 struct ch_filter_specification *fs, 436 struct rte_flow_error *e) 437 { 438 const struct rte_flow_item_ipv6 *val = item->spec; 439 const struct rte_flow_item_ipv6 *umask = item->mask; 440 const struct rte_flow_item_ipv6 *mask; 441 u32 vtc_flow, vtc_flow_mask; 442 443 mask = umask ? umask : (const struct rte_flow_item_ipv6 *)dmask; 444 445 vtc_flow_mask = be32_to_cpu(mask->hdr.vtc_flow); 446 447 if (vtc_flow_mask & RTE_IPV6_HDR_FL_MASK || 448 mask->hdr.payload_len || mask->hdr.hop_limits) 449 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, 450 item, 451 "flow/hop are not supported"); 452 453 if (fs->mask.ethtype && 454 (fs->val.ethtype != RTE_ETHER_TYPE_IPV6)) 455 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 456 item, 457 "Couldn't find IPv6 ethertype"); 458 fs->type = FILTER_TYPE_IPV6; 459 if (!val) 460 return 0; /* ipv6 wild card */ 461 462 CXGBE_FILL_FS(val->hdr.proto, mask->hdr.proto, proto); 463 464 vtc_flow = be32_to_cpu(val->hdr.vtc_flow); 465 CXGBE_FILL_FS((vtc_flow & RTE_IPV6_HDR_TC_MASK) >> 466 RTE_IPV6_HDR_TC_SHIFT, 467 (vtc_flow_mask & RTE_IPV6_HDR_TC_MASK) >> 468 RTE_IPV6_HDR_TC_SHIFT, 469 tos); 470 471 CXGBE_FILL_FS_MEMCPY(val->hdr.dst_addr, mask->hdr.dst_addr, lip); 472 CXGBE_FILL_FS_MEMCPY(val->hdr.src_addr, mask->hdr.src_addr, fip); 473 474 return 0; 475 } 476 477 static int 478 cxgbe_rtef_parse_attr(struct rte_flow *flow, const struct rte_flow_attr *attr, 479 struct rte_flow_error *e) 480 { 481 if (attr->egress) 482 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR, 483 attr, "attribute:<egress> is" 484 " not supported !"); 485 if (attr->group > 0) 486 return rte_flow_error_set(e, ENOTSUP, RTE_FLOW_ERROR_TYPE_ATTR, 487 attr, "group parameter is" 488 " not supported."); 489 490 flow->fidx = attr->priority ? attr->priority - 1 : FILTER_ID_MAX; 491 492 return 0; 493 } 494 495 static inline int check_rxq(struct rte_eth_dev *dev, uint16_t rxq) 496 { 497 struct port_info *pi = ethdev2pinfo(dev); 498 499 if (rxq > pi->n_rx_qsets) 500 return -EINVAL; 501 return 0; 502 } 503 504 static int cxgbe_validate_fidxondel(struct filter_entry *f, unsigned int fidx) 505 { 506 struct adapter *adap = ethdev2adap(f->dev); 507 struct ch_filter_specification fs = f->fs; 508 u8 nentries; 509 510 if (fidx >= adap->tids.nftids) { 511 dev_err(adap, "invalid flow index %d.\n", fidx); 512 return -EINVAL; 513 } 514 515 nentries = cxgbe_filter_slots(adap, fs.type); 516 if (!cxgbe_is_filter_set(&adap->tids, fidx, nentries)) { 517 dev_err(adap, "Already free fidx:%d f:%p\n", fidx, f); 518 return -EINVAL; 519 } 520 521 return 0; 522 } 523 524 static int 525 cxgbe_validate_fidxonadd(struct ch_filter_specification *fs, 526 struct adapter *adap, unsigned int fidx) 527 { 528 u8 nentries; 529 530 nentries = cxgbe_filter_slots(adap, fs->type); 531 if (cxgbe_is_filter_set(&adap->tids, fidx, nentries)) { 532 dev_err(adap, "filter index: %d is busy.\n", fidx); 533 return -EBUSY; 534 } 535 536 if (fidx >= adap->tids.nftids) { 537 dev_err(adap, "filter index (%u) >= max(%u)\n", 538 fidx, adap->tids.nftids); 539 return -ERANGE; 540 } 541 542 return 0; 543 } 544 545 static int 546 cxgbe_verify_fidx(struct rte_flow *flow, unsigned int fidx, uint8_t del) 547 { 548 if (flow->fs.cap) 549 return 0; /* Hash filters */ 550 return del ? cxgbe_validate_fidxondel(flow->f, fidx) : 551 cxgbe_validate_fidxonadd(&flow->fs, 552 ethdev2adap(flow->dev), fidx); 553 } 554 555 static int cxgbe_get_fidx(struct rte_flow *flow, unsigned int *fidx) 556 { 557 struct ch_filter_specification *fs = &flow->fs; 558 struct adapter *adap = ethdev2adap(flow->dev); 559 560 /* For tcam get the next available slot, if default value specified */ 561 if (flow->fidx == FILTER_ID_MAX) { 562 u8 nentries; 563 int idx; 564 565 nentries = cxgbe_filter_slots(adap, fs->type); 566 idx = cxgbe_alloc_ftid(adap, nentries); 567 if (idx < 0) { 568 dev_err(adap, "unable to get a filter index in tcam\n"); 569 return -ENOMEM; 570 } 571 *fidx = (unsigned int)idx; 572 } else { 573 *fidx = flow->fidx; 574 } 575 576 return 0; 577 } 578 579 static int 580 cxgbe_get_flow_item_index(const struct rte_flow_item items[], u32 type) 581 { 582 const struct rte_flow_item *i; 583 int j, index = -ENOENT; 584 585 for (i = items, j = 0; i->type != RTE_FLOW_ITEM_TYPE_END; i++, j++) { 586 if (i->type == type) { 587 index = j; 588 break; 589 } 590 } 591 592 return index; 593 } 594 595 static int 596 ch_rte_parse_nat(uint8_t nmode, struct ch_filter_specification *fs) 597 { 598 /* nmode: 599 * BIT_0 = [src_ip], BIT_1 = [dst_ip] 600 * BIT_2 = [src_port], BIT_3 = [dst_port] 601 * 602 * Only below cases are supported as per our spec. 603 */ 604 switch (nmode) { 605 case 0: /* 0000b */ 606 fs->nat_mode = NAT_MODE_NONE; 607 break; 608 case 2: /* 0010b */ 609 fs->nat_mode = NAT_MODE_DIP; 610 break; 611 case 5: /* 0101b */ 612 fs->nat_mode = NAT_MODE_SIP_SP; 613 break; 614 case 7: /* 0111b */ 615 fs->nat_mode = NAT_MODE_DIP_SIP_SP; 616 break; 617 case 10: /* 1010b */ 618 fs->nat_mode = NAT_MODE_DIP_DP; 619 break; 620 case 11: /* 1011b */ 621 fs->nat_mode = NAT_MODE_DIP_DP_SIP; 622 break; 623 case 14: /* 1110b */ 624 fs->nat_mode = NAT_MODE_DIP_DP_SP; 625 break; 626 case 15: /* 1111b */ 627 fs->nat_mode = NAT_MODE_ALL; 628 break; 629 default: 630 return -EINVAL; 631 } 632 633 return 0; 634 } 635 636 static int 637 ch_rte_parse_atype_switch(const struct rte_flow_action *a, 638 const struct rte_flow_item items[], 639 uint8_t *nmode, 640 struct ch_filter_specification *fs, 641 struct rte_flow_error *e) 642 { 643 const struct rte_flow_action_of_set_vlan_vid *vlanid; 644 const struct rte_flow_action_of_set_vlan_pcp *vlanpcp; 645 const struct rte_flow_action_of_push_vlan *pushvlan; 646 const struct rte_flow_action_set_ipv4 *ipv4; 647 const struct rte_flow_action_set_ipv6 *ipv6; 648 const struct rte_flow_action_set_tp *tp_port; 649 const struct rte_flow_action_phy_port *port; 650 const struct rte_flow_action_set_mac *mac; 651 int item_index; 652 u16 tmp_vlan; 653 654 switch (a->type) { 655 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 656 vlanid = (const struct rte_flow_action_of_set_vlan_vid *) 657 a->conf; 658 /* If explicitly asked to push a new VLAN header, 659 * then don't set rewrite mode. Otherwise, the 660 * incoming VLAN packets will get their VLAN fields 661 * rewritten, instead of adding an additional outer 662 * VLAN header. 663 */ 664 if (fs->newvlan != VLAN_INSERT) 665 fs->newvlan = VLAN_REWRITE; 666 tmp_vlan = fs->vlan & 0xe000; 667 fs->vlan = (be16_to_cpu(vlanid->vlan_vid) & 0xfff) | tmp_vlan; 668 break; 669 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 670 vlanpcp = (const struct rte_flow_action_of_set_vlan_pcp *) 671 a->conf; 672 /* If explicitly asked to push a new VLAN header, 673 * then don't set rewrite mode. Otherwise, the 674 * incoming VLAN packets will get their VLAN fields 675 * rewritten, instead of adding an additional outer 676 * VLAN header. 677 */ 678 if (fs->newvlan != VLAN_INSERT) 679 fs->newvlan = VLAN_REWRITE; 680 tmp_vlan = fs->vlan & 0xfff; 681 fs->vlan = (vlanpcp->vlan_pcp << 13) | tmp_vlan; 682 break; 683 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 684 pushvlan = (const struct rte_flow_action_of_push_vlan *) 685 a->conf; 686 if (be16_to_cpu(pushvlan->ethertype) != RTE_ETHER_TYPE_VLAN) 687 return rte_flow_error_set(e, EINVAL, 688 RTE_FLOW_ERROR_TYPE_ACTION, a, 689 "only ethertype 0x8100 " 690 "supported for push vlan."); 691 fs->newvlan = VLAN_INSERT; 692 break; 693 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 694 fs->newvlan = VLAN_REMOVE; 695 break; 696 case RTE_FLOW_ACTION_TYPE_PHY_PORT: 697 port = (const struct rte_flow_action_phy_port *)a->conf; 698 fs->eport = port->index; 699 break; 700 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 701 item_index = cxgbe_get_flow_item_index(items, 702 RTE_FLOW_ITEM_TYPE_IPV4); 703 if (item_index < 0) 704 return rte_flow_error_set(e, EINVAL, 705 RTE_FLOW_ERROR_TYPE_ACTION, a, 706 "No RTE_FLOW_ITEM_TYPE_IPV4 " 707 "found."); 708 709 ipv4 = (const struct rte_flow_action_set_ipv4 *)a->conf; 710 memcpy(fs->nat_fip, &ipv4->ipv4_addr, sizeof(ipv4->ipv4_addr)); 711 *nmode |= 1 << 0; 712 break; 713 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 714 item_index = cxgbe_get_flow_item_index(items, 715 RTE_FLOW_ITEM_TYPE_IPV4); 716 if (item_index < 0) 717 return rte_flow_error_set(e, EINVAL, 718 RTE_FLOW_ERROR_TYPE_ACTION, a, 719 "No RTE_FLOW_ITEM_TYPE_IPV4 " 720 "found."); 721 722 ipv4 = (const struct rte_flow_action_set_ipv4 *)a->conf; 723 memcpy(fs->nat_lip, &ipv4->ipv4_addr, sizeof(ipv4->ipv4_addr)); 724 *nmode |= 1 << 1; 725 break; 726 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 727 item_index = cxgbe_get_flow_item_index(items, 728 RTE_FLOW_ITEM_TYPE_IPV6); 729 if (item_index < 0) 730 return rte_flow_error_set(e, EINVAL, 731 RTE_FLOW_ERROR_TYPE_ACTION, a, 732 "No RTE_FLOW_ITEM_TYPE_IPV6 " 733 "found."); 734 735 ipv6 = (const struct rte_flow_action_set_ipv6 *)a->conf; 736 memcpy(fs->nat_fip, ipv6->ipv6_addr, sizeof(ipv6->ipv6_addr)); 737 *nmode |= 1 << 0; 738 break; 739 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 740 item_index = cxgbe_get_flow_item_index(items, 741 RTE_FLOW_ITEM_TYPE_IPV6); 742 if (item_index < 0) 743 return rte_flow_error_set(e, EINVAL, 744 RTE_FLOW_ERROR_TYPE_ACTION, a, 745 "No RTE_FLOW_ITEM_TYPE_IPV6 " 746 "found."); 747 748 ipv6 = (const struct rte_flow_action_set_ipv6 *)a->conf; 749 memcpy(fs->nat_lip, ipv6->ipv6_addr, sizeof(ipv6->ipv6_addr)); 750 *nmode |= 1 << 1; 751 break; 752 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 753 item_index = cxgbe_get_flow_item_index(items, 754 RTE_FLOW_ITEM_TYPE_TCP); 755 if (item_index < 0) { 756 item_index = 757 cxgbe_get_flow_item_index(items, 758 RTE_FLOW_ITEM_TYPE_UDP); 759 if (item_index < 0) 760 return rte_flow_error_set(e, EINVAL, 761 RTE_FLOW_ERROR_TYPE_ACTION, a, 762 "No RTE_FLOW_ITEM_TYPE_TCP or " 763 "RTE_FLOW_ITEM_TYPE_UDP found"); 764 } 765 766 tp_port = (const struct rte_flow_action_set_tp *)a->conf; 767 fs->nat_fport = be16_to_cpu(tp_port->port); 768 *nmode |= 1 << 2; 769 break; 770 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 771 item_index = cxgbe_get_flow_item_index(items, 772 RTE_FLOW_ITEM_TYPE_TCP); 773 if (item_index < 0) { 774 item_index = 775 cxgbe_get_flow_item_index(items, 776 RTE_FLOW_ITEM_TYPE_UDP); 777 if (item_index < 0) 778 return rte_flow_error_set(e, EINVAL, 779 RTE_FLOW_ERROR_TYPE_ACTION, a, 780 "No RTE_FLOW_ITEM_TYPE_TCP or " 781 "RTE_FLOW_ITEM_TYPE_UDP found"); 782 } 783 784 tp_port = (const struct rte_flow_action_set_tp *)a->conf; 785 fs->nat_lport = be16_to_cpu(tp_port->port); 786 *nmode |= 1 << 3; 787 break; 788 case RTE_FLOW_ACTION_TYPE_MAC_SWAP: 789 item_index = cxgbe_get_flow_item_index(items, 790 RTE_FLOW_ITEM_TYPE_ETH); 791 if (item_index < 0) 792 return rte_flow_error_set(e, EINVAL, 793 RTE_FLOW_ERROR_TYPE_ACTION, a, 794 "No RTE_FLOW_ITEM_TYPE_ETH " 795 "found"); 796 fs->swapmac = 1; 797 break; 798 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 799 item_index = cxgbe_get_flow_item_index(items, 800 RTE_FLOW_ITEM_TYPE_ETH); 801 if (item_index < 0) 802 return rte_flow_error_set(e, EINVAL, 803 RTE_FLOW_ERROR_TYPE_ACTION, a, 804 "No RTE_FLOW_ITEM_TYPE_ETH " 805 "found"); 806 mac = (const struct rte_flow_action_set_mac *)a->conf; 807 808 fs->newsmac = 1; 809 memcpy(fs->smac, mac->mac_addr, sizeof(fs->smac)); 810 break; 811 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 812 item_index = cxgbe_get_flow_item_index(items, 813 RTE_FLOW_ITEM_TYPE_ETH); 814 if (item_index < 0) 815 return rte_flow_error_set(e, EINVAL, 816 RTE_FLOW_ERROR_TYPE_ACTION, a, 817 "No RTE_FLOW_ITEM_TYPE_ETH found"); 818 mac = (const struct rte_flow_action_set_mac *)a->conf; 819 820 fs->newdmac = 1; 821 memcpy(fs->dmac, mac->mac_addr, sizeof(fs->dmac)); 822 break; 823 default: 824 /* We are not supposed to come here */ 825 return rte_flow_error_set(e, EINVAL, 826 RTE_FLOW_ERROR_TYPE_ACTION, a, 827 "Action not supported"); 828 } 829 830 return 0; 831 } 832 833 static int 834 cxgbe_rtef_parse_actions(struct rte_flow *flow, 835 const struct rte_flow_item items[], 836 const struct rte_flow_action action[], 837 struct rte_flow_error *e) 838 { 839 struct ch_filter_specification *fs = &flow->fs; 840 uint8_t nmode = 0, nat_ipv4 = 0, nat_ipv6 = 0; 841 uint8_t vlan_set_vid = 0, vlan_set_pcp = 0; 842 const struct rte_flow_action_queue *q; 843 const struct rte_flow_action *a; 844 char abit = 0; 845 int ret; 846 847 for (a = action; a->type != RTE_FLOW_ACTION_TYPE_END; a++) { 848 switch (a->type) { 849 case RTE_FLOW_ACTION_TYPE_VOID: 850 continue; 851 case RTE_FLOW_ACTION_TYPE_DROP: 852 if (abit++) 853 return rte_flow_error_set(e, EINVAL, 854 RTE_FLOW_ERROR_TYPE_ACTION, a, 855 "specify only 1 pass/drop"); 856 fs->action = FILTER_DROP; 857 break; 858 case RTE_FLOW_ACTION_TYPE_QUEUE: 859 q = (const struct rte_flow_action_queue *)a->conf; 860 if (!q) 861 return rte_flow_error_set(e, EINVAL, 862 RTE_FLOW_ERROR_TYPE_ACTION, q, 863 "specify rx queue index"); 864 if (check_rxq(flow->dev, q->index)) 865 return rte_flow_error_set(e, EINVAL, 866 RTE_FLOW_ERROR_TYPE_ACTION, q, 867 "Invalid rx queue"); 868 if (abit++) 869 return rte_flow_error_set(e, EINVAL, 870 RTE_FLOW_ERROR_TYPE_ACTION, a, 871 "specify only 1 pass/drop"); 872 fs->action = FILTER_PASS; 873 fs->dirsteer = 1; 874 fs->iq = q->index; 875 break; 876 case RTE_FLOW_ACTION_TYPE_COUNT: 877 fs->hitcnts = 1; 878 break; 879 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 880 vlan_set_vid++; 881 goto action_switch; 882 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 883 vlan_set_pcp++; 884 goto action_switch; 885 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 886 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 887 case RTE_FLOW_ACTION_TYPE_PHY_PORT: 888 case RTE_FLOW_ACTION_TYPE_MAC_SWAP: 889 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 890 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 891 nat_ipv4++; 892 goto action_switch; 893 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 894 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 895 nat_ipv6++; 896 goto action_switch; 897 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 898 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 899 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 900 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 901 action_switch: 902 /* We allow multiple switch actions, but switch is 903 * not compatible with either queue or drop 904 */ 905 if (abit++ && fs->action != FILTER_SWITCH) 906 return rte_flow_error_set(e, EINVAL, 907 RTE_FLOW_ERROR_TYPE_ACTION, a, 908 "overlapping action specified"); 909 if (nat_ipv4 && nat_ipv6) 910 return rte_flow_error_set(e, EINVAL, 911 RTE_FLOW_ERROR_TYPE_ACTION, a, 912 "Can't have one address ipv4 and the" 913 " other ipv6"); 914 915 ret = ch_rte_parse_atype_switch(a, items, &nmode, fs, 916 e); 917 if (ret) 918 return ret; 919 fs->action = FILTER_SWITCH; 920 break; 921 default: 922 /* Not supported action : return error */ 923 return rte_flow_error_set(e, ENOTSUP, 924 RTE_FLOW_ERROR_TYPE_ACTION, 925 a, "Action not supported"); 926 } 927 } 928 929 if (fs->newvlan == VLAN_REWRITE && (!vlan_set_vid || !vlan_set_pcp)) 930 return rte_flow_error_set(e, EINVAL, 931 RTE_FLOW_ERROR_TYPE_ACTION, a, 932 "Both OF_SET_VLAN_VID and " 933 "OF_SET_VLAN_PCP must be specified"); 934 935 if (ch_rte_parse_nat(nmode, fs)) 936 return rte_flow_error_set(e, EINVAL, 937 RTE_FLOW_ERROR_TYPE_ACTION, a, 938 "invalid settings for swich action"); 939 return 0; 940 } 941 942 static struct chrte_fparse parseitem[] = { 943 [RTE_FLOW_ITEM_TYPE_ETH] = { 944 .fptr = ch_rte_parsetype_eth, 945 .dmask = &(const struct rte_flow_item_eth){ 946 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 947 .src.addr_bytes = "\x00\x00\x00\x00\x00\x00", 948 .type = 0xffff, 949 } 950 }, 951 952 [RTE_FLOW_ITEM_TYPE_PHY_PORT] = { 953 .fptr = ch_rte_parsetype_port, 954 .dmask = &(const struct rte_flow_item_phy_port){ 955 .index = 0x7, 956 } 957 }, 958 959 [RTE_FLOW_ITEM_TYPE_VLAN] = { 960 .fptr = ch_rte_parsetype_vlan, 961 .dmask = &(const struct rte_flow_item_vlan){ 962 .tci = 0xffff, 963 .inner_type = 0xffff, 964 } 965 }, 966 967 [RTE_FLOW_ITEM_TYPE_IPV4] = { 968 .fptr = ch_rte_parsetype_ipv4, 969 .dmask = &(const struct rte_flow_item_ipv4) { 970 .hdr = { 971 .src_addr = RTE_BE32(0xffffffff), 972 .dst_addr = RTE_BE32(0xffffffff), 973 .type_of_service = 0xff, 974 }, 975 }, 976 }, 977 978 [RTE_FLOW_ITEM_TYPE_IPV6] = { 979 .fptr = ch_rte_parsetype_ipv6, 980 .dmask = &(const struct rte_flow_item_ipv6) { 981 .hdr = { 982 .src_addr = 983 "\xff\xff\xff\xff\xff\xff\xff\xff" 984 "\xff\xff\xff\xff\xff\xff\xff\xff", 985 .dst_addr = 986 "\xff\xff\xff\xff\xff\xff\xff\xff" 987 "\xff\xff\xff\xff\xff\xff\xff\xff", 988 .vtc_flow = RTE_BE32(0xff000000), 989 }, 990 }, 991 }, 992 993 [RTE_FLOW_ITEM_TYPE_UDP] = { 994 .fptr = ch_rte_parsetype_udp, 995 .dmask = &rte_flow_item_udp_mask, 996 }, 997 998 [RTE_FLOW_ITEM_TYPE_TCP] = { 999 .fptr = ch_rte_parsetype_tcp, 1000 .dmask = &rte_flow_item_tcp_mask, 1001 }, 1002 1003 [RTE_FLOW_ITEM_TYPE_PF] = { 1004 .fptr = ch_rte_parsetype_pf, 1005 .dmask = NULL, 1006 }, 1007 1008 [RTE_FLOW_ITEM_TYPE_VF] = { 1009 .fptr = ch_rte_parsetype_vf, 1010 .dmask = &(const struct rte_flow_item_vf){ 1011 .id = 0xffffffff, 1012 } 1013 }, 1014 }; 1015 1016 static int 1017 cxgbe_rtef_parse_items(struct rte_flow *flow, 1018 const struct rte_flow_item items[], 1019 struct rte_flow_error *e) 1020 { 1021 struct adapter *adap = ethdev2adap(flow->dev); 1022 const struct rte_flow_item *i; 1023 char repeat[ARRAY_SIZE(parseitem)] = {0}; 1024 1025 for (i = items; i->type != RTE_FLOW_ITEM_TYPE_END; i++) { 1026 struct chrte_fparse *idx; 1027 int ret; 1028 1029 if (i->type >= ARRAY_SIZE(parseitem)) 1030 return rte_flow_error_set(e, ENOTSUP, 1031 RTE_FLOW_ERROR_TYPE_ITEM, 1032 i, "Item not supported"); 1033 1034 switch (i->type) { 1035 case RTE_FLOW_ITEM_TYPE_VOID: 1036 continue; 1037 default: 1038 /* check if item is repeated */ 1039 if (repeat[i->type] && 1040 i->type != RTE_FLOW_ITEM_TYPE_VLAN) 1041 return rte_flow_error_set(e, ENOTSUP, 1042 RTE_FLOW_ERROR_TYPE_ITEM, i, 1043 "parse items cannot be repeated(except void/vlan)"); 1044 1045 repeat[i->type] = 1; 1046 1047 /* validate the item */ 1048 ret = cxgbe_validate_item(i, e); 1049 if (ret) 1050 return ret; 1051 1052 idx = &flow->item_parser[i->type]; 1053 if (!idx || !idx->fptr) { 1054 return rte_flow_error_set(e, ENOTSUP, 1055 RTE_FLOW_ERROR_TYPE_ITEM, i, 1056 "Item not supported"); 1057 } else { 1058 ret = idx->fptr(idx->dmask, i, &flow->fs, e); 1059 if (ret) 1060 return ret; 1061 } 1062 } 1063 } 1064 1065 cxgbe_fill_filter_region(adap, &flow->fs); 1066 cxgbe_tweak_filter_spec(adap, &flow->fs); 1067 1068 return 0; 1069 } 1070 1071 static int 1072 cxgbe_flow_parse(struct rte_flow *flow, 1073 const struct rte_flow_attr *attr, 1074 const struct rte_flow_item item[], 1075 const struct rte_flow_action action[], 1076 struct rte_flow_error *e) 1077 { 1078 int ret; 1079 /* parse user request into ch_filter_specification */ 1080 ret = cxgbe_rtef_parse_attr(flow, attr, e); 1081 if (ret) 1082 return ret; 1083 ret = cxgbe_rtef_parse_items(flow, item, e); 1084 if (ret) 1085 return ret; 1086 return cxgbe_rtef_parse_actions(flow, item, action, e); 1087 } 1088 1089 static int __cxgbe_flow_create(struct rte_eth_dev *dev, struct rte_flow *flow) 1090 { 1091 struct ch_filter_specification *fs = &flow->fs; 1092 struct adapter *adap = ethdev2adap(dev); 1093 struct tid_info *t = &adap->tids; 1094 struct filter_ctx ctx; 1095 unsigned int fidx; 1096 int err; 1097 1098 if (cxgbe_get_fidx(flow, &fidx)) 1099 return -ENOMEM; 1100 if (cxgbe_verify_fidx(flow, fidx, 0)) 1101 return -1; 1102 1103 t4_init_completion(&ctx.completion); 1104 /* go create the filter */ 1105 err = cxgbe_set_filter(dev, fidx, fs, &ctx); 1106 if (err) { 1107 dev_err(adap, "Error %d while creating filter.\n", err); 1108 return err; 1109 } 1110 1111 /* Poll the FW for reply */ 1112 err = cxgbe_poll_for_completion(&adap->sge.fw_evtq, 1113 CXGBE_FLOW_POLL_MS, 1114 CXGBE_FLOW_POLL_CNT, 1115 &ctx.completion); 1116 if (err) { 1117 dev_err(adap, "Filter set operation timed out (%d)\n", err); 1118 return err; 1119 } 1120 if (ctx.result) { 1121 dev_err(adap, "Hardware error %d while creating the filter.\n", 1122 ctx.result); 1123 return ctx.result; 1124 } 1125 1126 if (fs->cap) { /* to destroy the filter */ 1127 flow->fidx = ctx.tid; 1128 flow->f = lookup_tid(t, ctx.tid); 1129 } else { 1130 flow->fidx = fidx; 1131 flow->f = &adap->tids.ftid_tab[fidx]; 1132 } 1133 1134 return 0; 1135 } 1136 1137 static struct rte_flow * 1138 cxgbe_flow_create(struct rte_eth_dev *dev, 1139 const struct rte_flow_attr *attr, 1140 const struct rte_flow_item item[], 1141 const struct rte_flow_action action[], 1142 struct rte_flow_error *e) 1143 { 1144 struct adapter *adap = ethdev2adap(dev); 1145 struct rte_flow *flow; 1146 int ret; 1147 1148 flow = t4_os_alloc(sizeof(struct rte_flow)); 1149 if (!flow) { 1150 rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 1151 NULL, "Unable to allocate memory for" 1152 " filter_entry"); 1153 return NULL; 1154 } 1155 1156 flow->item_parser = parseitem; 1157 flow->dev = dev; 1158 flow->fs.private = (void *)flow; 1159 1160 if (cxgbe_flow_parse(flow, attr, item, action, e)) { 1161 t4_os_free(flow); 1162 return NULL; 1163 } 1164 1165 t4_os_lock(&adap->flow_lock); 1166 /* go, interact with cxgbe_filter */ 1167 ret = __cxgbe_flow_create(dev, flow); 1168 t4_os_unlock(&adap->flow_lock); 1169 if (ret) { 1170 rte_flow_error_set(e, ret, RTE_FLOW_ERROR_TYPE_HANDLE, 1171 NULL, "Unable to create flow rule"); 1172 t4_os_free(flow); 1173 return NULL; 1174 } 1175 1176 flow->f->private = flow; /* Will be used during flush */ 1177 1178 return flow; 1179 } 1180 1181 static int __cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 1182 { 1183 struct adapter *adap = ethdev2adap(dev); 1184 struct filter_entry *f = flow->f; 1185 struct ch_filter_specification *fs; 1186 struct filter_ctx ctx; 1187 int err; 1188 1189 fs = &f->fs; 1190 if (cxgbe_verify_fidx(flow, flow->fidx, 1)) 1191 return -1; 1192 1193 t4_init_completion(&ctx.completion); 1194 err = cxgbe_del_filter(dev, flow->fidx, fs, &ctx); 1195 if (err) { 1196 dev_err(adap, "Error %d while deleting filter.\n", err); 1197 return err; 1198 } 1199 1200 /* Poll the FW for reply */ 1201 err = cxgbe_poll_for_completion(&adap->sge.fw_evtq, 1202 CXGBE_FLOW_POLL_MS, 1203 CXGBE_FLOW_POLL_CNT, 1204 &ctx.completion); 1205 if (err) { 1206 dev_err(adap, "Filter delete operation timed out (%d)\n", err); 1207 return err; 1208 } 1209 if (ctx.result) { 1210 dev_err(adap, "Hardware error %d while deleting the filter.\n", 1211 ctx.result); 1212 return ctx.result; 1213 } 1214 1215 fs = &flow->fs; 1216 if (fs->mask.macidx) { 1217 struct port_info *pi = (struct port_info *) 1218 (dev->data->dev_private); 1219 int ret; 1220 1221 ret = cxgbe_mpstcam_remove(pi, fs->val.macidx); 1222 if (!ret) 1223 return ret; 1224 } 1225 1226 return 0; 1227 } 1228 1229 static int 1230 cxgbe_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1231 struct rte_flow_error *e) 1232 { 1233 struct adapter *adap = ethdev2adap(dev); 1234 int ret; 1235 1236 t4_os_lock(&adap->flow_lock); 1237 ret = __cxgbe_flow_destroy(dev, flow); 1238 t4_os_unlock(&adap->flow_lock); 1239 if (ret) 1240 return rte_flow_error_set(e, ret, RTE_FLOW_ERROR_TYPE_HANDLE, 1241 flow, "error destroying filter."); 1242 t4_os_free(flow); 1243 return 0; 1244 } 1245 1246 static int __cxgbe_flow_query(struct rte_flow *flow, u64 *count, 1247 u64 *byte_count) 1248 { 1249 struct adapter *adap = ethdev2adap(flow->dev); 1250 struct ch_filter_specification fs = flow->f->fs; 1251 unsigned int fidx = flow->fidx; 1252 int ret = 0; 1253 1254 ret = cxgbe_get_filter_count(adap, fidx, count, fs.cap, 0); 1255 if (ret) 1256 return ret; 1257 return cxgbe_get_filter_count(adap, fidx, byte_count, fs.cap, 1); 1258 } 1259 1260 static int 1261 cxgbe_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1262 const struct rte_flow_action *action, void *data, 1263 struct rte_flow_error *e) 1264 { 1265 struct adapter *adap = ethdev2adap(flow->dev); 1266 struct ch_filter_specification fs; 1267 struct rte_flow_query_count *c; 1268 struct filter_entry *f; 1269 int ret; 1270 1271 RTE_SET_USED(dev); 1272 1273 f = flow->f; 1274 fs = f->fs; 1275 1276 if (action->type != RTE_FLOW_ACTION_TYPE_COUNT) 1277 return rte_flow_error_set(e, ENOTSUP, 1278 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1279 "only count supported for query"); 1280 1281 /* 1282 * This is a valid operation, Since we are allowed to do chelsio 1283 * specific operations in rte side of our code but not vise-versa 1284 * 1285 * So, fs can be queried/modified here BUT rte_flow_query_count 1286 * cannot be worked on by the lower layer since we want to maintain 1287 * it as rte_flow agnostic. 1288 */ 1289 if (!fs.hitcnts) 1290 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 1291 &fs, "filter hit counters were not" 1292 " enabled during filter creation"); 1293 1294 c = (struct rte_flow_query_count *)data; 1295 1296 t4_os_lock(&adap->flow_lock); 1297 ret = __cxgbe_flow_query(flow, &c->hits, &c->bytes); 1298 if (ret) { 1299 rte_flow_error_set(e, -ret, RTE_FLOW_ERROR_TYPE_ACTION, 1300 f, "cxgbe pmd failed to perform query"); 1301 goto out; 1302 } 1303 1304 /* Query was successful */ 1305 c->bytes_set = 1; 1306 c->hits_set = 1; 1307 if (c->reset) 1308 cxgbe_clear_filter_count(adap, flow->fidx, f->fs.cap, true); 1309 1310 out: 1311 t4_os_unlock(&adap->flow_lock); 1312 return ret; 1313 } 1314 1315 static int 1316 cxgbe_flow_validate(struct rte_eth_dev *dev, 1317 const struct rte_flow_attr *attr, 1318 const struct rte_flow_item item[], 1319 const struct rte_flow_action action[], 1320 struct rte_flow_error *e) 1321 { 1322 struct adapter *adap = ethdev2adap(dev); 1323 struct rte_flow *flow; 1324 unsigned int fidx; 1325 int ret = 0; 1326 1327 flow = t4_os_alloc(sizeof(struct rte_flow)); 1328 if (!flow) 1329 return rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 1330 NULL, 1331 "Unable to allocate memory for filter_entry"); 1332 1333 flow->item_parser = parseitem; 1334 flow->dev = dev; 1335 1336 ret = cxgbe_flow_parse(flow, attr, item, action, e); 1337 if (ret) { 1338 t4_os_free(flow); 1339 return ret; 1340 } 1341 1342 if (cxgbe_validate_filter(adap, &flow->fs)) { 1343 t4_os_free(flow); 1344 return rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, 1345 NULL, 1346 "validation failed. Check f/w config file."); 1347 } 1348 1349 t4_os_lock(&adap->flow_lock); 1350 if (cxgbe_get_fidx(flow, &fidx)) { 1351 ret = rte_flow_error_set(e, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 1352 NULL, "no memory in tcam."); 1353 goto out; 1354 } 1355 1356 if (cxgbe_verify_fidx(flow, fidx, 0)) { 1357 ret = rte_flow_error_set(e, EINVAL, RTE_FLOW_ERROR_TYPE_HANDLE, 1358 NULL, "validation failed"); 1359 goto out; 1360 } 1361 1362 out: 1363 t4_os_unlock(&adap->flow_lock); 1364 t4_os_free(flow); 1365 return ret; 1366 } 1367 1368 /* 1369 * @ret : > 0 filter destroyed succsesfully 1370 * < 0 error destroying filter 1371 * == 1 filter not active / not found 1372 */ 1373 static int 1374 cxgbe_check_n_destroy(struct filter_entry *f, struct rte_eth_dev *dev) 1375 { 1376 if (f && (f->valid || f->pending) && 1377 f->dev == dev && /* Only if user has asked for this port */ 1378 f->private) /* We (rte_flow) created this filter */ 1379 return __cxgbe_flow_destroy(dev, (struct rte_flow *)f->private); 1380 return 1; 1381 } 1382 1383 static int cxgbe_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *e) 1384 { 1385 struct adapter *adap = ethdev2adap(dev); 1386 unsigned int i; 1387 int ret = 0; 1388 1389 t4_os_lock(&adap->flow_lock); 1390 if (adap->tids.ftid_tab) { 1391 struct filter_entry *f = &adap->tids.ftid_tab[0]; 1392 1393 for (i = 0; i < adap->tids.nftids; i++, f++) { 1394 ret = cxgbe_check_n_destroy(f, dev); 1395 if (ret < 0) { 1396 rte_flow_error_set(e, ret, 1397 RTE_FLOW_ERROR_TYPE_HANDLE, 1398 f->private, 1399 "error destroying TCAM " 1400 "filter."); 1401 goto out; 1402 } 1403 } 1404 } 1405 1406 if (is_hashfilter(adap) && adap->tids.tid_tab) { 1407 struct filter_entry *f; 1408 1409 for (i = adap->tids.hash_base; i <= adap->tids.ntids; i++) { 1410 f = (struct filter_entry *)adap->tids.tid_tab[i]; 1411 1412 ret = cxgbe_check_n_destroy(f, dev); 1413 if (ret < 0) { 1414 rte_flow_error_set(e, ret, 1415 RTE_FLOW_ERROR_TYPE_HANDLE, 1416 f->private, 1417 "error destroying HASH " 1418 "filter."); 1419 goto out; 1420 } 1421 } 1422 } 1423 1424 out: 1425 t4_os_unlock(&adap->flow_lock); 1426 return ret >= 0 ? 0 : ret; 1427 } 1428 1429 static const struct rte_flow_ops cxgbe_flow_ops = { 1430 .validate = cxgbe_flow_validate, 1431 .create = cxgbe_flow_create, 1432 .destroy = cxgbe_flow_destroy, 1433 .flush = cxgbe_flow_flush, 1434 .query = cxgbe_flow_query, 1435 .isolate = NULL, 1436 }; 1437 1438 int 1439 cxgbe_dev_filter_ctrl(struct rte_eth_dev *dev, 1440 enum rte_filter_type filter_type, 1441 enum rte_filter_op filter_op, 1442 void *arg) 1443 { 1444 int ret = 0; 1445 1446 RTE_SET_USED(dev); 1447 switch (filter_type) { 1448 case RTE_ETH_FILTER_GENERIC: 1449 if (filter_op != RTE_ETH_FILTER_GET) 1450 return -EINVAL; 1451 *(const void **)arg = &cxgbe_flow_ops; 1452 break; 1453 default: 1454 ret = -ENOTSUP; 1455 break; 1456 } 1457 return ret; 1458 } 1459