1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "t4_pci_id_tbl.h" 60 61 #define CXGBE_TX_OFFLOADS (DEV_TX_OFFLOAD_VLAN_INSERT |\ 62 DEV_TX_OFFLOAD_IPV4_CKSUM |\ 63 DEV_TX_OFFLOAD_UDP_CKSUM |\ 64 DEV_TX_OFFLOAD_TCP_CKSUM |\ 65 DEV_TX_OFFLOAD_TCP_TSO) 66 67 #define CXGBE_RX_OFFLOADS (DEV_RX_OFFLOAD_VLAN_STRIP |\ 68 DEV_RX_OFFLOAD_CRC_STRIP |\ 69 DEV_RX_OFFLOAD_IPV4_CKSUM |\ 70 DEV_RX_OFFLOAD_JUMBO_FRAME |\ 71 DEV_RX_OFFLOAD_UDP_CKSUM |\ 72 DEV_RX_OFFLOAD_TCP_CKSUM) 73 74 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 75 uint16_t nb_pkts) 76 { 77 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 78 uint16_t pkts_sent, pkts_remain; 79 uint16_t total_sent = 0; 80 int ret = 0; 81 82 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 83 __func__, txq, tx_pkts, nb_pkts); 84 85 t4_os_lock(&txq->txq_lock); 86 /* free up desc from already completed tx */ 87 reclaim_completed_tx(&txq->q); 88 while (total_sent < nb_pkts) { 89 pkts_remain = nb_pkts - total_sent; 90 91 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 92 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent], 93 nb_pkts); 94 if (ret < 0) 95 break; 96 } 97 if (!pkts_sent) 98 break; 99 total_sent += pkts_sent; 100 /* reclaim as much as possible */ 101 reclaim_completed_tx(&txq->q); 102 } 103 104 t4_os_unlock(&txq->txq_lock); 105 return total_sent; 106 } 107 108 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 109 uint16_t nb_pkts) 110 { 111 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 112 unsigned int work_done; 113 114 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 115 __func__, rxq->rspq.cntxt_id, nb_pkts); 116 117 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 118 dev_err(adapter, "error in cxgbe poll\n"); 119 120 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 121 return work_done; 122 } 123 124 void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 125 struct rte_eth_dev_info *device_info) 126 { 127 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 128 struct adapter *adapter = pi->adapter; 129 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 130 131 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 132 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 133 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 134 .nb_align = 1, 135 }; 136 137 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 138 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 139 device_info->max_rx_queues = max_queues; 140 device_info->max_tx_queues = max_queues; 141 device_info->max_mac_addrs = 1; 142 /* XXX: For now we support one MAC/port */ 143 device_info->max_vfs = adapter->params.arch.vfcount; 144 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 145 146 device_info->rx_queue_offload_capa = 0UL; 147 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 148 149 device_info->tx_queue_offload_capa = 0UL; 150 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 151 152 device_info->reta_size = pi->rss_size; 153 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 154 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 155 156 device_info->rx_desc_lim = cxgbe_desc_lim; 157 device_info->tx_desc_lim = cxgbe_desc_lim; 158 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 159 } 160 161 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 162 { 163 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 164 struct adapter *adapter = pi->adapter; 165 166 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 167 1, -1, 1, -1, false); 168 } 169 170 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 171 { 172 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 173 struct adapter *adapter = pi->adapter; 174 175 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 176 0, -1, 1, -1, false); 177 } 178 179 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 180 { 181 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 182 struct adapter *adapter = pi->adapter; 183 184 /* TODO: address filters ?? */ 185 186 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 187 -1, 1, 1, -1, false); 188 } 189 190 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 191 { 192 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 193 struct adapter *adapter = pi->adapter; 194 195 /* TODO: address filters ?? */ 196 197 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 198 -1, 0, 1, -1, false); 199 } 200 201 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 202 __rte_unused int wait_to_complete) 203 { 204 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 205 struct adapter *adapter = pi->adapter; 206 struct sge *s = &adapter->sge; 207 struct rte_eth_link new_link; 208 unsigned int work_done, budget = 4; 209 210 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 211 212 new_link.link_status = force_linkup(adapter) ? 213 ETH_LINK_UP : pi->link_cfg.link_ok; 214 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 215 new_link.link_speed = pi->link_cfg.speed; 216 217 return rte_eth_linkstatus_set(eth_dev, &new_link); 218 } 219 220 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 221 { 222 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 223 struct adapter *adapter = pi->adapter; 224 struct rte_eth_dev_info dev_info; 225 int err; 226 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 227 228 cxgbe_dev_info_get(eth_dev, &dev_info); 229 230 /* Must accommodate at least ETHER_MIN_MTU */ 231 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen)) 232 return -EINVAL; 233 234 /* set to jumbo mode if needed */ 235 if (new_mtu > ETHER_MAX_LEN) 236 eth_dev->data->dev_conf.rxmode.offloads |= 237 DEV_RX_OFFLOAD_JUMBO_FRAME; 238 else 239 eth_dev->data->dev_conf.rxmode.offloads &= 240 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 241 242 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 243 -1, -1, true); 244 if (!err) 245 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 246 247 return err; 248 } 249 250 /* 251 * Stop device. 252 */ 253 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 254 { 255 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 256 struct adapter *adapter = pi->adapter; 257 258 CXGBE_FUNC_TRACE(); 259 260 if (!(adapter->flags & FULL_INIT_DONE)) 261 return; 262 263 cxgbe_down(pi); 264 265 /* 266 * We clear queues only if both tx and rx path of the port 267 * have been disabled 268 */ 269 t4_sge_eth_clear_queues(pi); 270 } 271 272 /* Start the device. 273 * It returns 0 on success. 274 */ 275 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 276 { 277 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 278 struct adapter *adapter = pi->adapter; 279 int err = 0, i; 280 281 CXGBE_FUNC_TRACE(); 282 283 /* 284 * If we don't have a connection to the firmware there's nothing we 285 * can do. 286 */ 287 if (!(adapter->flags & FW_OK)) { 288 err = -ENXIO; 289 goto out; 290 } 291 292 if (!(adapter->flags & FULL_INIT_DONE)) { 293 err = cxgbe_up(adapter); 294 if (err < 0) 295 goto out; 296 } 297 298 cxgbe_enable_rx_queues(pi); 299 300 err = setup_rss(pi); 301 if (err) 302 goto out; 303 304 for (i = 0; i < pi->n_tx_qsets; i++) { 305 err = cxgbe_dev_tx_queue_start(eth_dev, i); 306 if (err) 307 goto out; 308 } 309 310 for (i = 0; i < pi->n_rx_qsets; i++) { 311 err = cxgbe_dev_rx_queue_start(eth_dev, i); 312 if (err) 313 goto out; 314 } 315 316 err = link_start(pi); 317 if (err) 318 goto out; 319 320 out: 321 return err; 322 } 323 324 /* 325 * Stop device: disable rx and tx functions to allow for reconfiguring. 326 */ 327 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 328 { 329 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 330 struct adapter *adapter = pi->adapter; 331 332 CXGBE_FUNC_TRACE(); 333 334 if (!(adapter->flags & FULL_INIT_DONE)) 335 return; 336 337 cxgbe_down(pi); 338 339 /* 340 * We clear queues only if both tx and rx path of the port 341 * have been disabled 342 */ 343 t4_sge_eth_clear_queues(pi); 344 } 345 346 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 347 { 348 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 349 struct adapter *adapter = pi->adapter; 350 uint64_t configured_offloads; 351 int err; 352 353 CXGBE_FUNC_TRACE(); 354 configured_offloads = eth_dev->data->dev_conf.rxmode.offloads; 355 if (!(configured_offloads & DEV_RX_OFFLOAD_CRC_STRIP)) { 356 dev_info(adapter, "can't disable hw crc strip\n"); 357 eth_dev->data->dev_conf.rxmode.offloads |= 358 DEV_RX_OFFLOAD_CRC_STRIP; 359 } 360 361 if (!(adapter->flags & FW_QUEUE_BOUND)) { 362 err = setup_sge_fwevtq(adapter); 363 if (err) 364 return err; 365 adapter->flags |= FW_QUEUE_BOUND; 366 } 367 368 err = cfg_queue_count(eth_dev); 369 if (err) 370 return err; 371 372 return 0; 373 } 374 375 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 376 { 377 int ret; 378 struct sge_eth_txq *txq = (struct sge_eth_txq *) 379 (eth_dev->data->tx_queues[tx_queue_id]); 380 381 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 382 383 ret = t4_sge_eth_txq_start(txq); 384 if (ret == 0) 385 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 386 387 return ret; 388 } 389 390 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 391 { 392 int ret; 393 struct sge_eth_txq *txq = (struct sge_eth_txq *) 394 (eth_dev->data->tx_queues[tx_queue_id]); 395 396 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 397 398 ret = t4_sge_eth_txq_stop(txq); 399 if (ret == 0) 400 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 401 402 return ret; 403 } 404 405 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 406 uint16_t queue_idx, uint16_t nb_desc, 407 unsigned int socket_id, 408 const struct rte_eth_txconf *tx_conf __rte_unused) 409 { 410 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 411 struct adapter *adapter = pi->adapter; 412 struct sge *s = &adapter->sge; 413 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 414 int err = 0; 415 unsigned int temp_nb_desc; 416 417 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 418 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 419 socket_id, pi->first_qset); 420 421 /* Free up the existing queue */ 422 if (eth_dev->data->tx_queues[queue_idx]) { 423 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 424 eth_dev->data->tx_queues[queue_idx] = NULL; 425 } 426 427 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 428 429 /* Sanity Checking 430 * 431 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 432 */ 433 temp_nb_desc = nb_desc; 434 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 435 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 436 __func__, CXGBE_MIN_RING_DESC_SIZE, 437 CXGBE_DEFAULT_TX_DESC_SIZE); 438 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 439 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 440 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 441 __func__, CXGBE_MIN_RING_DESC_SIZE, 442 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 443 return -(EINVAL); 444 } 445 446 txq->q.size = temp_nb_desc; 447 448 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 449 s->fw_evtq.cntxt_id, socket_id); 450 451 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 452 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 453 return err; 454 } 455 456 void cxgbe_dev_tx_queue_release(void *q) 457 { 458 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 459 460 if (txq) { 461 struct port_info *pi = (struct port_info *) 462 (txq->eth_dev->data->dev_private); 463 struct adapter *adap = pi->adapter; 464 465 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 466 __func__, pi->port_id, txq->q.cntxt_id); 467 468 t4_sge_eth_txq_release(adap, txq); 469 } 470 } 471 472 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 473 { 474 int ret; 475 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 476 struct adapter *adap = pi->adapter; 477 struct sge_rspq *q; 478 479 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 480 __func__, pi->port_id, rx_queue_id); 481 482 q = eth_dev->data->rx_queues[rx_queue_id]; 483 484 ret = t4_sge_eth_rxq_start(adap, q); 485 if (ret == 0) 486 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 487 488 return ret; 489 } 490 491 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 492 { 493 int ret; 494 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 495 struct adapter *adap = pi->adapter; 496 struct sge_rspq *q; 497 498 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 499 __func__, pi->port_id, rx_queue_id); 500 501 q = eth_dev->data->rx_queues[rx_queue_id]; 502 ret = t4_sge_eth_rxq_stop(adap, q); 503 if (ret == 0) 504 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 505 506 return ret; 507 } 508 509 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 510 uint16_t queue_idx, uint16_t nb_desc, 511 unsigned int socket_id, 512 const struct rte_eth_rxconf *rx_conf __rte_unused, 513 struct rte_mempool *mp) 514 { 515 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 516 struct adapter *adapter = pi->adapter; 517 struct sge *s = &adapter->sge; 518 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 519 int err = 0; 520 int msi_idx = 0; 521 unsigned int temp_nb_desc; 522 struct rte_eth_dev_info dev_info; 523 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 524 525 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 526 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 527 socket_id, mp); 528 529 cxgbe_dev_info_get(eth_dev, &dev_info); 530 531 /* Must accommodate at least ETHER_MIN_MTU */ 532 if ((pkt_len < dev_info.min_rx_bufsize) || 533 (pkt_len > dev_info.max_rx_pktlen)) { 534 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 535 __func__, dev_info.min_rx_bufsize, 536 dev_info.max_rx_pktlen); 537 return -EINVAL; 538 } 539 540 /* Free up the existing queue */ 541 if (eth_dev->data->rx_queues[queue_idx]) { 542 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 543 eth_dev->data->rx_queues[queue_idx] = NULL; 544 } 545 546 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 547 548 /* Sanity Checking 549 * 550 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 551 */ 552 temp_nb_desc = nb_desc; 553 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 554 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 555 __func__, CXGBE_MIN_RING_DESC_SIZE, 556 CXGBE_DEFAULT_RX_DESC_SIZE); 557 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 558 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 559 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 560 __func__, CXGBE_MIN_RING_DESC_SIZE, 561 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 562 return -(EINVAL); 563 } 564 565 rxq->rspq.size = temp_nb_desc; 566 if ((&rxq->fl) != NULL) 567 rxq->fl.size = temp_nb_desc; 568 569 /* Set to jumbo mode if necessary */ 570 if (pkt_len > ETHER_MAX_LEN) 571 eth_dev->data->dev_conf.rxmode.offloads |= 572 DEV_RX_OFFLOAD_JUMBO_FRAME; 573 else 574 eth_dev->data->dev_conf.rxmode.offloads &= 575 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 576 577 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 578 &rxq->fl, t4_ethrx_handler, 579 is_pf4(adapter) ? 580 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 581 queue_idx, socket_id); 582 583 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 584 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 585 rxq->rspq.abs_id); 586 return err; 587 } 588 589 void cxgbe_dev_rx_queue_release(void *q) 590 { 591 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 592 struct sge_rspq *rq = &rxq->rspq; 593 594 if (rq) { 595 struct port_info *pi = (struct port_info *) 596 (rq->eth_dev->data->dev_private); 597 struct adapter *adap = pi->adapter; 598 599 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 600 __func__, pi->port_id, rxq->rspq.cntxt_id); 601 602 t4_sge_eth_rxq_release(adap, rxq); 603 } 604 } 605 606 /* 607 * Get port statistics. 608 */ 609 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 610 struct rte_eth_stats *eth_stats) 611 { 612 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 613 struct adapter *adapter = pi->adapter; 614 struct sge *s = &adapter->sge; 615 struct port_stats ps; 616 unsigned int i; 617 618 cxgbe_stats_get(pi, &ps); 619 620 /* RX Stats */ 621 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 622 ps.rx_ovflow2 + ps.rx_ovflow3 + 623 ps.rx_trunc0 + ps.rx_trunc1 + 624 ps.rx_trunc2 + ps.rx_trunc3; 625 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 626 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 627 ps.rx_len_err; 628 629 /* TX Stats */ 630 eth_stats->opackets = ps.tx_frames; 631 eth_stats->obytes = ps.tx_octets; 632 eth_stats->oerrors = ps.tx_error_frames; 633 634 for (i = 0; i < pi->n_rx_qsets; i++) { 635 struct sge_eth_rxq *rxq = 636 &s->ethrxq[pi->first_qset + i]; 637 638 eth_stats->q_ipackets[i] = rxq->stats.pkts; 639 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 640 eth_stats->ipackets += eth_stats->q_ipackets[i]; 641 eth_stats->ibytes += eth_stats->q_ibytes[i]; 642 } 643 644 for (i = 0; i < pi->n_tx_qsets; i++) { 645 struct sge_eth_txq *txq = 646 &s->ethtxq[pi->first_qset + i]; 647 648 eth_stats->q_opackets[i] = txq->stats.pkts; 649 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 650 eth_stats->q_errors[i] = txq->stats.mapping_err; 651 } 652 return 0; 653 } 654 655 /* 656 * Reset port statistics. 657 */ 658 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 659 { 660 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 661 struct adapter *adapter = pi->adapter; 662 struct sge *s = &adapter->sge; 663 unsigned int i; 664 665 cxgbe_stats_reset(pi); 666 for (i = 0; i < pi->n_rx_qsets; i++) { 667 struct sge_eth_rxq *rxq = 668 &s->ethrxq[pi->first_qset + i]; 669 670 rxq->stats.pkts = 0; 671 rxq->stats.rx_bytes = 0; 672 } 673 for (i = 0; i < pi->n_tx_qsets; i++) { 674 struct sge_eth_txq *txq = 675 &s->ethtxq[pi->first_qset + i]; 676 677 txq->stats.pkts = 0; 678 txq->stats.tx_bytes = 0; 679 txq->stats.mapping_err = 0; 680 } 681 } 682 683 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 684 struct rte_eth_fc_conf *fc_conf) 685 { 686 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 687 struct link_config *lc = &pi->link_cfg; 688 int rx_pause, tx_pause; 689 690 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 691 rx_pause = lc->fc & PAUSE_RX; 692 tx_pause = lc->fc & PAUSE_TX; 693 694 if (rx_pause && tx_pause) 695 fc_conf->mode = RTE_FC_FULL; 696 else if (rx_pause) 697 fc_conf->mode = RTE_FC_RX_PAUSE; 698 else if (tx_pause) 699 fc_conf->mode = RTE_FC_TX_PAUSE; 700 else 701 fc_conf->mode = RTE_FC_NONE; 702 return 0; 703 } 704 705 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 706 struct rte_eth_fc_conf *fc_conf) 707 { 708 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 709 struct adapter *adapter = pi->adapter; 710 struct link_config *lc = &pi->link_cfg; 711 712 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 713 if (fc_conf->autoneg) 714 lc->requested_fc |= PAUSE_AUTONEG; 715 else 716 lc->requested_fc &= ~PAUSE_AUTONEG; 717 } 718 719 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 720 (fc_conf->mode & RTE_FC_RX_PAUSE)) 721 lc->requested_fc |= PAUSE_RX; 722 else 723 lc->requested_fc &= ~PAUSE_RX; 724 725 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 726 (fc_conf->mode & RTE_FC_TX_PAUSE)) 727 lc->requested_fc |= PAUSE_TX; 728 else 729 lc->requested_fc &= ~PAUSE_TX; 730 731 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 732 &pi->link_cfg); 733 } 734 735 const uint32_t * 736 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 737 { 738 static const uint32_t ptypes[] = { 739 RTE_PTYPE_L3_IPV4, 740 RTE_PTYPE_L3_IPV6, 741 RTE_PTYPE_UNKNOWN 742 }; 743 744 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 745 return ptypes; 746 return NULL; 747 } 748 749 /* Update RSS hash configuration 750 */ 751 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 752 struct rte_eth_rss_conf *rss_conf) 753 { 754 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 755 struct adapter *adapter = pi->adapter; 756 int err; 757 758 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 759 if (err) 760 return err; 761 762 pi->rss_hf = rss_conf->rss_hf; 763 764 if (rss_conf->rss_key) { 765 u32 key[10], mod_key[10]; 766 int i, j; 767 768 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 769 770 for (i = 9, j = 0; i >= 0; i--, j++) 771 mod_key[j] = cpu_to_be32(key[i]); 772 773 t4_write_rss_key(adapter, mod_key, -1); 774 } 775 776 return 0; 777 } 778 779 /* Get RSS hash configuration 780 */ 781 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 782 struct rte_eth_rss_conf *rss_conf) 783 { 784 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 785 struct adapter *adapter = pi->adapter; 786 u64 rss_hf = 0; 787 u64 flags = 0; 788 int err; 789 790 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 791 &flags, NULL); 792 793 if (err) 794 return err; 795 796 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 797 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 798 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 799 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 800 } 801 802 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 803 rss_hf |= ETH_RSS_IPV6; 804 805 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 806 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 807 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 808 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 809 } 810 811 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 812 rss_hf |= ETH_RSS_IPV4; 813 814 rss_conf->rss_hf = rss_hf; 815 816 if (rss_conf->rss_key) { 817 u32 key[10], mod_key[10]; 818 int i, j; 819 820 t4_read_rss_key(adapter, key); 821 822 for (i = 9, j = 0; i >= 0; i--, j++) 823 mod_key[j] = be32_to_cpu(key[i]); 824 825 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 826 } 827 828 return 0; 829 } 830 831 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 832 { 833 RTE_SET_USED(dev); 834 return EEPROMSIZE; 835 } 836 837 /** 838 * eeprom_ptov - translate a physical EEPROM address to virtual 839 * @phys_addr: the physical EEPROM address 840 * @fn: the PCI function number 841 * @sz: size of function-specific area 842 * 843 * Translate a physical EEPROM address to virtual. The first 1K is 844 * accessed through virtual addresses starting at 31K, the rest is 845 * accessed through virtual addresses starting at 0. 846 * 847 * The mapping is as follows: 848 * [0..1K) -> [31K..32K) 849 * [1K..1K+A) -> [31K-A..31K) 850 * [1K+A..ES) -> [0..ES-A-1K) 851 * 852 * where A = @fn * @sz, and ES = EEPROM size. 853 */ 854 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 855 { 856 fn *= sz; 857 if (phys_addr < 1024) 858 return phys_addr + (31 << 10); 859 if (phys_addr < 1024 + fn) 860 return fn + phys_addr - 1024; 861 if (phys_addr < EEPROMSIZE) 862 return phys_addr - 1024 - fn; 863 if (phys_addr < EEPROMVSIZE) 864 return phys_addr - 1024; 865 return -EINVAL; 866 } 867 868 /* The next two routines implement eeprom read/write from physical addresses. 869 */ 870 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 871 { 872 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 873 874 if (vaddr >= 0) 875 vaddr = t4_seeprom_read(adap, vaddr, v); 876 return vaddr < 0 ? vaddr : 0; 877 } 878 879 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 880 { 881 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 882 883 if (vaddr >= 0) 884 vaddr = t4_seeprom_write(adap, vaddr, v); 885 return vaddr < 0 ? vaddr : 0; 886 } 887 888 #define EEPROM_MAGIC 0x38E2F10C 889 890 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 891 struct rte_dev_eeprom_info *e) 892 { 893 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 894 struct adapter *adapter = pi->adapter; 895 u32 i, err = 0; 896 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 897 898 if (!buf) 899 return -ENOMEM; 900 901 e->magic = EEPROM_MAGIC; 902 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 903 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 904 905 if (!err) 906 rte_memcpy(e->data, buf + e->offset, e->length); 907 rte_free(buf); 908 return err; 909 } 910 911 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 912 struct rte_dev_eeprom_info *eeprom) 913 { 914 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 915 struct adapter *adapter = pi->adapter; 916 u8 *buf; 917 int err = 0; 918 u32 aligned_offset, aligned_len, *p; 919 920 if (eeprom->magic != EEPROM_MAGIC) 921 return -EINVAL; 922 923 aligned_offset = eeprom->offset & ~3; 924 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 925 926 if (adapter->pf > 0) { 927 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 928 929 if (aligned_offset < start || 930 aligned_offset + aligned_len > start + EEPROMPFSIZE) 931 return -EPERM; 932 } 933 934 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 935 /* RMW possibly needed for first or last words. 936 */ 937 buf = rte_zmalloc(NULL, aligned_len, 0); 938 if (!buf) 939 return -ENOMEM; 940 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 941 if (!err && aligned_len > 4) 942 err = eeprom_rd_phys(adapter, 943 aligned_offset + aligned_len - 4, 944 (u32 *)&buf[aligned_len - 4]); 945 if (err) 946 goto out; 947 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 948 eeprom->length); 949 } else { 950 buf = eeprom->data; 951 } 952 953 err = t4_seeprom_wp(adapter, false); 954 if (err) 955 goto out; 956 957 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 958 err = eeprom_wr_phys(adapter, aligned_offset, *p); 959 aligned_offset += 4; 960 } 961 962 if (!err) 963 err = t4_seeprom_wp(adapter, true); 964 out: 965 if (buf != eeprom->data) 966 rte_free(buf); 967 return err; 968 } 969 970 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 971 { 972 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 973 struct adapter *adapter = pi->adapter; 974 975 return t4_get_regs_len(adapter) / sizeof(uint32_t); 976 } 977 978 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 979 struct rte_dev_reg_info *regs) 980 { 981 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 982 struct adapter *adapter = pi->adapter; 983 984 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 985 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 986 (1 << 16); 987 988 if (regs->data == NULL) { 989 regs->length = cxgbe_get_regs_len(eth_dev); 990 regs->width = sizeof(uint32_t); 991 992 return 0; 993 } 994 995 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 996 997 return 0; 998 } 999 1000 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *addr) 1001 { 1002 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 1003 struct adapter *adapter = pi->adapter; 1004 int ret; 1005 1006 ret = t4_change_mac(adapter, adapter->mbox, pi->viid, 1007 pi->xact_addr_filt, (u8 *)addr, true, true); 1008 if (ret < 0) { 1009 dev_err(adapter, "failed to set mac addr; err = %d\n", 1010 ret); 1011 return ret; 1012 } 1013 pi->xact_addr_filt = ret; 1014 return 0; 1015 } 1016 1017 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1018 .dev_start = cxgbe_dev_start, 1019 .dev_stop = cxgbe_dev_stop, 1020 .dev_close = cxgbe_dev_close, 1021 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1022 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1023 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1024 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1025 .dev_configure = cxgbe_dev_configure, 1026 .dev_infos_get = cxgbe_dev_info_get, 1027 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1028 .link_update = cxgbe_dev_link_update, 1029 .mtu_set = cxgbe_dev_mtu_set, 1030 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1031 .tx_queue_start = cxgbe_dev_tx_queue_start, 1032 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1033 .tx_queue_release = cxgbe_dev_tx_queue_release, 1034 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1035 .rx_queue_start = cxgbe_dev_rx_queue_start, 1036 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1037 .rx_queue_release = cxgbe_dev_rx_queue_release, 1038 .stats_get = cxgbe_dev_stats_get, 1039 .stats_reset = cxgbe_dev_stats_reset, 1040 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1041 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1042 .get_eeprom_length = cxgbe_get_eeprom_length, 1043 .get_eeprom = cxgbe_get_eeprom, 1044 .set_eeprom = cxgbe_set_eeprom, 1045 .get_reg = cxgbe_get_regs, 1046 .rss_hash_update = cxgbe_dev_rss_hash_update, 1047 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1048 .mac_addr_set = cxgbe_mac_addr_set, 1049 }; 1050 1051 /* 1052 * Initialize driver 1053 * It returns 0 on success. 1054 */ 1055 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1056 { 1057 struct rte_pci_device *pci_dev; 1058 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 1059 struct adapter *adapter = NULL; 1060 char name[RTE_ETH_NAME_MAX_LEN]; 1061 int err = 0; 1062 1063 CXGBE_FUNC_TRACE(); 1064 1065 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1066 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1067 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1068 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1069 1070 /* for secondary processes, we attach to ethdevs allocated by primary 1071 * and do minimal initialization. 1072 */ 1073 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1074 int i; 1075 1076 for (i = 1; i < MAX_NPORTS; i++) { 1077 struct rte_eth_dev *rest_eth_dev; 1078 char namei[RTE_ETH_NAME_MAX_LEN]; 1079 1080 snprintf(namei, sizeof(namei), "%s_%d", 1081 pci_dev->device.name, i); 1082 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1083 if (rest_eth_dev) { 1084 rest_eth_dev->device = &pci_dev->device; 1085 rest_eth_dev->dev_ops = 1086 eth_dev->dev_ops; 1087 rest_eth_dev->rx_pkt_burst = 1088 eth_dev->rx_pkt_burst; 1089 rest_eth_dev->tx_pkt_burst = 1090 eth_dev->tx_pkt_burst; 1091 rte_eth_dev_probing_finish(rest_eth_dev); 1092 } 1093 } 1094 return 0; 1095 } 1096 1097 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1098 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1099 if (!adapter) 1100 return -1; 1101 1102 adapter->use_unpacked_mode = 1; 1103 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1104 if (!adapter->regs) { 1105 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1106 err = -ENOMEM; 1107 goto out_free_adapter; 1108 } 1109 adapter->pdev = pci_dev; 1110 adapter->eth_dev = eth_dev; 1111 pi->adapter = adapter; 1112 1113 err = cxgbe_probe(adapter); 1114 if (err) { 1115 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1116 __func__, err); 1117 goto out_free_adapter; 1118 } 1119 1120 return 0; 1121 1122 out_free_adapter: 1123 rte_free(adapter); 1124 return err; 1125 } 1126 1127 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1128 { 1129 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 1130 struct adapter *adap = pi->adapter; 1131 1132 /* Free up other ports and all resources */ 1133 cxgbe_close(adap); 1134 return 0; 1135 } 1136 1137 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1138 struct rte_pci_device *pci_dev) 1139 { 1140 return rte_eth_dev_pci_generic_probe(pci_dev, 1141 sizeof(struct port_info), eth_cxgbe_dev_init); 1142 } 1143 1144 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1145 { 1146 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1147 } 1148 1149 static struct rte_pci_driver rte_cxgbe_pmd = { 1150 .id_table = cxgb4_pci_tbl, 1151 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1152 .probe = eth_cxgbe_pci_probe, 1153 .remove = eth_cxgbe_pci_remove, 1154 }; 1155 1156 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1157 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1158 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1159 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1160 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> " 1161 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> "); 1162