1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 /* 42 * Macros needed to support the PCI Device ID Table ... 43 */ 44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 45 static const struct rte_pci_id cxgb4_pci_tbl[] = { 46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 47 48 #define PCI_VENDOR_ID_CHELSIO 0x1425 49 50 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 52 53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 54 { .vendor_id = 0, } \ 55 } 56 57 /* 58 *... and the PCI ID Table itself ... 59 */ 60 #include "base/t4_pci_id_tbl.h" 61 62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 63 uint16_t nb_pkts) 64 { 65 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 66 uint16_t pkts_sent, pkts_remain; 67 uint16_t total_sent = 0; 68 uint16_t idx = 0; 69 int ret = 0; 70 71 t4_os_lock(&txq->txq_lock); 72 /* free up desc from already completed tx */ 73 reclaim_completed_tx(&txq->q); 74 if (unlikely(!nb_pkts)) 75 goto out_unlock; 76 77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 78 while (total_sent < nb_pkts) { 79 pkts_remain = nb_pkts - total_sent; 80 81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 82 idx = total_sent + pkts_sent; 83 if ((idx + 1) < nb_pkts) 84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 85 volatile void *)); 86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 87 if (ret < 0) 88 break; 89 } 90 if (!pkts_sent) 91 break; 92 total_sent += pkts_sent; 93 /* reclaim as much as possible */ 94 reclaim_completed_tx(&txq->q); 95 } 96 97 out_unlock: 98 t4_os_unlock(&txq->txq_lock); 99 return total_sent; 100 } 101 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 103 uint16_t nb_pkts) 104 { 105 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 106 unsigned int work_done; 107 108 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 109 dev_err(adapter, "error in cxgbe poll\n"); 110 111 return work_done; 112 } 113 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 115 struct rte_eth_dev_info *device_info) 116 { 117 struct port_info *pi = eth_dev->data->dev_private; 118 struct adapter *adapter = pi->adapter; 119 120 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 121 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 122 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 123 .nb_align = 1, 124 }; 125 126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 128 device_info->max_rx_queues = adapter->sge.max_ethqsets; 129 device_info->max_tx_queues = adapter->sge.max_ethqsets; 130 device_info->max_mac_addrs = 1; 131 /* XXX: For now we support one MAC/port */ 132 device_info->max_vfs = adapter->params.arch.vfcount; 133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 134 135 device_info->rx_queue_offload_capa = 0UL; 136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 137 138 device_info->tx_queue_offload_capa = 0UL; 139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 140 141 device_info->reta_size = pi->rss_size; 142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 144 145 device_info->rx_desc_lim = cxgbe_desc_lim; 146 device_info->tx_desc_lim = cxgbe_desc_lim; 147 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 148 149 return 0; 150 } 151 152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 153 { 154 struct port_info *pi = eth_dev->data->dev_private; 155 struct adapter *adapter = pi->adapter; 156 157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 158 1, -1, 1, -1, false); 159 } 160 161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 162 { 163 struct port_info *pi = eth_dev->data->dev_private; 164 struct adapter *adapter = pi->adapter; 165 166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 167 0, -1, 1, -1, false); 168 } 169 170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 171 { 172 struct port_info *pi = eth_dev->data->dev_private; 173 struct adapter *adapter = pi->adapter; 174 175 /* TODO: address filters ?? */ 176 177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 178 -1, 1, 1, -1, false); 179 } 180 181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 182 { 183 struct port_info *pi = eth_dev->data->dev_private; 184 struct adapter *adapter = pi->adapter; 185 186 /* TODO: address filters ?? */ 187 188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 189 -1, 0, 1, -1, false); 190 } 191 192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 193 int wait_to_complete) 194 { 195 struct port_info *pi = eth_dev->data->dev_private; 196 struct adapter *adapter = pi->adapter; 197 struct sge *s = &adapter->sge; 198 struct rte_eth_link new_link = { 0 }; 199 unsigned int i, work_done, budget = 32; 200 u8 old_link = pi->link_cfg.link_ok; 201 202 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 203 if (!s->fw_evtq.desc) 204 break; 205 206 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 207 208 /* Exit if link status changed or always forced up */ 209 if (pi->link_cfg.link_ok != old_link || 210 cxgbe_force_linkup(adapter)) 211 break; 212 213 if (!wait_to_complete) 214 break; 215 216 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 217 } 218 219 new_link.link_status = cxgbe_force_linkup(adapter) ? 220 ETH_LINK_UP : pi->link_cfg.link_ok; 221 new_link.link_autoneg = pi->link_cfg.autoneg; 222 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 223 new_link.link_speed = pi->link_cfg.speed; 224 225 return rte_eth_linkstatus_set(eth_dev, &new_link); 226 } 227 228 /** 229 * Set device link up. 230 */ 231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 232 { 233 struct port_info *pi = dev->data->dev_private; 234 struct adapter *adapter = pi->adapter; 235 unsigned int work_done, budget = 32; 236 struct sge *s = &adapter->sge; 237 int ret; 238 239 if (!s->fw_evtq.desc) 240 return -ENOMEM; 241 242 /* Flush all link events */ 243 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 244 245 /* If link already up, nothing to do */ 246 if (pi->link_cfg.link_ok) 247 return 0; 248 249 ret = cxgbe_set_link_status(pi, true); 250 if (ret) 251 return ret; 252 253 cxgbe_dev_link_update(dev, 1); 254 return 0; 255 } 256 257 /** 258 * Set device link down. 259 */ 260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 261 { 262 struct port_info *pi = dev->data->dev_private; 263 struct adapter *adapter = pi->adapter; 264 unsigned int work_done, budget = 32; 265 struct sge *s = &adapter->sge; 266 int ret; 267 268 if (!s->fw_evtq.desc) 269 return -ENOMEM; 270 271 /* Flush all link events */ 272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 273 274 /* If link already down, nothing to do */ 275 if (!pi->link_cfg.link_ok) 276 return 0; 277 278 ret = cxgbe_set_link_status(pi, false); 279 if (ret) 280 return ret; 281 282 cxgbe_dev_link_update(dev, 0); 283 return 0; 284 } 285 286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 287 { 288 struct port_info *pi = eth_dev->data->dev_private; 289 struct adapter *adapter = pi->adapter; 290 struct rte_eth_dev_info dev_info; 291 int err; 292 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 293 294 err = cxgbe_dev_info_get(eth_dev, &dev_info); 295 if (err != 0) 296 return err; 297 298 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 299 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 300 return -EINVAL; 301 302 /* set to jumbo mode if needed */ 303 if (new_mtu > RTE_ETHER_MAX_LEN) 304 eth_dev->data->dev_conf.rxmode.offloads |= 305 DEV_RX_OFFLOAD_JUMBO_FRAME; 306 else 307 eth_dev->data->dev_conf.rxmode.offloads &= 308 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 309 310 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 311 -1, -1, true); 312 if (!err) 313 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 314 315 return err; 316 } 317 318 /* 319 * Stop device. 320 */ 321 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 322 { 323 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 324 struct adapter *adapter = pi->adapter; 325 u8 i; 326 327 CXGBE_FUNC_TRACE(); 328 329 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 330 return 0; 331 332 if (!(adapter->flags & FULL_INIT_DONE)) 333 return 0; 334 335 if (!pi->viid) 336 return 0; 337 338 cxgbe_down(pi); 339 t4_sge_eth_release_queues(pi); 340 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 341 pi->viid = 0; 342 343 /* Free up the adapter-wide resources only after all the ports 344 * under this PF have been closed. 345 */ 346 for_each_port(adapter, i) { 347 temp_pi = adap2pinfo(adapter, i); 348 if (temp_pi->viid) 349 return 0; 350 } 351 352 cxgbe_close(adapter); 353 rte_free(adapter); 354 355 return 0; 356 } 357 358 /* Start the device. 359 * It returns 0 on success. 360 */ 361 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 362 { 363 struct port_info *pi = eth_dev->data->dev_private; 364 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 365 struct adapter *adapter = pi->adapter; 366 int err = 0, i; 367 368 CXGBE_FUNC_TRACE(); 369 370 /* 371 * If we don't have a connection to the firmware there's nothing we 372 * can do. 373 */ 374 if (!(adapter->flags & FW_OK)) { 375 err = -ENXIO; 376 goto out; 377 } 378 379 if (!(adapter->flags & FULL_INIT_DONE)) { 380 err = cxgbe_up(adapter); 381 if (err < 0) 382 goto out; 383 } 384 385 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 386 eth_dev->data->scattered_rx = 1; 387 else 388 eth_dev->data->scattered_rx = 0; 389 390 cxgbe_enable_rx_queues(pi); 391 392 err = cxgbe_setup_rss(pi); 393 if (err) 394 goto out; 395 396 for (i = 0; i < pi->n_tx_qsets; i++) { 397 err = cxgbe_dev_tx_queue_start(eth_dev, i); 398 if (err) 399 goto out; 400 } 401 402 for (i = 0; i < pi->n_rx_qsets; i++) { 403 err = cxgbe_dev_rx_queue_start(eth_dev, i); 404 if (err) 405 goto out; 406 } 407 408 err = cxgbe_link_start(pi); 409 if (err) 410 goto out; 411 412 out: 413 return err; 414 } 415 416 /* 417 * Stop device: disable rx and tx functions to allow for reconfiguring. 418 */ 419 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 420 { 421 struct port_info *pi = eth_dev->data->dev_private; 422 struct adapter *adapter = pi->adapter; 423 424 CXGBE_FUNC_TRACE(); 425 426 if (!(adapter->flags & FULL_INIT_DONE)) 427 return; 428 429 cxgbe_down(pi); 430 431 /* 432 * We clear queues only if both tx and rx path of the port 433 * have been disabled 434 */ 435 t4_sge_eth_clear_queues(pi); 436 eth_dev->data->scattered_rx = 0; 437 } 438 439 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 440 { 441 struct port_info *pi = eth_dev->data->dev_private; 442 struct adapter *adapter = pi->adapter; 443 int err; 444 445 CXGBE_FUNC_TRACE(); 446 447 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 448 eth_dev->data->dev_conf.rxmode.offloads |= 449 DEV_RX_OFFLOAD_RSS_HASH; 450 451 if (!(adapter->flags & FW_QUEUE_BOUND)) { 452 err = cxgbe_setup_sge_fwevtq(adapter); 453 if (err) 454 return err; 455 adapter->flags |= FW_QUEUE_BOUND; 456 if (is_pf4(adapter)) { 457 err = cxgbe_setup_sge_ctrl_txq(adapter); 458 if (err) 459 return err; 460 } 461 } 462 463 err = cxgbe_cfg_queue_count(eth_dev); 464 if (err) 465 return err; 466 467 return 0; 468 } 469 470 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 471 { 472 int ret; 473 struct sge_eth_txq *txq = (struct sge_eth_txq *) 474 (eth_dev->data->tx_queues[tx_queue_id]); 475 476 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 477 478 ret = t4_sge_eth_txq_start(txq); 479 if (ret == 0) 480 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 481 482 return ret; 483 } 484 485 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 486 { 487 int ret; 488 struct sge_eth_txq *txq = (struct sge_eth_txq *) 489 (eth_dev->data->tx_queues[tx_queue_id]); 490 491 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 492 493 ret = t4_sge_eth_txq_stop(txq); 494 if (ret == 0) 495 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 496 497 return ret; 498 } 499 500 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 501 uint16_t queue_idx, uint16_t nb_desc, 502 unsigned int socket_id, 503 const struct rte_eth_txconf *tx_conf __rte_unused) 504 { 505 struct port_info *pi = eth_dev->data->dev_private; 506 struct adapter *adapter = pi->adapter; 507 struct sge *s = &adapter->sge; 508 unsigned int temp_nb_desc; 509 struct sge_eth_txq *txq; 510 int err = 0; 511 512 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 513 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 514 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 515 socket_id, pi->first_txqset); 516 517 /* Free up the existing queue */ 518 if (eth_dev->data->tx_queues[queue_idx]) { 519 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 520 eth_dev->data->tx_queues[queue_idx] = NULL; 521 } 522 523 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 524 525 /* Sanity Checking 526 * 527 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 528 */ 529 temp_nb_desc = nb_desc; 530 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 531 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 532 __func__, CXGBE_MIN_RING_DESC_SIZE, 533 CXGBE_DEFAULT_TX_DESC_SIZE); 534 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 535 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 536 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 537 __func__, CXGBE_MIN_RING_DESC_SIZE, 538 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 539 return -(EINVAL); 540 } 541 542 txq->q.size = temp_nb_desc; 543 544 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 545 s->fw_evtq.cntxt_id, socket_id); 546 547 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 548 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 549 return err; 550 } 551 552 void cxgbe_dev_tx_queue_release(void *q) 553 { 554 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 555 556 if (txq) { 557 struct port_info *pi = (struct port_info *) 558 (txq->eth_dev->data->dev_private); 559 struct adapter *adap = pi->adapter; 560 561 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 562 __func__, pi->port_id, txq->q.cntxt_id); 563 564 t4_sge_eth_txq_release(adap, txq); 565 } 566 } 567 568 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 569 { 570 struct port_info *pi = eth_dev->data->dev_private; 571 struct adapter *adap = pi->adapter; 572 struct sge_eth_rxq *rxq; 573 int ret; 574 575 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 576 __func__, pi->port_id, rx_queue_id); 577 578 rxq = eth_dev->data->rx_queues[rx_queue_id]; 579 ret = t4_sge_eth_rxq_start(adap, rxq); 580 if (ret == 0) 581 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 582 583 return ret; 584 } 585 586 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 587 { 588 struct port_info *pi = eth_dev->data->dev_private; 589 struct adapter *adap = pi->adapter; 590 struct sge_eth_rxq *rxq; 591 int ret; 592 593 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 594 __func__, pi->port_id, rx_queue_id); 595 596 rxq = eth_dev->data->rx_queues[rx_queue_id]; 597 ret = t4_sge_eth_rxq_stop(adap, rxq); 598 if (ret == 0) 599 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 600 601 return ret; 602 } 603 604 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 605 uint16_t queue_idx, uint16_t nb_desc, 606 unsigned int socket_id, 607 const struct rte_eth_rxconf *rx_conf __rte_unused, 608 struct rte_mempool *mp) 609 { 610 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 611 struct port_info *pi = eth_dev->data->dev_private; 612 struct adapter *adapter = pi->adapter; 613 struct rte_eth_dev_info dev_info; 614 struct sge *s = &adapter->sge; 615 unsigned int temp_nb_desc; 616 int err = 0, msi_idx = 0; 617 struct sge_eth_rxq *rxq; 618 619 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 620 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 621 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 622 socket_id, mp); 623 624 err = cxgbe_dev_info_get(eth_dev, &dev_info); 625 if (err != 0) { 626 dev_err(adap, "%s: error during getting ethernet device info", 627 __func__); 628 return err; 629 } 630 631 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 632 if ((pkt_len < dev_info.min_rx_bufsize) || 633 (pkt_len > dev_info.max_rx_pktlen)) { 634 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 635 __func__, dev_info.min_rx_bufsize, 636 dev_info.max_rx_pktlen); 637 return -EINVAL; 638 } 639 640 /* Free up the existing queue */ 641 if (eth_dev->data->rx_queues[queue_idx]) { 642 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 643 eth_dev->data->rx_queues[queue_idx] = NULL; 644 } 645 646 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 647 648 /* Sanity Checking 649 * 650 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 651 */ 652 temp_nb_desc = nb_desc; 653 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 654 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 655 __func__, CXGBE_MIN_RING_DESC_SIZE, 656 CXGBE_DEFAULT_RX_DESC_SIZE); 657 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 658 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 659 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 660 __func__, CXGBE_MIN_RING_DESC_SIZE, 661 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 662 return -(EINVAL); 663 } 664 665 rxq->rspq.size = temp_nb_desc; 666 if ((&rxq->fl) != NULL) 667 rxq->fl.size = temp_nb_desc; 668 669 /* Set to jumbo mode if necessary */ 670 if (pkt_len > RTE_ETHER_MAX_LEN) 671 eth_dev->data->dev_conf.rxmode.offloads |= 672 DEV_RX_OFFLOAD_JUMBO_FRAME; 673 else 674 eth_dev->data->dev_conf.rxmode.offloads &= 675 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 676 677 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 678 &rxq->fl, NULL, 679 is_pf4(adapter) ? 680 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 681 queue_idx, socket_id); 682 683 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 684 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 685 rxq->rspq.abs_id); 686 return err; 687 } 688 689 void cxgbe_dev_rx_queue_release(void *q) 690 { 691 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 692 693 if (rxq) { 694 struct port_info *pi = (struct port_info *) 695 (rxq->rspq.eth_dev->data->dev_private); 696 struct adapter *adap = pi->adapter; 697 698 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 699 __func__, pi->port_id, rxq->rspq.cntxt_id); 700 701 t4_sge_eth_rxq_release(adap, rxq); 702 } 703 } 704 705 /* 706 * Get port statistics. 707 */ 708 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 709 struct rte_eth_stats *eth_stats) 710 { 711 struct port_info *pi = eth_dev->data->dev_private; 712 struct adapter *adapter = pi->adapter; 713 struct sge *s = &adapter->sge; 714 struct port_stats ps; 715 unsigned int i; 716 717 cxgbe_stats_get(pi, &ps); 718 719 /* RX Stats */ 720 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 721 ps.rx_ovflow2 + ps.rx_ovflow3 + 722 ps.rx_trunc0 + ps.rx_trunc1 + 723 ps.rx_trunc2 + ps.rx_trunc3; 724 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 725 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 726 ps.rx_len_err; 727 728 /* TX Stats */ 729 eth_stats->opackets = ps.tx_frames; 730 eth_stats->obytes = ps.tx_octets; 731 eth_stats->oerrors = ps.tx_error_frames; 732 733 for (i = 0; i < pi->n_rx_qsets; i++) { 734 struct sge_eth_rxq *rxq = 735 &s->ethrxq[pi->first_rxqset + i]; 736 737 eth_stats->q_ipackets[i] = rxq->stats.pkts; 738 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 739 eth_stats->ipackets += eth_stats->q_ipackets[i]; 740 eth_stats->ibytes += eth_stats->q_ibytes[i]; 741 } 742 743 for (i = 0; i < pi->n_tx_qsets; i++) { 744 struct sge_eth_txq *txq = 745 &s->ethtxq[pi->first_txqset + i]; 746 747 eth_stats->q_opackets[i] = txq->stats.pkts; 748 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 749 } 750 return 0; 751 } 752 753 /* 754 * Reset port statistics. 755 */ 756 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 757 { 758 struct port_info *pi = eth_dev->data->dev_private; 759 struct adapter *adapter = pi->adapter; 760 struct sge *s = &adapter->sge; 761 unsigned int i; 762 763 cxgbe_stats_reset(pi); 764 for (i = 0; i < pi->n_rx_qsets; i++) { 765 struct sge_eth_rxq *rxq = 766 &s->ethrxq[pi->first_rxqset + i]; 767 768 rxq->stats.pkts = 0; 769 rxq->stats.rx_bytes = 0; 770 } 771 for (i = 0; i < pi->n_tx_qsets; i++) { 772 struct sge_eth_txq *txq = 773 &s->ethtxq[pi->first_txqset + i]; 774 775 txq->stats.pkts = 0; 776 txq->stats.tx_bytes = 0; 777 txq->stats.mapping_err = 0; 778 } 779 780 return 0; 781 } 782 783 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 784 struct rte_eth_fc_conf *fc_conf) 785 { 786 struct port_info *pi = eth_dev->data->dev_private; 787 struct link_config *lc = &pi->link_cfg; 788 int rx_pause, tx_pause; 789 790 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 791 rx_pause = lc->fc & PAUSE_RX; 792 tx_pause = lc->fc & PAUSE_TX; 793 794 if (rx_pause && tx_pause) 795 fc_conf->mode = RTE_FC_FULL; 796 else if (rx_pause) 797 fc_conf->mode = RTE_FC_RX_PAUSE; 798 else if (tx_pause) 799 fc_conf->mode = RTE_FC_TX_PAUSE; 800 else 801 fc_conf->mode = RTE_FC_NONE; 802 return 0; 803 } 804 805 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 806 struct rte_eth_fc_conf *fc_conf) 807 { 808 struct port_info *pi = eth_dev->data->dev_private; 809 struct adapter *adapter = pi->adapter; 810 struct link_config *lc = &pi->link_cfg; 811 812 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 813 if (fc_conf->autoneg) 814 lc->requested_fc |= PAUSE_AUTONEG; 815 else 816 lc->requested_fc &= ~PAUSE_AUTONEG; 817 } 818 819 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 820 (fc_conf->mode & RTE_FC_RX_PAUSE)) 821 lc->requested_fc |= PAUSE_RX; 822 else 823 lc->requested_fc &= ~PAUSE_RX; 824 825 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 826 (fc_conf->mode & RTE_FC_TX_PAUSE)) 827 lc->requested_fc |= PAUSE_TX; 828 else 829 lc->requested_fc &= ~PAUSE_TX; 830 831 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 832 &pi->link_cfg); 833 } 834 835 const uint32_t * 836 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 837 { 838 static const uint32_t ptypes[] = { 839 RTE_PTYPE_L3_IPV4, 840 RTE_PTYPE_L3_IPV6, 841 RTE_PTYPE_UNKNOWN 842 }; 843 844 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 845 return ptypes; 846 return NULL; 847 } 848 849 /* Update RSS hash configuration 850 */ 851 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 852 struct rte_eth_rss_conf *rss_conf) 853 { 854 struct port_info *pi = dev->data->dev_private; 855 struct adapter *adapter = pi->adapter; 856 int err; 857 858 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 859 if (err) 860 return err; 861 862 pi->rss_hf = rss_conf->rss_hf; 863 864 if (rss_conf->rss_key) { 865 u32 key[10], mod_key[10]; 866 int i, j; 867 868 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 869 870 for (i = 9, j = 0; i >= 0; i--, j++) 871 mod_key[j] = cpu_to_be32(key[i]); 872 873 t4_write_rss_key(adapter, mod_key, -1); 874 } 875 876 return 0; 877 } 878 879 /* Get RSS hash configuration 880 */ 881 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 882 struct rte_eth_rss_conf *rss_conf) 883 { 884 struct port_info *pi = dev->data->dev_private; 885 struct adapter *adapter = pi->adapter; 886 u64 rss_hf = 0; 887 u64 flags = 0; 888 int err; 889 890 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 891 &flags, NULL); 892 893 if (err) 894 return err; 895 896 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 897 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 898 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 899 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 900 } 901 902 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 903 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 904 905 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 906 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 907 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 908 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 909 } 910 911 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 912 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 913 914 rss_conf->rss_hf = rss_hf; 915 916 if (rss_conf->rss_key) { 917 u32 key[10], mod_key[10]; 918 int i, j; 919 920 t4_read_rss_key(adapter, key); 921 922 for (i = 9, j = 0; i >= 0; i--, j++) 923 mod_key[j] = be32_to_cpu(key[i]); 924 925 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 926 } 927 928 return 0; 929 } 930 931 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 932 struct rte_eth_rss_reta_entry64 *reta_conf, 933 uint16_t reta_size) 934 { 935 struct port_info *pi = dev->data->dev_private; 936 struct adapter *adapter = pi->adapter; 937 u16 i, idx, shift, *rss; 938 int ret; 939 940 if (!(adapter->flags & FULL_INIT_DONE)) 941 return -ENOMEM; 942 943 if (!reta_size || reta_size > pi->rss_size) 944 return -EINVAL; 945 946 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 947 if (!rss) 948 return -ENOMEM; 949 950 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 951 for (i = 0; i < reta_size; i++) { 952 idx = i / RTE_RETA_GROUP_SIZE; 953 shift = i % RTE_RETA_GROUP_SIZE; 954 if (!(reta_conf[idx].mask & (1ULL << shift))) 955 continue; 956 957 rss[i] = reta_conf[idx].reta[shift]; 958 } 959 960 ret = cxgbe_write_rss(pi, rss); 961 if (!ret) 962 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 963 964 rte_free(rss); 965 return ret; 966 } 967 968 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 969 struct rte_eth_rss_reta_entry64 *reta_conf, 970 uint16_t reta_size) 971 { 972 struct port_info *pi = dev->data->dev_private; 973 struct adapter *adapter = pi->adapter; 974 u16 i, idx, shift; 975 976 if (!(adapter->flags & FULL_INIT_DONE)) 977 return -ENOMEM; 978 979 if (!reta_size || reta_size > pi->rss_size) 980 return -EINVAL; 981 982 for (i = 0; i < reta_size; i++) { 983 idx = i / RTE_RETA_GROUP_SIZE; 984 shift = i % RTE_RETA_GROUP_SIZE; 985 if (!(reta_conf[idx].mask & (1ULL << shift))) 986 continue; 987 988 reta_conf[idx].reta[shift] = pi->rss[i]; 989 } 990 991 return 0; 992 } 993 994 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 995 { 996 RTE_SET_USED(dev); 997 return EEPROMSIZE; 998 } 999 1000 /** 1001 * eeprom_ptov - translate a physical EEPROM address to virtual 1002 * @phys_addr: the physical EEPROM address 1003 * @fn: the PCI function number 1004 * @sz: size of function-specific area 1005 * 1006 * Translate a physical EEPROM address to virtual. The first 1K is 1007 * accessed through virtual addresses starting at 31K, the rest is 1008 * accessed through virtual addresses starting at 0. 1009 * 1010 * The mapping is as follows: 1011 * [0..1K) -> [31K..32K) 1012 * [1K..1K+A) -> [31K-A..31K) 1013 * [1K+A..ES) -> [0..ES-A-1K) 1014 * 1015 * where A = @fn * @sz, and ES = EEPROM size. 1016 */ 1017 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1018 { 1019 fn *= sz; 1020 if (phys_addr < 1024) 1021 return phys_addr + (31 << 10); 1022 if (phys_addr < 1024 + fn) 1023 return fn + phys_addr - 1024; 1024 if (phys_addr < EEPROMSIZE) 1025 return phys_addr - 1024 - fn; 1026 if (phys_addr < EEPROMVSIZE) 1027 return phys_addr - 1024; 1028 return -EINVAL; 1029 } 1030 1031 /* The next two routines implement eeprom read/write from physical addresses. 1032 */ 1033 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1034 { 1035 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1036 1037 if (vaddr >= 0) 1038 vaddr = t4_seeprom_read(adap, vaddr, v); 1039 return vaddr < 0 ? vaddr : 0; 1040 } 1041 1042 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1043 { 1044 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1045 1046 if (vaddr >= 0) 1047 vaddr = t4_seeprom_write(adap, vaddr, v); 1048 return vaddr < 0 ? vaddr : 0; 1049 } 1050 1051 #define EEPROM_MAGIC 0x38E2F10C 1052 1053 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1054 struct rte_dev_eeprom_info *e) 1055 { 1056 struct port_info *pi = dev->data->dev_private; 1057 struct adapter *adapter = pi->adapter; 1058 u32 i, err = 0; 1059 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1060 1061 if (!buf) 1062 return -ENOMEM; 1063 1064 e->magic = EEPROM_MAGIC; 1065 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1066 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1067 1068 if (!err) 1069 rte_memcpy(e->data, buf + e->offset, e->length); 1070 rte_free(buf); 1071 return err; 1072 } 1073 1074 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1075 struct rte_dev_eeprom_info *eeprom) 1076 { 1077 struct port_info *pi = dev->data->dev_private; 1078 struct adapter *adapter = pi->adapter; 1079 u8 *buf; 1080 int err = 0; 1081 u32 aligned_offset, aligned_len, *p; 1082 1083 if (eeprom->magic != EEPROM_MAGIC) 1084 return -EINVAL; 1085 1086 aligned_offset = eeprom->offset & ~3; 1087 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1088 1089 if (adapter->pf > 0) { 1090 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1091 1092 if (aligned_offset < start || 1093 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1094 return -EPERM; 1095 } 1096 1097 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1098 /* RMW possibly needed for first or last words. 1099 */ 1100 buf = rte_zmalloc(NULL, aligned_len, 0); 1101 if (!buf) 1102 return -ENOMEM; 1103 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1104 if (!err && aligned_len > 4) 1105 err = eeprom_rd_phys(adapter, 1106 aligned_offset + aligned_len - 4, 1107 (u32 *)&buf[aligned_len - 4]); 1108 if (err) 1109 goto out; 1110 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1111 eeprom->length); 1112 } else { 1113 buf = eeprom->data; 1114 } 1115 1116 err = t4_seeprom_wp(adapter, false); 1117 if (err) 1118 goto out; 1119 1120 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1121 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1122 aligned_offset += 4; 1123 } 1124 1125 if (!err) 1126 err = t4_seeprom_wp(adapter, true); 1127 out: 1128 if (buf != eeprom->data) 1129 rte_free(buf); 1130 return err; 1131 } 1132 1133 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1134 { 1135 struct port_info *pi = eth_dev->data->dev_private; 1136 struct adapter *adapter = pi->adapter; 1137 1138 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1139 } 1140 1141 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1142 struct rte_dev_reg_info *regs) 1143 { 1144 struct port_info *pi = eth_dev->data->dev_private; 1145 struct adapter *adapter = pi->adapter; 1146 1147 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1148 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1149 (1 << 16); 1150 1151 if (regs->data == NULL) { 1152 regs->length = cxgbe_get_regs_len(eth_dev); 1153 regs->width = sizeof(uint32_t); 1154 1155 return 0; 1156 } 1157 1158 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1159 1160 return 0; 1161 } 1162 1163 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1164 { 1165 struct port_info *pi = dev->data->dev_private; 1166 int ret; 1167 1168 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1169 if (ret < 0) { 1170 dev_err(adapter, "failed to set mac addr; err = %d\n", 1171 ret); 1172 return ret; 1173 } 1174 pi->xact_addr_filt = ret; 1175 return 0; 1176 } 1177 1178 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1179 .dev_start = cxgbe_dev_start, 1180 .dev_stop = cxgbe_dev_stop, 1181 .dev_close = cxgbe_dev_close, 1182 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1183 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1184 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1185 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1186 .dev_configure = cxgbe_dev_configure, 1187 .dev_infos_get = cxgbe_dev_info_get, 1188 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1189 .link_update = cxgbe_dev_link_update, 1190 .dev_set_link_up = cxgbe_dev_set_link_up, 1191 .dev_set_link_down = cxgbe_dev_set_link_down, 1192 .mtu_set = cxgbe_dev_mtu_set, 1193 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1194 .tx_queue_start = cxgbe_dev_tx_queue_start, 1195 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1196 .tx_queue_release = cxgbe_dev_tx_queue_release, 1197 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1198 .rx_queue_start = cxgbe_dev_rx_queue_start, 1199 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1200 .rx_queue_release = cxgbe_dev_rx_queue_release, 1201 .filter_ctrl = cxgbe_dev_filter_ctrl, 1202 .stats_get = cxgbe_dev_stats_get, 1203 .stats_reset = cxgbe_dev_stats_reset, 1204 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1205 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1206 .get_eeprom_length = cxgbe_get_eeprom_length, 1207 .get_eeprom = cxgbe_get_eeprom, 1208 .set_eeprom = cxgbe_set_eeprom, 1209 .get_reg = cxgbe_get_regs, 1210 .rss_hash_update = cxgbe_dev_rss_hash_update, 1211 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1212 .mac_addr_set = cxgbe_mac_addr_set, 1213 .reta_update = cxgbe_dev_rss_reta_update, 1214 .reta_query = cxgbe_dev_rss_reta_query, 1215 }; 1216 1217 /* 1218 * Initialize driver 1219 * It returns 0 on success. 1220 */ 1221 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1222 { 1223 struct rte_pci_device *pci_dev; 1224 struct port_info *pi = eth_dev->data->dev_private; 1225 struct adapter *adapter = NULL; 1226 char name[RTE_ETH_NAME_MAX_LEN]; 1227 int err = 0; 1228 1229 CXGBE_FUNC_TRACE(); 1230 1231 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1232 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1233 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1234 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1235 1236 /* for secondary processes, we attach to ethdevs allocated by primary 1237 * and do minimal initialization. 1238 */ 1239 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1240 int i; 1241 1242 for (i = 1; i < MAX_NPORTS; i++) { 1243 struct rte_eth_dev *rest_eth_dev; 1244 char namei[RTE_ETH_NAME_MAX_LEN]; 1245 1246 snprintf(namei, sizeof(namei), "%s_%d", 1247 pci_dev->device.name, i); 1248 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1249 if (rest_eth_dev) { 1250 rest_eth_dev->device = &pci_dev->device; 1251 rest_eth_dev->dev_ops = 1252 eth_dev->dev_ops; 1253 rest_eth_dev->rx_pkt_burst = 1254 eth_dev->rx_pkt_burst; 1255 rest_eth_dev->tx_pkt_burst = 1256 eth_dev->tx_pkt_burst; 1257 rte_eth_dev_probing_finish(rest_eth_dev); 1258 } 1259 } 1260 return 0; 1261 } 1262 1263 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1264 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1265 if (!adapter) 1266 return -1; 1267 1268 adapter->use_unpacked_mode = 1; 1269 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1270 if (!adapter->regs) { 1271 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1272 err = -ENOMEM; 1273 goto out_free_adapter; 1274 } 1275 adapter->pdev = pci_dev; 1276 adapter->eth_dev = eth_dev; 1277 pi->adapter = adapter; 1278 1279 cxgbe_process_devargs(adapter); 1280 1281 err = cxgbe_probe(adapter); 1282 if (err) { 1283 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1284 __func__, err); 1285 goto out_free_adapter; 1286 } 1287 1288 return 0; 1289 1290 out_free_adapter: 1291 rte_free(adapter); 1292 return err; 1293 } 1294 1295 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1296 { 1297 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1298 uint16_t port_id; 1299 1300 /* Free up other ports and all resources */ 1301 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1302 rte_eth_dev_close(port_id); 1303 1304 return 0; 1305 } 1306 1307 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1308 struct rte_pci_device *pci_dev) 1309 { 1310 return rte_eth_dev_pci_generic_probe(pci_dev, 1311 sizeof(struct port_info), eth_cxgbe_dev_init); 1312 } 1313 1314 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1315 { 1316 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1317 } 1318 1319 static struct rte_pci_driver rte_cxgbe_pmd = { 1320 .id_table = cxgb4_pci_tbl, 1321 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1322 .probe = eth_cxgbe_pci_probe, 1323 .remove = eth_cxgbe_pci_remove, 1324 }; 1325 1326 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1327 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1328 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1329 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1330 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1331 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1332 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1333 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1334 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE); 1335 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE); 1336