1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 /* 42 * Macros needed to support the PCI Device ID Table ... 43 */ 44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 45 static const struct rte_pci_id cxgb4_pci_tbl[] = { 46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 47 48 #define PCI_VENDOR_ID_CHELSIO 0x1425 49 50 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 52 53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 54 { .vendor_id = 0, } \ 55 } 56 57 /* 58 *... and the PCI ID Table itself ... 59 */ 60 #include "base/t4_pci_id_tbl.h" 61 62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 63 uint16_t nb_pkts) 64 { 65 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 66 uint16_t pkts_sent, pkts_remain; 67 uint16_t total_sent = 0; 68 uint16_t idx = 0; 69 int ret = 0; 70 71 t4_os_lock(&txq->txq_lock); 72 /* free up desc from already completed tx */ 73 reclaim_completed_tx(&txq->q); 74 if (unlikely(!nb_pkts)) 75 goto out_unlock; 76 77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 78 while (total_sent < nb_pkts) { 79 pkts_remain = nb_pkts - total_sent; 80 81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 82 idx = total_sent + pkts_sent; 83 if ((idx + 1) < nb_pkts) 84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 85 volatile void *)); 86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 87 if (ret < 0) 88 break; 89 } 90 if (!pkts_sent) 91 break; 92 total_sent += pkts_sent; 93 /* reclaim as much as possible */ 94 reclaim_completed_tx(&txq->q); 95 } 96 97 out_unlock: 98 t4_os_unlock(&txq->txq_lock); 99 return total_sent; 100 } 101 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 103 uint16_t nb_pkts) 104 { 105 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 106 unsigned int work_done; 107 108 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 109 dev_err(adapter, "error in cxgbe poll\n"); 110 111 return work_done; 112 } 113 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 115 struct rte_eth_dev_info *device_info) 116 { 117 struct port_info *pi = eth_dev->data->dev_private; 118 struct adapter *adapter = pi->adapter; 119 120 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 121 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 122 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 123 .nb_align = 1, 124 }; 125 126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 128 device_info->max_rx_queues = adapter->sge.max_ethqsets; 129 device_info->max_tx_queues = adapter->sge.max_ethqsets; 130 device_info->max_mac_addrs = 1; 131 /* XXX: For now we support one MAC/port */ 132 device_info->max_vfs = adapter->params.arch.vfcount; 133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 134 135 device_info->rx_queue_offload_capa = 0UL; 136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 137 138 device_info->tx_queue_offload_capa = 0UL; 139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 140 141 device_info->reta_size = pi->rss_size; 142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 144 145 device_info->rx_desc_lim = cxgbe_desc_lim; 146 device_info->tx_desc_lim = cxgbe_desc_lim; 147 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 148 149 return 0; 150 } 151 152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 153 { 154 struct port_info *pi = eth_dev->data->dev_private; 155 struct adapter *adapter = pi->adapter; 156 157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 158 1, -1, 1, -1, false); 159 } 160 161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 162 { 163 struct port_info *pi = eth_dev->data->dev_private; 164 struct adapter *adapter = pi->adapter; 165 166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 167 0, -1, 1, -1, false); 168 } 169 170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 171 { 172 struct port_info *pi = eth_dev->data->dev_private; 173 struct adapter *adapter = pi->adapter; 174 175 /* TODO: address filters ?? */ 176 177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 178 -1, 1, 1, -1, false); 179 } 180 181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 182 { 183 struct port_info *pi = eth_dev->data->dev_private; 184 struct adapter *adapter = pi->adapter; 185 186 /* TODO: address filters ?? */ 187 188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 189 -1, 0, 1, -1, false); 190 } 191 192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 193 int wait_to_complete) 194 { 195 struct port_info *pi = eth_dev->data->dev_private; 196 struct adapter *adapter = pi->adapter; 197 struct sge *s = &adapter->sge; 198 struct rte_eth_link new_link = { 0 }; 199 unsigned int i, work_done, budget = 32; 200 u8 old_link = pi->link_cfg.link_ok; 201 202 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 203 if (!s->fw_evtq.desc) 204 break; 205 206 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 207 208 /* Exit if link status changed or always forced up */ 209 if (pi->link_cfg.link_ok != old_link || 210 cxgbe_force_linkup(adapter)) 211 break; 212 213 if (!wait_to_complete) 214 break; 215 216 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 217 } 218 219 new_link.link_status = cxgbe_force_linkup(adapter) ? 220 ETH_LINK_UP : pi->link_cfg.link_ok; 221 new_link.link_autoneg = pi->link_cfg.autoneg; 222 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 223 new_link.link_speed = pi->link_cfg.speed; 224 225 return rte_eth_linkstatus_set(eth_dev, &new_link); 226 } 227 228 /** 229 * Set device link up. 230 */ 231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 232 { 233 struct port_info *pi = dev->data->dev_private; 234 struct adapter *adapter = pi->adapter; 235 unsigned int work_done, budget = 32; 236 struct sge *s = &adapter->sge; 237 int ret; 238 239 if (!s->fw_evtq.desc) 240 return -ENOMEM; 241 242 /* Flush all link events */ 243 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 244 245 /* If link already up, nothing to do */ 246 if (pi->link_cfg.link_ok) 247 return 0; 248 249 ret = cxgbe_set_link_status(pi, true); 250 if (ret) 251 return ret; 252 253 cxgbe_dev_link_update(dev, 1); 254 return 0; 255 } 256 257 /** 258 * Set device link down. 259 */ 260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 261 { 262 struct port_info *pi = dev->data->dev_private; 263 struct adapter *adapter = pi->adapter; 264 unsigned int work_done, budget = 32; 265 struct sge *s = &adapter->sge; 266 int ret; 267 268 if (!s->fw_evtq.desc) 269 return -ENOMEM; 270 271 /* Flush all link events */ 272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 273 274 /* If link already down, nothing to do */ 275 if (!pi->link_cfg.link_ok) 276 return 0; 277 278 ret = cxgbe_set_link_status(pi, false); 279 if (ret) 280 return ret; 281 282 cxgbe_dev_link_update(dev, 0); 283 return 0; 284 } 285 286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 287 { 288 struct port_info *pi = eth_dev->data->dev_private; 289 struct adapter *adapter = pi->adapter; 290 struct rte_eth_dev_info dev_info; 291 int err; 292 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 293 294 err = cxgbe_dev_info_get(eth_dev, &dev_info); 295 if (err != 0) 296 return err; 297 298 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 299 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 300 return -EINVAL; 301 302 /* set to jumbo mode if needed */ 303 if (new_mtu > RTE_ETHER_MAX_LEN) 304 eth_dev->data->dev_conf.rxmode.offloads |= 305 DEV_RX_OFFLOAD_JUMBO_FRAME; 306 else 307 eth_dev->data->dev_conf.rxmode.offloads &= 308 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 309 310 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 311 -1, -1, true); 312 if (!err) 313 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 314 315 return err; 316 } 317 318 /* 319 * Stop device. 320 */ 321 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 322 { 323 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 324 struct adapter *adapter = pi->adapter; 325 u8 i; 326 327 CXGBE_FUNC_TRACE(); 328 329 if (!(adapter->flags & FULL_INIT_DONE)) 330 return; 331 332 if (!pi->viid) 333 return; 334 335 cxgbe_down(pi); 336 t4_sge_eth_release_queues(pi); 337 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 338 pi->viid = 0; 339 340 /* Free up the adapter-wide resources only after all the ports 341 * under this PF have been closed. 342 */ 343 for_each_port(adapter, i) { 344 temp_pi = adap2pinfo(adapter, i); 345 if (temp_pi->viid) 346 return; 347 } 348 349 cxgbe_close(adapter); 350 rte_free(adapter); 351 } 352 353 /* Start the device. 354 * It returns 0 on success. 355 */ 356 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 357 { 358 struct port_info *pi = eth_dev->data->dev_private; 359 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 360 struct adapter *adapter = pi->adapter; 361 int err = 0, i; 362 363 CXGBE_FUNC_TRACE(); 364 365 /* 366 * If we don't have a connection to the firmware there's nothing we 367 * can do. 368 */ 369 if (!(adapter->flags & FW_OK)) { 370 err = -ENXIO; 371 goto out; 372 } 373 374 if (!(adapter->flags & FULL_INIT_DONE)) { 375 err = cxgbe_up(adapter); 376 if (err < 0) 377 goto out; 378 } 379 380 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 381 eth_dev->data->scattered_rx = 1; 382 else 383 eth_dev->data->scattered_rx = 0; 384 385 cxgbe_enable_rx_queues(pi); 386 387 err = cxgbe_setup_rss(pi); 388 if (err) 389 goto out; 390 391 for (i = 0; i < pi->n_tx_qsets; i++) { 392 err = cxgbe_dev_tx_queue_start(eth_dev, i); 393 if (err) 394 goto out; 395 } 396 397 for (i = 0; i < pi->n_rx_qsets; i++) { 398 err = cxgbe_dev_rx_queue_start(eth_dev, i); 399 if (err) 400 goto out; 401 } 402 403 err = cxgbe_link_start(pi); 404 if (err) 405 goto out; 406 407 out: 408 return err; 409 } 410 411 /* 412 * Stop device: disable rx and tx functions to allow for reconfiguring. 413 */ 414 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 415 { 416 struct port_info *pi = eth_dev->data->dev_private; 417 struct adapter *adapter = pi->adapter; 418 419 CXGBE_FUNC_TRACE(); 420 421 if (!(adapter->flags & FULL_INIT_DONE)) 422 return; 423 424 cxgbe_down(pi); 425 426 /* 427 * We clear queues only if both tx and rx path of the port 428 * have been disabled 429 */ 430 t4_sge_eth_clear_queues(pi); 431 eth_dev->data->scattered_rx = 0; 432 } 433 434 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 435 { 436 struct port_info *pi = eth_dev->data->dev_private; 437 struct adapter *adapter = pi->adapter; 438 int err; 439 440 CXGBE_FUNC_TRACE(); 441 442 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 443 eth_dev->data->dev_conf.rxmode.offloads |= 444 DEV_RX_OFFLOAD_RSS_HASH; 445 446 if (!(adapter->flags & FW_QUEUE_BOUND)) { 447 err = cxgbe_setup_sge_fwevtq(adapter); 448 if (err) 449 return err; 450 adapter->flags |= FW_QUEUE_BOUND; 451 if (is_pf4(adapter)) { 452 err = cxgbe_setup_sge_ctrl_txq(adapter); 453 if (err) 454 return err; 455 } 456 } 457 458 err = cxgbe_cfg_queue_count(eth_dev); 459 if (err) 460 return err; 461 462 return 0; 463 } 464 465 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 466 { 467 int ret; 468 struct sge_eth_txq *txq = (struct sge_eth_txq *) 469 (eth_dev->data->tx_queues[tx_queue_id]); 470 471 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 472 473 ret = t4_sge_eth_txq_start(txq); 474 if (ret == 0) 475 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 476 477 return ret; 478 } 479 480 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 481 { 482 int ret; 483 struct sge_eth_txq *txq = (struct sge_eth_txq *) 484 (eth_dev->data->tx_queues[tx_queue_id]); 485 486 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 487 488 ret = t4_sge_eth_txq_stop(txq); 489 if (ret == 0) 490 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 491 492 return ret; 493 } 494 495 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 496 uint16_t queue_idx, uint16_t nb_desc, 497 unsigned int socket_id, 498 const struct rte_eth_txconf *tx_conf __rte_unused) 499 { 500 struct port_info *pi = eth_dev->data->dev_private; 501 struct adapter *adapter = pi->adapter; 502 struct sge *s = &adapter->sge; 503 unsigned int temp_nb_desc; 504 struct sge_eth_txq *txq; 505 int err = 0; 506 507 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 508 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 509 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 510 socket_id, pi->first_txqset); 511 512 /* Free up the existing queue */ 513 if (eth_dev->data->tx_queues[queue_idx]) { 514 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 515 eth_dev->data->tx_queues[queue_idx] = NULL; 516 } 517 518 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 519 520 /* Sanity Checking 521 * 522 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 523 */ 524 temp_nb_desc = nb_desc; 525 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 526 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 527 __func__, CXGBE_MIN_RING_DESC_SIZE, 528 CXGBE_DEFAULT_TX_DESC_SIZE); 529 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 530 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 531 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 532 __func__, CXGBE_MIN_RING_DESC_SIZE, 533 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 534 return -(EINVAL); 535 } 536 537 txq->q.size = temp_nb_desc; 538 539 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 540 s->fw_evtq.cntxt_id, socket_id); 541 542 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 543 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 544 return err; 545 } 546 547 void cxgbe_dev_tx_queue_release(void *q) 548 { 549 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 550 551 if (txq) { 552 struct port_info *pi = (struct port_info *) 553 (txq->eth_dev->data->dev_private); 554 struct adapter *adap = pi->adapter; 555 556 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 557 __func__, pi->port_id, txq->q.cntxt_id); 558 559 t4_sge_eth_txq_release(adap, txq); 560 } 561 } 562 563 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 564 { 565 struct port_info *pi = eth_dev->data->dev_private; 566 struct adapter *adap = pi->adapter; 567 struct sge_eth_rxq *rxq; 568 int ret; 569 570 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 571 __func__, pi->port_id, rx_queue_id); 572 573 rxq = eth_dev->data->rx_queues[rx_queue_id]; 574 ret = t4_sge_eth_rxq_start(adap, rxq); 575 if (ret == 0) 576 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 577 578 return ret; 579 } 580 581 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 582 { 583 struct port_info *pi = eth_dev->data->dev_private; 584 struct adapter *adap = pi->adapter; 585 struct sge_eth_rxq *rxq; 586 int ret; 587 588 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 589 __func__, pi->port_id, rx_queue_id); 590 591 rxq = eth_dev->data->rx_queues[rx_queue_id]; 592 ret = t4_sge_eth_rxq_stop(adap, rxq); 593 if (ret == 0) 594 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 595 596 return ret; 597 } 598 599 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 600 uint16_t queue_idx, uint16_t nb_desc, 601 unsigned int socket_id, 602 const struct rte_eth_rxconf *rx_conf __rte_unused, 603 struct rte_mempool *mp) 604 { 605 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 606 struct port_info *pi = eth_dev->data->dev_private; 607 struct adapter *adapter = pi->adapter; 608 struct rte_eth_dev_info dev_info; 609 struct sge *s = &adapter->sge; 610 unsigned int temp_nb_desc; 611 int err = 0, msi_idx = 0; 612 struct sge_eth_rxq *rxq; 613 614 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 615 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 616 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 617 socket_id, mp); 618 619 err = cxgbe_dev_info_get(eth_dev, &dev_info); 620 if (err != 0) { 621 dev_err(adap, "%s: error during getting ethernet device info", 622 __func__); 623 return err; 624 } 625 626 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 627 if ((pkt_len < dev_info.min_rx_bufsize) || 628 (pkt_len > dev_info.max_rx_pktlen)) { 629 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 630 __func__, dev_info.min_rx_bufsize, 631 dev_info.max_rx_pktlen); 632 return -EINVAL; 633 } 634 635 /* Free up the existing queue */ 636 if (eth_dev->data->rx_queues[queue_idx]) { 637 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 638 eth_dev->data->rx_queues[queue_idx] = NULL; 639 } 640 641 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 642 643 /* Sanity Checking 644 * 645 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 646 */ 647 temp_nb_desc = nb_desc; 648 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 649 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 650 __func__, CXGBE_MIN_RING_DESC_SIZE, 651 CXGBE_DEFAULT_RX_DESC_SIZE); 652 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 653 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 654 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 655 __func__, CXGBE_MIN_RING_DESC_SIZE, 656 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 657 return -(EINVAL); 658 } 659 660 rxq->rspq.size = temp_nb_desc; 661 if ((&rxq->fl) != NULL) 662 rxq->fl.size = temp_nb_desc; 663 664 /* Set to jumbo mode if necessary */ 665 if (pkt_len > RTE_ETHER_MAX_LEN) 666 eth_dev->data->dev_conf.rxmode.offloads |= 667 DEV_RX_OFFLOAD_JUMBO_FRAME; 668 else 669 eth_dev->data->dev_conf.rxmode.offloads &= 670 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 671 672 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 673 &rxq->fl, NULL, 674 is_pf4(adapter) ? 675 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 676 queue_idx, socket_id); 677 678 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 679 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 680 rxq->rspq.abs_id); 681 return err; 682 } 683 684 void cxgbe_dev_rx_queue_release(void *q) 685 { 686 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 687 688 if (rxq) { 689 struct port_info *pi = (struct port_info *) 690 (rxq->rspq.eth_dev->data->dev_private); 691 struct adapter *adap = pi->adapter; 692 693 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 694 __func__, pi->port_id, rxq->rspq.cntxt_id); 695 696 t4_sge_eth_rxq_release(adap, rxq); 697 } 698 } 699 700 /* 701 * Get port statistics. 702 */ 703 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 704 struct rte_eth_stats *eth_stats) 705 { 706 struct port_info *pi = eth_dev->data->dev_private; 707 struct adapter *adapter = pi->adapter; 708 struct sge *s = &adapter->sge; 709 struct port_stats ps; 710 unsigned int i; 711 712 cxgbe_stats_get(pi, &ps); 713 714 /* RX Stats */ 715 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 716 ps.rx_ovflow2 + ps.rx_ovflow3 + 717 ps.rx_trunc0 + ps.rx_trunc1 + 718 ps.rx_trunc2 + ps.rx_trunc3; 719 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 720 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 721 ps.rx_len_err; 722 723 /* TX Stats */ 724 eth_stats->opackets = ps.tx_frames; 725 eth_stats->obytes = ps.tx_octets; 726 eth_stats->oerrors = ps.tx_error_frames; 727 728 for (i = 0; i < pi->n_rx_qsets; i++) { 729 struct sge_eth_rxq *rxq = 730 &s->ethrxq[pi->first_rxqset + i]; 731 732 eth_stats->q_ipackets[i] = rxq->stats.pkts; 733 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 734 eth_stats->ipackets += eth_stats->q_ipackets[i]; 735 eth_stats->ibytes += eth_stats->q_ibytes[i]; 736 } 737 738 for (i = 0; i < pi->n_tx_qsets; i++) { 739 struct sge_eth_txq *txq = 740 &s->ethtxq[pi->first_txqset + i]; 741 742 eth_stats->q_opackets[i] = txq->stats.pkts; 743 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 744 } 745 return 0; 746 } 747 748 /* 749 * Reset port statistics. 750 */ 751 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 752 { 753 struct port_info *pi = eth_dev->data->dev_private; 754 struct adapter *adapter = pi->adapter; 755 struct sge *s = &adapter->sge; 756 unsigned int i; 757 758 cxgbe_stats_reset(pi); 759 for (i = 0; i < pi->n_rx_qsets; i++) { 760 struct sge_eth_rxq *rxq = 761 &s->ethrxq[pi->first_rxqset + i]; 762 763 rxq->stats.pkts = 0; 764 rxq->stats.rx_bytes = 0; 765 } 766 for (i = 0; i < pi->n_tx_qsets; i++) { 767 struct sge_eth_txq *txq = 768 &s->ethtxq[pi->first_txqset + i]; 769 770 txq->stats.pkts = 0; 771 txq->stats.tx_bytes = 0; 772 txq->stats.mapping_err = 0; 773 } 774 775 return 0; 776 } 777 778 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 779 struct rte_eth_fc_conf *fc_conf) 780 { 781 struct port_info *pi = eth_dev->data->dev_private; 782 struct link_config *lc = &pi->link_cfg; 783 int rx_pause, tx_pause; 784 785 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 786 rx_pause = lc->fc & PAUSE_RX; 787 tx_pause = lc->fc & PAUSE_TX; 788 789 if (rx_pause && tx_pause) 790 fc_conf->mode = RTE_FC_FULL; 791 else if (rx_pause) 792 fc_conf->mode = RTE_FC_RX_PAUSE; 793 else if (tx_pause) 794 fc_conf->mode = RTE_FC_TX_PAUSE; 795 else 796 fc_conf->mode = RTE_FC_NONE; 797 return 0; 798 } 799 800 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 801 struct rte_eth_fc_conf *fc_conf) 802 { 803 struct port_info *pi = eth_dev->data->dev_private; 804 struct adapter *adapter = pi->adapter; 805 struct link_config *lc = &pi->link_cfg; 806 807 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 808 if (fc_conf->autoneg) 809 lc->requested_fc |= PAUSE_AUTONEG; 810 else 811 lc->requested_fc &= ~PAUSE_AUTONEG; 812 } 813 814 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 815 (fc_conf->mode & RTE_FC_RX_PAUSE)) 816 lc->requested_fc |= PAUSE_RX; 817 else 818 lc->requested_fc &= ~PAUSE_RX; 819 820 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 821 (fc_conf->mode & RTE_FC_TX_PAUSE)) 822 lc->requested_fc |= PAUSE_TX; 823 else 824 lc->requested_fc &= ~PAUSE_TX; 825 826 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 827 &pi->link_cfg); 828 } 829 830 const uint32_t * 831 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 832 { 833 static const uint32_t ptypes[] = { 834 RTE_PTYPE_L3_IPV4, 835 RTE_PTYPE_L3_IPV6, 836 RTE_PTYPE_UNKNOWN 837 }; 838 839 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 840 return ptypes; 841 return NULL; 842 } 843 844 /* Update RSS hash configuration 845 */ 846 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 847 struct rte_eth_rss_conf *rss_conf) 848 { 849 struct port_info *pi = dev->data->dev_private; 850 struct adapter *adapter = pi->adapter; 851 int err; 852 853 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 854 if (err) 855 return err; 856 857 pi->rss_hf = rss_conf->rss_hf; 858 859 if (rss_conf->rss_key) { 860 u32 key[10], mod_key[10]; 861 int i, j; 862 863 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 864 865 for (i = 9, j = 0; i >= 0; i--, j++) 866 mod_key[j] = cpu_to_be32(key[i]); 867 868 t4_write_rss_key(adapter, mod_key, -1); 869 } 870 871 return 0; 872 } 873 874 /* Get RSS hash configuration 875 */ 876 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 877 struct rte_eth_rss_conf *rss_conf) 878 { 879 struct port_info *pi = dev->data->dev_private; 880 struct adapter *adapter = pi->adapter; 881 u64 rss_hf = 0; 882 u64 flags = 0; 883 int err; 884 885 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 886 &flags, NULL); 887 888 if (err) 889 return err; 890 891 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 892 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 893 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 894 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 895 } 896 897 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 898 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 899 900 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 901 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 902 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 903 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 904 } 905 906 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 907 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 908 909 rss_conf->rss_hf = rss_hf; 910 911 if (rss_conf->rss_key) { 912 u32 key[10], mod_key[10]; 913 int i, j; 914 915 t4_read_rss_key(adapter, key); 916 917 for (i = 9, j = 0; i >= 0; i--, j++) 918 mod_key[j] = be32_to_cpu(key[i]); 919 920 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 921 } 922 923 return 0; 924 } 925 926 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 927 struct rte_eth_rss_reta_entry64 *reta_conf, 928 uint16_t reta_size) 929 { 930 struct port_info *pi = dev->data->dev_private; 931 struct adapter *adapter = pi->adapter; 932 u16 i, idx, shift, *rss; 933 int ret; 934 935 if (!(adapter->flags & FULL_INIT_DONE)) 936 return -ENOMEM; 937 938 if (!reta_size || reta_size > pi->rss_size) 939 return -EINVAL; 940 941 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 942 if (!rss) 943 return -ENOMEM; 944 945 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 946 for (i = 0; i < reta_size; i++) { 947 idx = i / RTE_RETA_GROUP_SIZE; 948 shift = i % RTE_RETA_GROUP_SIZE; 949 if (!(reta_conf[idx].mask & (1ULL << shift))) 950 continue; 951 952 rss[i] = reta_conf[idx].reta[shift]; 953 } 954 955 ret = cxgbe_write_rss(pi, rss); 956 if (!ret) 957 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 958 959 rte_free(rss); 960 return ret; 961 } 962 963 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 964 struct rte_eth_rss_reta_entry64 *reta_conf, 965 uint16_t reta_size) 966 { 967 struct port_info *pi = dev->data->dev_private; 968 struct adapter *adapter = pi->adapter; 969 u16 i, idx, shift; 970 971 if (!(adapter->flags & FULL_INIT_DONE)) 972 return -ENOMEM; 973 974 if (!reta_size || reta_size > pi->rss_size) 975 return -EINVAL; 976 977 for (i = 0; i < reta_size; i++) { 978 idx = i / RTE_RETA_GROUP_SIZE; 979 shift = i % RTE_RETA_GROUP_SIZE; 980 if (!(reta_conf[idx].mask & (1ULL << shift))) 981 continue; 982 983 reta_conf[idx].reta[shift] = pi->rss[i]; 984 } 985 986 return 0; 987 } 988 989 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 990 { 991 RTE_SET_USED(dev); 992 return EEPROMSIZE; 993 } 994 995 /** 996 * eeprom_ptov - translate a physical EEPROM address to virtual 997 * @phys_addr: the physical EEPROM address 998 * @fn: the PCI function number 999 * @sz: size of function-specific area 1000 * 1001 * Translate a physical EEPROM address to virtual. The first 1K is 1002 * accessed through virtual addresses starting at 31K, the rest is 1003 * accessed through virtual addresses starting at 0. 1004 * 1005 * The mapping is as follows: 1006 * [0..1K) -> [31K..32K) 1007 * [1K..1K+A) -> [31K-A..31K) 1008 * [1K+A..ES) -> [0..ES-A-1K) 1009 * 1010 * where A = @fn * @sz, and ES = EEPROM size. 1011 */ 1012 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1013 { 1014 fn *= sz; 1015 if (phys_addr < 1024) 1016 return phys_addr + (31 << 10); 1017 if (phys_addr < 1024 + fn) 1018 return fn + phys_addr - 1024; 1019 if (phys_addr < EEPROMSIZE) 1020 return phys_addr - 1024 - fn; 1021 if (phys_addr < EEPROMVSIZE) 1022 return phys_addr - 1024; 1023 return -EINVAL; 1024 } 1025 1026 /* The next two routines implement eeprom read/write from physical addresses. 1027 */ 1028 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1029 { 1030 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1031 1032 if (vaddr >= 0) 1033 vaddr = t4_seeprom_read(adap, vaddr, v); 1034 return vaddr < 0 ? vaddr : 0; 1035 } 1036 1037 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1038 { 1039 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1040 1041 if (vaddr >= 0) 1042 vaddr = t4_seeprom_write(adap, vaddr, v); 1043 return vaddr < 0 ? vaddr : 0; 1044 } 1045 1046 #define EEPROM_MAGIC 0x38E2F10C 1047 1048 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1049 struct rte_dev_eeprom_info *e) 1050 { 1051 struct port_info *pi = dev->data->dev_private; 1052 struct adapter *adapter = pi->adapter; 1053 u32 i, err = 0; 1054 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1055 1056 if (!buf) 1057 return -ENOMEM; 1058 1059 e->magic = EEPROM_MAGIC; 1060 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1061 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1062 1063 if (!err) 1064 rte_memcpy(e->data, buf + e->offset, e->length); 1065 rte_free(buf); 1066 return err; 1067 } 1068 1069 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1070 struct rte_dev_eeprom_info *eeprom) 1071 { 1072 struct port_info *pi = dev->data->dev_private; 1073 struct adapter *adapter = pi->adapter; 1074 u8 *buf; 1075 int err = 0; 1076 u32 aligned_offset, aligned_len, *p; 1077 1078 if (eeprom->magic != EEPROM_MAGIC) 1079 return -EINVAL; 1080 1081 aligned_offset = eeprom->offset & ~3; 1082 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1083 1084 if (adapter->pf > 0) { 1085 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1086 1087 if (aligned_offset < start || 1088 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1089 return -EPERM; 1090 } 1091 1092 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1093 /* RMW possibly needed for first or last words. 1094 */ 1095 buf = rte_zmalloc(NULL, aligned_len, 0); 1096 if (!buf) 1097 return -ENOMEM; 1098 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1099 if (!err && aligned_len > 4) 1100 err = eeprom_rd_phys(adapter, 1101 aligned_offset + aligned_len - 4, 1102 (u32 *)&buf[aligned_len - 4]); 1103 if (err) 1104 goto out; 1105 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1106 eeprom->length); 1107 } else { 1108 buf = eeprom->data; 1109 } 1110 1111 err = t4_seeprom_wp(adapter, false); 1112 if (err) 1113 goto out; 1114 1115 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1116 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1117 aligned_offset += 4; 1118 } 1119 1120 if (!err) 1121 err = t4_seeprom_wp(adapter, true); 1122 out: 1123 if (buf != eeprom->data) 1124 rte_free(buf); 1125 return err; 1126 } 1127 1128 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1129 { 1130 struct port_info *pi = eth_dev->data->dev_private; 1131 struct adapter *adapter = pi->adapter; 1132 1133 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1134 } 1135 1136 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1137 struct rte_dev_reg_info *regs) 1138 { 1139 struct port_info *pi = eth_dev->data->dev_private; 1140 struct adapter *adapter = pi->adapter; 1141 1142 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1143 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1144 (1 << 16); 1145 1146 if (regs->data == NULL) { 1147 regs->length = cxgbe_get_regs_len(eth_dev); 1148 regs->width = sizeof(uint32_t); 1149 1150 return 0; 1151 } 1152 1153 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1154 1155 return 0; 1156 } 1157 1158 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1159 { 1160 struct port_info *pi = dev->data->dev_private; 1161 int ret; 1162 1163 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1164 if (ret < 0) { 1165 dev_err(adapter, "failed to set mac addr; err = %d\n", 1166 ret); 1167 return ret; 1168 } 1169 pi->xact_addr_filt = ret; 1170 return 0; 1171 } 1172 1173 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1174 .dev_start = cxgbe_dev_start, 1175 .dev_stop = cxgbe_dev_stop, 1176 .dev_close = cxgbe_dev_close, 1177 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1178 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1179 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1180 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1181 .dev_configure = cxgbe_dev_configure, 1182 .dev_infos_get = cxgbe_dev_info_get, 1183 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1184 .link_update = cxgbe_dev_link_update, 1185 .dev_set_link_up = cxgbe_dev_set_link_up, 1186 .dev_set_link_down = cxgbe_dev_set_link_down, 1187 .mtu_set = cxgbe_dev_mtu_set, 1188 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1189 .tx_queue_start = cxgbe_dev_tx_queue_start, 1190 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1191 .tx_queue_release = cxgbe_dev_tx_queue_release, 1192 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1193 .rx_queue_start = cxgbe_dev_rx_queue_start, 1194 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1195 .rx_queue_release = cxgbe_dev_rx_queue_release, 1196 .filter_ctrl = cxgbe_dev_filter_ctrl, 1197 .stats_get = cxgbe_dev_stats_get, 1198 .stats_reset = cxgbe_dev_stats_reset, 1199 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1200 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1201 .get_eeprom_length = cxgbe_get_eeprom_length, 1202 .get_eeprom = cxgbe_get_eeprom, 1203 .set_eeprom = cxgbe_set_eeprom, 1204 .get_reg = cxgbe_get_regs, 1205 .rss_hash_update = cxgbe_dev_rss_hash_update, 1206 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1207 .mac_addr_set = cxgbe_mac_addr_set, 1208 .reta_update = cxgbe_dev_rss_reta_update, 1209 .reta_query = cxgbe_dev_rss_reta_query, 1210 }; 1211 1212 /* 1213 * Initialize driver 1214 * It returns 0 on success. 1215 */ 1216 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1217 { 1218 struct rte_pci_device *pci_dev; 1219 struct port_info *pi = eth_dev->data->dev_private; 1220 struct adapter *adapter = NULL; 1221 char name[RTE_ETH_NAME_MAX_LEN]; 1222 int err = 0; 1223 1224 CXGBE_FUNC_TRACE(); 1225 1226 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1227 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1228 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1229 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1230 1231 /* for secondary processes, we attach to ethdevs allocated by primary 1232 * and do minimal initialization. 1233 */ 1234 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1235 int i; 1236 1237 for (i = 1; i < MAX_NPORTS; i++) { 1238 struct rte_eth_dev *rest_eth_dev; 1239 char namei[RTE_ETH_NAME_MAX_LEN]; 1240 1241 snprintf(namei, sizeof(namei), "%s_%d", 1242 pci_dev->device.name, i); 1243 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1244 if (rest_eth_dev) { 1245 rest_eth_dev->device = &pci_dev->device; 1246 rest_eth_dev->dev_ops = 1247 eth_dev->dev_ops; 1248 rest_eth_dev->rx_pkt_burst = 1249 eth_dev->rx_pkt_burst; 1250 rest_eth_dev->tx_pkt_burst = 1251 eth_dev->tx_pkt_burst; 1252 rte_eth_dev_probing_finish(rest_eth_dev); 1253 } 1254 } 1255 return 0; 1256 } 1257 1258 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1259 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1260 if (!adapter) 1261 return -1; 1262 1263 adapter->use_unpacked_mode = 1; 1264 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1265 if (!adapter->regs) { 1266 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1267 err = -ENOMEM; 1268 goto out_free_adapter; 1269 } 1270 adapter->pdev = pci_dev; 1271 adapter->eth_dev = eth_dev; 1272 pi->adapter = adapter; 1273 1274 cxgbe_process_devargs(adapter); 1275 1276 err = cxgbe_probe(adapter); 1277 if (err) { 1278 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1279 __func__, err); 1280 goto out_free_adapter; 1281 } 1282 1283 return 0; 1284 1285 out_free_adapter: 1286 rte_free(adapter); 1287 return err; 1288 } 1289 1290 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1291 { 1292 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1293 uint16_t port_id; 1294 1295 /* Free up other ports and all resources */ 1296 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1297 rte_eth_dev_close(port_id); 1298 1299 return 0; 1300 } 1301 1302 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1303 struct rte_pci_device *pci_dev) 1304 { 1305 return rte_eth_dev_pci_generic_probe(pci_dev, 1306 sizeof(struct port_info), eth_cxgbe_dev_init); 1307 } 1308 1309 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1310 { 1311 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1312 } 1313 1314 static struct rte_pci_driver rte_cxgbe_pmd = { 1315 .id_table = cxgb4_pci_tbl, 1316 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1317 .probe = eth_cxgbe_pci_probe, 1318 .remove = eth_cxgbe_pci_remove, 1319 }; 1320 1321 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1322 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1323 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1324 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1325 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1326 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1327 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1328 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1329 RTE_LOG_REGISTER(cxgbe_logtype, pmd.net.cxgbe, NOTICE); 1330 RTE_LOG_REGISTER(cxgbe_mbox_logtype, pmd.net.cxgbe.mbox, NOTICE); 1331