1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <bus_pci_driver.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <ethdev_driver.h> 31 #include <ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <dev_driver.h> 35 36 #include "cxgbe.h" 37 #include "cxgbe_pfvf.h" 38 #include "cxgbe_flow.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "base/t4_pci_id_tbl.h" 60 61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 62 uint16_t nb_pkts) 63 { 64 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 65 uint16_t pkts_sent, pkts_remain; 66 uint16_t total_sent = 0; 67 uint16_t idx = 0; 68 int ret = 0; 69 70 t4_os_lock(&txq->txq_lock); 71 /* free up desc from already completed tx */ 72 reclaim_completed_tx(&txq->q); 73 if (unlikely(!nb_pkts)) 74 goto out_unlock; 75 76 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 77 while (total_sent < nb_pkts) { 78 pkts_remain = nb_pkts - total_sent; 79 80 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 81 idx = total_sent + pkts_sent; 82 if ((idx + 1) < nb_pkts) 83 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 84 volatile void *)); 85 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 86 if (ret < 0) 87 break; 88 } 89 if (!pkts_sent) 90 break; 91 total_sent += pkts_sent; 92 /* reclaim as much as possible */ 93 reclaim_completed_tx(&txq->q); 94 } 95 96 out_unlock: 97 t4_os_unlock(&txq->txq_lock); 98 return total_sent; 99 } 100 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 102 uint16_t nb_pkts) 103 { 104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 105 unsigned int work_done; 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 return work_done; 111 } 112 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 114 struct rte_eth_dev_info *device_info) 115 { 116 struct port_info *pi = eth_dev->data->dev_private; 117 struct adapter *adapter = pi->adapter; 118 119 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 120 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 121 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 122 .nb_align = 1, 123 }; 124 125 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 126 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 127 device_info->max_rx_queues = adapter->sge.max_ethqsets; 128 device_info->max_tx_queues = adapter->sge.max_ethqsets; 129 device_info->max_mac_addrs = 1; 130 /* XXX: For now we support one MAC/port */ 131 device_info->max_vfs = adapter->params.arch.vfcount; 132 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 133 134 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 135 136 device_info->rx_queue_offload_capa = 0UL; 137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 138 139 device_info->tx_queue_offload_capa = 0UL; 140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 141 142 device_info->reta_size = pi->rss_size; 143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 145 146 device_info->rx_desc_lim = cxgbe_desc_lim; 147 device_info->tx_desc_lim = cxgbe_desc_lim; 148 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 149 150 return 0; 151 } 152 153 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 154 { 155 struct port_info *pi = eth_dev->data->dev_private; 156 struct adapter *adapter = pi->adapter; 157 int ret; 158 159 if (adapter->params.rawf_size != 0) { 160 ret = cxgbe_mpstcam_rawf_enable(pi); 161 if (ret < 0) 162 return ret; 163 } 164 165 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 166 1, -1, 1, -1, false); 167 } 168 169 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 170 { 171 struct port_info *pi = eth_dev->data->dev_private; 172 struct adapter *adapter = pi->adapter; 173 int ret; 174 175 if (adapter->params.rawf_size != 0) { 176 ret = cxgbe_mpstcam_rawf_disable(pi); 177 if (ret < 0) 178 return ret; 179 } 180 181 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 182 0, -1, 1, -1, false); 183 } 184 185 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 186 { 187 struct port_info *pi = eth_dev->data->dev_private; 188 struct adapter *adapter = pi->adapter; 189 190 /* TODO: address filters ?? */ 191 192 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 193 -1, 1, 1, -1, false); 194 } 195 196 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 197 { 198 struct port_info *pi = eth_dev->data->dev_private; 199 struct adapter *adapter = pi->adapter; 200 201 /* TODO: address filters ?? */ 202 203 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 204 -1, 0, 1, -1, false); 205 } 206 207 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 208 int wait_to_complete) 209 { 210 struct port_info *pi = eth_dev->data->dev_private; 211 unsigned int i, work_done, budget = 32; 212 struct link_config *lc = &pi->link_cfg; 213 struct adapter *adapter = pi->adapter; 214 struct rte_eth_link new_link = { 0 }; 215 u8 old_link = pi->link_cfg.link_ok; 216 struct sge *s = &adapter->sge; 217 218 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 219 if (!s->fw_evtq.desc) 220 break; 221 222 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 223 224 /* Exit if link status changed or always forced up */ 225 if (pi->link_cfg.link_ok != old_link || 226 cxgbe_force_linkup(adapter)) 227 break; 228 229 if (!wait_to_complete) 230 break; 231 232 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 233 } 234 235 new_link.link_status = cxgbe_force_linkup(adapter) ? 236 RTE_ETH_LINK_UP : pi->link_cfg.link_ok; 237 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; 238 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 239 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps); 240 241 return rte_eth_linkstatus_set(eth_dev, &new_link); 242 } 243 244 /** 245 * Set device link up. 246 */ 247 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 248 { 249 struct port_info *pi = dev->data->dev_private; 250 struct adapter *adapter = pi->adapter; 251 unsigned int work_done, budget = 32; 252 struct sge *s = &adapter->sge; 253 int ret; 254 255 if (!s->fw_evtq.desc) 256 return -ENOMEM; 257 258 /* Flush all link events */ 259 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 260 261 /* If link already up, nothing to do */ 262 if (pi->link_cfg.link_ok) 263 return 0; 264 265 ret = cxgbe_set_link_status(pi, true); 266 if (ret) 267 return ret; 268 269 cxgbe_dev_link_update(dev, 1); 270 return 0; 271 } 272 273 /** 274 * Set device link down. 275 */ 276 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 277 { 278 struct port_info *pi = dev->data->dev_private; 279 struct adapter *adapter = pi->adapter; 280 unsigned int work_done, budget = 32; 281 struct sge *s = &adapter->sge; 282 int ret; 283 284 if (!s->fw_evtq.desc) 285 return -ENOMEM; 286 287 /* Flush all link events */ 288 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 289 290 /* If link already down, nothing to do */ 291 if (!pi->link_cfg.link_ok) 292 return 0; 293 294 ret = cxgbe_set_link_status(pi, false); 295 if (ret) 296 return ret; 297 298 cxgbe_dev_link_update(dev, 0); 299 return 0; 300 } 301 302 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 303 { 304 struct port_info *pi = eth_dev->data->dev_private; 305 struct adapter *adapter = pi->adapter; 306 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 307 308 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 309 -1, -1, true); 310 } 311 312 /* 313 * Stop device. 314 */ 315 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 316 { 317 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 318 struct adapter *adapter = pi->adapter; 319 u8 i; 320 321 CXGBE_FUNC_TRACE(); 322 323 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 324 return 0; 325 326 if (!(adapter->flags & FULL_INIT_DONE)) 327 return 0; 328 329 if (!pi->viid) 330 return 0; 331 332 cxgbe_down(pi); 333 t4_sge_eth_release_queues(pi); 334 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 335 pi->viid = 0; 336 337 /* Free up the adapter-wide resources only after all the ports 338 * under this PF have been closed. 339 */ 340 for_each_port(adapter, i) { 341 temp_pi = adap2pinfo(adapter, i); 342 if (temp_pi->viid) 343 return 0; 344 } 345 346 cxgbe_close(adapter); 347 rte_free(adapter); 348 349 return 0; 350 } 351 352 /* Start the device. 353 * It returns 0 on success. 354 */ 355 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 356 { 357 struct port_info *pi = eth_dev->data->dev_private; 358 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 359 struct adapter *adapter = pi->adapter; 360 int err = 0, i; 361 362 CXGBE_FUNC_TRACE(); 363 364 /* 365 * If we don't have a connection to the firmware there's nothing we 366 * can do. 367 */ 368 if (!(adapter->flags & FW_OK)) { 369 err = -ENXIO; 370 goto out; 371 } 372 373 if (!(adapter->flags & FULL_INIT_DONE)) { 374 err = cxgbe_up(adapter); 375 if (err < 0) 376 goto out; 377 } 378 379 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 380 eth_dev->data->scattered_rx = 1; 381 else 382 eth_dev->data->scattered_rx = 0; 383 384 cxgbe_enable_rx_queues(pi); 385 386 err = cxgbe_setup_rss(pi); 387 if (err) 388 goto out; 389 390 for (i = 0; i < pi->n_tx_qsets; i++) { 391 err = cxgbe_dev_tx_queue_start(eth_dev, i); 392 if (err) 393 goto out; 394 } 395 396 for (i = 0; i < pi->n_rx_qsets; i++) { 397 err = cxgbe_dev_rx_queue_start(eth_dev, i); 398 if (err) 399 goto out; 400 } 401 402 err = cxgbe_link_start(pi); 403 if (err) 404 goto out; 405 406 out: 407 return err; 408 } 409 410 /* 411 * Stop device: disable rx and tx functions to allow for reconfiguring. 412 */ 413 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 414 { 415 struct port_info *pi = eth_dev->data->dev_private; 416 struct adapter *adapter = pi->adapter; 417 uint16_t i; 418 419 CXGBE_FUNC_TRACE(); 420 421 if (!(adapter->flags & FULL_INIT_DONE)) 422 return 0; 423 424 cxgbe_down(pi); 425 426 /* 427 * We clear queues only if both tx and rx path of the port 428 * have been disabled 429 */ 430 t4_sge_eth_clear_queues(pi); 431 eth_dev->data->scattered_rx = 0; 432 433 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) 434 eth_dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 435 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 436 eth_dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 437 438 return 0; 439 } 440 441 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 442 { 443 struct port_info *pi = eth_dev->data->dev_private; 444 struct adapter *adapter = pi->adapter; 445 int err; 446 447 CXGBE_FUNC_TRACE(); 448 449 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 450 eth_dev->data->dev_conf.rxmode.offloads |= 451 RTE_ETH_RX_OFFLOAD_RSS_HASH; 452 453 if (!(adapter->flags & FW_QUEUE_BOUND)) { 454 err = cxgbe_setup_sge_fwevtq(adapter); 455 if (err) 456 return err; 457 adapter->flags |= FW_QUEUE_BOUND; 458 if (is_pf4(adapter)) { 459 err = cxgbe_setup_sge_ctrl_txq(adapter); 460 if (err) 461 return err; 462 } 463 } 464 465 err = cxgbe_cfg_queue_count(eth_dev); 466 if (err) 467 return err; 468 469 return 0; 470 } 471 472 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 473 { 474 int ret; 475 struct sge_eth_txq *txq = (struct sge_eth_txq *) 476 (eth_dev->data->tx_queues[tx_queue_id]); 477 478 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 479 480 ret = t4_sge_eth_txq_start(txq); 481 if (ret == 0) 482 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 483 484 return ret; 485 } 486 487 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 488 { 489 int ret; 490 struct sge_eth_txq *txq = (struct sge_eth_txq *) 491 (eth_dev->data->tx_queues[tx_queue_id]); 492 493 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 494 495 ret = t4_sge_eth_txq_stop(txq); 496 if (ret == 0) 497 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 498 499 return ret; 500 } 501 502 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 503 uint16_t queue_idx, uint16_t nb_desc, 504 unsigned int socket_id, 505 const struct rte_eth_txconf *tx_conf __rte_unused) 506 { 507 struct port_info *pi = eth_dev->data->dev_private; 508 struct adapter *adapter = pi->adapter; 509 struct sge *s = &adapter->sge; 510 unsigned int temp_nb_desc; 511 struct sge_eth_txq *txq; 512 int err = 0; 513 514 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 515 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 516 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 517 socket_id, pi->first_txqset); 518 519 /* Free up the existing queue */ 520 if (eth_dev->data->tx_queues[queue_idx]) { 521 cxgbe_dev_tx_queue_release(eth_dev, queue_idx); 522 eth_dev->data->tx_queues[queue_idx] = NULL; 523 } 524 525 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 526 527 /* Sanity Checking 528 * 529 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 530 */ 531 temp_nb_desc = nb_desc; 532 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 533 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 534 __func__, CXGBE_MIN_RING_DESC_SIZE, 535 CXGBE_DEFAULT_TX_DESC_SIZE); 536 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 537 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 538 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 539 __func__, CXGBE_MIN_RING_DESC_SIZE, 540 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 541 return -(EINVAL); 542 } 543 544 txq->q.size = temp_nb_desc; 545 546 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 547 s->fw_evtq.cntxt_id, socket_id); 548 549 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 550 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 551 return err; 552 } 553 554 void cxgbe_dev_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 555 { 556 struct sge_eth_txq *txq = eth_dev->data->tx_queues[qid]; 557 558 if (txq) { 559 struct port_info *pi = (struct port_info *) 560 (txq->eth_dev->data->dev_private); 561 struct adapter *adap = pi->adapter; 562 563 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 564 __func__, pi->port_id, txq->q.cntxt_id); 565 566 t4_sge_eth_txq_release(adap, txq); 567 } 568 } 569 570 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 571 { 572 struct port_info *pi = eth_dev->data->dev_private; 573 struct adapter *adap = pi->adapter; 574 struct sge_eth_rxq *rxq; 575 int ret; 576 577 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 578 __func__, pi->port_id, rx_queue_id); 579 580 rxq = eth_dev->data->rx_queues[rx_queue_id]; 581 ret = t4_sge_eth_rxq_start(adap, rxq); 582 if (ret == 0) 583 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 584 585 return ret; 586 } 587 588 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 589 { 590 struct port_info *pi = eth_dev->data->dev_private; 591 struct adapter *adap = pi->adapter; 592 struct sge_eth_rxq *rxq; 593 int ret; 594 595 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 596 __func__, pi->port_id, rx_queue_id); 597 598 rxq = eth_dev->data->rx_queues[rx_queue_id]; 599 ret = t4_sge_eth_rxq_stop(adap, rxq); 600 if (ret == 0) 601 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 602 603 return ret; 604 } 605 606 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 607 uint16_t queue_idx, uint16_t nb_desc, 608 unsigned int socket_id, 609 const struct rte_eth_rxconf *rx_conf __rte_unused, 610 struct rte_mempool *mp) 611 { 612 unsigned int pkt_len = eth_dev->data->mtu + RTE_ETHER_HDR_LEN + 613 RTE_ETHER_CRC_LEN; 614 struct port_info *pi = eth_dev->data->dev_private; 615 struct adapter *adapter = pi->adapter; 616 struct rte_eth_dev_info dev_info; 617 struct sge *s = &adapter->sge; 618 unsigned int temp_nb_desc; 619 int err = 0, msi_idx = 0; 620 struct sge_eth_rxq *rxq; 621 622 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 623 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 624 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 625 socket_id, mp); 626 627 err = cxgbe_dev_info_get(eth_dev, &dev_info); 628 if (err != 0) { 629 dev_err(adap, "%s: error during getting ethernet device info", 630 __func__); 631 return err; 632 } 633 634 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 635 if ((pkt_len < dev_info.min_rx_bufsize) || 636 (pkt_len > dev_info.max_rx_pktlen)) { 637 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 638 __func__, dev_info.min_rx_bufsize, 639 dev_info.max_rx_pktlen); 640 return -EINVAL; 641 } 642 643 /* Free up the existing queue */ 644 if (eth_dev->data->rx_queues[queue_idx]) { 645 cxgbe_dev_rx_queue_release(eth_dev, queue_idx); 646 eth_dev->data->rx_queues[queue_idx] = NULL; 647 } 648 649 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 650 651 /* Sanity Checking 652 * 653 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 654 */ 655 temp_nb_desc = nb_desc; 656 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 657 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 658 __func__, CXGBE_MIN_RING_DESC_SIZE, 659 CXGBE_DEFAULT_RX_DESC_SIZE); 660 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 661 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 662 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 663 __func__, CXGBE_MIN_RING_DESC_SIZE, 664 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 665 return -(EINVAL); 666 } 667 668 rxq->rspq.size = temp_nb_desc; 669 rxq->fl.size = temp_nb_desc; 670 671 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 672 &rxq->fl, NULL, 673 is_pf4(adapter) ? 674 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 675 queue_idx, socket_id); 676 677 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 678 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 679 rxq->rspq.abs_id); 680 return err; 681 } 682 683 void cxgbe_dev_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 684 { 685 struct sge_eth_rxq *rxq = eth_dev->data->rx_queues[qid]; 686 687 if (rxq) { 688 struct port_info *pi = (struct port_info *) 689 (rxq->rspq.eth_dev->data->dev_private); 690 struct adapter *adap = pi->adapter; 691 692 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 693 __func__, pi->port_id, rxq->rspq.cntxt_id); 694 695 t4_sge_eth_rxq_release(adap, rxq); 696 } 697 } 698 699 /* 700 * Get port statistics. 701 */ 702 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 703 struct rte_eth_stats *eth_stats) 704 { 705 struct port_info *pi = eth_dev->data->dev_private; 706 struct adapter *adapter = pi->adapter; 707 struct sge *s = &adapter->sge; 708 struct port_stats ps; 709 unsigned int i; 710 711 cxgbe_stats_get(pi, &ps); 712 713 /* RX Stats */ 714 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 715 ps.rx_ovflow2 + ps.rx_ovflow3 + 716 ps.rx_trunc0 + ps.rx_trunc1 + 717 ps.rx_trunc2 + ps.rx_trunc3; 718 for (i = 0; i < NCHAN; i++) 719 eth_stats->imissed += ps.rx_tp_tnl_cong_drops[i]; 720 721 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 722 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 723 ps.rx_len_err; 724 725 /* TX Stats */ 726 eth_stats->opackets = ps.tx_frames; 727 eth_stats->obytes = ps.tx_octets; 728 eth_stats->oerrors = ps.tx_error_frames; 729 730 for (i = 0; i < pi->n_rx_qsets; i++) { 731 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 732 733 eth_stats->ipackets += rxq->stats.pkts; 734 eth_stats->ibytes += rxq->stats.rx_bytes; 735 } 736 737 return 0; 738 } 739 740 /* 741 * Reset port statistics. 742 */ 743 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 744 { 745 struct port_info *pi = eth_dev->data->dev_private; 746 struct adapter *adapter = pi->adapter; 747 struct sge *s = &adapter->sge; 748 unsigned int i; 749 750 cxgbe_stats_reset(pi); 751 for (i = 0; i < pi->n_rx_qsets; i++) { 752 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 753 754 memset(&rxq->stats, 0, sizeof(rxq->stats)); 755 } 756 for (i = 0; i < pi->n_tx_qsets; i++) { 757 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i]; 758 759 memset(&txq->stats, 0, sizeof(txq->stats)); 760 } 761 762 return 0; 763 } 764 765 /* Store extended statistics names and its offset in stats structure */ 766 struct cxgbe_dev_xstats_name_off { 767 char name[RTE_ETH_XSTATS_NAME_SIZE]; 768 unsigned int offset; 769 }; 770 771 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = { 772 {"packets", offsetof(struct sge_eth_rx_stats, pkts)}, 773 {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)}, 774 {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)}, 775 {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)}, 776 {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)}, 777 }; 778 779 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = { 780 {"packets", offsetof(struct sge_eth_tx_stats, pkts)}, 781 {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)}, 782 {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)}, 783 {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)}, 784 {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)}, 785 {"packet_mapping_errors", 786 offsetof(struct sge_eth_tx_stats, mapping_err)}, 787 {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)}, 788 {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)}, 789 }; 790 791 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = { 792 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 793 {"tx_packets", offsetof(struct port_stats, tx_frames)}, 794 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 795 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 796 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 797 {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)}, 798 {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)}, 799 {"tx_size_65_to_127_packets", 800 offsetof(struct port_stats, tx_frames_65_127)}, 801 {"tx_size_128_to_255_packets", 802 offsetof(struct port_stats, tx_frames_128_255)}, 803 {"tx_size_256_to_511_packets", 804 offsetof(struct port_stats, tx_frames_256_511)}, 805 {"tx_size_512_to_1023_packets", 806 offsetof(struct port_stats, tx_frames_512_1023)}, 807 {"tx_size_1024_to_1518_packets", 808 offsetof(struct port_stats, tx_frames_1024_1518)}, 809 {"tx_size_1519_to_max_packets", 810 offsetof(struct port_stats, tx_frames_1519_max)}, 811 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 812 {"tx_pause_frames", offsetof(struct port_stats, tx_pause)}, 813 {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)}, 814 {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)}, 815 {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)}, 816 {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)}, 817 {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)}, 818 {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)}, 819 {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)}, 820 {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)}, 821 {"rx_bytes", offsetof(struct port_stats, rx_octets)}, 822 {"rx_packets", offsetof(struct port_stats, rx_frames)}, 823 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 824 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 825 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 826 {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)}, 827 {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)}, 828 {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)}, 829 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 830 {"rx_symbol_error_packets", 831 offsetof(struct port_stats, rx_symbol_err)}, 832 {"rx_short_packets", offsetof(struct port_stats, rx_runt)}, 833 {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)}, 834 {"rx_size_65_to_127_packets", 835 offsetof(struct port_stats, rx_frames_65_127)}, 836 {"rx_size_128_to_255_packets", 837 offsetof(struct port_stats, rx_frames_128_255)}, 838 {"rx_size_256_to_511_packets", 839 offsetof(struct port_stats, rx_frames_256_511)}, 840 {"rx_size_512_to_1023_packets", 841 offsetof(struct port_stats, rx_frames_512_1023)}, 842 {"rx_size_1024_to_1518_packets", 843 offsetof(struct port_stats, rx_frames_1024_1518)}, 844 {"rx_size_1519_to_max_packets", 845 offsetof(struct port_stats, rx_frames_1519_max)}, 846 {"rx_pause_packets", offsetof(struct port_stats, rx_pause)}, 847 {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)}, 848 {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)}, 849 {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)}, 850 {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)}, 851 {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)}, 852 {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)}, 853 {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)}, 854 {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)}, 855 {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)}, 856 {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)}, 857 {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)}, 858 {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)}, 859 {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)}, 860 {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)}, 861 {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)}, 862 {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)}, 863 {"rx_tp_tnl_cong_drops0", 864 offsetof(struct port_stats, rx_tp_tnl_cong_drops[0])}, 865 {"rx_tp_tnl_cong_drops1", 866 offsetof(struct port_stats, rx_tp_tnl_cong_drops[1])}, 867 {"rx_tp_tnl_cong_drops2", 868 offsetof(struct port_stats, rx_tp_tnl_cong_drops[2])}, 869 {"rx_tp_tnl_cong_drops3", 870 offsetof(struct port_stats, rx_tp_tnl_cong_drops[3])}, 871 }; 872 873 static const struct cxgbe_dev_xstats_name_off 874 cxgbevf_dev_port_stats_strings[] = { 875 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 876 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 877 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 878 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 879 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 880 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 881 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 882 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 883 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 884 }; 885 886 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings) 887 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings) 888 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings) 889 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings) 890 891 static u16 cxgbe_dev_xstats_count(struct port_info *pi) 892 { 893 u16 count; 894 895 count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) + 896 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS); 897 898 if (is_pf4(pi->adapter) != 0) 899 count += CXGBE_NB_PORT_STATS; 900 else 901 count += CXGBEVF_NB_PORT_STATS; 902 903 return count; 904 } 905 906 static int cxgbe_dev_xstats(struct rte_eth_dev *dev, 907 struct rte_eth_xstat_name *xstats_names, 908 struct rte_eth_xstat *xstats, unsigned int size) 909 { 910 const struct cxgbe_dev_xstats_name_off *xstats_str; 911 struct port_info *pi = dev->data->dev_private; 912 struct adapter *adap = pi->adapter; 913 struct sge *s = &adap->sge; 914 u16 count, i, qid, nstats; 915 struct port_stats ps; 916 u64 *stats_ptr; 917 918 count = cxgbe_dev_xstats_count(pi); 919 if (size < count) 920 return count; 921 922 if (is_pf4(adap) != 0) { 923 /* port stats for PF*/ 924 cxgbe_stats_get(pi, &ps); 925 xstats_str = cxgbe_dev_port_stats_strings; 926 nstats = CXGBE_NB_PORT_STATS; 927 } else { 928 /* port stats for VF*/ 929 cxgbevf_stats_get(pi, &ps); 930 xstats_str = cxgbevf_dev_port_stats_strings; 931 nstats = CXGBEVF_NB_PORT_STATS; 932 } 933 934 count = 0; 935 for (i = 0; i < nstats; i++, count++) { 936 if (xstats_names != NULL) 937 snprintf(xstats_names[count].name, 938 sizeof(xstats_names[count].name), 939 "%s", xstats_str[i].name); 940 if (xstats != NULL) { 941 stats_ptr = RTE_PTR_ADD(&ps, 942 xstats_str[i].offset); 943 xstats[count].value = *stats_ptr; 944 xstats[count].id = count; 945 } 946 } 947 948 /* per-txq stats */ 949 xstats_str = cxgbe_dev_txq_stats_strings; 950 for (qid = 0; qid < pi->n_tx_qsets; qid++) { 951 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid]; 952 953 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) { 954 if (xstats_names != NULL) 955 snprintf(xstats_names[count].name, 956 sizeof(xstats_names[count].name), 957 "tx_q%u_%s", 958 qid, xstats_str[i].name); 959 if (xstats != NULL) { 960 stats_ptr = RTE_PTR_ADD(&txq->stats, 961 xstats_str[i].offset); 962 xstats[count].value = *stats_ptr; 963 xstats[count].id = count; 964 } 965 } 966 } 967 968 /* per-rxq stats */ 969 xstats_str = cxgbe_dev_rxq_stats_strings; 970 for (qid = 0; qid < pi->n_rx_qsets; qid++) { 971 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid]; 972 973 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) { 974 if (xstats_names != NULL) 975 snprintf(xstats_names[count].name, 976 sizeof(xstats_names[count].name), 977 "rx_q%u_%s", 978 qid, xstats_str[i].name); 979 if (xstats != NULL) { 980 stats_ptr = RTE_PTR_ADD(&rxq->stats, 981 xstats_str[i].offset); 982 xstats[count].value = *stats_ptr; 983 xstats[count].id = count; 984 } 985 } 986 } 987 988 return count; 989 } 990 991 /* Get port extended statistics by ID. */ 992 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 993 const uint64_t *ids, uint64_t *values, 994 unsigned int n) 995 { 996 struct port_info *pi = dev->data->dev_private; 997 struct rte_eth_xstat *xstats_copy; 998 u16 count, i; 999 int ret = 0; 1000 1001 count = cxgbe_dev_xstats_count(pi); 1002 if (ids == NULL || values == NULL) 1003 return count; 1004 1005 xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0); 1006 if (xstats_copy == NULL) 1007 return -ENOMEM; 1008 1009 cxgbe_dev_xstats(dev, NULL, xstats_copy, count); 1010 1011 for (i = 0; i < n; i++) { 1012 if (ids[i] >= count) { 1013 ret = -EINVAL; 1014 goto out_err; 1015 } 1016 values[i] = xstats_copy[ids[i]].value; 1017 } 1018 1019 ret = n; 1020 1021 out_err: 1022 rte_free(xstats_copy); 1023 return ret; 1024 } 1025 1026 /* Get names of port extended statistics by ID. */ 1027 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1028 const uint64_t *ids, 1029 struct rte_eth_xstat_name *xnames, 1030 unsigned int n) 1031 { 1032 struct port_info *pi = dev->data->dev_private; 1033 struct rte_eth_xstat_name *xnames_copy; 1034 u16 count, i; 1035 int ret = 0; 1036 1037 count = cxgbe_dev_xstats_count(pi); 1038 if (ids == NULL || xnames == NULL) 1039 return count; 1040 1041 xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0); 1042 if (xnames_copy == NULL) 1043 return -ENOMEM; 1044 1045 cxgbe_dev_xstats(dev, xnames_copy, NULL, count); 1046 1047 for (i = 0; i < n; i++) { 1048 if (ids[i] >= count) { 1049 ret = -EINVAL; 1050 goto out_err; 1051 } 1052 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name, 1053 sizeof(xnames[i].name)); 1054 } 1055 1056 ret = n; 1057 1058 out_err: 1059 rte_free(xnames_copy); 1060 return ret; 1061 } 1062 1063 /* Get port extended statistics. */ 1064 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev, 1065 struct rte_eth_xstat *xstats, unsigned int n) 1066 { 1067 return cxgbe_dev_xstats(dev, NULL, xstats, n); 1068 } 1069 1070 /* Get names of port extended statistics. */ 1071 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 1072 struct rte_eth_xstat_name *xstats_names, 1073 unsigned int n) 1074 { 1075 return cxgbe_dev_xstats(dev, xstats_names, NULL, n); 1076 } 1077 1078 /* Reset port extended statistics. */ 1079 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1080 { 1081 return cxgbe_dev_stats_reset(dev); 1082 } 1083 1084 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1085 struct rte_eth_fc_conf *fc_conf) 1086 { 1087 struct port_info *pi = eth_dev->data->dev_private; 1088 struct link_config *lc = &pi->link_cfg; 1089 u8 rx_pause = 0, tx_pause = 0; 1090 u32 caps = lc->link_caps; 1091 1092 if (caps & FW_PORT_CAP32_ANEG) 1093 fc_conf->autoneg = 1; 1094 1095 if (caps & FW_PORT_CAP32_FC_TX) 1096 tx_pause = 1; 1097 1098 if (caps & FW_PORT_CAP32_FC_RX) 1099 rx_pause = 1; 1100 1101 if (rx_pause && tx_pause) 1102 fc_conf->mode = RTE_ETH_FC_FULL; 1103 else if (rx_pause) 1104 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 1105 else if (tx_pause) 1106 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1107 else 1108 fc_conf->mode = RTE_ETH_FC_NONE; 1109 return 0; 1110 } 1111 1112 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1113 struct rte_eth_fc_conf *fc_conf) 1114 { 1115 struct port_info *pi = eth_dev->data->dev_private; 1116 struct link_config *lc = &pi->link_cfg; 1117 u32 new_caps = lc->admin_caps; 1118 u8 tx_pause = 0, rx_pause = 0; 1119 int ret; 1120 1121 if (fc_conf->mode == RTE_ETH_FC_FULL) { 1122 tx_pause = 1; 1123 rx_pause = 1; 1124 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE) { 1125 tx_pause = 1; 1126 } else if (fc_conf->mode == RTE_ETH_FC_RX_PAUSE) { 1127 rx_pause = 1; 1128 } 1129 1130 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause, 1131 rx_pause, &new_caps); 1132 if (ret != 0) 1133 return ret; 1134 1135 if (!fc_conf->autoneg) { 1136 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE) 1137 new_caps |= FW_PORT_CAP32_FORCE_PAUSE; 1138 } else { 1139 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE; 1140 } 1141 1142 if (new_caps != lc->admin_caps) { 1143 ret = t4_link_l1cfg(pi, new_caps); 1144 if (ret == 0) 1145 lc->admin_caps = new_caps; 1146 } 1147 1148 return ret; 1149 } 1150 1151 const uint32_t * 1152 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev, 1153 size_t *no_of_elements) 1154 { 1155 static const uint32_t ptypes[] = { 1156 RTE_PTYPE_L3_IPV4, 1157 RTE_PTYPE_L3_IPV6, 1158 }; 1159 1160 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) { 1161 *no_of_elements = RTE_DIM(ptypes); 1162 return ptypes; 1163 } 1164 return NULL; 1165 } 1166 1167 /* Update RSS hash configuration 1168 */ 1169 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 1170 struct rte_eth_rss_conf *rss_conf) 1171 { 1172 struct port_info *pi = dev->data->dev_private; 1173 struct adapter *adapter = pi->adapter; 1174 int err; 1175 1176 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 1177 if (err) 1178 return err; 1179 1180 pi->rss_hf = rss_conf->rss_hf; 1181 1182 if (rss_conf->rss_key) { 1183 u32 key[10], mod_key[10]; 1184 int i, j; 1185 1186 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1187 1188 for (i = 9, j = 0; i >= 0; i--, j++) 1189 mod_key[j] = cpu_to_be32(key[i]); 1190 1191 t4_write_rss_key(adapter, mod_key, -1); 1192 } 1193 1194 return 0; 1195 } 1196 1197 /* Get RSS hash configuration 1198 */ 1199 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1200 struct rte_eth_rss_conf *rss_conf) 1201 { 1202 struct port_info *pi = dev->data->dev_private; 1203 struct adapter *adapter = pi->adapter; 1204 u64 rss_hf = 0; 1205 u64 flags = 0; 1206 int err; 1207 1208 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 1209 &flags, NULL); 1210 1211 if (err) 1212 return err; 1213 1214 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 1215 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 1216 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1217 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 1218 } 1219 1220 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1221 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 1222 1223 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 1224 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 1225 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1226 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 1227 } 1228 1229 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1230 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 1231 1232 rss_conf->rss_hf = rss_hf; 1233 1234 if (rss_conf->rss_key) { 1235 u32 key[10], mod_key[10]; 1236 int i, j; 1237 1238 t4_read_rss_key(adapter, key); 1239 1240 for (i = 9, j = 0; i >= 0; i--, j++) 1241 mod_key[j] = be32_to_cpu(key[i]); 1242 1243 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1244 } 1245 1246 return 0; 1247 } 1248 1249 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 1250 struct rte_eth_rss_reta_entry64 *reta_conf, 1251 uint16_t reta_size) 1252 { 1253 struct port_info *pi = dev->data->dev_private; 1254 struct adapter *adapter = pi->adapter; 1255 u16 i, idx, shift, *rss; 1256 int ret; 1257 1258 if (!(adapter->flags & FULL_INIT_DONE)) 1259 return -ENOMEM; 1260 1261 if (!reta_size || reta_size > pi->rss_size) 1262 return -EINVAL; 1263 1264 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 1265 if (!rss) 1266 return -ENOMEM; 1267 1268 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 1269 for (i = 0; i < reta_size; i++) { 1270 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1271 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1272 if (!(reta_conf[idx].mask & (1ULL << shift))) 1273 continue; 1274 1275 rss[i] = reta_conf[idx].reta[shift]; 1276 } 1277 1278 ret = cxgbe_write_rss(pi, rss); 1279 if (!ret) 1280 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 1281 1282 rte_free(rss); 1283 return ret; 1284 } 1285 1286 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 1287 struct rte_eth_rss_reta_entry64 *reta_conf, 1288 uint16_t reta_size) 1289 { 1290 struct port_info *pi = dev->data->dev_private; 1291 struct adapter *adapter = pi->adapter; 1292 u16 i, idx, shift; 1293 1294 if (!(adapter->flags & FULL_INIT_DONE)) 1295 return -ENOMEM; 1296 1297 if (!reta_size || reta_size > pi->rss_size) 1298 return -EINVAL; 1299 1300 for (i = 0; i < reta_size; i++) { 1301 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1302 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1303 if (!(reta_conf[idx].mask & (1ULL << shift))) 1304 continue; 1305 1306 reta_conf[idx].reta[shift] = pi->rss[i]; 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 1313 { 1314 RTE_SET_USED(dev); 1315 return EEPROMSIZE; 1316 } 1317 1318 /** 1319 * eeprom_ptov - translate a physical EEPROM address to virtual 1320 * @phys_addr: the physical EEPROM address 1321 * @fn: the PCI function number 1322 * @sz: size of function-specific area 1323 * 1324 * Translate a physical EEPROM address to virtual. The first 1K is 1325 * accessed through virtual addresses starting at 31K, the rest is 1326 * accessed through virtual addresses starting at 0. 1327 * 1328 * The mapping is as follows: 1329 * [0..1K) -> [31K..32K) 1330 * [1K..1K+A) -> [31K-A..31K) 1331 * [1K+A..ES) -> [0..ES-A-1K) 1332 * 1333 * where A = @fn * @sz, and ES = EEPROM size. 1334 */ 1335 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1336 { 1337 fn *= sz; 1338 if (phys_addr < 1024) 1339 return phys_addr + (31 << 10); 1340 if (phys_addr < 1024 + fn) 1341 return fn + phys_addr - 1024; 1342 if (phys_addr < EEPROMSIZE) 1343 return phys_addr - 1024 - fn; 1344 if (phys_addr < EEPROMVSIZE) 1345 return phys_addr - 1024; 1346 return -EINVAL; 1347 } 1348 1349 /* The next two routines implement eeprom read/write from physical addresses. 1350 */ 1351 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1352 { 1353 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1354 1355 if (vaddr >= 0) 1356 vaddr = t4_seeprom_read(adap, vaddr, v); 1357 return vaddr < 0 ? vaddr : 0; 1358 } 1359 1360 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1361 { 1362 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1363 1364 if (vaddr >= 0) 1365 vaddr = t4_seeprom_write(adap, vaddr, v); 1366 return vaddr < 0 ? vaddr : 0; 1367 } 1368 1369 #define EEPROM_MAGIC 0x38E2F10C 1370 1371 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1372 struct rte_dev_eeprom_info *e) 1373 { 1374 struct port_info *pi = dev->data->dev_private; 1375 struct adapter *adapter = pi->adapter; 1376 u32 i, err = 0; 1377 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1378 1379 if (!buf) 1380 return -ENOMEM; 1381 1382 e->magic = EEPROM_MAGIC; 1383 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1384 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1385 1386 if (!err) 1387 rte_memcpy(e->data, buf + e->offset, e->length); 1388 rte_free(buf); 1389 return err; 1390 } 1391 1392 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1393 struct rte_dev_eeprom_info *eeprom) 1394 { 1395 struct port_info *pi = dev->data->dev_private; 1396 struct adapter *adapter = pi->adapter; 1397 u8 *buf; 1398 int err = 0; 1399 u32 aligned_offset, aligned_len, *p; 1400 1401 if (eeprom->magic != EEPROM_MAGIC) 1402 return -EINVAL; 1403 1404 aligned_offset = eeprom->offset & ~3; 1405 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1406 1407 if (adapter->pf > 0) { 1408 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1409 1410 if (aligned_offset < start || 1411 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1412 return -EPERM; 1413 } 1414 1415 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1416 /* RMW possibly needed for first or last words. 1417 */ 1418 buf = rte_zmalloc(NULL, aligned_len, 0); 1419 if (!buf) 1420 return -ENOMEM; 1421 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1422 if (!err && aligned_len > 4) 1423 err = eeprom_rd_phys(adapter, 1424 aligned_offset + aligned_len - 4, 1425 (u32 *)&buf[aligned_len - 4]); 1426 if (err) 1427 goto out; 1428 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1429 eeprom->length); 1430 } else { 1431 buf = eeprom->data; 1432 } 1433 1434 err = t4_seeprom_wp(adapter, false); 1435 if (err) 1436 goto out; 1437 1438 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1439 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1440 aligned_offset += 4; 1441 } 1442 1443 if (!err) 1444 err = t4_seeprom_wp(adapter, true); 1445 out: 1446 if (buf != eeprom->data) 1447 rte_free(buf); 1448 return err; 1449 } 1450 1451 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1452 { 1453 struct port_info *pi = eth_dev->data->dev_private; 1454 struct adapter *adapter = pi->adapter; 1455 1456 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1457 } 1458 1459 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1460 struct rte_dev_reg_info *regs) 1461 { 1462 struct port_info *pi = eth_dev->data->dev_private; 1463 struct adapter *adapter = pi->adapter; 1464 1465 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1466 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1467 (1 << 16); 1468 1469 if (regs->data == NULL) { 1470 regs->length = cxgbe_get_regs_len(eth_dev); 1471 regs->width = sizeof(uint32_t); 1472 1473 return 0; 1474 } 1475 1476 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1477 1478 return 0; 1479 } 1480 1481 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1482 { 1483 struct port_info *pi = dev->data->dev_private; 1484 int ret; 1485 1486 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1487 if (ret < 0) { 1488 dev_err(adapter, "failed to set mac addr; err = %d\n", 1489 ret); 1490 return ret; 1491 } 1492 pi->xact_addr_filt = ret; 1493 return 0; 1494 } 1495 1496 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc, 1497 struct rte_eth_fec_capa *capa_arr) 1498 { 1499 int num = 0; 1500 1501 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) { 1502 if (capa_arr) { 1503 capa_arr[num].speed = RTE_ETH_SPEED_NUM_100G; 1504 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1505 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1506 } 1507 num++; 1508 } 1509 1510 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) { 1511 if (capa_arr) { 1512 capa_arr[num].speed = RTE_ETH_SPEED_NUM_50G; 1513 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1514 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1515 } 1516 num++; 1517 } 1518 1519 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) { 1520 if (capa_arr) { 1521 capa_arr[num].speed = RTE_ETH_SPEED_NUM_25G; 1522 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1523 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 1524 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1525 } 1526 num++; 1527 } 1528 1529 return num; 1530 } 1531 1532 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev, 1533 struct rte_eth_fec_capa *speed_fec_capa, 1534 unsigned int num) 1535 { 1536 struct port_info *pi = dev->data->dev_private; 1537 struct link_config *lc = &pi->link_cfg; 1538 u8 num_entries; 1539 1540 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1541 return -EOPNOTSUPP; 1542 1543 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL); 1544 if (!speed_fec_capa || num < num_entries) 1545 return num_entries; 1546 1547 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa); 1548 } 1549 1550 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 1551 { 1552 struct port_info *pi = dev->data->dev_private; 1553 struct link_config *lc = &pi->link_cfg; 1554 u32 fec_caps = 0, caps = lc->link_caps; 1555 1556 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1557 return -EOPNOTSUPP; 1558 1559 if (caps & FW_PORT_CAP32_FEC_RS) 1560 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1561 else if (caps & FW_PORT_CAP32_FEC_BASER_RS) 1562 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1563 else 1564 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 1565 1566 *fec_capa = fec_caps; 1567 return 0; 1568 } 1569 1570 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 1571 { 1572 struct port_info *pi = dev->data->dev_private; 1573 u8 fec_rs = 0, fec_baser = 0, fec_none = 0; 1574 struct link_config *lc = &pi->link_cfg; 1575 u32 new_caps = lc->admin_caps; 1576 int ret; 1577 1578 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1579 return -EOPNOTSUPP; 1580 1581 if (!fec_capa) 1582 return -EINVAL; 1583 1584 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 1585 goto set_fec; 1586 1587 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) 1588 fec_none = 1; 1589 1590 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 1591 fec_baser = 1; 1592 1593 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 1594 fec_rs = 1; 1595 1596 set_fec: 1597 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps); 1598 if (ret != 0) 1599 return ret; 1600 1601 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 1602 new_caps |= FW_PORT_CAP32_FORCE_FEC; 1603 else 1604 new_caps &= ~FW_PORT_CAP32_FORCE_FEC; 1605 1606 if (new_caps != lc->admin_caps) { 1607 ret = t4_link_l1cfg(pi, new_caps); 1608 if (ret == 0) 1609 lc->admin_caps = new_caps; 1610 } 1611 1612 return ret; 1613 } 1614 1615 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 1616 size_t fw_size) 1617 { 1618 struct port_info *pi = dev->data->dev_private; 1619 struct adapter *adapter = pi->adapter; 1620 int ret; 1621 1622 if (adapter->params.fw_vers == 0) 1623 return -EIO; 1624 1625 ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u", 1626 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers), 1627 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers), 1628 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers), 1629 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers)); 1630 if (ret < 0) 1631 return -EINVAL; 1632 1633 ret += 1; 1634 if (fw_size < (size_t)ret) 1635 return ret; 1636 1637 return 0; 1638 } 1639 1640 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1641 .dev_start = cxgbe_dev_start, 1642 .dev_stop = cxgbe_dev_stop, 1643 .dev_close = cxgbe_dev_close, 1644 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1645 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1646 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1647 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1648 .dev_configure = cxgbe_dev_configure, 1649 .dev_infos_get = cxgbe_dev_info_get, 1650 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1651 .link_update = cxgbe_dev_link_update, 1652 .dev_set_link_up = cxgbe_dev_set_link_up, 1653 .dev_set_link_down = cxgbe_dev_set_link_down, 1654 .mtu_set = cxgbe_dev_mtu_set, 1655 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1656 .tx_queue_start = cxgbe_dev_tx_queue_start, 1657 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1658 .tx_queue_release = cxgbe_dev_tx_queue_release, 1659 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1660 .rx_queue_start = cxgbe_dev_rx_queue_start, 1661 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1662 .rx_queue_release = cxgbe_dev_rx_queue_release, 1663 .flow_ops_get = cxgbe_dev_flow_ops_get, 1664 .stats_get = cxgbe_dev_stats_get, 1665 .stats_reset = cxgbe_dev_stats_reset, 1666 .xstats_get = cxgbe_dev_xstats_get, 1667 .xstats_get_by_id = cxgbe_dev_xstats_get_by_id, 1668 .xstats_get_names = cxgbe_dev_xstats_get_names, 1669 .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id, 1670 .xstats_reset = cxgbe_dev_xstats_reset, 1671 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1672 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1673 .get_eeprom_length = cxgbe_get_eeprom_length, 1674 .get_eeprom = cxgbe_get_eeprom, 1675 .set_eeprom = cxgbe_set_eeprom, 1676 .get_reg = cxgbe_get_regs, 1677 .rss_hash_update = cxgbe_dev_rss_hash_update, 1678 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1679 .mac_addr_set = cxgbe_mac_addr_set, 1680 .reta_update = cxgbe_dev_rss_reta_update, 1681 .reta_query = cxgbe_dev_rss_reta_query, 1682 .fec_get_capability = cxgbe_fec_get_capability, 1683 .fec_get = cxgbe_fec_get, 1684 .fec_set = cxgbe_fec_set, 1685 .fw_version_get = cxgbe_fw_version_get, 1686 }; 1687 1688 /* 1689 * Initialize driver 1690 * It returns 0 on success. 1691 */ 1692 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1693 { 1694 struct rte_pci_device *pci_dev; 1695 struct port_info *pi = eth_dev->data->dev_private; 1696 struct adapter *adapter = NULL; 1697 char name[RTE_ETH_NAME_MAX_LEN]; 1698 int err = 0; 1699 1700 CXGBE_FUNC_TRACE(); 1701 1702 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1703 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1704 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1705 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1706 1707 /* for secondary processes, we attach to ethdevs allocated by primary 1708 * and do minimal initialization. 1709 */ 1710 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1711 int i; 1712 1713 for (i = 1; i < MAX_NPORTS; i++) { 1714 struct rte_eth_dev *rest_eth_dev; 1715 char namei[RTE_ETH_NAME_MAX_LEN]; 1716 1717 snprintf(namei, sizeof(namei), "%s_%d", 1718 pci_dev->device.name, i); 1719 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1720 if (rest_eth_dev) { 1721 rest_eth_dev->device = &pci_dev->device; 1722 rest_eth_dev->dev_ops = 1723 eth_dev->dev_ops; 1724 rest_eth_dev->rx_pkt_burst = 1725 eth_dev->rx_pkt_burst; 1726 rest_eth_dev->tx_pkt_burst = 1727 eth_dev->tx_pkt_burst; 1728 rte_eth_dev_probing_finish(rest_eth_dev); 1729 } 1730 } 1731 return 0; 1732 } 1733 1734 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1735 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1736 if (!adapter) 1737 return -1; 1738 1739 adapter->use_unpacked_mode = 1; 1740 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1741 if (!adapter->regs) { 1742 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1743 err = -ENOMEM; 1744 goto out_free_adapter; 1745 } 1746 adapter->pdev = pci_dev; 1747 adapter->eth_dev = eth_dev; 1748 pi->adapter = adapter; 1749 1750 cxgbe_process_devargs(adapter); 1751 1752 err = cxgbe_probe(adapter); 1753 if (err) { 1754 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1755 __func__, err); 1756 goto out_free_adapter; 1757 } 1758 1759 return 0; 1760 1761 out_free_adapter: 1762 rte_free(adapter); 1763 return err; 1764 } 1765 1766 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1767 { 1768 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1769 uint16_t port_id; 1770 int err = 0; 1771 1772 /* Free up other ports and all resources */ 1773 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1774 err |= rte_eth_dev_close(port_id); 1775 1776 return err == 0 ? 0 : -EIO; 1777 } 1778 1779 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1780 struct rte_pci_device *pci_dev) 1781 { 1782 return rte_eth_dev_pci_generic_probe(pci_dev, 1783 sizeof(struct port_info), eth_cxgbe_dev_init); 1784 } 1785 1786 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1787 { 1788 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1789 } 1790 1791 static struct rte_pci_driver rte_cxgbe_pmd = { 1792 .id_table = cxgb4_pci_tbl, 1793 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1794 .probe = eth_cxgbe_pci_probe, 1795 .remove = eth_cxgbe_pci_remove, 1796 }; 1797 1798 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1799 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1800 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1801 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1802 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1803 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1804 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1805 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1806 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE); 1807 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE); 1808