1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <ethdev_driver.h> 31 #include <ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 36 #include "cxgbe.h" 37 #include "cxgbe_pfvf.h" 38 #include "cxgbe_flow.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "base/t4_pci_id_tbl.h" 60 61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 62 uint16_t nb_pkts) 63 { 64 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 65 uint16_t pkts_sent, pkts_remain; 66 uint16_t total_sent = 0; 67 uint16_t idx = 0; 68 int ret = 0; 69 70 t4_os_lock(&txq->txq_lock); 71 /* free up desc from already completed tx */ 72 reclaim_completed_tx(&txq->q); 73 if (unlikely(!nb_pkts)) 74 goto out_unlock; 75 76 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 77 while (total_sent < nb_pkts) { 78 pkts_remain = nb_pkts - total_sent; 79 80 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 81 idx = total_sent + pkts_sent; 82 if ((idx + 1) < nb_pkts) 83 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 84 volatile void *)); 85 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 86 if (ret < 0) 87 break; 88 } 89 if (!pkts_sent) 90 break; 91 total_sent += pkts_sent; 92 /* reclaim as much as possible */ 93 reclaim_completed_tx(&txq->q); 94 } 95 96 out_unlock: 97 t4_os_unlock(&txq->txq_lock); 98 return total_sent; 99 } 100 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 102 uint16_t nb_pkts) 103 { 104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 105 unsigned int work_done; 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 return work_done; 111 } 112 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 114 struct rte_eth_dev_info *device_info) 115 { 116 struct port_info *pi = eth_dev->data->dev_private; 117 struct adapter *adapter = pi->adapter; 118 119 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 120 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 121 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 122 .nb_align = 1, 123 }; 124 125 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 126 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 127 device_info->max_rx_queues = adapter->sge.max_ethqsets; 128 device_info->max_tx_queues = adapter->sge.max_ethqsets; 129 device_info->max_mac_addrs = 1; 130 /* XXX: For now we support one MAC/port */ 131 device_info->max_vfs = adapter->params.arch.vfcount; 132 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 133 134 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 135 136 device_info->rx_queue_offload_capa = 0UL; 137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 138 139 device_info->tx_queue_offload_capa = 0UL; 140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 141 142 device_info->reta_size = pi->rss_size; 143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 145 146 device_info->rx_desc_lim = cxgbe_desc_lim; 147 device_info->tx_desc_lim = cxgbe_desc_lim; 148 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 149 150 return 0; 151 } 152 153 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 154 { 155 struct port_info *pi = eth_dev->data->dev_private; 156 struct adapter *adapter = pi->adapter; 157 int ret; 158 159 if (adapter->params.rawf_size != 0) { 160 ret = cxgbe_mpstcam_rawf_enable(pi); 161 if (ret < 0) 162 return ret; 163 } 164 165 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 166 1, -1, 1, -1, false); 167 } 168 169 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 170 { 171 struct port_info *pi = eth_dev->data->dev_private; 172 struct adapter *adapter = pi->adapter; 173 int ret; 174 175 if (adapter->params.rawf_size != 0) { 176 ret = cxgbe_mpstcam_rawf_disable(pi); 177 if (ret < 0) 178 return ret; 179 } 180 181 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 182 0, -1, 1, -1, false); 183 } 184 185 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 186 { 187 struct port_info *pi = eth_dev->data->dev_private; 188 struct adapter *adapter = pi->adapter; 189 190 /* TODO: address filters ?? */ 191 192 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 193 -1, 1, 1, -1, false); 194 } 195 196 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 197 { 198 struct port_info *pi = eth_dev->data->dev_private; 199 struct adapter *adapter = pi->adapter; 200 201 /* TODO: address filters ?? */ 202 203 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 204 -1, 0, 1, -1, false); 205 } 206 207 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 208 int wait_to_complete) 209 { 210 struct port_info *pi = eth_dev->data->dev_private; 211 unsigned int i, work_done, budget = 32; 212 struct link_config *lc = &pi->link_cfg; 213 struct adapter *adapter = pi->adapter; 214 struct rte_eth_link new_link = { 0 }; 215 u8 old_link = pi->link_cfg.link_ok; 216 struct sge *s = &adapter->sge; 217 218 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 219 if (!s->fw_evtq.desc) 220 break; 221 222 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 223 224 /* Exit if link status changed or always forced up */ 225 if (pi->link_cfg.link_ok != old_link || 226 cxgbe_force_linkup(adapter)) 227 break; 228 229 if (!wait_to_complete) 230 break; 231 232 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 233 } 234 235 new_link.link_status = cxgbe_force_linkup(adapter) ? 236 RTE_ETH_LINK_UP : pi->link_cfg.link_ok; 237 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; 238 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 239 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps); 240 241 return rte_eth_linkstatus_set(eth_dev, &new_link); 242 } 243 244 /** 245 * Set device link up. 246 */ 247 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 248 { 249 struct port_info *pi = dev->data->dev_private; 250 struct adapter *adapter = pi->adapter; 251 unsigned int work_done, budget = 32; 252 struct sge *s = &adapter->sge; 253 int ret; 254 255 if (!s->fw_evtq.desc) 256 return -ENOMEM; 257 258 /* Flush all link events */ 259 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 260 261 /* If link already up, nothing to do */ 262 if (pi->link_cfg.link_ok) 263 return 0; 264 265 ret = cxgbe_set_link_status(pi, true); 266 if (ret) 267 return ret; 268 269 cxgbe_dev_link_update(dev, 1); 270 return 0; 271 } 272 273 /** 274 * Set device link down. 275 */ 276 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 277 { 278 struct port_info *pi = dev->data->dev_private; 279 struct adapter *adapter = pi->adapter; 280 unsigned int work_done, budget = 32; 281 struct sge *s = &adapter->sge; 282 int ret; 283 284 if (!s->fw_evtq.desc) 285 return -ENOMEM; 286 287 /* Flush all link events */ 288 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 289 290 /* If link already down, nothing to do */ 291 if (!pi->link_cfg.link_ok) 292 return 0; 293 294 ret = cxgbe_set_link_status(pi, false); 295 if (ret) 296 return ret; 297 298 cxgbe_dev_link_update(dev, 0); 299 return 0; 300 } 301 302 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 303 { 304 struct port_info *pi = eth_dev->data->dev_private; 305 struct adapter *adapter = pi->adapter; 306 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 307 308 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 309 -1, -1, true); 310 } 311 312 /* 313 * Stop device. 314 */ 315 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 316 { 317 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 318 struct adapter *adapter = pi->adapter; 319 u8 i; 320 321 CXGBE_FUNC_TRACE(); 322 323 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 324 return 0; 325 326 if (!(adapter->flags & FULL_INIT_DONE)) 327 return 0; 328 329 if (!pi->viid) 330 return 0; 331 332 cxgbe_down(pi); 333 t4_sge_eth_release_queues(pi); 334 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 335 pi->viid = 0; 336 337 /* Free up the adapter-wide resources only after all the ports 338 * under this PF have been closed. 339 */ 340 for_each_port(adapter, i) { 341 temp_pi = adap2pinfo(adapter, i); 342 if (temp_pi->viid) 343 return 0; 344 } 345 346 cxgbe_close(adapter); 347 rte_free(adapter); 348 349 return 0; 350 } 351 352 /* Start the device. 353 * It returns 0 on success. 354 */ 355 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 356 { 357 struct port_info *pi = eth_dev->data->dev_private; 358 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 359 struct adapter *adapter = pi->adapter; 360 int err = 0, i; 361 362 CXGBE_FUNC_TRACE(); 363 364 /* 365 * If we don't have a connection to the firmware there's nothing we 366 * can do. 367 */ 368 if (!(adapter->flags & FW_OK)) { 369 err = -ENXIO; 370 goto out; 371 } 372 373 if (!(adapter->flags & FULL_INIT_DONE)) { 374 err = cxgbe_up(adapter); 375 if (err < 0) 376 goto out; 377 } 378 379 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 380 eth_dev->data->scattered_rx = 1; 381 else 382 eth_dev->data->scattered_rx = 0; 383 384 cxgbe_enable_rx_queues(pi); 385 386 err = cxgbe_setup_rss(pi); 387 if (err) 388 goto out; 389 390 for (i = 0; i < pi->n_tx_qsets; i++) { 391 err = cxgbe_dev_tx_queue_start(eth_dev, i); 392 if (err) 393 goto out; 394 } 395 396 for (i = 0; i < pi->n_rx_qsets; i++) { 397 err = cxgbe_dev_rx_queue_start(eth_dev, i); 398 if (err) 399 goto out; 400 } 401 402 err = cxgbe_link_start(pi); 403 if (err) 404 goto out; 405 406 out: 407 return err; 408 } 409 410 /* 411 * Stop device: disable rx and tx functions to allow for reconfiguring. 412 */ 413 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 414 { 415 struct port_info *pi = eth_dev->data->dev_private; 416 struct adapter *adapter = pi->adapter; 417 418 CXGBE_FUNC_TRACE(); 419 420 if (!(adapter->flags & FULL_INIT_DONE)) 421 return 0; 422 423 cxgbe_down(pi); 424 425 /* 426 * We clear queues only if both tx and rx path of the port 427 * have been disabled 428 */ 429 t4_sge_eth_clear_queues(pi); 430 eth_dev->data->scattered_rx = 0; 431 432 return 0; 433 } 434 435 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 436 { 437 struct port_info *pi = eth_dev->data->dev_private; 438 struct adapter *adapter = pi->adapter; 439 int err; 440 441 CXGBE_FUNC_TRACE(); 442 443 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 444 eth_dev->data->dev_conf.rxmode.offloads |= 445 RTE_ETH_RX_OFFLOAD_RSS_HASH; 446 447 if (!(adapter->flags & FW_QUEUE_BOUND)) { 448 err = cxgbe_setup_sge_fwevtq(adapter); 449 if (err) 450 return err; 451 adapter->flags |= FW_QUEUE_BOUND; 452 if (is_pf4(adapter)) { 453 err = cxgbe_setup_sge_ctrl_txq(adapter); 454 if (err) 455 return err; 456 } 457 } 458 459 err = cxgbe_cfg_queue_count(eth_dev); 460 if (err) 461 return err; 462 463 return 0; 464 } 465 466 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 467 { 468 int ret; 469 struct sge_eth_txq *txq = (struct sge_eth_txq *) 470 (eth_dev->data->tx_queues[tx_queue_id]); 471 472 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 473 474 ret = t4_sge_eth_txq_start(txq); 475 if (ret == 0) 476 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 477 478 return ret; 479 } 480 481 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 482 { 483 int ret; 484 struct sge_eth_txq *txq = (struct sge_eth_txq *) 485 (eth_dev->data->tx_queues[tx_queue_id]); 486 487 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 488 489 ret = t4_sge_eth_txq_stop(txq); 490 if (ret == 0) 491 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 492 493 return ret; 494 } 495 496 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 497 uint16_t queue_idx, uint16_t nb_desc, 498 unsigned int socket_id, 499 const struct rte_eth_txconf *tx_conf __rte_unused) 500 { 501 struct port_info *pi = eth_dev->data->dev_private; 502 struct adapter *adapter = pi->adapter; 503 struct sge *s = &adapter->sge; 504 unsigned int temp_nb_desc; 505 struct sge_eth_txq *txq; 506 int err = 0; 507 508 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 509 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 510 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 511 socket_id, pi->first_txqset); 512 513 /* Free up the existing queue */ 514 if (eth_dev->data->tx_queues[queue_idx]) { 515 cxgbe_dev_tx_queue_release(eth_dev, queue_idx); 516 eth_dev->data->tx_queues[queue_idx] = NULL; 517 } 518 519 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 520 521 /* Sanity Checking 522 * 523 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 524 */ 525 temp_nb_desc = nb_desc; 526 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 527 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 528 __func__, CXGBE_MIN_RING_DESC_SIZE, 529 CXGBE_DEFAULT_TX_DESC_SIZE); 530 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 531 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 532 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 533 __func__, CXGBE_MIN_RING_DESC_SIZE, 534 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 535 return -(EINVAL); 536 } 537 538 txq->q.size = temp_nb_desc; 539 540 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 541 s->fw_evtq.cntxt_id, socket_id); 542 543 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 544 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 545 return err; 546 } 547 548 void cxgbe_dev_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 549 { 550 struct sge_eth_txq *txq = eth_dev->data->tx_queues[qid]; 551 552 if (txq) { 553 struct port_info *pi = (struct port_info *) 554 (txq->eth_dev->data->dev_private); 555 struct adapter *adap = pi->adapter; 556 557 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 558 __func__, pi->port_id, txq->q.cntxt_id); 559 560 t4_sge_eth_txq_release(adap, txq); 561 } 562 } 563 564 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 565 { 566 struct port_info *pi = eth_dev->data->dev_private; 567 struct adapter *adap = pi->adapter; 568 struct sge_eth_rxq *rxq; 569 int ret; 570 571 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 572 __func__, pi->port_id, rx_queue_id); 573 574 rxq = eth_dev->data->rx_queues[rx_queue_id]; 575 ret = t4_sge_eth_rxq_start(adap, rxq); 576 if (ret == 0) 577 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 578 579 return ret; 580 } 581 582 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 583 { 584 struct port_info *pi = eth_dev->data->dev_private; 585 struct adapter *adap = pi->adapter; 586 struct sge_eth_rxq *rxq; 587 int ret; 588 589 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 590 __func__, pi->port_id, rx_queue_id); 591 592 rxq = eth_dev->data->rx_queues[rx_queue_id]; 593 ret = t4_sge_eth_rxq_stop(adap, rxq); 594 if (ret == 0) 595 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 596 597 return ret; 598 } 599 600 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 601 uint16_t queue_idx, uint16_t nb_desc, 602 unsigned int socket_id, 603 const struct rte_eth_rxconf *rx_conf __rte_unused, 604 struct rte_mempool *mp) 605 { 606 unsigned int pkt_len = eth_dev->data->mtu + RTE_ETHER_HDR_LEN + 607 RTE_ETHER_CRC_LEN; 608 struct port_info *pi = eth_dev->data->dev_private; 609 struct adapter *adapter = pi->adapter; 610 struct rte_eth_dev_info dev_info; 611 struct sge *s = &adapter->sge; 612 unsigned int temp_nb_desc; 613 int err = 0, msi_idx = 0; 614 struct sge_eth_rxq *rxq; 615 616 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 617 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 618 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 619 socket_id, mp); 620 621 err = cxgbe_dev_info_get(eth_dev, &dev_info); 622 if (err != 0) { 623 dev_err(adap, "%s: error during getting ethernet device info", 624 __func__); 625 return err; 626 } 627 628 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 629 if ((pkt_len < dev_info.min_rx_bufsize) || 630 (pkt_len > dev_info.max_rx_pktlen)) { 631 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 632 __func__, dev_info.min_rx_bufsize, 633 dev_info.max_rx_pktlen); 634 return -EINVAL; 635 } 636 637 /* Free up the existing queue */ 638 if (eth_dev->data->rx_queues[queue_idx]) { 639 cxgbe_dev_rx_queue_release(eth_dev, queue_idx); 640 eth_dev->data->rx_queues[queue_idx] = NULL; 641 } 642 643 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 644 645 /* Sanity Checking 646 * 647 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 648 */ 649 temp_nb_desc = nb_desc; 650 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 651 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 652 __func__, CXGBE_MIN_RING_DESC_SIZE, 653 CXGBE_DEFAULT_RX_DESC_SIZE); 654 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 655 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 656 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 657 __func__, CXGBE_MIN_RING_DESC_SIZE, 658 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 659 return -(EINVAL); 660 } 661 662 rxq->rspq.size = temp_nb_desc; 663 rxq->fl.size = temp_nb_desc; 664 665 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 666 &rxq->fl, NULL, 667 is_pf4(adapter) ? 668 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 669 queue_idx, socket_id); 670 671 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 672 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 673 rxq->rspq.abs_id); 674 return err; 675 } 676 677 void cxgbe_dev_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 678 { 679 struct sge_eth_rxq *rxq = eth_dev->data->rx_queues[qid]; 680 681 if (rxq) { 682 struct port_info *pi = (struct port_info *) 683 (rxq->rspq.eth_dev->data->dev_private); 684 struct adapter *adap = pi->adapter; 685 686 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 687 __func__, pi->port_id, rxq->rspq.cntxt_id); 688 689 t4_sge_eth_rxq_release(adap, rxq); 690 } 691 } 692 693 /* 694 * Get port statistics. 695 */ 696 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 697 struct rte_eth_stats *eth_stats) 698 { 699 struct port_info *pi = eth_dev->data->dev_private; 700 struct adapter *adapter = pi->adapter; 701 struct sge *s = &adapter->sge; 702 struct port_stats ps; 703 unsigned int i; 704 705 cxgbe_stats_get(pi, &ps); 706 707 /* RX Stats */ 708 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 709 ps.rx_ovflow2 + ps.rx_ovflow3 + 710 ps.rx_trunc0 + ps.rx_trunc1 + 711 ps.rx_trunc2 + ps.rx_trunc3; 712 for (i = 0; i < NCHAN; i++) 713 eth_stats->imissed += ps.rx_tp_tnl_cong_drops[i]; 714 715 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 716 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 717 ps.rx_len_err; 718 719 /* TX Stats */ 720 eth_stats->opackets = ps.tx_frames; 721 eth_stats->obytes = ps.tx_octets; 722 eth_stats->oerrors = ps.tx_error_frames; 723 724 for (i = 0; i < pi->n_rx_qsets; i++) { 725 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 726 727 eth_stats->ipackets += rxq->stats.pkts; 728 eth_stats->ibytes += rxq->stats.rx_bytes; 729 } 730 731 return 0; 732 } 733 734 /* 735 * Reset port statistics. 736 */ 737 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 738 { 739 struct port_info *pi = eth_dev->data->dev_private; 740 struct adapter *adapter = pi->adapter; 741 struct sge *s = &adapter->sge; 742 unsigned int i; 743 744 cxgbe_stats_reset(pi); 745 for (i = 0; i < pi->n_rx_qsets; i++) { 746 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 747 748 memset(&rxq->stats, 0, sizeof(rxq->stats)); 749 } 750 for (i = 0; i < pi->n_tx_qsets; i++) { 751 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i]; 752 753 memset(&txq->stats, 0, sizeof(txq->stats)); 754 } 755 756 return 0; 757 } 758 759 /* Store extended statistics names and its offset in stats structure */ 760 struct cxgbe_dev_xstats_name_off { 761 char name[RTE_ETH_XSTATS_NAME_SIZE]; 762 unsigned int offset; 763 }; 764 765 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = { 766 {"packets", offsetof(struct sge_eth_rx_stats, pkts)}, 767 {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)}, 768 {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)}, 769 {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)}, 770 {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)}, 771 }; 772 773 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = { 774 {"packets", offsetof(struct sge_eth_tx_stats, pkts)}, 775 {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)}, 776 {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)}, 777 {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)}, 778 {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)}, 779 {"packet_mapping_errors", 780 offsetof(struct sge_eth_tx_stats, mapping_err)}, 781 {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)}, 782 {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)}, 783 }; 784 785 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = { 786 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 787 {"tx_packets", offsetof(struct port_stats, tx_frames)}, 788 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 789 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 790 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 791 {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)}, 792 {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)}, 793 {"tx_size_65_to_127_packets", 794 offsetof(struct port_stats, tx_frames_65_127)}, 795 {"tx_size_128_to_255_packets", 796 offsetof(struct port_stats, tx_frames_128_255)}, 797 {"tx_size_256_to_511_packets", 798 offsetof(struct port_stats, tx_frames_256_511)}, 799 {"tx_size_512_to_1023_packets", 800 offsetof(struct port_stats, tx_frames_512_1023)}, 801 {"tx_size_1024_to_1518_packets", 802 offsetof(struct port_stats, tx_frames_1024_1518)}, 803 {"tx_size_1519_to_max_packets", 804 offsetof(struct port_stats, tx_frames_1519_max)}, 805 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 806 {"tx_pause_frames", offsetof(struct port_stats, tx_pause)}, 807 {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)}, 808 {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)}, 809 {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)}, 810 {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)}, 811 {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)}, 812 {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)}, 813 {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)}, 814 {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)}, 815 {"rx_bytes", offsetof(struct port_stats, rx_octets)}, 816 {"rx_packets", offsetof(struct port_stats, rx_frames)}, 817 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 818 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 819 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 820 {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)}, 821 {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)}, 822 {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)}, 823 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 824 {"rx_symbol_error_packets", 825 offsetof(struct port_stats, rx_symbol_err)}, 826 {"rx_short_packets", offsetof(struct port_stats, rx_runt)}, 827 {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)}, 828 {"rx_size_65_to_127_packets", 829 offsetof(struct port_stats, rx_frames_65_127)}, 830 {"rx_size_128_to_255_packets", 831 offsetof(struct port_stats, rx_frames_128_255)}, 832 {"rx_size_256_to_511_packets", 833 offsetof(struct port_stats, rx_frames_256_511)}, 834 {"rx_size_512_to_1023_packets", 835 offsetof(struct port_stats, rx_frames_512_1023)}, 836 {"rx_size_1024_to_1518_packets", 837 offsetof(struct port_stats, rx_frames_1024_1518)}, 838 {"rx_size_1519_to_max_packets", 839 offsetof(struct port_stats, rx_frames_1519_max)}, 840 {"rx_pause_packets", offsetof(struct port_stats, rx_pause)}, 841 {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)}, 842 {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)}, 843 {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)}, 844 {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)}, 845 {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)}, 846 {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)}, 847 {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)}, 848 {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)}, 849 {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)}, 850 {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)}, 851 {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)}, 852 {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)}, 853 {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)}, 854 {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)}, 855 {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)}, 856 {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)}, 857 {"rx_tp_tnl_cong_drops0", 858 offsetof(struct port_stats, rx_tp_tnl_cong_drops[0])}, 859 {"rx_tp_tnl_cong_drops1", 860 offsetof(struct port_stats, rx_tp_tnl_cong_drops[1])}, 861 {"rx_tp_tnl_cong_drops2", 862 offsetof(struct port_stats, rx_tp_tnl_cong_drops[2])}, 863 {"rx_tp_tnl_cong_drops3", 864 offsetof(struct port_stats, rx_tp_tnl_cong_drops[3])}, 865 }; 866 867 static const struct cxgbe_dev_xstats_name_off 868 cxgbevf_dev_port_stats_strings[] = { 869 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 870 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 871 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 872 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 873 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 874 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 875 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 876 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 877 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 878 }; 879 880 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings) 881 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings) 882 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings) 883 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings) 884 885 static u16 cxgbe_dev_xstats_count(struct port_info *pi) 886 { 887 u16 count; 888 889 count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) + 890 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS); 891 892 if (is_pf4(pi->adapter) != 0) 893 count += CXGBE_NB_PORT_STATS; 894 else 895 count += CXGBEVF_NB_PORT_STATS; 896 897 return count; 898 } 899 900 static int cxgbe_dev_xstats(struct rte_eth_dev *dev, 901 struct rte_eth_xstat_name *xstats_names, 902 struct rte_eth_xstat *xstats, unsigned int size) 903 { 904 const struct cxgbe_dev_xstats_name_off *xstats_str; 905 struct port_info *pi = dev->data->dev_private; 906 struct adapter *adap = pi->adapter; 907 struct sge *s = &adap->sge; 908 u16 count, i, qid, nstats; 909 struct port_stats ps; 910 u64 *stats_ptr; 911 912 count = cxgbe_dev_xstats_count(pi); 913 if (size < count) 914 return count; 915 916 if (is_pf4(adap) != 0) { 917 /* port stats for PF*/ 918 cxgbe_stats_get(pi, &ps); 919 xstats_str = cxgbe_dev_port_stats_strings; 920 nstats = CXGBE_NB_PORT_STATS; 921 } else { 922 /* port stats for VF*/ 923 cxgbevf_stats_get(pi, &ps); 924 xstats_str = cxgbevf_dev_port_stats_strings; 925 nstats = CXGBEVF_NB_PORT_STATS; 926 } 927 928 count = 0; 929 for (i = 0; i < nstats; i++, count++) { 930 if (xstats_names != NULL) 931 snprintf(xstats_names[count].name, 932 sizeof(xstats_names[count].name), 933 "%s", xstats_str[i].name); 934 if (xstats != NULL) { 935 stats_ptr = RTE_PTR_ADD(&ps, 936 xstats_str[i].offset); 937 xstats[count].value = *stats_ptr; 938 xstats[count].id = count; 939 } 940 } 941 942 /* per-txq stats */ 943 xstats_str = cxgbe_dev_txq_stats_strings; 944 for (qid = 0; qid < pi->n_tx_qsets; qid++) { 945 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid]; 946 947 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) { 948 if (xstats_names != NULL) 949 snprintf(xstats_names[count].name, 950 sizeof(xstats_names[count].name), 951 "tx_q%u_%s", 952 qid, xstats_str[i].name); 953 if (xstats != NULL) { 954 stats_ptr = RTE_PTR_ADD(&txq->stats, 955 xstats_str[i].offset); 956 xstats[count].value = *stats_ptr; 957 xstats[count].id = count; 958 } 959 } 960 } 961 962 /* per-rxq stats */ 963 xstats_str = cxgbe_dev_rxq_stats_strings; 964 for (qid = 0; qid < pi->n_rx_qsets; qid++) { 965 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid]; 966 967 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) { 968 if (xstats_names != NULL) 969 snprintf(xstats_names[count].name, 970 sizeof(xstats_names[count].name), 971 "rx_q%u_%s", 972 qid, xstats_str[i].name); 973 if (xstats != NULL) { 974 stats_ptr = RTE_PTR_ADD(&rxq->stats, 975 xstats_str[i].offset); 976 xstats[count].value = *stats_ptr; 977 xstats[count].id = count; 978 } 979 } 980 } 981 982 return count; 983 } 984 985 /* Get port extended statistics by ID. */ 986 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 987 const uint64_t *ids, uint64_t *values, 988 unsigned int n) 989 { 990 struct port_info *pi = dev->data->dev_private; 991 struct rte_eth_xstat *xstats_copy; 992 u16 count, i; 993 int ret = 0; 994 995 count = cxgbe_dev_xstats_count(pi); 996 if (ids == NULL || values == NULL) 997 return count; 998 999 xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0); 1000 if (xstats_copy == NULL) 1001 return -ENOMEM; 1002 1003 cxgbe_dev_xstats(dev, NULL, xstats_copy, count); 1004 1005 for (i = 0; i < n; i++) { 1006 if (ids[i] >= count) { 1007 ret = -EINVAL; 1008 goto out_err; 1009 } 1010 values[i] = xstats_copy[ids[i]].value; 1011 } 1012 1013 ret = n; 1014 1015 out_err: 1016 rte_free(xstats_copy); 1017 return ret; 1018 } 1019 1020 /* Get names of port extended statistics by ID. */ 1021 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1022 const uint64_t *ids, 1023 struct rte_eth_xstat_name *xnames, 1024 unsigned int n) 1025 { 1026 struct port_info *pi = dev->data->dev_private; 1027 struct rte_eth_xstat_name *xnames_copy; 1028 u16 count, i; 1029 int ret = 0; 1030 1031 count = cxgbe_dev_xstats_count(pi); 1032 if (ids == NULL || xnames == NULL) 1033 return count; 1034 1035 xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0); 1036 if (xnames_copy == NULL) 1037 return -ENOMEM; 1038 1039 cxgbe_dev_xstats(dev, xnames_copy, NULL, count); 1040 1041 for (i = 0; i < n; i++) { 1042 if (ids[i] >= count) { 1043 ret = -EINVAL; 1044 goto out_err; 1045 } 1046 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name, 1047 sizeof(xnames[i].name)); 1048 } 1049 1050 ret = n; 1051 1052 out_err: 1053 rte_free(xnames_copy); 1054 return ret; 1055 } 1056 1057 /* Get port extended statistics. */ 1058 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev, 1059 struct rte_eth_xstat *xstats, unsigned int n) 1060 { 1061 return cxgbe_dev_xstats(dev, NULL, xstats, n); 1062 } 1063 1064 /* Get names of port extended statistics. */ 1065 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 1066 struct rte_eth_xstat_name *xstats_names, 1067 unsigned int n) 1068 { 1069 return cxgbe_dev_xstats(dev, xstats_names, NULL, n); 1070 } 1071 1072 /* Reset port extended statistics. */ 1073 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1074 { 1075 return cxgbe_dev_stats_reset(dev); 1076 } 1077 1078 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1079 struct rte_eth_fc_conf *fc_conf) 1080 { 1081 struct port_info *pi = eth_dev->data->dev_private; 1082 struct link_config *lc = &pi->link_cfg; 1083 u8 rx_pause = 0, tx_pause = 0; 1084 u32 caps = lc->link_caps; 1085 1086 if (caps & FW_PORT_CAP32_ANEG) 1087 fc_conf->autoneg = 1; 1088 1089 if (caps & FW_PORT_CAP32_FC_TX) 1090 tx_pause = 1; 1091 1092 if (caps & FW_PORT_CAP32_FC_RX) 1093 rx_pause = 1; 1094 1095 if (rx_pause && tx_pause) 1096 fc_conf->mode = RTE_ETH_FC_FULL; 1097 else if (rx_pause) 1098 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 1099 else if (tx_pause) 1100 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1101 else 1102 fc_conf->mode = RTE_ETH_FC_NONE; 1103 return 0; 1104 } 1105 1106 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1107 struct rte_eth_fc_conf *fc_conf) 1108 { 1109 struct port_info *pi = eth_dev->data->dev_private; 1110 struct link_config *lc = &pi->link_cfg; 1111 u32 new_caps = lc->admin_caps; 1112 u8 tx_pause = 0, rx_pause = 0; 1113 int ret; 1114 1115 if (fc_conf->mode == RTE_ETH_FC_FULL) { 1116 tx_pause = 1; 1117 rx_pause = 1; 1118 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE) { 1119 tx_pause = 1; 1120 } else if (fc_conf->mode == RTE_ETH_FC_RX_PAUSE) { 1121 rx_pause = 1; 1122 } 1123 1124 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause, 1125 rx_pause, &new_caps); 1126 if (ret != 0) 1127 return ret; 1128 1129 if (!fc_conf->autoneg) { 1130 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE) 1131 new_caps |= FW_PORT_CAP32_FORCE_PAUSE; 1132 } else { 1133 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE; 1134 } 1135 1136 if (new_caps != lc->admin_caps) { 1137 ret = t4_link_l1cfg(pi, new_caps); 1138 if (ret == 0) 1139 lc->admin_caps = new_caps; 1140 } 1141 1142 return ret; 1143 } 1144 1145 const uint32_t * 1146 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1147 { 1148 static const uint32_t ptypes[] = { 1149 RTE_PTYPE_L3_IPV4, 1150 RTE_PTYPE_L3_IPV6, 1151 RTE_PTYPE_UNKNOWN 1152 }; 1153 1154 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 1155 return ptypes; 1156 return NULL; 1157 } 1158 1159 /* Update RSS hash configuration 1160 */ 1161 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 1162 struct rte_eth_rss_conf *rss_conf) 1163 { 1164 struct port_info *pi = dev->data->dev_private; 1165 struct adapter *adapter = pi->adapter; 1166 int err; 1167 1168 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 1169 if (err) 1170 return err; 1171 1172 pi->rss_hf = rss_conf->rss_hf; 1173 1174 if (rss_conf->rss_key) { 1175 u32 key[10], mod_key[10]; 1176 int i, j; 1177 1178 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1179 1180 for (i = 9, j = 0; i >= 0; i--, j++) 1181 mod_key[j] = cpu_to_be32(key[i]); 1182 1183 t4_write_rss_key(adapter, mod_key, -1); 1184 } 1185 1186 return 0; 1187 } 1188 1189 /* Get RSS hash configuration 1190 */ 1191 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1192 struct rte_eth_rss_conf *rss_conf) 1193 { 1194 struct port_info *pi = dev->data->dev_private; 1195 struct adapter *adapter = pi->adapter; 1196 u64 rss_hf = 0; 1197 u64 flags = 0; 1198 int err; 1199 1200 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 1201 &flags, NULL); 1202 1203 if (err) 1204 return err; 1205 1206 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 1207 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 1208 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1209 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 1210 } 1211 1212 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1213 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 1214 1215 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 1216 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 1217 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1218 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 1219 } 1220 1221 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1222 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 1223 1224 rss_conf->rss_hf = rss_hf; 1225 1226 if (rss_conf->rss_key) { 1227 u32 key[10], mod_key[10]; 1228 int i, j; 1229 1230 t4_read_rss_key(adapter, key); 1231 1232 for (i = 9, j = 0; i >= 0; i--, j++) 1233 mod_key[j] = be32_to_cpu(key[i]); 1234 1235 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1236 } 1237 1238 return 0; 1239 } 1240 1241 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 1242 struct rte_eth_rss_reta_entry64 *reta_conf, 1243 uint16_t reta_size) 1244 { 1245 struct port_info *pi = dev->data->dev_private; 1246 struct adapter *adapter = pi->adapter; 1247 u16 i, idx, shift, *rss; 1248 int ret; 1249 1250 if (!(adapter->flags & FULL_INIT_DONE)) 1251 return -ENOMEM; 1252 1253 if (!reta_size || reta_size > pi->rss_size) 1254 return -EINVAL; 1255 1256 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 1257 if (!rss) 1258 return -ENOMEM; 1259 1260 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 1261 for (i = 0; i < reta_size; i++) { 1262 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1263 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1264 if (!(reta_conf[idx].mask & (1ULL << shift))) 1265 continue; 1266 1267 rss[i] = reta_conf[idx].reta[shift]; 1268 } 1269 1270 ret = cxgbe_write_rss(pi, rss); 1271 if (!ret) 1272 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 1273 1274 rte_free(rss); 1275 return ret; 1276 } 1277 1278 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 1279 struct rte_eth_rss_reta_entry64 *reta_conf, 1280 uint16_t reta_size) 1281 { 1282 struct port_info *pi = dev->data->dev_private; 1283 struct adapter *adapter = pi->adapter; 1284 u16 i, idx, shift; 1285 1286 if (!(adapter->flags & FULL_INIT_DONE)) 1287 return -ENOMEM; 1288 1289 if (!reta_size || reta_size > pi->rss_size) 1290 return -EINVAL; 1291 1292 for (i = 0; i < reta_size; i++) { 1293 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1294 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1295 if (!(reta_conf[idx].mask & (1ULL << shift))) 1296 continue; 1297 1298 reta_conf[idx].reta[shift] = pi->rss[i]; 1299 } 1300 1301 return 0; 1302 } 1303 1304 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 1305 { 1306 RTE_SET_USED(dev); 1307 return EEPROMSIZE; 1308 } 1309 1310 /** 1311 * eeprom_ptov - translate a physical EEPROM address to virtual 1312 * @phys_addr: the physical EEPROM address 1313 * @fn: the PCI function number 1314 * @sz: size of function-specific area 1315 * 1316 * Translate a physical EEPROM address to virtual. The first 1K is 1317 * accessed through virtual addresses starting at 31K, the rest is 1318 * accessed through virtual addresses starting at 0. 1319 * 1320 * The mapping is as follows: 1321 * [0..1K) -> [31K..32K) 1322 * [1K..1K+A) -> [31K-A..31K) 1323 * [1K+A..ES) -> [0..ES-A-1K) 1324 * 1325 * where A = @fn * @sz, and ES = EEPROM size. 1326 */ 1327 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1328 { 1329 fn *= sz; 1330 if (phys_addr < 1024) 1331 return phys_addr + (31 << 10); 1332 if (phys_addr < 1024 + fn) 1333 return fn + phys_addr - 1024; 1334 if (phys_addr < EEPROMSIZE) 1335 return phys_addr - 1024 - fn; 1336 if (phys_addr < EEPROMVSIZE) 1337 return phys_addr - 1024; 1338 return -EINVAL; 1339 } 1340 1341 /* The next two routines implement eeprom read/write from physical addresses. 1342 */ 1343 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1344 { 1345 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1346 1347 if (vaddr >= 0) 1348 vaddr = t4_seeprom_read(adap, vaddr, v); 1349 return vaddr < 0 ? vaddr : 0; 1350 } 1351 1352 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1353 { 1354 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1355 1356 if (vaddr >= 0) 1357 vaddr = t4_seeprom_write(adap, vaddr, v); 1358 return vaddr < 0 ? vaddr : 0; 1359 } 1360 1361 #define EEPROM_MAGIC 0x38E2F10C 1362 1363 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1364 struct rte_dev_eeprom_info *e) 1365 { 1366 struct port_info *pi = dev->data->dev_private; 1367 struct adapter *adapter = pi->adapter; 1368 u32 i, err = 0; 1369 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1370 1371 if (!buf) 1372 return -ENOMEM; 1373 1374 e->magic = EEPROM_MAGIC; 1375 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1376 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1377 1378 if (!err) 1379 rte_memcpy(e->data, buf + e->offset, e->length); 1380 rte_free(buf); 1381 return err; 1382 } 1383 1384 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1385 struct rte_dev_eeprom_info *eeprom) 1386 { 1387 struct port_info *pi = dev->data->dev_private; 1388 struct adapter *adapter = pi->adapter; 1389 u8 *buf; 1390 int err = 0; 1391 u32 aligned_offset, aligned_len, *p; 1392 1393 if (eeprom->magic != EEPROM_MAGIC) 1394 return -EINVAL; 1395 1396 aligned_offset = eeprom->offset & ~3; 1397 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1398 1399 if (adapter->pf > 0) { 1400 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1401 1402 if (aligned_offset < start || 1403 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1404 return -EPERM; 1405 } 1406 1407 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1408 /* RMW possibly needed for first or last words. 1409 */ 1410 buf = rte_zmalloc(NULL, aligned_len, 0); 1411 if (!buf) 1412 return -ENOMEM; 1413 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1414 if (!err && aligned_len > 4) 1415 err = eeprom_rd_phys(adapter, 1416 aligned_offset + aligned_len - 4, 1417 (u32 *)&buf[aligned_len - 4]); 1418 if (err) 1419 goto out; 1420 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1421 eeprom->length); 1422 } else { 1423 buf = eeprom->data; 1424 } 1425 1426 err = t4_seeprom_wp(adapter, false); 1427 if (err) 1428 goto out; 1429 1430 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1431 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1432 aligned_offset += 4; 1433 } 1434 1435 if (!err) 1436 err = t4_seeprom_wp(adapter, true); 1437 out: 1438 if (buf != eeprom->data) 1439 rte_free(buf); 1440 return err; 1441 } 1442 1443 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1444 { 1445 struct port_info *pi = eth_dev->data->dev_private; 1446 struct adapter *adapter = pi->adapter; 1447 1448 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1449 } 1450 1451 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1452 struct rte_dev_reg_info *regs) 1453 { 1454 struct port_info *pi = eth_dev->data->dev_private; 1455 struct adapter *adapter = pi->adapter; 1456 1457 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1458 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1459 (1 << 16); 1460 1461 if (regs->data == NULL) { 1462 regs->length = cxgbe_get_regs_len(eth_dev); 1463 regs->width = sizeof(uint32_t); 1464 1465 return 0; 1466 } 1467 1468 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1469 1470 return 0; 1471 } 1472 1473 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1474 { 1475 struct port_info *pi = dev->data->dev_private; 1476 int ret; 1477 1478 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1479 if (ret < 0) { 1480 dev_err(adapter, "failed to set mac addr; err = %d\n", 1481 ret); 1482 return ret; 1483 } 1484 pi->xact_addr_filt = ret; 1485 return 0; 1486 } 1487 1488 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc, 1489 struct rte_eth_fec_capa *capa_arr) 1490 { 1491 int num = 0; 1492 1493 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) { 1494 if (capa_arr) { 1495 capa_arr[num].speed = RTE_ETH_SPEED_NUM_100G; 1496 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1497 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1498 } 1499 num++; 1500 } 1501 1502 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) { 1503 if (capa_arr) { 1504 capa_arr[num].speed = RTE_ETH_SPEED_NUM_50G; 1505 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1506 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1507 } 1508 num++; 1509 } 1510 1511 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) { 1512 if (capa_arr) { 1513 capa_arr[num].speed = RTE_ETH_SPEED_NUM_25G; 1514 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1515 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 1516 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1517 } 1518 num++; 1519 } 1520 1521 return num; 1522 } 1523 1524 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev, 1525 struct rte_eth_fec_capa *speed_fec_capa, 1526 unsigned int num) 1527 { 1528 struct port_info *pi = dev->data->dev_private; 1529 struct link_config *lc = &pi->link_cfg; 1530 u8 num_entries; 1531 1532 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1533 return -EOPNOTSUPP; 1534 1535 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL); 1536 if (!speed_fec_capa || num < num_entries) 1537 return num_entries; 1538 1539 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa); 1540 } 1541 1542 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 1543 { 1544 struct port_info *pi = dev->data->dev_private; 1545 struct link_config *lc = &pi->link_cfg; 1546 u32 fec_caps = 0, caps = lc->link_caps; 1547 1548 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1549 return -EOPNOTSUPP; 1550 1551 if (caps & FW_PORT_CAP32_FEC_RS) 1552 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1553 else if (caps & FW_PORT_CAP32_FEC_BASER_RS) 1554 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1555 else 1556 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 1557 1558 *fec_capa = fec_caps; 1559 return 0; 1560 } 1561 1562 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 1563 { 1564 struct port_info *pi = dev->data->dev_private; 1565 u8 fec_rs = 0, fec_baser = 0, fec_none = 0; 1566 struct link_config *lc = &pi->link_cfg; 1567 u32 new_caps = lc->admin_caps; 1568 int ret; 1569 1570 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1571 return -EOPNOTSUPP; 1572 1573 if (!fec_capa) 1574 return -EINVAL; 1575 1576 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 1577 goto set_fec; 1578 1579 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) 1580 fec_none = 1; 1581 1582 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 1583 fec_baser = 1; 1584 1585 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 1586 fec_rs = 1; 1587 1588 set_fec: 1589 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps); 1590 if (ret != 0) 1591 return ret; 1592 1593 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 1594 new_caps |= FW_PORT_CAP32_FORCE_FEC; 1595 else 1596 new_caps &= ~FW_PORT_CAP32_FORCE_FEC; 1597 1598 if (new_caps != lc->admin_caps) { 1599 ret = t4_link_l1cfg(pi, new_caps); 1600 if (ret == 0) 1601 lc->admin_caps = new_caps; 1602 } 1603 1604 return ret; 1605 } 1606 1607 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 1608 size_t fw_size) 1609 { 1610 struct port_info *pi = dev->data->dev_private; 1611 struct adapter *adapter = pi->adapter; 1612 int ret; 1613 1614 if (adapter->params.fw_vers == 0) 1615 return -EIO; 1616 1617 ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u", 1618 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers), 1619 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers), 1620 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers), 1621 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers)); 1622 if (ret < 0) 1623 return -EINVAL; 1624 1625 ret += 1; 1626 if (fw_size < (size_t)ret) 1627 return ret; 1628 1629 return 0; 1630 } 1631 1632 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1633 .dev_start = cxgbe_dev_start, 1634 .dev_stop = cxgbe_dev_stop, 1635 .dev_close = cxgbe_dev_close, 1636 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1637 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1638 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1639 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1640 .dev_configure = cxgbe_dev_configure, 1641 .dev_infos_get = cxgbe_dev_info_get, 1642 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1643 .link_update = cxgbe_dev_link_update, 1644 .dev_set_link_up = cxgbe_dev_set_link_up, 1645 .dev_set_link_down = cxgbe_dev_set_link_down, 1646 .mtu_set = cxgbe_dev_mtu_set, 1647 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1648 .tx_queue_start = cxgbe_dev_tx_queue_start, 1649 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1650 .tx_queue_release = cxgbe_dev_tx_queue_release, 1651 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1652 .rx_queue_start = cxgbe_dev_rx_queue_start, 1653 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1654 .rx_queue_release = cxgbe_dev_rx_queue_release, 1655 .flow_ops_get = cxgbe_dev_flow_ops_get, 1656 .stats_get = cxgbe_dev_stats_get, 1657 .stats_reset = cxgbe_dev_stats_reset, 1658 .xstats_get = cxgbe_dev_xstats_get, 1659 .xstats_get_by_id = cxgbe_dev_xstats_get_by_id, 1660 .xstats_get_names = cxgbe_dev_xstats_get_names, 1661 .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id, 1662 .xstats_reset = cxgbe_dev_xstats_reset, 1663 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1664 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1665 .get_eeprom_length = cxgbe_get_eeprom_length, 1666 .get_eeprom = cxgbe_get_eeprom, 1667 .set_eeprom = cxgbe_set_eeprom, 1668 .get_reg = cxgbe_get_regs, 1669 .rss_hash_update = cxgbe_dev_rss_hash_update, 1670 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1671 .mac_addr_set = cxgbe_mac_addr_set, 1672 .reta_update = cxgbe_dev_rss_reta_update, 1673 .reta_query = cxgbe_dev_rss_reta_query, 1674 .fec_get_capability = cxgbe_fec_get_capability, 1675 .fec_get = cxgbe_fec_get, 1676 .fec_set = cxgbe_fec_set, 1677 .fw_version_get = cxgbe_fw_version_get, 1678 }; 1679 1680 /* 1681 * Initialize driver 1682 * It returns 0 on success. 1683 */ 1684 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1685 { 1686 struct rte_pci_device *pci_dev; 1687 struct port_info *pi = eth_dev->data->dev_private; 1688 struct adapter *adapter = NULL; 1689 char name[RTE_ETH_NAME_MAX_LEN]; 1690 int err = 0; 1691 1692 CXGBE_FUNC_TRACE(); 1693 1694 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1695 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1696 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1697 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1698 1699 /* for secondary processes, we attach to ethdevs allocated by primary 1700 * and do minimal initialization. 1701 */ 1702 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1703 int i; 1704 1705 for (i = 1; i < MAX_NPORTS; i++) { 1706 struct rte_eth_dev *rest_eth_dev; 1707 char namei[RTE_ETH_NAME_MAX_LEN]; 1708 1709 snprintf(namei, sizeof(namei), "%s_%d", 1710 pci_dev->device.name, i); 1711 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1712 if (rest_eth_dev) { 1713 rest_eth_dev->device = &pci_dev->device; 1714 rest_eth_dev->dev_ops = 1715 eth_dev->dev_ops; 1716 rest_eth_dev->rx_pkt_burst = 1717 eth_dev->rx_pkt_burst; 1718 rest_eth_dev->tx_pkt_burst = 1719 eth_dev->tx_pkt_burst; 1720 rte_eth_dev_probing_finish(rest_eth_dev); 1721 } 1722 } 1723 return 0; 1724 } 1725 1726 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1727 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1728 if (!adapter) 1729 return -1; 1730 1731 adapter->use_unpacked_mode = 1; 1732 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1733 if (!adapter->regs) { 1734 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1735 err = -ENOMEM; 1736 goto out_free_adapter; 1737 } 1738 adapter->pdev = pci_dev; 1739 adapter->eth_dev = eth_dev; 1740 pi->adapter = adapter; 1741 1742 cxgbe_process_devargs(adapter); 1743 1744 err = cxgbe_probe(adapter); 1745 if (err) { 1746 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1747 __func__, err); 1748 goto out_free_adapter; 1749 } 1750 1751 return 0; 1752 1753 out_free_adapter: 1754 rte_free(adapter); 1755 return err; 1756 } 1757 1758 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1759 { 1760 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1761 uint16_t port_id; 1762 int err = 0; 1763 1764 /* Free up other ports and all resources */ 1765 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1766 err |= rte_eth_dev_close(port_id); 1767 1768 return err == 0 ? 0 : -EIO; 1769 } 1770 1771 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1772 struct rte_pci_device *pci_dev) 1773 { 1774 return rte_eth_dev_pci_generic_probe(pci_dev, 1775 sizeof(struct port_info), eth_cxgbe_dev_init); 1776 } 1777 1778 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1779 { 1780 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1781 } 1782 1783 static struct rte_pci_driver rte_cxgbe_pmd = { 1784 .id_table = cxgb4_pci_tbl, 1785 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1786 .probe = eth_cxgbe_pci_probe, 1787 .remove = eth_cxgbe_pci_remove, 1788 }; 1789 1790 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1791 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1792 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1793 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1794 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1795 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1796 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1797 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1798 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE); 1799 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE); 1800