1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <ethdev_driver.h> 31 #include <ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 36 #include "cxgbe.h" 37 #include "cxgbe_pfvf.h" 38 #include "cxgbe_flow.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "base/t4_pci_id_tbl.h" 60 61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 62 uint16_t nb_pkts) 63 { 64 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 65 uint16_t pkts_sent, pkts_remain; 66 uint16_t total_sent = 0; 67 uint16_t idx = 0; 68 int ret = 0; 69 70 t4_os_lock(&txq->txq_lock); 71 /* free up desc from already completed tx */ 72 reclaim_completed_tx(&txq->q); 73 if (unlikely(!nb_pkts)) 74 goto out_unlock; 75 76 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 77 while (total_sent < nb_pkts) { 78 pkts_remain = nb_pkts - total_sent; 79 80 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 81 idx = total_sent + pkts_sent; 82 if ((idx + 1) < nb_pkts) 83 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 84 volatile void *)); 85 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 86 if (ret < 0) 87 break; 88 } 89 if (!pkts_sent) 90 break; 91 total_sent += pkts_sent; 92 /* reclaim as much as possible */ 93 reclaim_completed_tx(&txq->q); 94 } 95 96 out_unlock: 97 t4_os_unlock(&txq->txq_lock); 98 return total_sent; 99 } 100 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 102 uint16_t nb_pkts) 103 { 104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 105 unsigned int work_done; 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 return work_done; 111 } 112 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 114 struct rte_eth_dev_info *device_info) 115 { 116 struct port_info *pi = eth_dev->data->dev_private; 117 struct adapter *adapter = pi->adapter; 118 119 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 120 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 121 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 122 .nb_align = 1, 123 }; 124 125 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 126 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 127 device_info->max_rx_queues = adapter->sge.max_ethqsets; 128 device_info->max_tx_queues = adapter->sge.max_ethqsets; 129 device_info->max_mac_addrs = 1; 130 /* XXX: For now we support one MAC/port */ 131 device_info->max_vfs = adapter->params.arch.vfcount; 132 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 133 134 device_info->rx_queue_offload_capa = 0UL; 135 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 136 137 device_info->tx_queue_offload_capa = 0UL; 138 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 139 140 device_info->reta_size = pi->rss_size; 141 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 142 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 143 144 device_info->rx_desc_lim = cxgbe_desc_lim; 145 device_info->tx_desc_lim = cxgbe_desc_lim; 146 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 147 148 return 0; 149 } 150 151 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 152 { 153 struct port_info *pi = eth_dev->data->dev_private; 154 struct adapter *adapter = pi->adapter; 155 int ret; 156 157 if (adapter->params.rawf_size != 0) { 158 ret = cxgbe_mpstcam_rawf_enable(pi); 159 if (ret < 0) 160 return ret; 161 } 162 163 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 164 1, -1, 1, -1, false); 165 } 166 167 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 168 { 169 struct port_info *pi = eth_dev->data->dev_private; 170 struct adapter *adapter = pi->adapter; 171 int ret; 172 173 if (adapter->params.rawf_size != 0) { 174 ret = cxgbe_mpstcam_rawf_disable(pi); 175 if (ret < 0) 176 return ret; 177 } 178 179 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 180 0, -1, 1, -1, false); 181 } 182 183 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 184 { 185 struct port_info *pi = eth_dev->data->dev_private; 186 struct adapter *adapter = pi->adapter; 187 188 /* TODO: address filters ?? */ 189 190 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 191 -1, 1, 1, -1, false); 192 } 193 194 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 195 { 196 struct port_info *pi = eth_dev->data->dev_private; 197 struct adapter *adapter = pi->adapter; 198 199 /* TODO: address filters ?? */ 200 201 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 202 -1, 0, 1, -1, false); 203 } 204 205 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 206 int wait_to_complete) 207 { 208 struct port_info *pi = eth_dev->data->dev_private; 209 unsigned int i, work_done, budget = 32; 210 struct link_config *lc = &pi->link_cfg; 211 struct adapter *adapter = pi->adapter; 212 struct rte_eth_link new_link = { 0 }; 213 u8 old_link = pi->link_cfg.link_ok; 214 struct sge *s = &adapter->sge; 215 216 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 217 if (!s->fw_evtq.desc) 218 break; 219 220 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 221 222 /* Exit if link status changed or always forced up */ 223 if (pi->link_cfg.link_ok != old_link || 224 cxgbe_force_linkup(adapter)) 225 break; 226 227 if (!wait_to_complete) 228 break; 229 230 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 231 } 232 233 new_link.link_status = cxgbe_force_linkup(adapter) ? 234 RTE_ETH_LINK_UP : pi->link_cfg.link_ok; 235 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; 236 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 237 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps); 238 239 return rte_eth_linkstatus_set(eth_dev, &new_link); 240 } 241 242 /** 243 * Set device link up. 244 */ 245 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 246 { 247 struct port_info *pi = dev->data->dev_private; 248 struct adapter *adapter = pi->adapter; 249 unsigned int work_done, budget = 32; 250 struct sge *s = &adapter->sge; 251 int ret; 252 253 if (!s->fw_evtq.desc) 254 return -ENOMEM; 255 256 /* Flush all link events */ 257 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 258 259 /* If link already up, nothing to do */ 260 if (pi->link_cfg.link_ok) 261 return 0; 262 263 ret = cxgbe_set_link_status(pi, true); 264 if (ret) 265 return ret; 266 267 cxgbe_dev_link_update(dev, 1); 268 return 0; 269 } 270 271 /** 272 * Set device link down. 273 */ 274 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 275 { 276 struct port_info *pi = dev->data->dev_private; 277 struct adapter *adapter = pi->adapter; 278 unsigned int work_done, budget = 32; 279 struct sge *s = &adapter->sge; 280 int ret; 281 282 if (!s->fw_evtq.desc) 283 return -ENOMEM; 284 285 /* Flush all link events */ 286 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 287 288 /* If link already down, nothing to do */ 289 if (!pi->link_cfg.link_ok) 290 return 0; 291 292 ret = cxgbe_set_link_status(pi, false); 293 if (ret) 294 return ret; 295 296 cxgbe_dev_link_update(dev, 0); 297 return 0; 298 } 299 300 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 301 { 302 struct port_info *pi = eth_dev->data->dev_private; 303 struct adapter *adapter = pi->adapter; 304 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 305 306 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 307 -1, -1, true); 308 } 309 310 /* 311 * Stop device. 312 */ 313 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 314 { 315 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 316 struct adapter *adapter = pi->adapter; 317 u8 i; 318 319 CXGBE_FUNC_TRACE(); 320 321 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 322 return 0; 323 324 if (!(adapter->flags & FULL_INIT_DONE)) 325 return 0; 326 327 if (!pi->viid) 328 return 0; 329 330 cxgbe_down(pi); 331 t4_sge_eth_release_queues(pi); 332 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 333 pi->viid = 0; 334 335 /* Free up the adapter-wide resources only after all the ports 336 * under this PF have been closed. 337 */ 338 for_each_port(adapter, i) { 339 temp_pi = adap2pinfo(adapter, i); 340 if (temp_pi->viid) 341 return 0; 342 } 343 344 cxgbe_close(adapter); 345 rte_free(adapter); 346 347 return 0; 348 } 349 350 /* Start the device. 351 * It returns 0 on success. 352 */ 353 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 354 { 355 struct port_info *pi = eth_dev->data->dev_private; 356 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 357 struct adapter *adapter = pi->adapter; 358 int err = 0, i; 359 360 CXGBE_FUNC_TRACE(); 361 362 /* 363 * If we don't have a connection to the firmware there's nothing we 364 * can do. 365 */ 366 if (!(adapter->flags & FW_OK)) { 367 err = -ENXIO; 368 goto out; 369 } 370 371 if (!(adapter->flags & FULL_INIT_DONE)) { 372 err = cxgbe_up(adapter); 373 if (err < 0) 374 goto out; 375 } 376 377 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 378 eth_dev->data->scattered_rx = 1; 379 else 380 eth_dev->data->scattered_rx = 0; 381 382 cxgbe_enable_rx_queues(pi); 383 384 err = cxgbe_setup_rss(pi); 385 if (err) 386 goto out; 387 388 for (i = 0; i < pi->n_tx_qsets; i++) { 389 err = cxgbe_dev_tx_queue_start(eth_dev, i); 390 if (err) 391 goto out; 392 } 393 394 for (i = 0; i < pi->n_rx_qsets; i++) { 395 err = cxgbe_dev_rx_queue_start(eth_dev, i); 396 if (err) 397 goto out; 398 } 399 400 err = cxgbe_link_start(pi); 401 if (err) 402 goto out; 403 404 out: 405 return err; 406 } 407 408 /* 409 * Stop device: disable rx and tx functions to allow for reconfiguring. 410 */ 411 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 412 { 413 struct port_info *pi = eth_dev->data->dev_private; 414 struct adapter *adapter = pi->adapter; 415 416 CXGBE_FUNC_TRACE(); 417 418 if (!(adapter->flags & FULL_INIT_DONE)) 419 return 0; 420 421 cxgbe_down(pi); 422 423 /* 424 * We clear queues only if both tx and rx path of the port 425 * have been disabled 426 */ 427 t4_sge_eth_clear_queues(pi); 428 eth_dev->data->scattered_rx = 0; 429 430 return 0; 431 } 432 433 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 434 { 435 struct port_info *pi = eth_dev->data->dev_private; 436 struct adapter *adapter = pi->adapter; 437 int err; 438 439 CXGBE_FUNC_TRACE(); 440 441 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 442 eth_dev->data->dev_conf.rxmode.offloads |= 443 RTE_ETH_RX_OFFLOAD_RSS_HASH; 444 445 if (!(adapter->flags & FW_QUEUE_BOUND)) { 446 err = cxgbe_setup_sge_fwevtq(adapter); 447 if (err) 448 return err; 449 adapter->flags |= FW_QUEUE_BOUND; 450 if (is_pf4(adapter)) { 451 err = cxgbe_setup_sge_ctrl_txq(adapter); 452 if (err) 453 return err; 454 } 455 } 456 457 err = cxgbe_cfg_queue_count(eth_dev); 458 if (err) 459 return err; 460 461 return 0; 462 } 463 464 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 465 { 466 int ret; 467 struct sge_eth_txq *txq = (struct sge_eth_txq *) 468 (eth_dev->data->tx_queues[tx_queue_id]); 469 470 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 471 472 ret = t4_sge_eth_txq_start(txq); 473 if (ret == 0) 474 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 475 476 return ret; 477 } 478 479 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 480 { 481 int ret; 482 struct sge_eth_txq *txq = (struct sge_eth_txq *) 483 (eth_dev->data->tx_queues[tx_queue_id]); 484 485 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 486 487 ret = t4_sge_eth_txq_stop(txq); 488 if (ret == 0) 489 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 490 491 return ret; 492 } 493 494 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 495 uint16_t queue_idx, uint16_t nb_desc, 496 unsigned int socket_id, 497 const struct rte_eth_txconf *tx_conf __rte_unused) 498 { 499 struct port_info *pi = eth_dev->data->dev_private; 500 struct adapter *adapter = pi->adapter; 501 struct sge *s = &adapter->sge; 502 unsigned int temp_nb_desc; 503 struct sge_eth_txq *txq; 504 int err = 0; 505 506 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 507 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 508 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 509 socket_id, pi->first_txqset); 510 511 /* Free up the existing queue */ 512 if (eth_dev->data->tx_queues[queue_idx]) { 513 cxgbe_dev_tx_queue_release(eth_dev, queue_idx); 514 eth_dev->data->tx_queues[queue_idx] = NULL; 515 } 516 517 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 518 519 /* Sanity Checking 520 * 521 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 522 */ 523 temp_nb_desc = nb_desc; 524 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 525 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 526 __func__, CXGBE_MIN_RING_DESC_SIZE, 527 CXGBE_DEFAULT_TX_DESC_SIZE); 528 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 529 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 530 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 531 __func__, CXGBE_MIN_RING_DESC_SIZE, 532 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 533 return -(EINVAL); 534 } 535 536 txq->q.size = temp_nb_desc; 537 538 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 539 s->fw_evtq.cntxt_id, socket_id); 540 541 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 542 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 543 return err; 544 } 545 546 void cxgbe_dev_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 547 { 548 struct sge_eth_txq *txq = eth_dev->data->tx_queues[qid]; 549 550 if (txq) { 551 struct port_info *pi = (struct port_info *) 552 (txq->eth_dev->data->dev_private); 553 struct adapter *adap = pi->adapter; 554 555 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 556 __func__, pi->port_id, txq->q.cntxt_id); 557 558 t4_sge_eth_txq_release(adap, txq); 559 } 560 } 561 562 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 563 { 564 struct port_info *pi = eth_dev->data->dev_private; 565 struct adapter *adap = pi->adapter; 566 struct sge_eth_rxq *rxq; 567 int ret; 568 569 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 570 __func__, pi->port_id, rx_queue_id); 571 572 rxq = eth_dev->data->rx_queues[rx_queue_id]; 573 ret = t4_sge_eth_rxq_start(adap, rxq); 574 if (ret == 0) 575 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 576 577 return ret; 578 } 579 580 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 581 { 582 struct port_info *pi = eth_dev->data->dev_private; 583 struct adapter *adap = pi->adapter; 584 struct sge_eth_rxq *rxq; 585 int ret; 586 587 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 588 __func__, pi->port_id, rx_queue_id); 589 590 rxq = eth_dev->data->rx_queues[rx_queue_id]; 591 ret = t4_sge_eth_rxq_stop(adap, rxq); 592 if (ret == 0) 593 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 594 595 return ret; 596 } 597 598 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 599 uint16_t queue_idx, uint16_t nb_desc, 600 unsigned int socket_id, 601 const struct rte_eth_rxconf *rx_conf __rte_unused, 602 struct rte_mempool *mp) 603 { 604 unsigned int pkt_len = eth_dev->data->mtu + RTE_ETHER_HDR_LEN + 605 RTE_ETHER_CRC_LEN; 606 struct port_info *pi = eth_dev->data->dev_private; 607 struct adapter *adapter = pi->adapter; 608 struct rte_eth_dev_info dev_info; 609 struct sge *s = &adapter->sge; 610 unsigned int temp_nb_desc; 611 int err = 0, msi_idx = 0; 612 struct sge_eth_rxq *rxq; 613 614 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 615 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 616 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 617 socket_id, mp); 618 619 err = cxgbe_dev_info_get(eth_dev, &dev_info); 620 if (err != 0) { 621 dev_err(adap, "%s: error during getting ethernet device info", 622 __func__); 623 return err; 624 } 625 626 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 627 if ((pkt_len < dev_info.min_rx_bufsize) || 628 (pkt_len > dev_info.max_rx_pktlen)) { 629 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 630 __func__, dev_info.min_rx_bufsize, 631 dev_info.max_rx_pktlen); 632 return -EINVAL; 633 } 634 635 /* Free up the existing queue */ 636 if (eth_dev->data->rx_queues[queue_idx]) { 637 cxgbe_dev_rx_queue_release(eth_dev, queue_idx); 638 eth_dev->data->rx_queues[queue_idx] = NULL; 639 } 640 641 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 642 643 /* Sanity Checking 644 * 645 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 646 */ 647 temp_nb_desc = nb_desc; 648 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 649 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 650 __func__, CXGBE_MIN_RING_DESC_SIZE, 651 CXGBE_DEFAULT_RX_DESC_SIZE); 652 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 653 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 654 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 655 __func__, CXGBE_MIN_RING_DESC_SIZE, 656 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 657 return -(EINVAL); 658 } 659 660 rxq->rspq.size = temp_nb_desc; 661 rxq->fl.size = temp_nb_desc; 662 663 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 664 &rxq->fl, NULL, 665 is_pf4(adapter) ? 666 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 667 queue_idx, socket_id); 668 669 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 670 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 671 rxq->rspq.abs_id); 672 return err; 673 } 674 675 void cxgbe_dev_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 676 { 677 struct sge_eth_rxq *rxq = eth_dev->data->rx_queues[qid]; 678 679 if (rxq) { 680 struct port_info *pi = (struct port_info *) 681 (rxq->rspq.eth_dev->data->dev_private); 682 struct adapter *adap = pi->adapter; 683 684 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 685 __func__, pi->port_id, rxq->rspq.cntxt_id); 686 687 t4_sge_eth_rxq_release(adap, rxq); 688 } 689 } 690 691 /* 692 * Get port statistics. 693 */ 694 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 695 struct rte_eth_stats *eth_stats) 696 { 697 struct port_info *pi = eth_dev->data->dev_private; 698 struct adapter *adapter = pi->adapter; 699 struct sge *s = &adapter->sge; 700 struct port_stats ps; 701 unsigned int i; 702 703 cxgbe_stats_get(pi, &ps); 704 705 /* RX Stats */ 706 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 707 ps.rx_ovflow2 + ps.rx_ovflow3 + 708 ps.rx_trunc0 + ps.rx_trunc1 + 709 ps.rx_trunc2 + ps.rx_trunc3; 710 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 711 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 712 ps.rx_len_err; 713 714 /* TX Stats */ 715 eth_stats->opackets = ps.tx_frames; 716 eth_stats->obytes = ps.tx_octets; 717 eth_stats->oerrors = ps.tx_error_frames; 718 719 for (i = 0; i < pi->n_rx_qsets; i++) { 720 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 721 722 eth_stats->ipackets += rxq->stats.pkts; 723 eth_stats->ibytes += rxq->stats.rx_bytes; 724 } 725 726 return 0; 727 } 728 729 /* 730 * Reset port statistics. 731 */ 732 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 733 { 734 struct port_info *pi = eth_dev->data->dev_private; 735 struct adapter *adapter = pi->adapter; 736 struct sge *s = &adapter->sge; 737 unsigned int i; 738 739 cxgbe_stats_reset(pi); 740 for (i = 0; i < pi->n_rx_qsets; i++) { 741 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 742 743 memset(&rxq->stats, 0, sizeof(rxq->stats)); 744 } 745 for (i = 0; i < pi->n_tx_qsets; i++) { 746 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i]; 747 748 memset(&txq->stats, 0, sizeof(txq->stats)); 749 } 750 751 return 0; 752 } 753 754 /* Store extended statistics names and its offset in stats structure */ 755 struct cxgbe_dev_xstats_name_off { 756 char name[RTE_ETH_XSTATS_NAME_SIZE]; 757 unsigned int offset; 758 }; 759 760 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = { 761 {"packets", offsetof(struct sge_eth_rx_stats, pkts)}, 762 {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)}, 763 {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)}, 764 {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)}, 765 {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)}, 766 }; 767 768 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = { 769 {"packets", offsetof(struct sge_eth_tx_stats, pkts)}, 770 {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)}, 771 {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)}, 772 {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)}, 773 {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)}, 774 {"packet_mapping_errors", 775 offsetof(struct sge_eth_tx_stats, mapping_err)}, 776 {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)}, 777 {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)}, 778 }; 779 780 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = { 781 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 782 {"tx_packets", offsetof(struct port_stats, tx_frames)}, 783 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 784 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 785 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 786 {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)}, 787 {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)}, 788 {"tx_size_65_to_127_packets", 789 offsetof(struct port_stats, tx_frames_65_127)}, 790 {"tx_size_128_to_255_packets", 791 offsetof(struct port_stats, tx_frames_128_255)}, 792 {"tx_size_256_to_511_packets", 793 offsetof(struct port_stats, tx_frames_256_511)}, 794 {"tx_size_512_to_1023_packets", 795 offsetof(struct port_stats, tx_frames_512_1023)}, 796 {"tx_size_1024_to_1518_packets", 797 offsetof(struct port_stats, tx_frames_1024_1518)}, 798 {"tx_size_1519_to_max_packets", 799 offsetof(struct port_stats, tx_frames_1519_max)}, 800 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 801 {"tx_pause_frames", offsetof(struct port_stats, tx_pause)}, 802 {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)}, 803 {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)}, 804 {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)}, 805 {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)}, 806 {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)}, 807 {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)}, 808 {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)}, 809 {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)}, 810 {"rx_bytes", offsetof(struct port_stats, rx_octets)}, 811 {"rx_packets", offsetof(struct port_stats, rx_frames)}, 812 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 813 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 814 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 815 {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)}, 816 {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)}, 817 {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)}, 818 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 819 {"rx_symbol_error_packets", 820 offsetof(struct port_stats, rx_symbol_err)}, 821 {"rx_short_packets", offsetof(struct port_stats, rx_runt)}, 822 {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)}, 823 {"rx_size_65_to_127_packets", 824 offsetof(struct port_stats, rx_frames_65_127)}, 825 {"rx_size_128_to_255_packets", 826 offsetof(struct port_stats, rx_frames_128_255)}, 827 {"rx_size_256_to_511_packets", 828 offsetof(struct port_stats, rx_frames_256_511)}, 829 {"rx_size_512_to_1023_packets", 830 offsetof(struct port_stats, rx_frames_512_1023)}, 831 {"rx_size_1024_to_1518_packets", 832 offsetof(struct port_stats, rx_frames_1024_1518)}, 833 {"rx_size_1519_to_max_packets", 834 offsetof(struct port_stats, rx_frames_1519_max)}, 835 {"rx_pause_packets", offsetof(struct port_stats, rx_pause)}, 836 {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)}, 837 {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)}, 838 {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)}, 839 {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)}, 840 {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)}, 841 {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)}, 842 {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)}, 843 {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)}, 844 {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)}, 845 {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)}, 846 {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)}, 847 {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)}, 848 {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)}, 849 {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)}, 850 {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)}, 851 {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)}, 852 }; 853 854 static const struct cxgbe_dev_xstats_name_off 855 cxgbevf_dev_port_stats_strings[] = { 856 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 857 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 858 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 859 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 860 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 861 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 862 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 863 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 864 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 865 }; 866 867 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings) 868 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings) 869 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings) 870 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings) 871 872 static u16 cxgbe_dev_xstats_count(struct port_info *pi) 873 { 874 u16 count; 875 876 count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) + 877 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS); 878 879 if (is_pf4(pi->adapter) != 0) 880 count += CXGBE_NB_PORT_STATS; 881 else 882 count += CXGBEVF_NB_PORT_STATS; 883 884 return count; 885 } 886 887 static int cxgbe_dev_xstats(struct rte_eth_dev *dev, 888 struct rte_eth_xstat_name *xstats_names, 889 struct rte_eth_xstat *xstats, unsigned int size) 890 { 891 const struct cxgbe_dev_xstats_name_off *xstats_str; 892 struct port_info *pi = dev->data->dev_private; 893 struct adapter *adap = pi->adapter; 894 struct sge *s = &adap->sge; 895 u16 count, i, qid, nstats; 896 struct port_stats ps; 897 u64 *stats_ptr; 898 899 count = cxgbe_dev_xstats_count(pi); 900 if (size < count) 901 return count; 902 903 if (is_pf4(adap) != 0) { 904 /* port stats for PF*/ 905 cxgbe_stats_get(pi, &ps); 906 xstats_str = cxgbe_dev_port_stats_strings; 907 nstats = CXGBE_NB_PORT_STATS; 908 } else { 909 /* port stats for VF*/ 910 cxgbevf_stats_get(pi, &ps); 911 xstats_str = cxgbevf_dev_port_stats_strings; 912 nstats = CXGBEVF_NB_PORT_STATS; 913 } 914 915 count = 0; 916 for (i = 0; i < nstats; i++, count++) { 917 if (xstats_names != NULL) 918 snprintf(xstats_names[count].name, 919 sizeof(xstats_names[count].name), 920 "%s", xstats_str[i].name); 921 if (xstats != NULL) { 922 stats_ptr = RTE_PTR_ADD(&ps, 923 xstats_str[i].offset); 924 xstats[count].value = *stats_ptr; 925 xstats[count].id = count; 926 } 927 } 928 929 /* per-txq stats */ 930 xstats_str = cxgbe_dev_txq_stats_strings; 931 for (qid = 0; qid < pi->n_tx_qsets; qid++) { 932 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid]; 933 934 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) { 935 if (xstats_names != NULL) 936 snprintf(xstats_names[count].name, 937 sizeof(xstats_names[count].name), 938 "tx_q%u_%s", 939 qid, xstats_str[i].name); 940 if (xstats != NULL) { 941 stats_ptr = RTE_PTR_ADD(&txq->stats, 942 xstats_str[i].offset); 943 xstats[count].value = *stats_ptr; 944 xstats[count].id = count; 945 } 946 } 947 } 948 949 /* per-rxq stats */ 950 xstats_str = cxgbe_dev_rxq_stats_strings; 951 for (qid = 0; qid < pi->n_rx_qsets; qid++) { 952 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid]; 953 954 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) { 955 if (xstats_names != NULL) 956 snprintf(xstats_names[count].name, 957 sizeof(xstats_names[count].name), 958 "rx_q%u_%s", 959 qid, xstats_str[i].name); 960 if (xstats != NULL) { 961 stats_ptr = RTE_PTR_ADD(&rxq->stats, 962 xstats_str[i].offset); 963 xstats[count].value = *stats_ptr; 964 xstats[count].id = count; 965 } 966 } 967 } 968 969 return count; 970 } 971 972 /* Get port extended statistics by ID. */ 973 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 974 const uint64_t *ids, uint64_t *values, 975 unsigned int n) 976 { 977 struct port_info *pi = dev->data->dev_private; 978 struct rte_eth_xstat *xstats_copy; 979 u16 count, i; 980 int ret = 0; 981 982 count = cxgbe_dev_xstats_count(pi); 983 if (ids == NULL || values == NULL) 984 return count; 985 986 xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0); 987 if (xstats_copy == NULL) 988 return -ENOMEM; 989 990 cxgbe_dev_xstats(dev, NULL, xstats_copy, count); 991 992 for (i = 0; i < n; i++) { 993 if (ids[i] >= count) { 994 ret = -EINVAL; 995 goto out_err; 996 } 997 values[i] = xstats_copy[ids[i]].value; 998 } 999 1000 ret = n; 1001 1002 out_err: 1003 rte_free(xstats_copy); 1004 return ret; 1005 } 1006 1007 /* Get names of port extended statistics by ID. */ 1008 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1009 const uint64_t *ids, 1010 struct rte_eth_xstat_name *xnames, 1011 unsigned int n) 1012 { 1013 struct port_info *pi = dev->data->dev_private; 1014 struct rte_eth_xstat_name *xnames_copy; 1015 u16 count, i; 1016 int ret = 0; 1017 1018 count = cxgbe_dev_xstats_count(pi); 1019 if (ids == NULL || xnames == NULL) 1020 return count; 1021 1022 xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0); 1023 if (xnames_copy == NULL) 1024 return -ENOMEM; 1025 1026 cxgbe_dev_xstats(dev, xnames_copy, NULL, count); 1027 1028 for (i = 0; i < n; i++) { 1029 if (ids[i] >= count) { 1030 ret = -EINVAL; 1031 goto out_err; 1032 } 1033 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name, 1034 sizeof(xnames[i].name)); 1035 } 1036 1037 ret = n; 1038 1039 out_err: 1040 rte_free(xnames_copy); 1041 return ret; 1042 } 1043 1044 /* Get port extended statistics. */ 1045 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev, 1046 struct rte_eth_xstat *xstats, unsigned int n) 1047 { 1048 return cxgbe_dev_xstats(dev, NULL, xstats, n); 1049 } 1050 1051 /* Get names of port extended statistics. */ 1052 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 1053 struct rte_eth_xstat_name *xstats_names, 1054 unsigned int n) 1055 { 1056 return cxgbe_dev_xstats(dev, xstats_names, NULL, n); 1057 } 1058 1059 /* Reset port extended statistics. */ 1060 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1061 { 1062 return cxgbe_dev_stats_reset(dev); 1063 } 1064 1065 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1066 struct rte_eth_fc_conf *fc_conf) 1067 { 1068 struct port_info *pi = eth_dev->data->dev_private; 1069 struct link_config *lc = &pi->link_cfg; 1070 u8 rx_pause = 0, tx_pause = 0; 1071 u32 caps = lc->link_caps; 1072 1073 if (caps & FW_PORT_CAP32_ANEG) 1074 fc_conf->autoneg = 1; 1075 1076 if (caps & FW_PORT_CAP32_FC_TX) 1077 tx_pause = 1; 1078 1079 if (caps & FW_PORT_CAP32_FC_RX) 1080 rx_pause = 1; 1081 1082 if (rx_pause && tx_pause) 1083 fc_conf->mode = RTE_ETH_FC_FULL; 1084 else if (rx_pause) 1085 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 1086 else if (tx_pause) 1087 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1088 else 1089 fc_conf->mode = RTE_ETH_FC_NONE; 1090 return 0; 1091 } 1092 1093 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1094 struct rte_eth_fc_conf *fc_conf) 1095 { 1096 struct port_info *pi = eth_dev->data->dev_private; 1097 struct link_config *lc = &pi->link_cfg; 1098 u32 new_caps = lc->admin_caps; 1099 u8 tx_pause = 0, rx_pause = 0; 1100 int ret; 1101 1102 if (fc_conf->mode == RTE_ETH_FC_FULL) { 1103 tx_pause = 1; 1104 rx_pause = 1; 1105 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE) { 1106 tx_pause = 1; 1107 } else if (fc_conf->mode == RTE_ETH_FC_RX_PAUSE) { 1108 rx_pause = 1; 1109 } 1110 1111 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause, 1112 rx_pause, &new_caps); 1113 if (ret != 0) 1114 return ret; 1115 1116 if (!fc_conf->autoneg) { 1117 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE) 1118 new_caps |= FW_PORT_CAP32_FORCE_PAUSE; 1119 } else { 1120 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE; 1121 } 1122 1123 if (new_caps != lc->admin_caps) { 1124 ret = t4_link_l1cfg(pi, new_caps); 1125 if (ret == 0) 1126 lc->admin_caps = new_caps; 1127 } 1128 1129 return ret; 1130 } 1131 1132 const uint32_t * 1133 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 1134 { 1135 static const uint32_t ptypes[] = { 1136 RTE_PTYPE_L3_IPV4, 1137 RTE_PTYPE_L3_IPV6, 1138 RTE_PTYPE_UNKNOWN 1139 }; 1140 1141 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 1142 return ptypes; 1143 return NULL; 1144 } 1145 1146 /* Update RSS hash configuration 1147 */ 1148 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 1149 struct rte_eth_rss_conf *rss_conf) 1150 { 1151 struct port_info *pi = dev->data->dev_private; 1152 struct adapter *adapter = pi->adapter; 1153 int err; 1154 1155 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 1156 if (err) 1157 return err; 1158 1159 pi->rss_hf = rss_conf->rss_hf; 1160 1161 if (rss_conf->rss_key) { 1162 u32 key[10], mod_key[10]; 1163 int i, j; 1164 1165 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1166 1167 for (i = 9, j = 0; i >= 0; i--, j++) 1168 mod_key[j] = cpu_to_be32(key[i]); 1169 1170 t4_write_rss_key(adapter, mod_key, -1); 1171 } 1172 1173 return 0; 1174 } 1175 1176 /* Get RSS hash configuration 1177 */ 1178 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1179 struct rte_eth_rss_conf *rss_conf) 1180 { 1181 struct port_info *pi = dev->data->dev_private; 1182 struct adapter *adapter = pi->adapter; 1183 u64 rss_hf = 0; 1184 u64 flags = 0; 1185 int err; 1186 1187 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 1188 &flags, NULL); 1189 1190 if (err) 1191 return err; 1192 1193 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 1194 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 1195 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1196 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 1197 } 1198 1199 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1200 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 1201 1202 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 1203 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 1204 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1205 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 1206 } 1207 1208 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1209 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 1210 1211 rss_conf->rss_hf = rss_hf; 1212 1213 if (rss_conf->rss_key) { 1214 u32 key[10], mod_key[10]; 1215 int i, j; 1216 1217 t4_read_rss_key(adapter, key); 1218 1219 for (i = 9, j = 0; i >= 0; i--, j++) 1220 mod_key[j] = be32_to_cpu(key[i]); 1221 1222 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1223 } 1224 1225 return 0; 1226 } 1227 1228 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 1229 struct rte_eth_rss_reta_entry64 *reta_conf, 1230 uint16_t reta_size) 1231 { 1232 struct port_info *pi = dev->data->dev_private; 1233 struct adapter *adapter = pi->adapter; 1234 u16 i, idx, shift, *rss; 1235 int ret; 1236 1237 if (!(adapter->flags & FULL_INIT_DONE)) 1238 return -ENOMEM; 1239 1240 if (!reta_size || reta_size > pi->rss_size) 1241 return -EINVAL; 1242 1243 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 1244 if (!rss) 1245 return -ENOMEM; 1246 1247 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 1248 for (i = 0; i < reta_size; i++) { 1249 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1250 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1251 if (!(reta_conf[idx].mask & (1ULL << shift))) 1252 continue; 1253 1254 rss[i] = reta_conf[idx].reta[shift]; 1255 } 1256 1257 ret = cxgbe_write_rss(pi, rss); 1258 if (!ret) 1259 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 1260 1261 rte_free(rss); 1262 return ret; 1263 } 1264 1265 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 1266 struct rte_eth_rss_reta_entry64 *reta_conf, 1267 uint16_t reta_size) 1268 { 1269 struct port_info *pi = dev->data->dev_private; 1270 struct adapter *adapter = pi->adapter; 1271 u16 i, idx, shift; 1272 1273 if (!(adapter->flags & FULL_INIT_DONE)) 1274 return -ENOMEM; 1275 1276 if (!reta_size || reta_size > pi->rss_size) 1277 return -EINVAL; 1278 1279 for (i = 0; i < reta_size; i++) { 1280 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1281 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1282 if (!(reta_conf[idx].mask & (1ULL << shift))) 1283 continue; 1284 1285 reta_conf[idx].reta[shift] = pi->rss[i]; 1286 } 1287 1288 return 0; 1289 } 1290 1291 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 1292 { 1293 RTE_SET_USED(dev); 1294 return EEPROMSIZE; 1295 } 1296 1297 /** 1298 * eeprom_ptov - translate a physical EEPROM address to virtual 1299 * @phys_addr: the physical EEPROM address 1300 * @fn: the PCI function number 1301 * @sz: size of function-specific area 1302 * 1303 * Translate a physical EEPROM address to virtual. The first 1K is 1304 * accessed through virtual addresses starting at 31K, the rest is 1305 * accessed through virtual addresses starting at 0. 1306 * 1307 * The mapping is as follows: 1308 * [0..1K) -> [31K..32K) 1309 * [1K..1K+A) -> [31K-A..31K) 1310 * [1K+A..ES) -> [0..ES-A-1K) 1311 * 1312 * where A = @fn * @sz, and ES = EEPROM size. 1313 */ 1314 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1315 { 1316 fn *= sz; 1317 if (phys_addr < 1024) 1318 return phys_addr + (31 << 10); 1319 if (phys_addr < 1024 + fn) 1320 return fn + phys_addr - 1024; 1321 if (phys_addr < EEPROMSIZE) 1322 return phys_addr - 1024 - fn; 1323 if (phys_addr < EEPROMVSIZE) 1324 return phys_addr - 1024; 1325 return -EINVAL; 1326 } 1327 1328 /* The next two routines implement eeprom read/write from physical addresses. 1329 */ 1330 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1331 { 1332 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1333 1334 if (vaddr >= 0) 1335 vaddr = t4_seeprom_read(adap, vaddr, v); 1336 return vaddr < 0 ? vaddr : 0; 1337 } 1338 1339 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1340 { 1341 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1342 1343 if (vaddr >= 0) 1344 vaddr = t4_seeprom_write(adap, vaddr, v); 1345 return vaddr < 0 ? vaddr : 0; 1346 } 1347 1348 #define EEPROM_MAGIC 0x38E2F10C 1349 1350 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1351 struct rte_dev_eeprom_info *e) 1352 { 1353 struct port_info *pi = dev->data->dev_private; 1354 struct adapter *adapter = pi->adapter; 1355 u32 i, err = 0; 1356 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1357 1358 if (!buf) 1359 return -ENOMEM; 1360 1361 e->magic = EEPROM_MAGIC; 1362 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1363 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1364 1365 if (!err) 1366 rte_memcpy(e->data, buf + e->offset, e->length); 1367 rte_free(buf); 1368 return err; 1369 } 1370 1371 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1372 struct rte_dev_eeprom_info *eeprom) 1373 { 1374 struct port_info *pi = dev->data->dev_private; 1375 struct adapter *adapter = pi->adapter; 1376 u8 *buf; 1377 int err = 0; 1378 u32 aligned_offset, aligned_len, *p; 1379 1380 if (eeprom->magic != EEPROM_MAGIC) 1381 return -EINVAL; 1382 1383 aligned_offset = eeprom->offset & ~3; 1384 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1385 1386 if (adapter->pf > 0) { 1387 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1388 1389 if (aligned_offset < start || 1390 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1391 return -EPERM; 1392 } 1393 1394 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1395 /* RMW possibly needed for first or last words. 1396 */ 1397 buf = rte_zmalloc(NULL, aligned_len, 0); 1398 if (!buf) 1399 return -ENOMEM; 1400 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1401 if (!err && aligned_len > 4) 1402 err = eeprom_rd_phys(adapter, 1403 aligned_offset + aligned_len - 4, 1404 (u32 *)&buf[aligned_len - 4]); 1405 if (err) 1406 goto out; 1407 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1408 eeprom->length); 1409 } else { 1410 buf = eeprom->data; 1411 } 1412 1413 err = t4_seeprom_wp(adapter, false); 1414 if (err) 1415 goto out; 1416 1417 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1418 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1419 aligned_offset += 4; 1420 } 1421 1422 if (!err) 1423 err = t4_seeprom_wp(adapter, true); 1424 out: 1425 if (buf != eeprom->data) 1426 rte_free(buf); 1427 return err; 1428 } 1429 1430 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1431 { 1432 struct port_info *pi = eth_dev->data->dev_private; 1433 struct adapter *adapter = pi->adapter; 1434 1435 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1436 } 1437 1438 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1439 struct rte_dev_reg_info *regs) 1440 { 1441 struct port_info *pi = eth_dev->data->dev_private; 1442 struct adapter *adapter = pi->adapter; 1443 1444 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1445 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1446 (1 << 16); 1447 1448 if (regs->data == NULL) { 1449 regs->length = cxgbe_get_regs_len(eth_dev); 1450 regs->width = sizeof(uint32_t); 1451 1452 return 0; 1453 } 1454 1455 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1456 1457 return 0; 1458 } 1459 1460 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1461 { 1462 struct port_info *pi = dev->data->dev_private; 1463 int ret; 1464 1465 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1466 if (ret < 0) { 1467 dev_err(adapter, "failed to set mac addr; err = %d\n", 1468 ret); 1469 return ret; 1470 } 1471 pi->xact_addr_filt = ret; 1472 return 0; 1473 } 1474 1475 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc, 1476 struct rte_eth_fec_capa *capa_arr) 1477 { 1478 int num = 0; 1479 1480 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) { 1481 if (capa_arr) { 1482 capa_arr[num].speed = RTE_ETH_SPEED_NUM_100G; 1483 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1484 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1485 } 1486 num++; 1487 } 1488 1489 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) { 1490 if (capa_arr) { 1491 capa_arr[num].speed = RTE_ETH_SPEED_NUM_50G; 1492 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1493 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1494 } 1495 num++; 1496 } 1497 1498 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) { 1499 if (capa_arr) { 1500 capa_arr[num].speed = RTE_ETH_SPEED_NUM_25G; 1501 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1502 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 1503 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1504 } 1505 num++; 1506 } 1507 1508 return num; 1509 } 1510 1511 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev, 1512 struct rte_eth_fec_capa *speed_fec_capa, 1513 unsigned int num) 1514 { 1515 struct port_info *pi = dev->data->dev_private; 1516 struct link_config *lc = &pi->link_cfg; 1517 u8 num_entries; 1518 1519 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1520 return -EOPNOTSUPP; 1521 1522 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL); 1523 if (!speed_fec_capa || num < num_entries) 1524 return num_entries; 1525 1526 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa); 1527 } 1528 1529 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 1530 { 1531 struct port_info *pi = dev->data->dev_private; 1532 struct link_config *lc = &pi->link_cfg; 1533 u32 fec_caps = 0, caps = lc->link_caps; 1534 1535 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1536 return -EOPNOTSUPP; 1537 1538 if (caps & FW_PORT_CAP32_FEC_RS) 1539 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1540 else if (caps & FW_PORT_CAP32_FEC_BASER_RS) 1541 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1542 else 1543 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 1544 1545 *fec_capa = fec_caps; 1546 return 0; 1547 } 1548 1549 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 1550 { 1551 struct port_info *pi = dev->data->dev_private; 1552 u8 fec_rs = 0, fec_baser = 0, fec_none = 0; 1553 struct link_config *lc = &pi->link_cfg; 1554 u32 new_caps = lc->admin_caps; 1555 int ret; 1556 1557 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1558 return -EOPNOTSUPP; 1559 1560 if (!fec_capa) 1561 return -EINVAL; 1562 1563 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 1564 goto set_fec; 1565 1566 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) 1567 fec_none = 1; 1568 1569 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 1570 fec_baser = 1; 1571 1572 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 1573 fec_rs = 1; 1574 1575 set_fec: 1576 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps); 1577 if (ret != 0) 1578 return ret; 1579 1580 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 1581 new_caps |= FW_PORT_CAP32_FORCE_FEC; 1582 else 1583 new_caps &= ~FW_PORT_CAP32_FORCE_FEC; 1584 1585 if (new_caps != lc->admin_caps) { 1586 ret = t4_link_l1cfg(pi, new_caps); 1587 if (ret == 0) 1588 lc->admin_caps = new_caps; 1589 } 1590 1591 return ret; 1592 } 1593 1594 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 1595 size_t fw_size) 1596 { 1597 struct port_info *pi = dev->data->dev_private; 1598 struct adapter *adapter = pi->adapter; 1599 int ret; 1600 1601 if (adapter->params.fw_vers == 0) 1602 return -EIO; 1603 1604 ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u", 1605 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers), 1606 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers), 1607 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers), 1608 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers)); 1609 if (ret < 0) 1610 return -EINVAL; 1611 1612 ret += 1; 1613 if (fw_size < (size_t)ret) 1614 return ret; 1615 1616 return 0; 1617 } 1618 1619 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1620 .dev_start = cxgbe_dev_start, 1621 .dev_stop = cxgbe_dev_stop, 1622 .dev_close = cxgbe_dev_close, 1623 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1624 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1625 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1626 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1627 .dev_configure = cxgbe_dev_configure, 1628 .dev_infos_get = cxgbe_dev_info_get, 1629 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1630 .link_update = cxgbe_dev_link_update, 1631 .dev_set_link_up = cxgbe_dev_set_link_up, 1632 .dev_set_link_down = cxgbe_dev_set_link_down, 1633 .mtu_set = cxgbe_dev_mtu_set, 1634 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1635 .tx_queue_start = cxgbe_dev_tx_queue_start, 1636 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1637 .tx_queue_release = cxgbe_dev_tx_queue_release, 1638 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1639 .rx_queue_start = cxgbe_dev_rx_queue_start, 1640 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1641 .rx_queue_release = cxgbe_dev_rx_queue_release, 1642 .flow_ops_get = cxgbe_dev_flow_ops_get, 1643 .stats_get = cxgbe_dev_stats_get, 1644 .stats_reset = cxgbe_dev_stats_reset, 1645 .xstats_get = cxgbe_dev_xstats_get, 1646 .xstats_get_by_id = cxgbe_dev_xstats_get_by_id, 1647 .xstats_get_names = cxgbe_dev_xstats_get_names, 1648 .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id, 1649 .xstats_reset = cxgbe_dev_xstats_reset, 1650 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1651 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1652 .get_eeprom_length = cxgbe_get_eeprom_length, 1653 .get_eeprom = cxgbe_get_eeprom, 1654 .set_eeprom = cxgbe_set_eeprom, 1655 .get_reg = cxgbe_get_regs, 1656 .rss_hash_update = cxgbe_dev_rss_hash_update, 1657 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1658 .mac_addr_set = cxgbe_mac_addr_set, 1659 .reta_update = cxgbe_dev_rss_reta_update, 1660 .reta_query = cxgbe_dev_rss_reta_query, 1661 .fec_get_capability = cxgbe_fec_get_capability, 1662 .fec_get = cxgbe_fec_get, 1663 .fec_set = cxgbe_fec_set, 1664 .fw_version_get = cxgbe_fw_version_get, 1665 }; 1666 1667 /* 1668 * Initialize driver 1669 * It returns 0 on success. 1670 */ 1671 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1672 { 1673 struct rte_pci_device *pci_dev; 1674 struct port_info *pi = eth_dev->data->dev_private; 1675 struct adapter *adapter = NULL; 1676 char name[RTE_ETH_NAME_MAX_LEN]; 1677 int err = 0; 1678 1679 CXGBE_FUNC_TRACE(); 1680 1681 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1682 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1683 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1684 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1685 1686 /* for secondary processes, we attach to ethdevs allocated by primary 1687 * and do minimal initialization. 1688 */ 1689 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1690 int i; 1691 1692 for (i = 1; i < MAX_NPORTS; i++) { 1693 struct rte_eth_dev *rest_eth_dev; 1694 char namei[RTE_ETH_NAME_MAX_LEN]; 1695 1696 snprintf(namei, sizeof(namei), "%s_%d", 1697 pci_dev->device.name, i); 1698 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1699 if (rest_eth_dev) { 1700 rest_eth_dev->device = &pci_dev->device; 1701 rest_eth_dev->dev_ops = 1702 eth_dev->dev_ops; 1703 rest_eth_dev->rx_pkt_burst = 1704 eth_dev->rx_pkt_burst; 1705 rest_eth_dev->tx_pkt_burst = 1706 eth_dev->tx_pkt_burst; 1707 rte_eth_dev_probing_finish(rest_eth_dev); 1708 } 1709 } 1710 return 0; 1711 } 1712 1713 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1714 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1715 if (!adapter) 1716 return -1; 1717 1718 adapter->use_unpacked_mode = 1; 1719 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1720 if (!adapter->regs) { 1721 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1722 err = -ENOMEM; 1723 goto out_free_adapter; 1724 } 1725 adapter->pdev = pci_dev; 1726 adapter->eth_dev = eth_dev; 1727 pi->adapter = adapter; 1728 1729 cxgbe_process_devargs(adapter); 1730 1731 err = cxgbe_probe(adapter); 1732 if (err) { 1733 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1734 __func__, err); 1735 goto out_free_adapter; 1736 } 1737 1738 return 0; 1739 1740 out_free_adapter: 1741 rte_free(adapter); 1742 return err; 1743 } 1744 1745 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1746 { 1747 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1748 uint16_t port_id; 1749 int err = 0; 1750 1751 /* Free up other ports and all resources */ 1752 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1753 err |= rte_eth_dev_close(port_id); 1754 1755 return err == 0 ? 0 : -EIO; 1756 } 1757 1758 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1759 struct rte_pci_device *pci_dev) 1760 { 1761 return rte_eth_dev_pci_generic_probe(pci_dev, 1762 sizeof(struct port_info), eth_cxgbe_dev_init); 1763 } 1764 1765 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1766 { 1767 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1768 } 1769 1770 static struct rte_pci_driver rte_cxgbe_pmd = { 1771 .id_table = cxgb4_pci_tbl, 1772 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1773 .probe = eth_cxgbe_pci_probe, 1774 .remove = eth_cxgbe_pci_remove, 1775 }; 1776 1777 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1778 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1779 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1780 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1781 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1782 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1783 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1784 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1785 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE); 1786 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE); 1787