1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 int cxgbe_logtype; 42 43 /* 44 * Macros needed to support the PCI Device ID Table ... 45 */ 46 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 47 static const struct rte_pci_id cxgb4_pci_tbl[] = { 48 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 49 50 #define PCI_VENDOR_ID_CHELSIO 0x1425 51 52 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 54 55 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 56 { .vendor_id = 0, } \ 57 } 58 59 /* 60 *... and the PCI ID Table itself ... 61 */ 62 #include "base/t4_pci_id_tbl.h" 63 64 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 65 uint16_t nb_pkts) 66 { 67 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 68 uint16_t pkts_sent, pkts_remain; 69 uint16_t total_sent = 0; 70 int ret = 0; 71 72 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 73 __func__, txq, tx_pkts, nb_pkts); 74 75 t4_os_lock(&txq->txq_lock); 76 /* free up desc from already completed tx */ 77 reclaim_completed_tx(&txq->q); 78 while (total_sent < nb_pkts) { 79 pkts_remain = nb_pkts - total_sent; 80 81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 82 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent], 83 nb_pkts); 84 if (ret < 0) 85 break; 86 } 87 if (!pkts_sent) 88 break; 89 total_sent += pkts_sent; 90 /* reclaim as much as possible */ 91 reclaim_completed_tx(&txq->q); 92 } 93 94 t4_os_unlock(&txq->txq_lock); 95 return total_sent; 96 } 97 98 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 99 uint16_t nb_pkts) 100 { 101 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 102 unsigned int work_done; 103 104 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 105 __func__, rxq->rspq.cntxt_id, nb_pkts); 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 111 return work_done; 112 } 113 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 115 struct rte_eth_dev_info *device_info) 116 { 117 struct port_info *pi = eth_dev->data->dev_private; 118 struct adapter *adapter = pi->adapter; 119 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 120 121 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 122 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 123 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 124 .nb_align = 1, 125 }; 126 127 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 128 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 129 device_info->max_rx_queues = max_queues; 130 device_info->max_tx_queues = max_queues; 131 device_info->max_mac_addrs = 1; 132 /* XXX: For now we support one MAC/port */ 133 device_info->max_vfs = adapter->params.arch.vfcount; 134 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 135 136 device_info->rx_queue_offload_capa = 0UL; 137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 138 139 device_info->tx_queue_offload_capa = 0UL; 140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 141 142 device_info->reta_size = pi->rss_size; 143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 145 146 device_info->rx_desc_lim = cxgbe_desc_lim; 147 device_info->tx_desc_lim = cxgbe_desc_lim; 148 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 149 150 return 0; 151 } 152 153 void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 154 { 155 struct port_info *pi = eth_dev->data->dev_private; 156 struct adapter *adapter = pi->adapter; 157 158 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 159 1, -1, 1, -1, false); 160 } 161 162 void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 163 { 164 struct port_info *pi = eth_dev->data->dev_private; 165 struct adapter *adapter = pi->adapter; 166 167 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 168 0, -1, 1, -1, false); 169 } 170 171 void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 172 { 173 struct port_info *pi = eth_dev->data->dev_private; 174 struct adapter *adapter = pi->adapter; 175 176 /* TODO: address filters ?? */ 177 178 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 179 -1, 1, 1, -1, false); 180 } 181 182 void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 183 { 184 struct port_info *pi = eth_dev->data->dev_private; 185 struct adapter *adapter = pi->adapter; 186 187 /* TODO: address filters ?? */ 188 189 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 190 -1, 0, 1, -1, false); 191 } 192 193 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 194 int wait_to_complete) 195 { 196 struct port_info *pi = eth_dev->data->dev_private; 197 struct adapter *adapter = pi->adapter; 198 struct sge *s = &adapter->sge; 199 struct rte_eth_link new_link = { 0 }; 200 unsigned int i, work_done, budget = 32; 201 u8 old_link = pi->link_cfg.link_ok; 202 203 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 204 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 205 206 /* Exit if link status changed or always forced up */ 207 if (pi->link_cfg.link_ok != old_link || 208 cxgbe_force_linkup(adapter)) 209 break; 210 211 if (!wait_to_complete) 212 break; 213 214 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 215 } 216 217 new_link.link_status = cxgbe_force_linkup(adapter) ? 218 ETH_LINK_UP : pi->link_cfg.link_ok; 219 new_link.link_autoneg = pi->link_cfg.autoneg; 220 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 221 new_link.link_speed = pi->link_cfg.speed; 222 223 return rte_eth_linkstatus_set(eth_dev, &new_link); 224 } 225 226 /** 227 * Set device link up. 228 */ 229 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 230 { 231 struct port_info *pi = dev->data->dev_private; 232 struct adapter *adapter = pi->adapter; 233 unsigned int work_done, budget = 32; 234 struct sge *s = &adapter->sge; 235 int ret; 236 237 /* Flush all link events */ 238 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 239 240 /* If link already up, nothing to do */ 241 if (pi->link_cfg.link_ok) 242 return 0; 243 244 ret = cxgbe_set_link_status(pi, true); 245 if (ret) 246 return ret; 247 248 cxgbe_dev_link_update(dev, 1); 249 return 0; 250 } 251 252 /** 253 * Set device link down. 254 */ 255 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 256 { 257 struct port_info *pi = dev->data->dev_private; 258 struct adapter *adapter = pi->adapter; 259 unsigned int work_done, budget = 32; 260 struct sge *s = &adapter->sge; 261 int ret; 262 263 /* Flush all link events */ 264 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 265 266 /* If link already down, nothing to do */ 267 if (!pi->link_cfg.link_ok) 268 return 0; 269 270 ret = cxgbe_set_link_status(pi, false); 271 if (ret) 272 return ret; 273 274 cxgbe_dev_link_update(dev, 0); 275 return 0; 276 } 277 278 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 279 { 280 struct port_info *pi = eth_dev->data->dev_private; 281 struct adapter *adapter = pi->adapter; 282 struct rte_eth_dev_info dev_info; 283 int err; 284 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 285 286 err = cxgbe_dev_info_get(eth_dev, &dev_info); 287 if (err != 0) 288 return err; 289 290 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 291 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 292 return -EINVAL; 293 294 /* set to jumbo mode if needed */ 295 if (new_mtu > RTE_ETHER_MAX_LEN) 296 eth_dev->data->dev_conf.rxmode.offloads |= 297 DEV_RX_OFFLOAD_JUMBO_FRAME; 298 else 299 eth_dev->data->dev_conf.rxmode.offloads &= 300 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 301 302 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 303 -1, -1, true); 304 if (!err) 305 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 306 307 return err; 308 } 309 310 /* 311 * Stop device. 312 */ 313 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 314 { 315 struct port_info *pi = eth_dev->data->dev_private; 316 struct adapter *adapter = pi->adapter; 317 318 CXGBE_FUNC_TRACE(); 319 320 if (!(adapter->flags & FULL_INIT_DONE)) 321 return; 322 323 cxgbe_down(pi); 324 325 /* 326 * We clear queues only if both tx and rx path of the port 327 * have been disabled 328 */ 329 t4_sge_eth_clear_queues(pi); 330 } 331 332 /* Start the device. 333 * It returns 0 on success. 334 */ 335 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 336 { 337 struct port_info *pi = eth_dev->data->dev_private; 338 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 339 struct adapter *adapter = pi->adapter; 340 int err = 0, i; 341 342 CXGBE_FUNC_TRACE(); 343 344 /* 345 * If we don't have a connection to the firmware there's nothing we 346 * can do. 347 */ 348 if (!(adapter->flags & FW_OK)) { 349 err = -ENXIO; 350 goto out; 351 } 352 353 if (!(adapter->flags & FULL_INIT_DONE)) { 354 err = cxgbe_up(adapter); 355 if (err < 0) 356 goto out; 357 } 358 359 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 360 eth_dev->data->scattered_rx = 1; 361 else 362 eth_dev->data->scattered_rx = 0; 363 364 cxgbe_enable_rx_queues(pi); 365 366 err = cxgbe_setup_rss(pi); 367 if (err) 368 goto out; 369 370 for (i = 0; i < pi->n_tx_qsets; i++) { 371 err = cxgbe_dev_tx_queue_start(eth_dev, i); 372 if (err) 373 goto out; 374 } 375 376 for (i = 0; i < pi->n_rx_qsets; i++) { 377 err = cxgbe_dev_rx_queue_start(eth_dev, i); 378 if (err) 379 goto out; 380 } 381 382 err = cxgbe_link_start(pi); 383 if (err) 384 goto out; 385 386 out: 387 return err; 388 } 389 390 /* 391 * Stop device: disable rx and tx functions to allow for reconfiguring. 392 */ 393 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 394 { 395 struct port_info *pi = eth_dev->data->dev_private; 396 struct adapter *adapter = pi->adapter; 397 398 CXGBE_FUNC_TRACE(); 399 400 if (!(adapter->flags & FULL_INIT_DONE)) 401 return; 402 403 cxgbe_down(pi); 404 405 /* 406 * We clear queues only if both tx and rx path of the port 407 * have been disabled 408 */ 409 t4_sge_eth_clear_queues(pi); 410 eth_dev->data->scattered_rx = 0; 411 } 412 413 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 414 { 415 struct port_info *pi = eth_dev->data->dev_private; 416 struct adapter *adapter = pi->adapter; 417 int err; 418 419 CXGBE_FUNC_TRACE(); 420 421 if (!(adapter->flags & FW_QUEUE_BOUND)) { 422 err = cxgbe_setup_sge_fwevtq(adapter); 423 if (err) 424 return err; 425 adapter->flags |= FW_QUEUE_BOUND; 426 if (is_pf4(adapter)) { 427 err = cxgbe_setup_sge_ctrl_txq(adapter); 428 if (err) 429 return err; 430 } 431 } 432 433 err = cxgbe_cfg_queue_count(eth_dev); 434 if (err) 435 return err; 436 437 return 0; 438 } 439 440 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 441 { 442 int ret; 443 struct sge_eth_txq *txq = (struct sge_eth_txq *) 444 (eth_dev->data->tx_queues[tx_queue_id]); 445 446 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 447 448 ret = t4_sge_eth_txq_start(txq); 449 if (ret == 0) 450 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 451 452 return ret; 453 } 454 455 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 456 { 457 int ret; 458 struct sge_eth_txq *txq = (struct sge_eth_txq *) 459 (eth_dev->data->tx_queues[tx_queue_id]); 460 461 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 462 463 ret = t4_sge_eth_txq_stop(txq); 464 if (ret == 0) 465 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 466 467 return ret; 468 } 469 470 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 471 uint16_t queue_idx, uint16_t nb_desc, 472 unsigned int socket_id, 473 const struct rte_eth_txconf *tx_conf __rte_unused) 474 { 475 struct port_info *pi = eth_dev->data->dev_private; 476 struct adapter *adapter = pi->adapter; 477 struct sge *s = &adapter->sge; 478 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 479 int err = 0; 480 unsigned int temp_nb_desc; 481 482 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 483 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 484 socket_id, pi->first_qset); 485 486 /* Free up the existing queue */ 487 if (eth_dev->data->tx_queues[queue_idx]) { 488 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 489 eth_dev->data->tx_queues[queue_idx] = NULL; 490 } 491 492 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 493 494 /* Sanity Checking 495 * 496 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 497 */ 498 temp_nb_desc = nb_desc; 499 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 500 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 501 __func__, CXGBE_MIN_RING_DESC_SIZE, 502 CXGBE_DEFAULT_TX_DESC_SIZE); 503 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 504 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 505 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 506 __func__, CXGBE_MIN_RING_DESC_SIZE, 507 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 508 return -(EINVAL); 509 } 510 511 txq->q.size = temp_nb_desc; 512 513 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 514 s->fw_evtq.cntxt_id, socket_id); 515 516 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 517 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 518 return err; 519 } 520 521 void cxgbe_dev_tx_queue_release(void *q) 522 { 523 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 524 525 if (txq) { 526 struct port_info *pi = (struct port_info *) 527 (txq->eth_dev->data->dev_private); 528 struct adapter *adap = pi->adapter; 529 530 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 531 __func__, pi->port_id, txq->q.cntxt_id); 532 533 t4_sge_eth_txq_release(adap, txq); 534 } 535 } 536 537 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 538 { 539 int ret; 540 struct port_info *pi = eth_dev->data->dev_private; 541 struct adapter *adap = pi->adapter; 542 struct sge_rspq *q; 543 544 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 545 __func__, pi->port_id, rx_queue_id); 546 547 q = eth_dev->data->rx_queues[rx_queue_id]; 548 549 ret = t4_sge_eth_rxq_start(adap, q); 550 if (ret == 0) 551 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 552 553 return ret; 554 } 555 556 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 557 { 558 int ret; 559 struct port_info *pi = eth_dev->data->dev_private; 560 struct adapter *adap = pi->adapter; 561 struct sge_rspq *q; 562 563 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 564 __func__, pi->port_id, rx_queue_id); 565 566 q = eth_dev->data->rx_queues[rx_queue_id]; 567 ret = t4_sge_eth_rxq_stop(adap, q); 568 if (ret == 0) 569 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 570 571 return ret; 572 } 573 574 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 575 uint16_t queue_idx, uint16_t nb_desc, 576 unsigned int socket_id, 577 const struct rte_eth_rxconf *rx_conf __rte_unused, 578 struct rte_mempool *mp) 579 { 580 struct port_info *pi = eth_dev->data->dev_private; 581 struct adapter *adapter = pi->adapter; 582 struct sge *s = &adapter->sge; 583 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 584 int err = 0; 585 int msi_idx = 0; 586 unsigned int temp_nb_desc; 587 struct rte_eth_dev_info dev_info; 588 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 589 590 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 591 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 592 socket_id, mp); 593 594 err = cxgbe_dev_info_get(eth_dev, &dev_info); 595 if (err != 0) { 596 dev_err(adap, "%s: error during getting ethernet device info", 597 __func__); 598 return err; 599 } 600 601 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 602 if ((pkt_len < dev_info.min_rx_bufsize) || 603 (pkt_len > dev_info.max_rx_pktlen)) { 604 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 605 __func__, dev_info.min_rx_bufsize, 606 dev_info.max_rx_pktlen); 607 return -EINVAL; 608 } 609 610 /* Free up the existing queue */ 611 if (eth_dev->data->rx_queues[queue_idx]) { 612 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 613 eth_dev->data->rx_queues[queue_idx] = NULL; 614 } 615 616 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 617 618 /* Sanity Checking 619 * 620 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 621 */ 622 temp_nb_desc = nb_desc; 623 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 624 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 625 __func__, CXGBE_MIN_RING_DESC_SIZE, 626 CXGBE_DEFAULT_RX_DESC_SIZE); 627 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 628 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 629 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 630 __func__, CXGBE_MIN_RING_DESC_SIZE, 631 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 632 return -(EINVAL); 633 } 634 635 rxq->rspq.size = temp_nb_desc; 636 if ((&rxq->fl) != NULL) 637 rxq->fl.size = temp_nb_desc; 638 639 /* Set to jumbo mode if necessary */ 640 if (pkt_len > RTE_ETHER_MAX_LEN) 641 eth_dev->data->dev_conf.rxmode.offloads |= 642 DEV_RX_OFFLOAD_JUMBO_FRAME; 643 else 644 eth_dev->data->dev_conf.rxmode.offloads &= 645 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 646 647 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 648 &rxq->fl, NULL, 649 is_pf4(adapter) ? 650 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 651 queue_idx, socket_id); 652 653 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 654 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 655 rxq->rspq.abs_id); 656 return err; 657 } 658 659 void cxgbe_dev_rx_queue_release(void *q) 660 { 661 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 662 struct sge_rspq *rq = &rxq->rspq; 663 664 if (rq) { 665 struct port_info *pi = (struct port_info *) 666 (rq->eth_dev->data->dev_private); 667 struct adapter *adap = pi->adapter; 668 669 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 670 __func__, pi->port_id, rxq->rspq.cntxt_id); 671 672 t4_sge_eth_rxq_release(adap, rxq); 673 } 674 } 675 676 /* 677 * Get port statistics. 678 */ 679 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 680 struct rte_eth_stats *eth_stats) 681 { 682 struct port_info *pi = eth_dev->data->dev_private; 683 struct adapter *adapter = pi->adapter; 684 struct sge *s = &adapter->sge; 685 struct port_stats ps; 686 unsigned int i; 687 688 cxgbe_stats_get(pi, &ps); 689 690 /* RX Stats */ 691 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 692 ps.rx_ovflow2 + ps.rx_ovflow3 + 693 ps.rx_trunc0 + ps.rx_trunc1 + 694 ps.rx_trunc2 + ps.rx_trunc3; 695 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 696 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 697 ps.rx_len_err; 698 699 /* TX Stats */ 700 eth_stats->opackets = ps.tx_frames; 701 eth_stats->obytes = ps.tx_octets; 702 eth_stats->oerrors = ps.tx_error_frames; 703 704 for (i = 0; i < pi->n_rx_qsets; i++) { 705 struct sge_eth_rxq *rxq = 706 &s->ethrxq[pi->first_qset + i]; 707 708 eth_stats->q_ipackets[i] = rxq->stats.pkts; 709 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 710 eth_stats->ipackets += eth_stats->q_ipackets[i]; 711 eth_stats->ibytes += eth_stats->q_ibytes[i]; 712 } 713 714 for (i = 0; i < pi->n_tx_qsets; i++) { 715 struct sge_eth_txq *txq = 716 &s->ethtxq[pi->first_qset + i]; 717 718 eth_stats->q_opackets[i] = txq->stats.pkts; 719 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 720 } 721 return 0; 722 } 723 724 /* 725 * Reset port statistics. 726 */ 727 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 728 { 729 struct port_info *pi = eth_dev->data->dev_private; 730 struct adapter *adapter = pi->adapter; 731 struct sge *s = &adapter->sge; 732 unsigned int i; 733 734 cxgbe_stats_reset(pi); 735 for (i = 0; i < pi->n_rx_qsets; i++) { 736 struct sge_eth_rxq *rxq = 737 &s->ethrxq[pi->first_qset + i]; 738 739 rxq->stats.pkts = 0; 740 rxq->stats.rx_bytes = 0; 741 } 742 for (i = 0; i < pi->n_tx_qsets; i++) { 743 struct sge_eth_txq *txq = 744 &s->ethtxq[pi->first_qset + i]; 745 746 txq->stats.pkts = 0; 747 txq->stats.tx_bytes = 0; 748 txq->stats.mapping_err = 0; 749 } 750 } 751 752 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 753 struct rte_eth_fc_conf *fc_conf) 754 { 755 struct port_info *pi = eth_dev->data->dev_private; 756 struct link_config *lc = &pi->link_cfg; 757 int rx_pause, tx_pause; 758 759 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 760 rx_pause = lc->fc & PAUSE_RX; 761 tx_pause = lc->fc & PAUSE_TX; 762 763 if (rx_pause && tx_pause) 764 fc_conf->mode = RTE_FC_FULL; 765 else if (rx_pause) 766 fc_conf->mode = RTE_FC_RX_PAUSE; 767 else if (tx_pause) 768 fc_conf->mode = RTE_FC_TX_PAUSE; 769 else 770 fc_conf->mode = RTE_FC_NONE; 771 return 0; 772 } 773 774 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 775 struct rte_eth_fc_conf *fc_conf) 776 { 777 struct port_info *pi = eth_dev->data->dev_private; 778 struct adapter *adapter = pi->adapter; 779 struct link_config *lc = &pi->link_cfg; 780 781 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 782 if (fc_conf->autoneg) 783 lc->requested_fc |= PAUSE_AUTONEG; 784 else 785 lc->requested_fc &= ~PAUSE_AUTONEG; 786 } 787 788 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 789 (fc_conf->mode & RTE_FC_RX_PAUSE)) 790 lc->requested_fc |= PAUSE_RX; 791 else 792 lc->requested_fc &= ~PAUSE_RX; 793 794 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 795 (fc_conf->mode & RTE_FC_TX_PAUSE)) 796 lc->requested_fc |= PAUSE_TX; 797 else 798 lc->requested_fc &= ~PAUSE_TX; 799 800 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 801 &pi->link_cfg); 802 } 803 804 const uint32_t * 805 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 806 { 807 static const uint32_t ptypes[] = { 808 RTE_PTYPE_L3_IPV4, 809 RTE_PTYPE_L3_IPV6, 810 RTE_PTYPE_UNKNOWN 811 }; 812 813 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 814 return ptypes; 815 return NULL; 816 } 817 818 /* Update RSS hash configuration 819 */ 820 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 821 struct rte_eth_rss_conf *rss_conf) 822 { 823 struct port_info *pi = dev->data->dev_private; 824 struct adapter *adapter = pi->adapter; 825 int err; 826 827 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 828 if (err) 829 return err; 830 831 pi->rss_hf = rss_conf->rss_hf; 832 833 if (rss_conf->rss_key) { 834 u32 key[10], mod_key[10]; 835 int i, j; 836 837 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 838 839 for (i = 9, j = 0; i >= 0; i--, j++) 840 mod_key[j] = cpu_to_be32(key[i]); 841 842 t4_write_rss_key(adapter, mod_key, -1); 843 } 844 845 return 0; 846 } 847 848 /* Get RSS hash configuration 849 */ 850 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 851 struct rte_eth_rss_conf *rss_conf) 852 { 853 struct port_info *pi = dev->data->dev_private; 854 struct adapter *adapter = pi->adapter; 855 u64 rss_hf = 0; 856 u64 flags = 0; 857 int err; 858 859 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 860 &flags, NULL); 861 862 if (err) 863 return err; 864 865 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 866 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 867 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 868 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 869 } 870 871 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 872 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 873 874 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 875 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 876 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 877 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 878 } 879 880 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 881 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 882 883 rss_conf->rss_hf = rss_hf; 884 885 if (rss_conf->rss_key) { 886 u32 key[10], mod_key[10]; 887 int i, j; 888 889 t4_read_rss_key(adapter, key); 890 891 for (i = 9, j = 0; i >= 0; i--, j++) 892 mod_key[j] = be32_to_cpu(key[i]); 893 894 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 895 } 896 897 return 0; 898 } 899 900 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 901 { 902 RTE_SET_USED(dev); 903 return EEPROMSIZE; 904 } 905 906 /** 907 * eeprom_ptov - translate a physical EEPROM address to virtual 908 * @phys_addr: the physical EEPROM address 909 * @fn: the PCI function number 910 * @sz: size of function-specific area 911 * 912 * Translate a physical EEPROM address to virtual. The first 1K is 913 * accessed through virtual addresses starting at 31K, the rest is 914 * accessed through virtual addresses starting at 0. 915 * 916 * The mapping is as follows: 917 * [0..1K) -> [31K..32K) 918 * [1K..1K+A) -> [31K-A..31K) 919 * [1K+A..ES) -> [0..ES-A-1K) 920 * 921 * where A = @fn * @sz, and ES = EEPROM size. 922 */ 923 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 924 { 925 fn *= sz; 926 if (phys_addr < 1024) 927 return phys_addr + (31 << 10); 928 if (phys_addr < 1024 + fn) 929 return fn + phys_addr - 1024; 930 if (phys_addr < EEPROMSIZE) 931 return phys_addr - 1024 - fn; 932 if (phys_addr < EEPROMVSIZE) 933 return phys_addr - 1024; 934 return -EINVAL; 935 } 936 937 /* The next two routines implement eeprom read/write from physical addresses. 938 */ 939 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 940 { 941 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 942 943 if (vaddr >= 0) 944 vaddr = t4_seeprom_read(adap, vaddr, v); 945 return vaddr < 0 ? vaddr : 0; 946 } 947 948 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 949 { 950 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 951 952 if (vaddr >= 0) 953 vaddr = t4_seeprom_write(adap, vaddr, v); 954 return vaddr < 0 ? vaddr : 0; 955 } 956 957 #define EEPROM_MAGIC 0x38E2F10C 958 959 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 960 struct rte_dev_eeprom_info *e) 961 { 962 struct port_info *pi = dev->data->dev_private; 963 struct adapter *adapter = pi->adapter; 964 u32 i, err = 0; 965 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 966 967 if (!buf) 968 return -ENOMEM; 969 970 e->magic = EEPROM_MAGIC; 971 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 972 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 973 974 if (!err) 975 rte_memcpy(e->data, buf + e->offset, e->length); 976 rte_free(buf); 977 return err; 978 } 979 980 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 981 struct rte_dev_eeprom_info *eeprom) 982 { 983 struct port_info *pi = dev->data->dev_private; 984 struct adapter *adapter = pi->adapter; 985 u8 *buf; 986 int err = 0; 987 u32 aligned_offset, aligned_len, *p; 988 989 if (eeprom->magic != EEPROM_MAGIC) 990 return -EINVAL; 991 992 aligned_offset = eeprom->offset & ~3; 993 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 994 995 if (adapter->pf > 0) { 996 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 997 998 if (aligned_offset < start || 999 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1000 return -EPERM; 1001 } 1002 1003 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1004 /* RMW possibly needed for first or last words. 1005 */ 1006 buf = rte_zmalloc(NULL, aligned_len, 0); 1007 if (!buf) 1008 return -ENOMEM; 1009 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1010 if (!err && aligned_len > 4) 1011 err = eeprom_rd_phys(adapter, 1012 aligned_offset + aligned_len - 4, 1013 (u32 *)&buf[aligned_len - 4]); 1014 if (err) 1015 goto out; 1016 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1017 eeprom->length); 1018 } else { 1019 buf = eeprom->data; 1020 } 1021 1022 err = t4_seeprom_wp(adapter, false); 1023 if (err) 1024 goto out; 1025 1026 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1027 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1028 aligned_offset += 4; 1029 } 1030 1031 if (!err) 1032 err = t4_seeprom_wp(adapter, true); 1033 out: 1034 if (buf != eeprom->data) 1035 rte_free(buf); 1036 return err; 1037 } 1038 1039 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1040 { 1041 struct port_info *pi = eth_dev->data->dev_private; 1042 struct adapter *adapter = pi->adapter; 1043 1044 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1045 } 1046 1047 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1048 struct rte_dev_reg_info *regs) 1049 { 1050 struct port_info *pi = eth_dev->data->dev_private; 1051 struct adapter *adapter = pi->adapter; 1052 1053 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1054 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1055 (1 << 16); 1056 1057 if (regs->data == NULL) { 1058 regs->length = cxgbe_get_regs_len(eth_dev); 1059 regs->width = sizeof(uint32_t); 1060 1061 return 0; 1062 } 1063 1064 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1065 1066 return 0; 1067 } 1068 1069 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1070 { 1071 struct port_info *pi = dev->data->dev_private; 1072 int ret; 1073 1074 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1075 if (ret < 0) { 1076 dev_err(adapter, "failed to set mac addr; err = %d\n", 1077 ret); 1078 return ret; 1079 } 1080 pi->xact_addr_filt = ret; 1081 return 0; 1082 } 1083 1084 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1085 .dev_start = cxgbe_dev_start, 1086 .dev_stop = cxgbe_dev_stop, 1087 .dev_close = cxgbe_dev_close, 1088 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1089 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1090 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1091 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1092 .dev_configure = cxgbe_dev_configure, 1093 .dev_infos_get = cxgbe_dev_info_get, 1094 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1095 .link_update = cxgbe_dev_link_update, 1096 .dev_set_link_up = cxgbe_dev_set_link_up, 1097 .dev_set_link_down = cxgbe_dev_set_link_down, 1098 .mtu_set = cxgbe_dev_mtu_set, 1099 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1100 .tx_queue_start = cxgbe_dev_tx_queue_start, 1101 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1102 .tx_queue_release = cxgbe_dev_tx_queue_release, 1103 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1104 .rx_queue_start = cxgbe_dev_rx_queue_start, 1105 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1106 .rx_queue_release = cxgbe_dev_rx_queue_release, 1107 .filter_ctrl = cxgbe_dev_filter_ctrl, 1108 .stats_get = cxgbe_dev_stats_get, 1109 .stats_reset = cxgbe_dev_stats_reset, 1110 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1111 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1112 .get_eeprom_length = cxgbe_get_eeprom_length, 1113 .get_eeprom = cxgbe_get_eeprom, 1114 .set_eeprom = cxgbe_set_eeprom, 1115 .get_reg = cxgbe_get_regs, 1116 .rss_hash_update = cxgbe_dev_rss_hash_update, 1117 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1118 .mac_addr_set = cxgbe_mac_addr_set, 1119 }; 1120 1121 /* 1122 * Initialize driver 1123 * It returns 0 on success. 1124 */ 1125 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1126 { 1127 struct rte_pci_device *pci_dev; 1128 struct port_info *pi = eth_dev->data->dev_private; 1129 struct adapter *adapter = NULL; 1130 char name[RTE_ETH_NAME_MAX_LEN]; 1131 int err = 0; 1132 1133 CXGBE_FUNC_TRACE(); 1134 1135 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1136 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1137 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1138 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1139 1140 /* for secondary processes, we attach to ethdevs allocated by primary 1141 * and do minimal initialization. 1142 */ 1143 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1144 int i; 1145 1146 for (i = 1; i < MAX_NPORTS; i++) { 1147 struct rte_eth_dev *rest_eth_dev; 1148 char namei[RTE_ETH_NAME_MAX_LEN]; 1149 1150 snprintf(namei, sizeof(namei), "%s_%d", 1151 pci_dev->device.name, i); 1152 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1153 if (rest_eth_dev) { 1154 rest_eth_dev->device = &pci_dev->device; 1155 rest_eth_dev->dev_ops = 1156 eth_dev->dev_ops; 1157 rest_eth_dev->rx_pkt_burst = 1158 eth_dev->rx_pkt_burst; 1159 rest_eth_dev->tx_pkt_burst = 1160 eth_dev->tx_pkt_burst; 1161 rte_eth_dev_probing_finish(rest_eth_dev); 1162 } 1163 } 1164 return 0; 1165 } 1166 1167 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1168 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1169 if (!adapter) 1170 return -1; 1171 1172 adapter->use_unpacked_mode = 1; 1173 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1174 if (!adapter->regs) { 1175 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1176 err = -ENOMEM; 1177 goto out_free_adapter; 1178 } 1179 adapter->pdev = pci_dev; 1180 adapter->eth_dev = eth_dev; 1181 pi->adapter = adapter; 1182 1183 err = cxgbe_probe(adapter); 1184 if (err) { 1185 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1186 __func__, err); 1187 goto out_free_adapter; 1188 } 1189 1190 return 0; 1191 1192 out_free_adapter: 1193 rte_free(adapter); 1194 return err; 1195 } 1196 1197 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1198 { 1199 struct port_info *pi = eth_dev->data->dev_private; 1200 struct adapter *adap = pi->adapter; 1201 1202 /* Free up other ports and all resources */ 1203 cxgbe_close(adap); 1204 return 0; 1205 } 1206 1207 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1208 struct rte_pci_device *pci_dev) 1209 { 1210 return rte_eth_dev_pci_generic_probe(pci_dev, 1211 sizeof(struct port_info), eth_cxgbe_dev_init); 1212 } 1213 1214 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1215 { 1216 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1217 } 1218 1219 static struct rte_pci_driver rte_cxgbe_pmd = { 1220 .id_table = cxgb4_pci_tbl, 1221 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1222 .probe = eth_cxgbe_pci_probe, 1223 .remove = eth_cxgbe_pci_remove, 1224 }; 1225 1226 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1227 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1228 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1229 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1230 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> " 1231 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> "); 1232 1233 RTE_INIT(cxgbe_init_log) 1234 { 1235 cxgbe_logtype = rte_log_register("pmd.net.cxgbe"); 1236 if (cxgbe_logtype >= 0) 1237 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE); 1238 } 1239