1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <ethdev_driver.h> 32 #include <ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 /* 42 * Macros needed to support the PCI Device ID Table ... 43 */ 44 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 45 static const struct rte_pci_id cxgb4_pci_tbl[] = { 46 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 47 48 #define PCI_VENDOR_ID_CHELSIO 0x1425 49 50 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 52 53 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 54 { .vendor_id = 0, } \ 55 } 56 57 /* 58 *... and the PCI ID Table itself ... 59 */ 60 #include "base/t4_pci_id_tbl.h" 61 62 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 63 uint16_t nb_pkts) 64 { 65 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 66 uint16_t pkts_sent, pkts_remain; 67 uint16_t total_sent = 0; 68 uint16_t idx = 0; 69 int ret = 0; 70 71 t4_os_lock(&txq->txq_lock); 72 /* free up desc from already completed tx */ 73 reclaim_completed_tx(&txq->q); 74 if (unlikely(!nb_pkts)) 75 goto out_unlock; 76 77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 78 while (total_sent < nb_pkts) { 79 pkts_remain = nb_pkts - total_sent; 80 81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 82 idx = total_sent + pkts_sent; 83 if ((idx + 1) < nb_pkts) 84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 85 volatile void *)); 86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 87 if (ret < 0) 88 break; 89 } 90 if (!pkts_sent) 91 break; 92 total_sent += pkts_sent; 93 /* reclaim as much as possible */ 94 reclaim_completed_tx(&txq->q); 95 } 96 97 out_unlock: 98 t4_os_unlock(&txq->txq_lock); 99 return total_sent; 100 } 101 102 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 103 uint16_t nb_pkts) 104 { 105 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 106 unsigned int work_done; 107 108 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 109 dev_err(adapter, "error in cxgbe poll\n"); 110 111 return work_done; 112 } 113 114 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 115 struct rte_eth_dev_info *device_info) 116 { 117 struct port_info *pi = eth_dev->data->dev_private; 118 struct adapter *adapter = pi->adapter; 119 120 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 121 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 122 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 123 .nb_align = 1, 124 }; 125 126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 128 device_info->max_rx_queues = adapter->sge.max_ethqsets; 129 device_info->max_tx_queues = adapter->sge.max_ethqsets; 130 device_info->max_mac_addrs = 1; 131 /* XXX: For now we support one MAC/port */ 132 device_info->max_vfs = adapter->params.arch.vfcount; 133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 134 135 device_info->rx_queue_offload_capa = 0UL; 136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 137 138 device_info->tx_queue_offload_capa = 0UL; 139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 140 141 device_info->reta_size = pi->rss_size; 142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 144 145 device_info->rx_desc_lim = cxgbe_desc_lim; 146 device_info->tx_desc_lim = cxgbe_desc_lim; 147 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 148 149 return 0; 150 } 151 152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 153 { 154 struct port_info *pi = eth_dev->data->dev_private; 155 struct adapter *adapter = pi->adapter; 156 157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 158 1, -1, 1, -1, false); 159 } 160 161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 162 { 163 struct port_info *pi = eth_dev->data->dev_private; 164 struct adapter *adapter = pi->adapter; 165 166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 167 0, -1, 1, -1, false); 168 } 169 170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 171 { 172 struct port_info *pi = eth_dev->data->dev_private; 173 struct adapter *adapter = pi->adapter; 174 175 /* TODO: address filters ?? */ 176 177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 178 -1, 1, 1, -1, false); 179 } 180 181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 182 { 183 struct port_info *pi = eth_dev->data->dev_private; 184 struct adapter *adapter = pi->adapter; 185 186 /* TODO: address filters ?? */ 187 188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 189 -1, 0, 1, -1, false); 190 } 191 192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 193 int wait_to_complete) 194 { 195 struct port_info *pi = eth_dev->data->dev_private; 196 unsigned int i, work_done, budget = 32; 197 struct link_config *lc = &pi->link_cfg; 198 struct adapter *adapter = pi->adapter; 199 struct rte_eth_link new_link = { 0 }; 200 u8 old_link = pi->link_cfg.link_ok; 201 struct sge *s = &adapter->sge; 202 203 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 204 if (!s->fw_evtq.desc) 205 break; 206 207 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 208 209 /* Exit if link status changed or always forced up */ 210 if (pi->link_cfg.link_ok != old_link || 211 cxgbe_force_linkup(adapter)) 212 break; 213 214 if (!wait_to_complete) 215 break; 216 217 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 218 } 219 220 new_link.link_status = cxgbe_force_linkup(adapter) ? 221 ETH_LINK_UP : pi->link_cfg.link_ok; 222 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; 223 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 224 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps); 225 226 return rte_eth_linkstatus_set(eth_dev, &new_link); 227 } 228 229 /** 230 * Set device link up. 231 */ 232 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 233 { 234 struct port_info *pi = dev->data->dev_private; 235 struct adapter *adapter = pi->adapter; 236 unsigned int work_done, budget = 32; 237 struct sge *s = &adapter->sge; 238 int ret; 239 240 if (!s->fw_evtq.desc) 241 return -ENOMEM; 242 243 /* Flush all link events */ 244 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 245 246 /* If link already up, nothing to do */ 247 if (pi->link_cfg.link_ok) 248 return 0; 249 250 ret = cxgbe_set_link_status(pi, true); 251 if (ret) 252 return ret; 253 254 cxgbe_dev_link_update(dev, 1); 255 return 0; 256 } 257 258 /** 259 * Set device link down. 260 */ 261 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 262 { 263 struct port_info *pi = dev->data->dev_private; 264 struct adapter *adapter = pi->adapter; 265 unsigned int work_done, budget = 32; 266 struct sge *s = &adapter->sge; 267 int ret; 268 269 if (!s->fw_evtq.desc) 270 return -ENOMEM; 271 272 /* Flush all link events */ 273 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 274 275 /* If link already down, nothing to do */ 276 if (!pi->link_cfg.link_ok) 277 return 0; 278 279 ret = cxgbe_set_link_status(pi, false); 280 if (ret) 281 return ret; 282 283 cxgbe_dev_link_update(dev, 0); 284 return 0; 285 } 286 287 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 288 { 289 struct port_info *pi = eth_dev->data->dev_private; 290 struct adapter *adapter = pi->adapter; 291 struct rte_eth_dev_info dev_info; 292 int err; 293 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 294 295 err = cxgbe_dev_info_get(eth_dev, &dev_info); 296 if (err != 0) 297 return err; 298 299 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 300 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 301 return -EINVAL; 302 303 /* set to jumbo mode if needed */ 304 if (new_mtu > CXGBE_ETH_MAX_LEN) 305 eth_dev->data->dev_conf.rxmode.offloads |= 306 DEV_RX_OFFLOAD_JUMBO_FRAME; 307 else 308 eth_dev->data->dev_conf.rxmode.offloads &= 309 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 310 311 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 312 -1, -1, true); 313 if (!err) 314 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 315 316 return err; 317 } 318 319 /* 320 * Stop device. 321 */ 322 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 323 { 324 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 325 struct adapter *adapter = pi->adapter; 326 u8 i; 327 328 CXGBE_FUNC_TRACE(); 329 330 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 331 return 0; 332 333 if (!(adapter->flags & FULL_INIT_DONE)) 334 return 0; 335 336 if (!pi->viid) 337 return 0; 338 339 cxgbe_down(pi); 340 t4_sge_eth_release_queues(pi); 341 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 342 pi->viid = 0; 343 344 /* Free up the adapter-wide resources only after all the ports 345 * under this PF have been closed. 346 */ 347 for_each_port(adapter, i) { 348 temp_pi = adap2pinfo(adapter, i); 349 if (temp_pi->viid) 350 return 0; 351 } 352 353 cxgbe_close(adapter); 354 rte_free(adapter); 355 356 return 0; 357 } 358 359 /* Start the device. 360 * It returns 0 on success. 361 */ 362 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 363 { 364 struct port_info *pi = eth_dev->data->dev_private; 365 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 366 struct adapter *adapter = pi->adapter; 367 int err = 0, i; 368 369 CXGBE_FUNC_TRACE(); 370 371 /* 372 * If we don't have a connection to the firmware there's nothing we 373 * can do. 374 */ 375 if (!(adapter->flags & FW_OK)) { 376 err = -ENXIO; 377 goto out; 378 } 379 380 if (!(adapter->flags & FULL_INIT_DONE)) { 381 err = cxgbe_up(adapter); 382 if (err < 0) 383 goto out; 384 } 385 386 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 387 eth_dev->data->scattered_rx = 1; 388 else 389 eth_dev->data->scattered_rx = 0; 390 391 cxgbe_enable_rx_queues(pi); 392 393 err = cxgbe_setup_rss(pi); 394 if (err) 395 goto out; 396 397 for (i = 0; i < pi->n_tx_qsets; i++) { 398 err = cxgbe_dev_tx_queue_start(eth_dev, i); 399 if (err) 400 goto out; 401 } 402 403 for (i = 0; i < pi->n_rx_qsets; i++) { 404 err = cxgbe_dev_rx_queue_start(eth_dev, i); 405 if (err) 406 goto out; 407 } 408 409 err = cxgbe_link_start(pi); 410 if (err) 411 goto out; 412 413 out: 414 return err; 415 } 416 417 /* 418 * Stop device: disable rx and tx functions to allow for reconfiguring. 419 */ 420 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 421 { 422 struct port_info *pi = eth_dev->data->dev_private; 423 struct adapter *adapter = pi->adapter; 424 425 CXGBE_FUNC_TRACE(); 426 427 if (!(adapter->flags & FULL_INIT_DONE)) 428 return 0; 429 430 cxgbe_down(pi); 431 432 /* 433 * We clear queues only if both tx and rx path of the port 434 * have been disabled 435 */ 436 t4_sge_eth_clear_queues(pi); 437 eth_dev->data->scattered_rx = 0; 438 439 return 0; 440 } 441 442 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 443 { 444 struct port_info *pi = eth_dev->data->dev_private; 445 struct adapter *adapter = pi->adapter; 446 int err; 447 448 CXGBE_FUNC_TRACE(); 449 450 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 451 eth_dev->data->dev_conf.rxmode.offloads |= 452 DEV_RX_OFFLOAD_RSS_HASH; 453 454 if (!(adapter->flags & FW_QUEUE_BOUND)) { 455 err = cxgbe_setup_sge_fwevtq(adapter); 456 if (err) 457 return err; 458 adapter->flags |= FW_QUEUE_BOUND; 459 if (is_pf4(adapter)) { 460 err = cxgbe_setup_sge_ctrl_txq(adapter); 461 if (err) 462 return err; 463 } 464 } 465 466 err = cxgbe_cfg_queue_count(eth_dev); 467 if (err) 468 return err; 469 470 return 0; 471 } 472 473 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 474 { 475 int ret; 476 struct sge_eth_txq *txq = (struct sge_eth_txq *) 477 (eth_dev->data->tx_queues[tx_queue_id]); 478 479 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 480 481 ret = t4_sge_eth_txq_start(txq); 482 if (ret == 0) 483 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 484 485 return ret; 486 } 487 488 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 489 { 490 int ret; 491 struct sge_eth_txq *txq = (struct sge_eth_txq *) 492 (eth_dev->data->tx_queues[tx_queue_id]); 493 494 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 495 496 ret = t4_sge_eth_txq_stop(txq); 497 if (ret == 0) 498 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 499 500 return ret; 501 } 502 503 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 504 uint16_t queue_idx, uint16_t nb_desc, 505 unsigned int socket_id, 506 const struct rte_eth_txconf *tx_conf __rte_unused) 507 { 508 struct port_info *pi = eth_dev->data->dev_private; 509 struct adapter *adapter = pi->adapter; 510 struct sge *s = &adapter->sge; 511 unsigned int temp_nb_desc; 512 struct sge_eth_txq *txq; 513 int err = 0; 514 515 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 516 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 517 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 518 socket_id, pi->first_txqset); 519 520 /* Free up the existing queue */ 521 if (eth_dev->data->tx_queues[queue_idx]) { 522 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 523 eth_dev->data->tx_queues[queue_idx] = NULL; 524 } 525 526 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 527 528 /* Sanity Checking 529 * 530 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 531 */ 532 temp_nb_desc = nb_desc; 533 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 534 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 535 __func__, CXGBE_MIN_RING_DESC_SIZE, 536 CXGBE_DEFAULT_TX_DESC_SIZE); 537 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 538 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 539 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 540 __func__, CXGBE_MIN_RING_DESC_SIZE, 541 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 542 return -(EINVAL); 543 } 544 545 txq->q.size = temp_nb_desc; 546 547 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 548 s->fw_evtq.cntxt_id, socket_id); 549 550 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 551 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 552 return err; 553 } 554 555 void cxgbe_dev_tx_queue_release(void *q) 556 { 557 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 558 559 if (txq) { 560 struct port_info *pi = (struct port_info *) 561 (txq->eth_dev->data->dev_private); 562 struct adapter *adap = pi->adapter; 563 564 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 565 __func__, pi->port_id, txq->q.cntxt_id); 566 567 t4_sge_eth_txq_release(adap, txq); 568 } 569 } 570 571 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 572 { 573 struct port_info *pi = eth_dev->data->dev_private; 574 struct adapter *adap = pi->adapter; 575 struct sge_eth_rxq *rxq; 576 int ret; 577 578 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 579 __func__, pi->port_id, rx_queue_id); 580 581 rxq = eth_dev->data->rx_queues[rx_queue_id]; 582 ret = t4_sge_eth_rxq_start(adap, rxq); 583 if (ret == 0) 584 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 585 586 return ret; 587 } 588 589 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 590 { 591 struct port_info *pi = eth_dev->data->dev_private; 592 struct adapter *adap = pi->adapter; 593 struct sge_eth_rxq *rxq; 594 int ret; 595 596 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 597 __func__, pi->port_id, rx_queue_id); 598 599 rxq = eth_dev->data->rx_queues[rx_queue_id]; 600 ret = t4_sge_eth_rxq_stop(adap, rxq); 601 if (ret == 0) 602 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 603 604 return ret; 605 } 606 607 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 608 uint16_t queue_idx, uint16_t nb_desc, 609 unsigned int socket_id, 610 const struct rte_eth_rxconf *rx_conf __rte_unused, 611 struct rte_mempool *mp) 612 { 613 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 614 struct port_info *pi = eth_dev->data->dev_private; 615 struct adapter *adapter = pi->adapter; 616 struct rte_eth_dev_info dev_info; 617 struct sge *s = &adapter->sge; 618 unsigned int temp_nb_desc; 619 int err = 0, msi_idx = 0; 620 struct sge_eth_rxq *rxq; 621 622 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 623 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 624 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 625 socket_id, mp); 626 627 err = cxgbe_dev_info_get(eth_dev, &dev_info); 628 if (err != 0) { 629 dev_err(adap, "%s: error during getting ethernet device info", 630 __func__); 631 return err; 632 } 633 634 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 635 if ((pkt_len < dev_info.min_rx_bufsize) || 636 (pkt_len > dev_info.max_rx_pktlen)) { 637 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 638 __func__, dev_info.min_rx_bufsize, 639 dev_info.max_rx_pktlen); 640 return -EINVAL; 641 } 642 643 /* Free up the existing queue */ 644 if (eth_dev->data->rx_queues[queue_idx]) { 645 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 646 eth_dev->data->rx_queues[queue_idx] = NULL; 647 } 648 649 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 650 651 /* Sanity Checking 652 * 653 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 654 */ 655 temp_nb_desc = nb_desc; 656 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 657 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 658 __func__, CXGBE_MIN_RING_DESC_SIZE, 659 CXGBE_DEFAULT_RX_DESC_SIZE); 660 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 661 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 662 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 663 __func__, CXGBE_MIN_RING_DESC_SIZE, 664 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 665 return -(EINVAL); 666 } 667 668 rxq->rspq.size = temp_nb_desc; 669 if ((&rxq->fl) != NULL) 670 rxq->fl.size = temp_nb_desc; 671 672 /* Set to jumbo mode if necessary */ 673 if (pkt_len > CXGBE_ETH_MAX_LEN) 674 eth_dev->data->dev_conf.rxmode.offloads |= 675 DEV_RX_OFFLOAD_JUMBO_FRAME; 676 else 677 eth_dev->data->dev_conf.rxmode.offloads &= 678 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 679 680 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 681 &rxq->fl, NULL, 682 is_pf4(adapter) ? 683 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 684 queue_idx, socket_id); 685 686 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 687 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 688 rxq->rspq.abs_id); 689 return err; 690 } 691 692 void cxgbe_dev_rx_queue_release(void *q) 693 { 694 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 695 696 if (rxq) { 697 struct port_info *pi = (struct port_info *) 698 (rxq->rspq.eth_dev->data->dev_private); 699 struct adapter *adap = pi->adapter; 700 701 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 702 __func__, pi->port_id, rxq->rspq.cntxt_id); 703 704 t4_sge_eth_rxq_release(adap, rxq); 705 } 706 } 707 708 /* 709 * Get port statistics. 710 */ 711 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 712 struct rte_eth_stats *eth_stats) 713 { 714 struct port_info *pi = eth_dev->data->dev_private; 715 struct adapter *adapter = pi->adapter; 716 struct sge *s = &adapter->sge; 717 struct port_stats ps; 718 unsigned int i; 719 720 cxgbe_stats_get(pi, &ps); 721 722 /* RX Stats */ 723 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 724 ps.rx_ovflow2 + ps.rx_ovflow3 + 725 ps.rx_trunc0 + ps.rx_trunc1 + 726 ps.rx_trunc2 + ps.rx_trunc3; 727 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 728 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 729 ps.rx_len_err; 730 731 /* TX Stats */ 732 eth_stats->opackets = ps.tx_frames; 733 eth_stats->obytes = ps.tx_octets; 734 eth_stats->oerrors = ps.tx_error_frames; 735 736 for (i = 0; i < pi->n_rx_qsets; i++) { 737 struct sge_eth_rxq *rxq = 738 &s->ethrxq[pi->first_rxqset + i]; 739 740 eth_stats->q_ipackets[i] = rxq->stats.pkts; 741 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 742 eth_stats->ipackets += eth_stats->q_ipackets[i]; 743 eth_stats->ibytes += eth_stats->q_ibytes[i]; 744 } 745 746 for (i = 0; i < pi->n_tx_qsets; i++) { 747 struct sge_eth_txq *txq = 748 &s->ethtxq[pi->first_txqset + i]; 749 750 eth_stats->q_opackets[i] = txq->stats.pkts; 751 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 752 } 753 return 0; 754 } 755 756 /* 757 * Reset port statistics. 758 */ 759 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 760 { 761 struct port_info *pi = eth_dev->data->dev_private; 762 struct adapter *adapter = pi->adapter; 763 struct sge *s = &adapter->sge; 764 unsigned int i; 765 766 cxgbe_stats_reset(pi); 767 for (i = 0; i < pi->n_rx_qsets; i++) { 768 struct sge_eth_rxq *rxq = 769 &s->ethrxq[pi->first_rxqset + i]; 770 771 rxq->stats.pkts = 0; 772 rxq->stats.rx_bytes = 0; 773 } 774 for (i = 0; i < pi->n_tx_qsets; i++) { 775 struct sge_eth_txq *txq = 776 &s->ethtxq[pi->first_txqset + i]; 777 778 txq->stats.pkts = 0; 779 txq->stats.tx_bytes = 0; 780 txq->stats.mapping_err = 0; 781 } 782 783 return 0; 784 } 785 786 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 787 struct rte_eth_fc_conf *fc_conf) 788 { 789 struct port_info *pi = eth_dev->data->dev_private; 790 struct link_config *lc = &pi->link_cfg; 791 u8 rx_pause = 0, tx_pause = 0; 792 u32 caps = lc->link_caps; 793 794 if (caps & FW_PORT_CAP32_ANEG) 795 fc_conf->autoneg = 1; 796 797 if (caps & FW_PORT_CAP32_FC_TX) 798 tx_pause = 1; 799 800 if (caps & FW_PORT_CAP32_FC_RX) 801 rx_pause = 1; 802 803 if (rx_pause && tx_pause) 804 fc_conf->mode = RTE_FC_FULL; 805 else if (rx_pause) 806 fc_conf->mode = RTE_FC_RX_PAUSE; 807 else if (tx_pause) 808 fc_conf->mode = RTE_FC_TX_PAUSE; 809 else 810 fc_conf->mode = RTE_FC_NONE; 811 return 0; 812 } 813 814 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 815 struct rte_eth_fc_conf *fc_conf) 816 { 817 struct port_info *pi = eth_dev->data->dev_private; 818 struct link_config *lc = &pi->link_cfg; 819 u32 new_caps = lc->admin_caps; 820 u8 tx_pause = 0, rx_pause = 0; 821 int ret; 822 823 if (fc_conf->mode == RTE_FC_FULL) { 824 tx_pause = 1; 825 rx_pause = 1; 826 } else if (fc_conf->mode == RTE_FC_TX_PAUSE) { 827 tx_pause = 1; 828 } else if (fc_conf->mode == RTE_FC_RX_PAUSE) { 829 rx_pause = 1; 830 } 831 832 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause, 833 rx_pause, &new_caps); 834 if (ret != 0) 835 return ret; 836 837 if (!fc_conf->autoneg) { 838 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE) 839 new_caps |= FW_PORT_CAP32_FORCE_PAUSE; 840 } else { 841 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE; 842 } 843 844 if (new_caps != lc->admin_caps) { 845 ret = t4_link_l1cfg(pi, new_caps); 846 if (ret == 0) 847 lc->admin_caps = new_caps; 848 } 849 850 return ret; 851 } 852 853 const uint32_t * 854 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 855 { 856 static const uint32_t ptypes[] = { 857 RTE_PTYPE_L3_IPV4, 858 RTE_PTYPE_L3_IPV6, 859 RTE_PTYPE_UNKNOWN 860 }; 861 862 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 863 return ptypes; 864 return NULL; 865 } 866 867 /* Update RSS hash configuration 868 */ 869 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 870 struct rte_eth_rss_conf *rss_conf) 871 { 872 struct port_info *pi = dev->data->dev_private; 873 struct adapter *adapter = pi->adapter; 874 int err; 875 876 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 877 if (err) 878 return err; 879 880 pi->rss_hf = rss_conf->rss_hf; 881 882 if (rss_conf->rss_key) { 883 u32 key[10], mod_key[10]; 884 int i, j; 885 886 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 887 888 for (i = 9, j = 0; i >= 0; i--, j++) 889 mod_key[j] = cpu_to_be32(key[i]); 890 891 t4_write_rss_key(adapter, mod_key, -1); 892 } 893 894 return 0; 895 } 896 897 /* Get RSS hash configuration 898 */ 899 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 900 struct rte_eth_rss_conf *rss_conf) 901 { 902 struct port_info *pi = dev->data->dev_private; 903 struct adapter *adapter = pi->adapter; 904 u64 rss_hf = 0; 905 u64 flags = 0; 906 int err; 907 908 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 909 &flags, NULL); 910 911 if (err) 912 return err; 913 914 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 915 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 916 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 917 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 918 } 919 920 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 921 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 922 923 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 924 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 925 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 926 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 927 } 928 929 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 930 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 931 932 rss_conf->rss_hf = rss_hf; 933 934 if (rss_conf->rss_key) { 935 u32 key[10], mod_key[10]; 936 int i, j; 937 938 t4_read_rss_key(adapter, key); 939 940 for (i = 9, j = 0; i >= 0; i--, j++) 941 mod_key[j] = be32_to_cpu(key[i]); 942 943 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 944 } 945 946 return 0; 947 } 948 949 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 950 struct rte_eth_rss_reta_entry64 *reta_conf, 951 uint16_t reta_size) 952 { 953 struct port_info *pi = dev->data->dev_private; 954 struct adapter *adapter = pi->adapter; 955 u16 i, idx, shift, *rss; 956 int ret; 957 958 if (!(adapter->flags & FULL_INIT_DONE)) 959 return -ENOMEM; 960 961 if (!reta_size || reta_size > pi->rss_size) 962 return -EINVAL; 963 964 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 965 if (!rss) 966 return -ENOMEM; 967 968 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 969 for (i = 0; i < reta_size; i++) { 970 idx = i / RTE_RETA_GROUP_SIZE; 971 shift = i % RTE_RETA_GROUP_SIZE; 972 if (!(reta_conf[idx].mask & (1ULL << shift))) 973 continue; 974 975 rss[i] = reta_conf[idx].reta[shift]; 976 } 977 978 ret = cxgbe_write_rss(pi, rss); 979 if (!ret) 980 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 981 982 rte_free(rss); 983 return ret; 984 } 985 986 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 987 struct rte_eth_rss_reta_entry64 *reta_conf, 988 uint16_t reta_size) 989 { 990 struct port_info *pi = dev->data->dev_private; 991 struct adapter *adapter = pi->adapter; 992 u16 i, idx, shift; 993 994 if (!(adapter->flags & FULL_INIT_DONE)) 995 return -ENOMEM; 996 997 if (!reta_size || reta_size > pi->rss_size) 998 return -EINVAL; 999 1000 for (i = 0; i < reta_size; i++) { 1001 idx = i / RTE_RETA_GROUP_SIZE; 1002 shift = i % RTE_RETA_GROUP_SIZE; 1003 if (!(reta_conf[idx].mask & (1ULL << shift))) 1004 continue; 1005 1006 reta_conf[idx].reta[shift] = pi->rss[i]; 1007 } 1008 1009 return 0; 1010 } 1011 1012 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 1013 { 1014 RTE_SET_USED(dev); 1015 return EEPROMSIZE; 1016 } 1017 1018 /** 1019 * eeprom_ptov - translate a physical EEPROM address to virtual 1020 * @phys_addr: the physical EEPROM address 1021 * @fn: the PCI function number 1022 * @sz: size of function-specific area 1023 * 1024 * Translate a physical EEPROM address to virtual. The first 1K is 1025 * accessed through virtual addresses starting at 31K, the rest is 1026 * accessed through virtual addresses starting at 0. 1027 * 1028 * The mapping is as follows: 1029 * [0..1K) -> [31K..32K) 1030 * [1K..1K+A) -> [31K-A..31K) 1031 * [1K+A..ES) -> [0..ES-A-1K) 1032 * 1033 * where A = @fn * @sz, and ES = EEPROM size. 1034 */ 1035 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1036 { 1037 fn *= sz; 1038 if (phys_addr < 1024) 1039 return phys_addr + (31 << 10); 1040 if (phys_addr < 1024 + fn) 1041 return fn + phys_addr - 1024; 1042 if (phys_addr < EEPROMSIZE) 1043 return phys_addr - 1024 - fn; 1044 if (phys_addr < EEPROMVSIZE) 1045 return phys_addr - 1024; 1046 return -EINVAL; 1047 } 1048 1049 /* The next two routines implement eeprom read/write from physical addresses. 1050 */ 1051 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1052 { 1053 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1054 1055 if (vaddr >= 0) 1056 vaddr = t4_seeprom_read(adap, vaddr, v); 1057 return vaddr < 0 ? vaddr : 0; 1058 } 1059 1060 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1061 { 1062 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1063 1064 if (vaddr >= 0) 1065 vaddr = t4_seeprom_write(adap, vaddr, v); 1066 return vaddr < 0 ? vaddr : 0; 1067 } 1068 1069 #define EEPROM_MAGIC 0x38E2F10C 1070 1071 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1072 struct rte_dev_eeprom_info *e) 1073 { 1074 struct port_info *pi = dev->data->dev_private; 1075 struct adapter *adapter = pi->adapter; 1076 u32 i, err = 0; 1077 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1078 1079 if (!buf) 1080 return -ENOMEM; 1081 1082 e->magic = EEPROM_MAGIC; 1083 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1084 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1085 1086 if (!err) 1087 rte_memcpy(e->data, buf + e->offset, e->length); 1088 rte_free(buf); 1089 return err; 1090 } 1091 1092 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1093 struct rte_dev_eeprom_info *eeprom) 1094 { 1095 struct port_info *pi = dev->data->dev_private; 1096 struct adapter *adapter = pi->adapter; 1097 u8 *buf; 1098 int err = 0; 1099 u32 aligned_offset, aligned_len, *p; 1100 1101 if (eeprom->magic != EEPROM_MAGIC) 1102 return -EINVAL; 1103 1104 aligned_offset = eeprom->offset & ~3; 1105 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1106 1107 if (adapter->pf > 0) { 1108 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1109 1110 if (aligned_offset < start || 1111 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1112 return -EPERM; 1113 } 1114 1115 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1116 /* RMW possibly needed for first or last words. 1117 */ 1118 buf = rte_zmalloc(NULL, aligned_len, 0); 1119 if (!buf) 1120 return -ENOMEM; 1121 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1122 if (!err && aligned_len > 4) 1123 err = eeprom_rd_phys(adapter, 1124 aligned_offset + aligned_len - 4, 1125 (u32 *)&buf[aligned_len - 4]); 1126 if (err) 1127 goto out; 1128 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1129 eeprom->length); 1130 } else { 1131 buf = eeprom->data; 1132 } 1133 1134 err = t4_seeprom_wp(adapter, false); 1135 if (err) 1136 goto out; 1137 1138 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1139 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1140 aligned_offset += 4; 1141 } 1142 1143 if (!err) 1144 err = t4_seeprom_wp(adapter, true); 1145 out: 1146 if (buf != eeprom->data) 1147 rte_free(buf); 1148 return err; 1149 } 1150 1151 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1152 { 1153 struct port_info *pi = eth_dev->data->dev_private; 1154 struct adapter *adapter = pi->adapter; 1155 1156 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1157 } 1158 1159 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1160 struct rte_dev_reg_info *regs) 1161 { 1162 struct port_info *pi = eth_dev->data->dev_private; 1163 struct adapter *adapter = pi->adapter; 1164 1165 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1166 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1167 (1 << 16); 1168 1169 if (regs->data == NULL) { 1170 regs->length = cxgbe_get_regs_len(eth_dev); 1171 regs->width = sizeof(uint32_t); 1172 1173 return 0; 1174 } 1175 1176 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1177 1178 return 0; 1179 } 1180 1181 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1182 { 1183 struct port_info *pi = dev->data->dev_private; 1184 int ret; 1185 1186 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1187 if (ret < 0) { 1188 dev_err(adapter, "failed to set mac addr; err = %d\n", 1189 ret); 1190 return ret; 1191 } 1192 pi->xact_addr_filt = ret; 1193 return 0; 1194 } 1195 1196 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc, 1197 struct rte_eth_fec_capa *capa_arr) 1198 { 1199 int num = 0; 1200 1201 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) { 1202 if (capa_arr) { 1203 capa_arr[num].speed = ETH_SPEED_NUM_100G; 1204 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1205 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1206 } 1207 num++; 1208 } 1209 1210 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) { 1211 if (capa_arr) { 1212 capa_arr[num].speed = ETH_SPEED_NUM_50G; 1213 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1214 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1215 } 1216 num++; 1217 } 1218 1219 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) { 1220 if (capa_arr) { 1221 capa_arr[num].speed = ETH_SPEED_NUM_25G; 1222 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1223 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 1224 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1225 } 1226 num++; 1227 } 1228 1229 return num; 1230 } 1231 1232 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev, 1233 struct rte_eth_fec_capa *speed_fec_capa, 1234 unsigned int num) 1235 { 1236 struct port_info *pi = dev->data->dev_private; 1237 struct link_config *lc = &pi->link_cfg; 1238 u8 num_entries; 1239 1240 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1241 return -EOPNOTSUPP; 1242 1243 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL); 1244 if (!speed_fec_capa || num < num_entries) 1245 return num_entries; 1246 1247 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa); 1248 } 1249 1250 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 1251 { 1252 struct port_info *pi = dev->data->dev_private; 1253 struct link_config *lc = &pi->link_cfg; 1254 u32 fec_caps = 0, caps = lc->link_caps; 1255 1256 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1257 return -EOPNOTSUPP; 1258 1259 if (caps & FW_PORT_CAP32_FEC_RS) 1260 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1261 else if (caps & FW_PORT_CAP32_FEC_BASER_RS) 1262 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1263 else 1264 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 1265 1266 *fec_capa = fec_caps; 1267 return 0; 1268 } 1269 1270 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 1271 { 1272 struct port_info *pi = dev->data->dev_private; 1273 u8 fec_rs = 0, fec_baser = 0, fec_none = 0; 1274 struct link_config *lc = &pi->link_cfg; 1275 u32 new_caps = lc->admin_caps; 1276 int ret; 1277 1278 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1279 return -EOPNOTSUPP; 1280 1281 if (!fec_capa) 1282 return -EINVAL; 1283 1284 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 1285 goto set_fec; 1286 1287 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) 1288 fec_none = 1; 1289 1290 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 1291 fec_baser = 1; 1292 1293 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 1294 fec_rs = 1; 1295 1296 set_fec: 1297 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps); 1298 if (ret != 0) 1299 return ret; 1300 1301 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 1302 new_caps |= FW_PORT_CAP32_FORCE_FEC; 1303 else 1304 new_caps &= ~FW_PORT_CAP32_FORCE_FEC; 1305 1306 if (new_caps != lc->admin_caps) { 1307 ret = t4_link_l1cfg(pi, new_caps); 1308 if (ret == 0) 1309 lc->admin_caps = new_caps; 1310 } 1311 1312 return ret; 1313 } 1314 1315 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1316 .dev_start = cxgbe_dev_start, 1317 .dev_stop = cxgbe_dev_stop, 1318 .dev_close = cxgbe_dev_close, 1319 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1320 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1321 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1322 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1323 .dev_configure = cxgbe_dev_configure, 1324 .dev_infos_get = cxgbe_dev_info_get, 1325 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1326 .link_update = cxgbe_dev_link_update, 1327 .dev_set_link_up = cxgbe_dev_set_link_up, 1328 .dev_set_link_down = cxgbe_dev_set_link_down, 1329 .mtu_set = cxgbe_dev_mtu_set, 1330 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1331 .tx_queue_start = cxgbe_dev_tx_queue_start, 1332 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1333 .tx_queue_release = cxgbe_dev_tx_queue_release, 1334 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1335 .rx_queue_start = cxgbe_dev_rx_queue_start, 1336 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1337 .rx_queue_release = cxgbe_dev_rx_queue_release, 1338 .flow_ops_get = cxgbe_dev_flow_ops_get, 1339 .stats_get = cxgbe_dev_stats_get, 1340 .stats_reset = cxgbe_dev_stats_reset, 1341 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1342 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1343 .get_eeprom_length = cxgbe_get_eeprom_length, 1344 .get_eeprom = cxgbe_get_eeprom, 1345 .set_eeprom = cxgbe_set_eeprom, 1346 .get_reg = cxgbe_get_regs, 1347 .rss_hash_update = cxgbe_dev_rss_hash_update, 1348 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1349 .mac_addr_set = cxgbe_mac_addr_set, 1350 .reta_update = cxgbe_dev_rss_reta_update, 1351 .reta_query = cxgbe_dev_rss_reta_query, 1352 .fec_get_capability = cxgbe_fec_get_capability, 1353 .fec_get = cxgbe_fec_get, 1354 .fec_set = cxgbe_fec_set, 1355 }; 1356 1357 /* 1358 * Initialize driver 1359 * It returns 0 on success. 1360 */ 1361 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1362 { 1363 struct rte_pci_device *pci_dev; 1364 struct port_info *pi = eth_dev->data->dev_private; 1365 struct adapter *adapter = NULL; 1366 char name[RTE_ETH_NAME_MAX_LEN]; 1367 int err = 0; 1368 1369 CXGBE_FUNC_TRACE(); 1370 1371 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1372 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1373 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1374 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1375 1376 /* for secondary processes, we attach to ethdevs allocated by primary 1377 * and do minimal initialization. 1378 */ 1379 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1380 int i; 1381 1382 for (i = 1; i < MAX_NPORTS; i++) { 1383 struct rte_eth_dev *rest_eth_dev; 1384 char namei[RTE_ETH_NAME_MAX_LEN]; 1385 1386 snprintf(namei, sizeof(namei), "%s_%d", 1387 pci_dev->device.name, i); 1388 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1389 if (rest_eth_dev) { 1390 rest_eth_dev->device = &pci_dev->device; 1391 rest_eth_dev->dev_ops = 1392 eth_dev->dev_ops; 1393 rest_eth_dev->rx_pkt_burst = 1394 eth_dev->rx_pkt_burst; 1395 rest_eth_dev->tx_pkt_burst = 1396 eth_dev->tx_pkt_burst; 1397 rte_eth_dev_probing_finish(rest_eth_dev); 1398 } 1399 } 1400 return 0; 1401 } 1402 1403 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1404 1405 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1406 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1407 if (!adapter) 1408 return -1; 1409 1410 adapter->use_unpacked_mode = 1; 1411 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1412 if (!adapter->regs) { 1413 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1414 err = -ENOMEM; 1415 goto out_free_adapter; 1416 } 1417 adapter->pdev = pci_dev; 1418 adapter->eth_dev = eth_dev; 1419 pi->adapter = adapter; 1420 1421 cxgbe_process_devargs(adapter); 1422 1423 err = cxgbe_probe(adapter); 1424 if (err) { 1425 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1426 __func__, err); 1427 goto out_free_adapter; 1428 } 1429 1430 return 0; 1431 1432 out_free_adapter: 1433 rte_free(adapter); 1434 return err; 1435 } 1436 1437 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1438 { 1439 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1440 uint16_t port_id; 1441 int err = 0; 1442 1443 /* Free up other ports and all resources */ 1444 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1445 err |= rte_eth_dev_close(port_id); 1446 1447 return err == 0 ? 0 : -EIO; 1448 } 1449 1450 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1451 struct rte_pci_device *pci_dev) 1452 { 1453 return rte_eth_dev_pci_generic_probe(pci_dev, 1454 sizeof(struct port_info), eth_cxgbe_dev_init); 1455 } 1456 1457 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1458 { 1459 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1460 } 1461 1462 static struct rte_pci_driver rte_cxgbe_pmd = { 1463 .id_table = cxgb4_pci_tbl, 1464 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1465 .probe = eth_cxgbe_pci_probe, 1466 .remove = eth_cxgbe_pci_remove, 1467 }; 1468 1469 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1470 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1471 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1472 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1473 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1474 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1475 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1476 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1477 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE); 1478 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE); 1479