1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2016 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 44 #include <rte_byteorder.h> 45 #include <rte_common.h> 46 #include <rte_cycles.h> 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_tailq.h> 56 #include <rte_eal.h> 57 #include <rte_alarm.h> 58 #include <rte_ether.h> 59 #include <rte_ethdev.h> 60 #include <rte_atomic.h> 61 #include <rte_malloc.h> 62 #include <rte_random.h> 63 #include <rte_dev.h> 64 65 #include "cxgbe.h" 66 67 /* 68 * Macros needed to support the PCI Device ID Table ... 69 */ 70 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 71 static struct rte_pci_id cxgb4_pci_tbl[] = { 72 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 73 74 #define PCI_VENDOR_ID_CHELSIO 0x1425 75 76 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 78 79 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 80 { .vendor_id = 0, } \ 81 } 82 83 /* 84 *... and the PCI ID Table itself ... 85 */ 86 #include "t4_pci_id_tbl.h" 87 88 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 89 uint16_t nb_pkts) 90 { 91 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 92 uint16_t pkts_sent, pkts_remain; 93 uint16_t total_sent = 0; 94 int ret = 0; 95 96 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 97 __func__, txq, tx_pkts, nb_pkts); 98 99 t4_os_lock(&txq->txq_lock); 100 /* free up desc from already completed tx */ 101 reclaim_completed_tx(&txq->q); 102 while (total_sent < nb_pkts) { 103 pkts_remain = nb_pkts - total_sent; 104 105 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 106 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent]); 107 if (ret < 0) 108 break; 109 } 110 if (!pkts_sent) 111 break; 112 total_sent += pkts_sent; 113 /* reclaim as much as possible */ 114 reclaim_completed_tx(&txq->q); 115 } 116 117 t4_os_unlock(&txq->txq_lock); 118 return total_sent; 119 } 120 121 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 122 uint16_t nb_pkts) 123 { 124 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 125 unsigned int work_done; 126 127 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 128 __func__, rxq->rspq.cntxt_id, nb_pkts); 129 130 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 131 dev_err(adapter, "error in cxgbe poll\n"); 132 133 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 134 return work_done; 135 } 136 137 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 138 struct rte_eth_dev_info *device_info) 139 { 140 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 141 struct adapter *adapter = pi->adapter; 142 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 143 144 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 145 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 146 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 147 .nb_align = 1, 148 }; 149 150 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 151 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 152 device_info->max_rx_queues = max_queues; 153 device_info->max_tx_queues = max_queues; 154 device_info->max_mac_addrs = 1; 155 /* XXX: For now we support one MAC/port */ 156 device_info->max_vfs = adapter->params.arch.vfcount; 157 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 158 159 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | 160 DEV_RX_OFFLOAD_IPV4_CKSUM | 161 DEV_RX_OFFLOAD_UDP_CKSUM | 162 DEV_RX_OFFLOAD_TCP_CKSUM; 163 164 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 165 DEV_TX_OFFLOAD_IPV4_CKSUM | 166 DEV_TX_OFFLOAD_UDP_CKSUM | 167 DEV_TX_OFFLOAD_TCP_CKSUM | 168 DEV_TX_OFFLOAD_TCP_TSO; 169 170 device_info->reta_size = pi->rss_size; 171 172 device_info->rx_desc_lim = cxgbe_desc_lim; 173 device_info->tx_desc_lim = cxgbe_desc_lim; 174 device_info->speed_capa = ETH_LINK_SPEED_10G | ETH_LINK_SPEED_40G; 175 } 176 177 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 178 { 179 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 180 struct adapter *adapter = pi->adapter; 181 182 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 183 1, -1, 1, -1, false); 184 } 185 186 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 187 { 188 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 189 struct adapter *adapter = pi->adapter; 190 191 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 192 0, -1, 1, -1, false); 193 } 194 195 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 196 { 197 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 198 struct adapter *adapter = pi->adapter; 199 200 /* TODO: address filters ?? */ 201 202 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 203 -1, 1, 1, -1, false); 204 } 205 206 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 207 { 208 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 209 struct adapter *adapter = pi->adapter; 210 211 /* TODO: address filters ?? */ 212 213 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 214 -1, 0, 1, -1, false); 215 } 216 217 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 218 __rte_unused int wait_to_complete) 219 { 220 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 221 struct adapter *adapter = pi->adapter; 222 struct sge *s = &adapter->sge; 223 struct rte_eth_link *old_link = ð_dev->data->dev_link; 224 unsigned int work_done, budget = 4; 225 226 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 227 if (old_link->link_status == pi->link_cfg.link_ok) 228 return -1; /* link not changed */ 229 230 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok; 231 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX; 232 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed; 233 234 /* link has changed */ 235 return 0; 236 } 237 238 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 239 { 240 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 241 struct adapter *adapter = pi->adapter; 242 struct rte_eth_dev_info dev_info; 243 int err; 244 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 245 246 cxgbe_dev_info_get(eth_dev, &dev_info); 247 248 /* Must accommodate at least ETHER_MIN_MTU */ 249 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen)) 250 return -EINVAL; 251 252 /* set to jumbo mode if needed */ 253 if (new_mtu > ETHER_MAX_LEN) 254 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; 255 else 256 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; 257 258 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 259 -1, -1, true); 260 if (!err) 261 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 262 263 return err; 264 } 265 266 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 267 uint16_t tx_queue_id); 268 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 269 uint16_t tx_queue_id); 270 static void cxgbe_dev_tx_queue_release(void *q); 271 static void cxgbe_dev_rx_queue_release(void *q); 272 273 /* 274 * Stop device. 275 */ 276 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 277 { 278 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 279 struct adapter *adapter = pi->adapter; 280 int i, dev_down = 0; 281 282 CXGBE_FUNC_TRACE(); 283 284 if (!(adapter->flags & FULL_INIT_DONE)) 285 return; 286 287 cxgbe_down(pi); 288 289 /* 290 * We clear queues only if both tx and rx path of the port 291 * have been disabled 292 */ 293 t4_sge_eth_clear_queues(pi); 294 295 /* See if all ports are down */ 296 for_each_port(adapter, i) { 297 pi = adap2pinfo(adapter, i); 298 /* 299 * Skip first port of the adapter since it will be closed 300 * by DPDK 301 */ 302 if (i == 0) 303 continue; 304 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0; 305 } 306 307 /* If rest of the ports are stopped, then free up resources */ 308 if (dev_down == (adapter->params.nports - 1)) 309 cxgbe_close(adapter); 310 } 311 312 /* Start the device. 313 * It returns 0 on success. 314 */ 315 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 316 { 317 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 318 struct adapter *adapter = pi->adapter; 319 int err = 0, i; 320 321 CXGBE_FUNC_TRACE(); 322 323 /* 324 * If we don't have a connection to the firmware there's nothing we 325 * can do. 326 */ 327 if (!(adapter->flags & FW_OK)) { 328 err = -ENXIO; 329 goto out; 330 } 331 332 if (!(adapter->flags & FULL_INIT_DONE)) { 333 err = cxgbe_up(adapter); 334 if (err < 0) 335 goto out; 336 } 337 338 err = setup_rss(pi); 339 if (err) 340 goto out; 341 342 for (i = 0; i < pi->n_tx_qsets; i++) { 343 err = cxgbe_dev_tx_queue_start(eth_dev, i); 344 if (err) 345 goto out; 346 } 347 348 for (i = 0; i < pi->n_rx_qsets; i++) { 349 err = cxgbe_dev_rx_queue_start(eth_dev, i); 350 if (err) 351 goto out; 352 } 353 354 err = link_start(pi); 355 if (err) 356 goto out; 357 358 out: 359 return err; 360 } 361 362 /* 363 * Stop device: disable rx and tx functions to allow for reconfiguring. 364 */ 365 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 366 { 367 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 368 struct adapter *adapter = pi->adapter; 369 370 CXGBE_FUNC_TRACE(); 371 372 if (!(adapter->flags & FULL_INIT_DONE)) 373 return; 374 375 cxgbe_down(pi); 376 377 /* 378 * We clear queues only if both tx and rx path of the port 379 * have been disabled 380 */ 381 t4_sge_eth_clear_queues(pi); 382 } 383 384 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 385 { 386 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 387 struct adapter *adapter = pi->adapter; 388 int err; 389 390 CXGBE_FUNC_TRACE(); 391 392 if (!(adapter->flags & FW_QUEUE_BOUND)) { 393 err = setup_sge_fwevtq(adapter); 394 if (err) 395 return err; 396 adapter->flags |= FW_QUEUE_BOUND; 397 } 398 399 err = cfg_queue_count(eth_dev); 400 if (err) 401 return err; 402 403 return 0; 404 } 405 406 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 407 uint16_t tx_queue_id) 408 { 409 int ret; 410 struct sge_eth_txq *txq = (struct sge_eth_txq *) 411 (eth_dev->data->tx_queues[tx_queue_id]); 412 413 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 414 415 ret = t4_sge_eth_txq_start(txq); 416 if (ret == 0) 417 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 418 419 return ret; 420 } 421 422 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 423 uint16_t tx_queue_id) 424 { 425 int ret; 426 struct sge_eth_txq *txq = (struct sge_eth_txq *) 427 (eth_dev->data->tx_queues[tx_queue_id]); 428 429 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 430 431 ret = t4_sge_eth_txq_stop(txq); 432 if (ret == 0) 433 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 434 435 return ret; 436 } 437 438 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 439 uint16_t queue_idx, uint16_t nb_desc, 440 unsigned int socket_id, 441 const struct rte_eth_txconf *tx_conf) 442 { 443 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 444 struct adapter *adapter = pi->adapter; 445 struct sge *s = &adapter->sge; 446 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 447 int err = 0; 448 unsigned int temp_nb_desc; 449 450 RTE_SET_USED(tx_conf); 451 452 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 453 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 454 socket_id, pi->first_qset); 455 456 /* Free up the existing queue */ 457 if (eth_dev->data->tx_queues[queue_idx]) { 458 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 459 eth_dev->data->tx_queues[queue_idx] = NULL; 460 } 461 462 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 463 464 /* Sanity Checking 465 * 466 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 467 */ 468 temp_nb_desc = nb_desc; 469 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 470 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 471 __func__, CXGBE_MIN_RING_DESC_SIZE, 472 CXGBE_DEFAULT_TX_DESC_SIZE); 473 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 474 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 475 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 476 __func__, CXGBE_MIN_RING_DESC_SIZE, 477 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 478 return -(EINVAL); 479 } 480 481 txq->q.size = temp_nb_desc; 482 483 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 484 s->fw_evtq.cntxt_id, socket_id); 485 486 dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n", 487 __func__, txq->q.cntxt_id, err); 488 489 return err; 490 } 491 492 static void cxgbe_dev_tx_queue_release(void *q) 493 { 494 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 495 496 if (txq) { 497 struct port_info *pi = (struct port_info *) 498 (txq->eth_dev->data->dev_private); 499 struct adapter *adap = pi->adapter; 500 501 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 502 __func__, pi->port_id, txq->q.cntxt_id); 503 504 t4_sge_eth_txq_release(adap, txq); 505 } 506 } 507 508 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 509 uint16_t rx_queue_id) 510 { 511 int ret; 512 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 513 struct adapter *adap = pi->adapter; 514 struct sge_rspq *q; 515 516 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 517 __func__, pi->port_id, rx_queue_id); 518 519 q = eth_dev->data->rx_queues[rx_queue_id]; 520 521 ret = t4_sge_eth_rxq_start(adap, q); 522 if (ret == 0) 523 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 524 525 return ret; 526 } 527 528 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 529 uint16_t rx_queue_id) 530 { 531 int ret; 532 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 533 struct adapter *adap = pi->adapter; 534 struct sge_rspq *q; 535 536 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 537 __func__, pi->port_id, rx_queue_id); 538 539 q = eth_dev->data->rx_queues[rx_queue_id]; 540 ret = t4_sge_eth_rxq_stop(adap, q); 541 if (ret == 0) 542 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 543 544 return ret; 545 } 546 547 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 548 uint16_t queue_idx, uint16_t nb_desc, 549 unsigned int socket_id, 550 const struct rte_eth_rxconf *rx_conf, 551 struct rte_mempool *mp) 552 { 553 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 554 struct adapter *adapter = pi->adapter; 555 struct sge *s = &adapter->sge; 556 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 557 int err = 0; 558 int msi_idx = 0; 559 unsigned int temp_nb_desc; 560 struct rte_eth_dev_info dev_info; 561 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 562 563 RTE_SET_USED(rx_conf); 564 565 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 566 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 567 socket_id, mp); 568 569 cxgbe_dev_info_get(eth_dev, &dev_info); 570 571 /* Must accommodate at least ETHER_MIN_MTU */ 572 if ((pkt_len < dev_info.min_rx_bufsize) || 573 (pkt_len > dev_info.max_rx_pktlen)) { 574 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 575 __func__, dev_info.min_rx_bufsize, 576 dev_info.max_rx_pktlen); 577 return -EINVAL; 578 } 579 580 /* Free up the existing queue */ 581 if (eth_dev->data->rx_queues[queue_idx]) { 582 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 583 eth_dev->data->rx_queues[queue_idx] = NULL; 584 } 585 586 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 587 588 /* Sanity Checking 589 * 590 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 591 */ 592 temp_nb_desc = nb_desc; 593 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 594 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 595 __func__, CXGBE_MIN_RING_DESC_SIZE, 596 CXGBE_DEFAULT_RX_DESC_SIZE); 597 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 598 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 599 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 600 __func__, CXGBE_MIN_RING_DESC_SIZE, 601 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 602 return -(EINVAL); 603 } 604 605 rxq->rspq.size = temp_nb_desc; 606 if ((&rxq->fl) != NULL) 607 rxq->fl.size = temp_nb_desc; 608 609 /* Set to jumbo mode if necessary */ 610 if (pkt_len > ETHER_MAX_LEN) 611 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; 612 else 613 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; 614 615 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 616 &rxq->fl, t4_ethrx_handler, 617 t4_get_mps_bg_map(adapter, pi->tx_chan), mp, 618 queue_idx, socket_id); 619 620 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n", 621 __func__, err, pi->port_id, rxq->rspq.cntxt_id); 622 return err; 623 } 624 625 static void cxgbe_dev_rx_queue_release(void *q) 626 { 627 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 628 struct sge_rspq *rq = &rxq->rspq; 629 630 if (rq) { 631 struct port_info *pi = (struct port_info *) 632 (rq->eth_dev->data->dev_private); 633 struct adapter *adap = pi->adapter; 634 635 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 636 __func__, pi->port_id, rxq->rspq.cntxt_id); 637 638 t4_sge_eth_rxq_release(adap, rxq); 639 } 640 } 641 642 /* 643 * Get port statistics. 644 */ 645 static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 646 struct rte_eth_stats *eth_stats) 647 { 648 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 649 struct adapter *adapter = pi->adapter; 650 struct sge *s = &adapter->sge; 651 struct port_stats ps; 652 unsigned int i; 653 654 cxgbe_stats_get(pi, &ps); 655 656 /* RX Stats */ 657 eth_stats->ipackets = ps.rx_frames; 658 eth_stats->ibytes = ps.rx_octets; 659 eth_stats->imcasts = ps.rx_mcast_frames; 660 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 661 ps.rx_ovflow2 + ps.rx_ovflow3 + 662 ps.rx_trunc0 + ps.rx_trunc1 + 663 ps.rx_trunc2 + ps.rx_trunc3; 664 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 665 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 666 ps.rx_len_err; 667 668 /* TX Stats */ 669 eth_stats->opackets = ps.tx_frames; 670 eth_stats->obytes = ps.tx_octets; 671 eth_stats->oerrors = ps.tx_error_frames; 672 673 for (i = 0; i < pi->n_rx_qsets; i++) { 674 struct sge_eth_rxq *rxq = 675 &s->ethrxq[pi->first_qset + i]; 676 677 eth_stats->q_ipackets[i] = rxq->stats.pkts; 678 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 679 } 680 681 for (i = 0; i < pi->n_tx_qsets; i++) { 682 struct sge_eth_txq *txq = 683 &s->ethtxq[pi->first_qset + i]; 684 685 eth_stats->q_opackets[i] = txq->stats.pkts; 686 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 687 eth_stats->q_errors[i] = txq->stats.mapping_err; 688 } 689 } 690 691 /* 692 * Reset port statistics. 693 */ 694 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 695 { 696 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 697 struct adapter *adapter = pi->adapter; 698 struct sge *s = &adapter->sge; 699 unsigned int i; 700 701 cxgbe_stats_reset(pi); 702 for (i = 0; i < pi->n_rx_qsets; i++) { 703 struct sge_eth_rxq *rxq = 704 &s->ethrxq[pi->first_qset + i]; 705 706 rxq->stats.pkts = 0; 707 rxq->stats.rx_bytes = 0; 708 } 709 for (i = 0; i < pi->n_tx_qsets; i++) { 710 struct sge_eth_txq *txq = 711 &s->ethtxq[pi->first_qset + i]; 712 713 txq->stats.pkts = 0; 714 txq->stats.tx_bytes = 0; 715 txq->stats.mapping_err = 0; 716 } 717 } 718 719 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 720 struct rte_eth_fc_conf *fc_conf) 721 { 722 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 723 struct link_config *lc = &pi->link_cfg; 724 int rx_pause, tx_pause; 725 726 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 727 rx_pause = lc->fc & PAUSE_RX; 728 tx_pause = lc->fc & PAUSE_TX; 729 730 if (rx_pause && tx_pause) 731 fc_conf->mode = RTE_FC_FULL; 732 else if (rx_pause) 733 fc_conf->mode = RTE_FC_RX_PAUSE; 734 else if (tx_pause) 735 fc_conf->mode = RTE_FC_TX_PAUSE; 736 else 737 fc_conf->mode = RTE_FC_NONE; 738 return 0; 739 } 740 741 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 742 struct rte_eth_fc_conf *fc_conf) 743 { 744 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 745 struct adapter *adapter = pi->adapter; 746 struct link_config *lc = &pi->link_cfg; 747 748 if (lc->supported & FW_PORT_CAP_ANEG) { 749 if (fc_conf->autoneg) 750 lc->requested_fc |= PAUSE_AUTONEG; 751 else 752 lc->requested_fc &= ~PAUSE_AUTONEG; 753 } 754 755 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 756 (fc_conf->mode & RTE_FC_RX_PAUSE)) 757 lc->requested_fc |= PAUSE_RX; 758 else 759 lc->requested_fc &= ~PAUSE_RX; 760 761 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 762 (fc_conf->mode & RTE_FC_TX_PAUSE)) 763 lc->requested_fc |= PAUSE_TX; 764 else 765 lc->requested_fc &= ~PAUSE_TX; 766 767 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 768 &pi->link_cfg); 769 } 770 771 static const uint32_t * 772 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 773 { 774 static const uint32_t ptypes[] = { 775 RTE_PTYPE_L3_IPV4, 776 RTE_PTYPE_L3_IPV6, 777 RTE_PTYPE_UNKNOWN 778 }; 779 780 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 781 return ptypes; 782 return NULL; 783 } 784 785 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 786 .dev_start = cxgbe_dev_start, 787 .dev_stop = cxgbe_dev_stop, 788 .dev_close = cxgbe_dev_close, 789 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 790 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 791 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 792 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 793 .dev_configure = cxgbe_dev_configure, 794 .dev_infos_get = cxgbe_dev_info_get, 795 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 796 .link_update = cxgbe_dev_link_update, 797 .mtu_set = cxgbe_dev_mtu_set, 798 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 799 .tx_queue_start = cxgbe_dev_tx_queue_start, 800 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 801 .tx_queue_release = cxgbe_dev_tx_queue_release, 802 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 803 .rx_queue_start = cxgbe_dev_rx_queue_start, 804 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 805 .rx_queue_release = cxgbe_dev_rx_queue_release, 806 .stats_get = cxgbe_dev_stats_get, 807 .stats_reset = cxgbe_dev_stats_reset, 808 .flow_ctrl_get = cxgbe_flow_ctrl_get, 809 .flow_ctrl_set = cxgbe_flow_ctrl_set, 810 }; 811 812 /* 813 * Initialize driver 814 * It returns 0 on success. 815 */ 816 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 817 { 818 struct rte_pci_device *pci_dev; 819 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 820 struct adapter *adapter = NULL; 821 char name[RTE_ETH_NAME_MAX_LEN]; 822 int err = 0; 823 824 CXGBE_FUNC_TRACE(); 825 826 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 827 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 828 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 829 830 /* for secondary processes, we don't initialise any further as primary 831 * has already done this work. 832 */ 833 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 834 return 0; 835 836 pci_dev = eth_dev->pci_dev; 837 838 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 839 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 840 if (!adapter) 841 return -1; 842 843 adapter->use_unpacked_mode = 1; 844 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 845 if (!adapter->regs) { 846 dev_err(adapter, "%s: cannot map device registers\n", __func__); 847 err = -ENOMEM; 848 goto out_free_adapter; 849 } 850 adapter->pdev = pci_dev; 851 adapter->eth_dev = eth_dev; 852 pi->adapter = adapter; 853 854 err = cxgbe_probe(adapter); 855 if (err) { 856 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 857 __func__, err); 858 goto out_free_adapter; 859 } 860 861 return 0; 862 863 out_free_adapter: 864 rte_free(adapter); 865 return err; 866 } 867 868 static struct eth_driver rte_cxgbe_pmd = { 869 .pci_drv = { 870 .name = "rte_cxgbe_pmd", 871 .id_table = cxgb4_pci_tbl, 872 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 873 }, 874 .eth_dev_init = eth_cxgbe_dev_init, 875 .dev_private_size = sizeof(struct port_info), 876 }; 877 878 /* 879 * Driver initialization routine. 880 * Invoked once at EAL init time. 881 * Register itself as the [Poll Mode] Driver of PCI CXGBE devices. 882 */ 883 static int rte_cxgbe_pmd_init(const char *name __rte_unused, 884 const char *params __rte_unused) 885 { 886 CXGBE_FUNC_TRACE(); 887 888 rte_eth_driver_register(&rte_cxgbe_pmd); 889 return 0; 890 } 891 892 static struct rte_driver rte_cxgbe_driver = { 893 .name = "cxgbe_driver", 894 .type = PMD_PDEV, 895 .init = rte_cxgbe_pmd_init, 896 }; 897 898 PMD_REGISTER_DRIVER(rte_cxgbe_driver); 899