1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <ethdev_driver.h> 31 #include <ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <rte_dev.h> 35 36 #include "cxgbe.h" 37 #include "cxgbe_pfvf.h" 38 #include "cxgbe_flow.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "base/t4_pci_id_tbl.h" 60 61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 62 uint16_t nb_pkts) 63 { 64 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 65 uint16_t pkts_sent, pkts_remain; 66 uint16_t total_sent = 0; 67 uint16_t idx = 0; 68 int ret = 0; 69 70 t4_os_lock(&txq->txq_lock); 71 /* free up desc from already completed tx */ 72 reclaim_completed_tx(&txq->q); 73 if (unlikely(!nb_pkts)) 74 goto out_unlock; 75 76 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 77 while (total_sent < nb_pkts) { 78 pkts_remain = nb_pkts - total_sent; 79 80 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 81 idx = total_sent + pkts_sent; 82 if ((idx + 1) < nb_pkts) 83 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 84 volatile void *)); 85 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 86 if (ret < 0) 87 break; 88 } 89 if (!pkts_sent) 90 break; 91 total_sent += pkts_sent; 92 /* reclaim as much as possible */ 93 reclaim_completed_tx(&txq->q); 94 } 95 96 out_unlock: 97 t4_os_unlock(&txq->txq_lock); 98 return total_sent; 99 } 100 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 102 uint16_t nb_pkts) 103 { 104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 105 unsigned int work_done; 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 return work_done; 111 } 112 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 114 struct rte_eth_dev_info *device_info) 115 { 116 struct port_info *pi = eth_dev->data->dev_private; 117 struct adapter *adapter = pi->adapter; 118 119 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 120 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 121 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 122 .nb_align = 1, 123 }; 124 125 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 126 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 127 device_info->max_rx_queues = adapter->sge.max_ethqsets; 128 device_info->max_tx_queues = adapter->sge.max_ethqsets; 129 device_info->max_mac_addrs = 1; 130 /* XXX: For now we support one MAC/port */ 131 device_info->max_vfs = adapter->params.arch.vfcount; 132 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 133 134 device_info->rx_queue_offload_capa = 0UL; 135 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 136 137 device_info->tx_queue_offload_capa = 0UL; 138 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 139 140 device_info->reta_size = pi->rss_size; 141 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 142 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 143 144 device_info->rx_desc_lim = cxgbe_desc_lim; 145 device_info->tx_desc_lim = cxgbe_desc_lim; 146 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 147 148 return 0; 149 } 150 151 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 152 { 153 struct port_info *pi = eth_dev->data->dev_private; 154 struct adapter *adapter = pi->adapter; 155 156 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 157 1, -1, 1, -1, false); 158 } 159 160 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 161 { 162 struct port_info *pi = eth_dev->data->dev_private; 163 struct adapter *adapter = pi->adapter; 164 165 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 166 0, -1, 1, -1, false); 167 } 168 169 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 170 { 171 struct port_info *pi = eth_dev->data->dev_private; 172 struct adapter *adapter = pi->adapter; 173 174 /* TODO: address filters ?? */ 175 176 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 177 -1, 1, 1, -1, false); 178 } 179 180 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 181 { 182 struct port_info *pi = eth_dev->data->dev_private; 183 struct adapter *adapter = pi->adapter; 184 185 /* TODO: address filters ?? */ 186 187 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 188 -1, 0, 1, -1, false); 189 } 190 191 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 192 int wait_to_complete) 193 { 194 struct port_info *pi = eth_dev->data->dev_private; 195 unsigned int i, work_done, budget = 32; 196 struct link_config *lc = &pi->link_cfg; 197 struct adapter *adapter = pi->adapter; 198 struct rte_eth_link new_link = { 0 }; 199 u8 old_link = pi->link_cfg.link_ok; 200 struct sge *s = &adapter->sge; 201 202 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 203 if (!s->fw_evtq.desc) 204 break; 205 206 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 207 208 /* Exit if link status changed or always forced up */ 209 if (pi->link_cfg.link_ok != old_link || 210 cxgbe_force_linkup(adapter)) 211 break; 212 213 if (!wait_to_complete) 214 break; 215 216 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 217 } 218 219 new_link.link_status = cxgbe_force_linkup(adapter) ? 220 ETH_LINK_UP : pi->link_cfg.link_ok; 221 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; 222 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 223 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps); 224 225 return rte_eth_linkstatus_set(eth_dev, &new_link); 226 } 227 228 /** 229 * Set device link up. 230 */ 231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 232 { 233 struct port_info *pi = dev->data->dev_private; 234 struct adapter *adapter = pi->adapter; 235 unsigned int work_done, budget = 32; 236 struct sge *s = &adapter->sge; 237 int ret; 238 239 if (!s->fw_evtq.desc) 240 return -ENOMEM; 241 242 /* Flush all link events */ 243 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 244 245 /* If link already up, nothing to do */ 246 if (pi->link_cfg.link_ok) 247 return 0; 248 249 ret = cxgbe_set_link_status(pi, true); 250 if (ret) 251 return ret; 252 253 cxgbe_dev_link_update(dev, 1); 254 return 0; 255 } 256 257 /** 258 * Set device link down. 259 */ 260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 261 { 262 struct port_info *pi = dev->data->dev_private; 263 struct adapter *adapter = pi->adapter; 264 unsigned int work_done, budget = 32; 265 struct sge *s = &adapter->sge; 266 int ret; 267 268 if (!s->fw_evtq.desc) 269 return -ENOMEM; 270 271 /* Flush all link events */ 272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 273 274 /* If link already down, nothing to do */ 275 if (!pi->link_cfg.link_ok) 276 return 0; 277 278 ret = cxgbe_set_link_status(pi, false); 279 if (ret) 280 return ret; 281 282 cxgbe_dev_link_update(dev, 0); 283 return 0; 284 } 285 286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 287 { 288 struct port_info *pi = eth_dev->data->dev_private; 289 struct adapter *adapter = pi->adapter; 290 struct rte_eth_dev_info dev_info; 291 int err; 292 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 293 294 err = cxgbe_dev_info_get(eth_dev, &dev_info); 295 if (err != 0) 296 return err; 297 298 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 299 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 300 return -EINVAL; 301 302 /* set to jumbo mode if needed */ 303 if (new_mtu > CXGBE_ETH_MAX_LEN) 304 eth_dev->data->dev_conf.rxmode.offloads |= 305 DEV_RX_OFFLOAD_JUMBO_FRAME; 306 else 307 eth_dev->data->dev_conf.rxmode.offloads &= 308 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 309 310 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 311 -1, -1, true); 312 if (!err) 313 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 314 315 return err; 316 } 317 318 /* 319 * Stop device. 320 */ 321 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 322 { 323 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 324 struct adapter *adapter = pi->adapter; 325 u8 i; 326 327 CXGBE_FUNC_TRACE(); 328 329 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 330 return 0; 331 332 if (!(adapter->flags & FULL_INIT_DONE)) 333 return 0; 334 335 if (!pi->viid) 336 return 0; 337 338 cxgbe_down(pi); 339 t4_sge_eth_release_queues(pi); 340 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 341 pi->viid = 0; 342 343 /* Free up the adapter-wide resources only after all the ports 344 * under this PF have been closed. 345 */ 346 for_each_port(adapter, i) { 347 temp_pi = adap2pinfo(adapter, i); 348 if (temp_pi->viid) 349 return 0; 350 } 351 352 cxgbe_close(adapter); 353 rte_free(adapter); 354 355 return 0; 356 } 357 358 /* Start the device. 359 * It returns 0 on success. 360 */ 361 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 362 { 363 struct port_info *pi = eth_dev->data->dev_private; 364 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 365 struct adapter *adapter = pi->adapter; 366 int err = 0, i; 367 368 CXGBE_FUNC_TRACE(); 369 370 /* 371 * If we don't have a connection to the firmware there's nothing we 372 * can do. 373 */ 374 if (!(adapter->flags & FW_OK)) { 375 err = -ENXIO; 376 goto out; 377 } 378 379 if (!(adapter->flags & FULL_INIT_DONE)) { 380 err = cxgbe_up(adapter); 381 if (err < 0) 382 goto out; 383 } 384 385 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 386 eth_dev->data->scattered_rx = 1; 387 else 388 eth_dev->data->scattered_rx = 0; 389 390 cxgbe_enable_rx_queues(pi); 391 392 err = cxgbe_setup_rss(pi); 393 if (err) 394 goto out; 395 396 for (i = 0; i < pi->n_tx_qsets; i++) { 397 err = cxgbe_dev_tx_queue_start(eth_dev, i); 398 if (err) 399 goto out; 400 } 401 402 for (i = 0; i < pi->n_rx_qsets; i++) { 403 err = cxgbe_dev_rx_queue_start(eth_dev, i); 404 if (err) 405 goto out; 406 } 407 408 err = cxgbe_link_start(pi); 409 if (err) 410 goto out; 411 412 out: 413 return err; 414 } 415 416 /* 417 * Stop device: disable rx and tx functions to allow for reconfiguring. 418 */ 419 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 420 { 421 struct port_info *pi = eth_dev->data->dev_private; 422 struct adapter *adapter = pi->adapter; 423 424 CXGBE_FUNC_TRACE(); 425 426 if (!(adapter->flags & FULL_INIT_DONE)) 427 return 0; 428 429 cxgbe_down(pi); 430 431 /* 432 * We clear queues only if both tx and rx path of the port 433 * have been disabled 434 */ 435 t4_sge_eth_clear_queues(pi); 436 eth_dev->data->scattered_rx = 0; 437 438 return 0; 439 } 440 441 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 442 { 443 struct port_info *pi = eth_dev->data->dev_private; 444 struct adapter *adapter = pi->adapter; 445 int err; 446 447 CXGBE_FUNC_TRACE(); 448 449 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 450 eth_dev->data->dev_conf.rxmode.offloads |= 451 DEV_RX_OFFLOAD_RSS_HASH; 452 453 if (!(adapter->flags & FW_QUEUE_BOUND)) { 454 err = cxgbe_setup_sge_fwevtq(adapter); 455 if (err) 456 return err; 457 adapter->flags |= FW_QUEUE_BOUND; 458 if (is_pf4(adapter)) { 459 err = cxgbe_setup_sge_ctrl_txq(adapter); 460 if (err) 461 return err; 462 } 463 } 464 465 err = cxgbe_cfg_queue_count(eth_dev); 466 if (err) 467 return err; 468 469 return 0; 470 } 471 472 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 473 { 474 int ret; 475 struct sge_eth_txq *txq = (struct sge_eth_txq *) 476 (eth_dev->data->tx_queues[tx_queue_id]); 477 478 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 479 480 ret = t4_sge_eth_txq_start(txq); 481 if (ret == 0) 482 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 483 484 return ret; 485 } 486 487 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 488 { 489 int ret; 490 struct sge_eth_txq *txq = (struct sge_eth_txq *) 491 (eth_dev->data->tx_queues[tx_queue_id]); 492 493 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 494 495 ret = t4_sge_eth_txq_stop(txq); 496 if (ret == 0) 497 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 498 499 return ret; 500 } 501 502 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 503 uint16_t queue_idx, uint16_t nb_desc, 504 unsigned int socket_id, 505 const struct rte_eth_txconf *tx_conf __rte_unused) 506 { 507 struct port_info *pi = eth_dev->data->dev_private; 508 struct adapter *adapter = pi->adapter; 509 struct sge *s = &adapter->sge; 510 unsigned int temp_nb_desc; 511 struct sge_eth_txq *txq; 512 int err = 0; 513 514 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 515 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 516 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 517 socket_id, pi->first_txqset); 518 519 /* Free up the existing queue */ 520 if (eth_dev->data->tx_queues[queue_idx]) { 521 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 522 eth_dev->data->tx_queues[queue_idx] = NULL; 523 } 524 525 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 526 527 /* Sanity Checking 528 * 529 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 530 */ 531 temp_nb_desc = nb_desc; 532 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 533 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 534 __func__, CXGBE_MIN_RING_DESC_SIZE, 535 CXGBE_DEFAULT_TX_DESC_SIZE); 536 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 537 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 538 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 539 __func__, CXGBE_MIN_RING_DESC_SIZE, 540 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 541 return -(EINVAL); 542 } 543 544 txq->q.size = temp_nb_desc; 545 546 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 547 s->fw_evtq.cntxt_id, socket_id); 548 549 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 550 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 551 return err; 552 } 553 554 void cxgbe_dev_tx_queue_release(void *q) 555 { 556 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 557 558 if (txq) { 559 struct port_info *pi = (struct port_info *) 560 (txq->eth_dev->data->dev_private); 561 struct adapter *adap = pi->adapter; 562 563 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 564 __func__, pi->port_id, txq->q.cntxt_id); 565 566 t4_sge_eth_txq_release(adap, txq); 567 } 568 } 569 570 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 571 { 572 struct port_info *pi = eth_dev->data->dev_private; 573 struct adapter *adap = pi->adapter; 574 struct sge_eth_rxq *rxq; 575 int ret; 576 577 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 578 __func__, pi->port_id, rx_queue_id); 579 580 rxq = eth_dev->data->rx_queues[rx_queue_id]; 581 ret = t4_sge_eth_rxq_start(adap, rxq); 582 if (ret == 0) 583 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 584 585 return ret; 586 } 587 588 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 589 { 590 struct port_info *pi = eth_dev->data->dev_private; 591 struct adapter *adap = pi->adapter; 592 struct sge_eth_rxq *rxq; 593 int ret; 594 595 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 596 __func__, pi->port_id, rx_queue_id); 597 598 rxq = eth_dev->data->rx_queues[rx_queue_id]; 599 ret = t4_sge_eth_rxq_stop(adap, rxq); 600 if (ret == 0) 601 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 602 603 return ret; 604 } 605 606 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 607 uint16_t queue_idx, uint16_t nb_desc, 608 unsigned int socket_id, 609 const struct rte_eth_rxconf *rx_conf __rte_unused, 610 struct rte_mempool *mp) 611 { 612 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 613 struct port_info *pi = eth_dev->data->dev_private; 614 struct adapter *adapter = pi->adapter; 615 struct rte_eth_dev_info dev_info; 616 struct sge *s = &adapter->sge; 617 unsigned int temp_nb_desc; 618 int err = 0, msi_idx = 0; 619 struct sge_eth_rxq *rxq; 620 621 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 622 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 623 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 624 socket_id, mp); 625 626 err = cxgbe_dev_info_get(eth_dev, &dev_info); 627 if (err != 0) { 628 dev_err(adap, "%s: error during getting ethernet device info", 629 __func__); 630 return err; 631 } 632 633 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 634 if ((pkt_len < dev_info.min_rx_bufsize) || 635 (pkt_len > dev_info.max_rx_pktlen)) { 636 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 637 __func__, dev_info.min_rx_bufsize, 638 dev_info.max_rx_pktlen); 639 return -EINVAL; 640 } 641 642 /* Free up the existing queue */ 643 if (eth_dev->data->rx_queues[queue_idx]) { 644 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 645 eth_dev->data->rx_queues[queue_idx] = NULL; 646 } 647 648 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 649 650 /* Sanity Checking 651 * 652 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 653 */ 654 temp_nb_desc = nb_desc; 655 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 656 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 657 __func__, CXGBE_MIN_RING_DESC_SIZE, 658 CXGBE_DEFAULT_RX_DESC_SIZE); 659 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 660 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 661 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 662 __func__, CXGBE_MIN_RING_DESC_SIZE, 663 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 664 return -(EINVAL); 665 } 666 667 rxq->rspq.size = temp_nb_desc; 668 if ((&rxq->fl) != NULL) 669 rxq->fl.size = temp_nb_desc; 670 671 /* Set to jumbo mode if necessary */ 672 if (pkt_len > CXGBE_ETH_MAX_LEN) 673 eth_dev->data->dev_conf.rxmode.offloads |= 674 DEV_RX_OFFLOAD_JUMBO_FRAME; 675 else 676 eth_dev->data->dev_conf.rxmode.offloads &= 677 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 678 679 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 680 &rxq->fl, NULL, 681 is_pf4(adapter) ? 682 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 683 queue_idx, socket_id); 684 685 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 686 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 687 rxq->rspq.abs_id); 688 return err; 689 } 690 691 void cxgbe_dev_rx_queue_release(void *q) 692 { 693 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 694 695 if (rxq) { 696 struct port_info *pi = (struct port_info *) 697 (rxq->rspq.eth_dev->data->dev_private); 698 struct adapter *adap = pi->adapter; 699 700 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 701 __func__, pi->port_id, rxq->rspq.cntxt_id); 702 703 t4_sge_eth_rxq_release(adap, rxq); 704 } 705 } 706 707 /* 708 * Get port statistics. 709 */ 710 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 711 struct rte_eth_stats *eth_stats) 712 { 713 struct port_info *pi = eth_dev->data->dev_private; 714 struct adapter *adapter = pi->adapter; 715 struct sge *s = &adapter->sge; 716 struct port_stats ps; 717 unsigned int i; 718 719 cxgbe_stats_get(pi, &ps); 720 721 /* RX Stats */ 722 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 723 ps.rx_ovflow2 + ps.rx_ovflow3 + 724 ps.rx_trunc0 + ps.rx_trunc1 + 725 ps.rx_trunc2 + ps.rx_trunc3; 726 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 727 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 728 ps.rx_len_err; 729 730 /* TX Stats */ 731 eth_stats->opackets = ps.tx_frames; 732 eth_stats->obytes = ps.tx_octets; 733 eth_stats->oerrors = ps.tx_error_frames; 734 735 for (i = 0; i < pi->n_rx_qsets; i++) { 736 struct sge_eth_rxq *rxq = 737 &s->ethrxq[pi->first_rxqset + i]; 738 739 eth_stats->q_ipackets[i] = rxq->stats.pkts; 740 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 741 eth_stats->ipackets += eth_stats->q_ipackets[i]; 742 eth_stats->ibytes += eth_stats->q_ibytes[i]; 743 } 744 745 for (i = 0; i < pi->n_tx_qsets; i++) { 746 struct sge_eth_txq *txq = 747 &s->ethtxq[pi->first_txqset + i]; 748 749 eth_stats->q_opackets[i] = txq->stats.pkts; 750 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 751 } 752 return 0; 753 } 754 755 /* 756 * Reset port statistics. 757 */ 758 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 759 { 760 struct port_info *pi = eth_dev->data->dev_private; 761 struct adapter *adapter = pi->adapter; 762 struct sge *s = &adapter->sge; 763 unsigned int i; 764 765 cxgbe_stats_reset(pi); 766 for (i = 0; i < pi->n_rx_qsets; i++) { 767 struct sge_eth_rxq *rxq = 768 &s->ethrxq[pi->first_rxqset + i]; 769 770 rxq->stats.pkts = 0; 771 rxq->stats.rx_bytes = 0; 772 } 773 for (i = 0; i < pi->n_tx_qsets; i++) { 774 struct sge_eth_txq *txq = 775 &s->ethtxq[pi->first_txqset + i]; 776 777 txq->stats.pkts = 0; 778 txq->stats.tx_bytes = 0; 779 txq->stats.mapping_err = 0; 780 } 781 782 return 0; 783 } 784 785 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 786 struct rte_eth_fc_conf *fc_conf) 787 { 788 struct port_info *pi = eth_dev->data->dev_private; 789 struct link_config *lc = &pi->link_cfg; 790 u8 rx_pause = 0, tx_pause = 0; 791 u32 caps = lc->link_caps; 792 793 if (caps & FW_PORT_CAP32_ANEG) 794 fc_conf->autoneg = 1; 795 796 if (caps & FW_PORT_CAP32_FC_TX) 797 tx_pause = 1; 798 799 if (caps & FW_PORT_CAP32_FC_RX) 800 rx_pause = 1; 801 802 if (rx_pause && tx_pause) 803 fc_conf->mode = RTE_FC_FULL; 804 else if (rx_pause) 805 fc_conf->mode = RTE_FC_RX_PAUSE; 806 else if (tx_pause) 807 fc_conf->mode = RTE_FC_TX_PAUSE; 808 else 809 fc_conf->mode = RTE_FC_NONE; 810 return 0; 811 } 812 813 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 814 struct rte_eth_fc_conf *fc_conf) 815 { 816 struct port_info *pi = eth_dev->data->dev_private; 817 struct link_config *lc = &pi->link_cfg; 818 u32 new_caps = lc->admin_caps; 819 u8 tx_pause = 0, rx_pause = 0; 820 int ret; 821 822 if (fc_conf->mode == RTE_FC_FULL) { 823 tx_pause = 1; 824 rx_pause = 1; 825 } else if (fc_conf->mode == RTE_FC_TX_PAUSE) { 826 tx_pause = 1; 827 } else if (fc_conf->mode == RTE_FC_RX_PAUSE) { 828 rx_pause = 1; 829 } 830 831 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause, 832 rx_pause, &new_caps); 833 if (ret != 0) 834 return ret; 835 836 if (!fc_conf->autoneg) { 837 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE) 838 new_caps |= FW_PORT_CAP32_FORCE_PAUSE; 839 } else { 840 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE; 841 } 842 843 if (new_caps != lc->admin_caps) { 844 ret = t4_link_l1cfg(pi, new_caps); 845 if (ret == 0) 846 lc->admin_caps = new_caps; 847 } 848 849 return ret; 850 } 851 852 const uint32_t * 853 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 854 { 855 static const uint32_t ptypes[] = { 856 RTE_PTYPE_L3_IPV4, 857 RTE_PTYPE_L3_IPV6, 858 RTE_PTYPE_UNKNOWN 859 }; 860 861 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 862 return ptypes; 863 return NULL; 864 } 865 866 /* Update RSS hash configuration 867 */ 868 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 869 struct rte_eth_rss_conf *rss_conf) 870 { 871 struct port_info *pi = dev->data->dev_private; 872 struct adapter *adapter = pi->adapter; 873 int err; 874 875 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 876 if (err) 877 return err; 878 879 pi->rss_hf = rss_conf->rss_hf; 880 881 if (rss_conf->rss_key) { 882 u32 key[10], mod_key[10]; 883 int i, j; 884 885 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 886 887 for (i = 9, j = 0; i >= 0; i--, j++) 888 mod_key[j] = cpu_to_be32(key[i]); 889 890 t4_write_rss_key(adapter, mod_key, -1); 891 } 892 893 return 0; 894 } 895 896 /* Get RSS hash configuration 897 */ 898 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 899 struct rte_eth_rss_conf *rss_conf) 900 { 901 struct port_info *pi = dev->data->dev_private; 902 struct adapter *adapter = pi->adapter; 903 u64 rss_hf = 0; 904 u64 flags = 0; 905 int err; 906 907 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 908 &flags, NULL); 909 910 if (err) 911 return err; 912 913 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 914 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 915 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 916 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 917 } 918 919 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 920 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 921 922 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 923 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 924 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 925 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 926 } 927 928 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 929 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 930 931 rss_conf->rss_hf = rss_hf; 932 933 if (rss_conf->rss_key) { 934 u32 key[10], mod_key[10]; 935 int i, j; 936 937 t4_read_rss_key(adapter, key); 938 939 for (i = 9, j = 0; i >= 0; i--, j++) 940 mod_key[j] = be32_to_cpu(key[i]); 941 942 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 943 } 944 945 return 0; 946 } 947 948 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 949 struct rte_eth_rss_reta_entry64 *reta_conf, 950 uint16_t reta_size) 951 { 952 struct port_info *pi = dev->data->dev_private; 953 struct adapter *adapter = pi->adapter; 954 u16 i, idx, shift, *rss; 955 int ret; 956 957 if (!(adapter->flags & FULL_INIT_DONE)) 958 return -ENOMEM; 959 960 if (!reta_size || reta_size > pi->rss_size) 961 return -EINVAL; 962 963 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 964 if (!rss) 965 return -ENOMEM; 966 967 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 968 for (i = 0; i < reta_size; i++) { 969 idx = i / RTE_RETA_GROUP_SIZE; 970 shift = i % RTE_RETA_GROUP_SIZE; 971 if (!(reta_conf[idx].mask & (1ULL << shift))) 972 continue; 973 974 rss[i] = reta_conf[idx].reta[shift]; 975 } 976 977 ret = cxgbe_write_rss(pi, rss); 978 if (!ret) 979 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 980 981 rte_free(rss); 982 return ret; 983 } 984 985 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 986 struct rte_eth_rss_reta_entry64 *reta_conf, 987 uint16_t reta_size) 988 { 989 struct port_info *pi = dev->data->dev_private; 990 struct adapter *adapter = pi->adapter; 991 u16 i, idx, shift; 992 993 if (!(adapter->flags & FULL_INIT_DONE)) 994 return -ENOMEM; 995 996 if (!reta_size || reta_size > pi->rss_size) 997 return -EINVAL; 998 999 for (i = 0; i < reta_size; i++) { 1000 idx = i / RTE_RETA_GROUP_SIZE; 1001 shift = i % RTE_RETA_GROUP_SIZE; 1002 if (!(reta_conf[idx].mask & (1ULL << shift))) 1003 continue; 1004 1005 reta_conf[idx].reta[shift] = pi->rss[i]; 1006 } 1007 1008 return 0; 1009 } 1010 1011 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 1012 { 1013 RTE_SET_USED(dev); 1014 return EEPROMSIZE; 1015 } 1016 1017 /** 1018 * eeprom_ptov - translate a physical EEPROM address to virtual 1019 * @phys_addr: the physical EEPROM address 1020 * @fn: the PCI function number 1021 * @sz: size of function-specific area 1022 * 1023 * Translate a physical EEPROM address to virtual. The first 1K is 1024 * accessed through virtual addresses starting at 31K, the rest is 1025 * accessed through virtual addresses starting at 0. 1026 * 1027 * The mapping is as follows: 1028 * [0..1K) -> [31K..32K) 1029 * [1K..1K+A) -> [31K-A..31K) 1030 * [1K+A..ES) -> [0..ES-A-1K) 1031 * 1032 * where A = @fn * @sz, and ES = EEPROM size. 1033 */ 1034 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1035 { 1036 fn *= sz; 1037 if (phys_addr < 1024) 1038 return phys_addr + (31 << 10); 1039 if (phys_addr < 1024 + fn) 1040 return fn + phys_addr - 1024; 1041 if (phys_addr < EEPROMSIZE) 1042 return phys_addr - 1024 - fn; 1043 if (phys_addr < EEPROMVSIZE) 1044 return phys_addr - 1024; 1045 return -EINVAL; 1046 } 1047 1048 /* The next two routines implement eeprom read/write from physical addresses. 1049 */ 1050 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1051 { 1052 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1053 1054 if (vaddr >= 0) 1055 vaddr = t4_seeprom_read(adap, vaddr, v); 1056 return vaddr < 0 ? vaddr : 0; 1057 } 1058 1059 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1060 { 1061 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1062 1063 if (vaddr >= 0) 1064 vaddr = t4_seeprom_write(adap, vaddr, v); 1065 return vaddr < 0 ? vaddr : 0; 1066 } 1067 1068 #define EEPROM_MAGIC 0x38E2F10C 1069 1070 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1071 struct rte_dev_eeprom_info *e) 1072 { 1073 struct port_info *pi = dev->data->dev_private; 1074 struct adapter *adapter = pi->adapter; 1075 u32 i, err = 0; 1076 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1077 1078 if (!buf) 1079 return -ENOMEM; 1080 1081 e->magic = EEPROM_MAGIC; 1082 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1083 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1084 1085 if (!err) 1086 rte_memcpy(e->data, buf + e->offset, e->length); 1087 rte_free(buf); 1088 return err; 1089 } 1090 1091 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1092 struct rte_dev_eeprom_info *eeprom) 1093 { 1094 struct port_info *pi = dev->data->dev_private; 1095 struct adapter *adapter = pi->adapter; 1096 u8 *buf; 1097 int err = 0; 1098 u32 aligned_offset, aligned_len, *p; 1099 1100 if (eeprom->magic != EEPROM_MAGIC) 1101 return -EINVAL; 1102 1103 aligned_offset = eeprom->offset & ~3; 1104 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1105 1106 if (adapter->pf > 0) { 1107 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1108 1109 if (aligned_offset < start || 1110 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1111 return -EPERM; 1112 } 1113 1114 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1115 /* RMW possibly needed for first or last words. 1116 */ 1117 buf = rte_zmalloc(NULL, aligned_len, 0); 1118 if (!buf) 1119 return -ENOMEM; 1120 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1121 if (!err && aligned_len > 4) 1122 err = eeprom_rd_phys(adapter, 1123 aligned_offset + aligned_len - 4, 1124 (u32 *)&buf[aligned_len - 4]); 1125 if (err) 1126 goto out; 1127 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1128 eeprom->length); 1129 } else { 1130 buf = eeprom->data; 1131 } 1132 1133 err = t4_seeprom_wp(adapter, false); 1134 if (err) 1135 goto out; 1136 1137 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1138 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1139 aligned_offset += 4; 1140 } 1141 1142 if (!err) 1143 err = t4_seeprom_wp(adapter, true); 1144 out: 1145 if (buf != eeprom->data) 1146 rte_free(buf); 1147 return err; 1148 } 1149 1150 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1151 { 1152 struct port_info *pi = eth_dev->data->dev_private; 1153 struct adapter *adapter = pi->adapter; 1154 1155 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1156 } 1157 1158 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1159 struct rte_dev_reg_info *regs) 1160 { 1161 struct port_info *pi = eth_dev->data->dev_private; 1162 struct adapter *adapter = pi->adapter; 1163 1164 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1165 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1166 (1 << 16); 1167 1168 if (regs->data == NULL) { 1169 regs->length = cxgbe_get_regs_len(eth_dev); 1170 regs->width = sizeof(uint32_t); 1171 1172 return 0; 1173 } 1174 1175 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1176 1177 return 0; 1178 } 1179 1180 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1181 { 1182 struct port_info *pi = dev->data->dev_private; 1183 int ret; 1184 1185 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1186 if (ret < 0) { 1187 dev_err(adapter, "failed to set mac addr; err = %d\n", 1188 ret); 1189 return ret; 1190 } 1191 pi->xact_addr_filt = ret; 1192 return 0; 1193 } 1194 1195 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc, 1196 struct rte_eth_fec_capa *capa_arr) 1197 { 1198 int num = 0; 1199 1200 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) { 1201 if (capa_arr) { 1202 capa_arr[num].speed = ETH_SPEED_NUM_100G; 1203 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1204 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1205 } 1206 num++; 1207 } 1208 1209 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) { 1210 if (capa_arr) { 1211 capa_arr[num].speed = ETH_SPEED_NUM_50G; 1212 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1213 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1214 } 1215 num++; 1216 } 1217 1218 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) { 1219 if (capa_arr) { 1220 capa_arr[num].speed = ETH_SPEED_NUM_25G; 1221 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1222 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 1223 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1224 } 1225 num++; 1226 } 1227 1228 return num; 1229 } 1230 1231 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev, 1232 struct rte_eth_fec_capa *speed_fec_capa, 1233 unsigned int num) 1234 { 1235 struct port_info *pi = dev->data->dev_private; 1236 struct link_config *lc = &pi->link_cfg; 1237 u8 num_entries; 1238 1239 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1240 return -EOPNOTSUPP; 1241 1242 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL); 1243 if (!speed_fec_capa || num < num_entries) 1244 return num_entries; 1245 1246 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa); 1247 } 1248 1249 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 1250 { 1251 struct port_info *pi = dev->data->dev_private; 1252 struct link_config *lc = &pi->link_cfg; 1253 u32 fec_caps = 0, caps = lc->link_caps; 1254 1255 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1256 return -EOPNOTSUPP; 1257 1258 if (caps & FW_PORT_CAP32_FEC_RS) 1259 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1260 else if (caps & FW_PORT_CAP32_FEC_BASER_RS) 1261 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1262 else 1263 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 1264 1265 *fec_capa = fec_caps; 1266 return 0; 1267 } 1268 1269 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 1270 { 1271 struct port_info *pi = dev->data->dev_private; 1272 u8 fec_rs = 0, fec_baser = 0, fec_none = 0; 1273 struct link_config *lc = &pi->link_cfg; 1274 u32 new_caps = lc->admin_caps; 1275 int ret; 1276 1277 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1278 return -EOPNOTSUPP; 1279 1280 if (!fec_capa) 1281 return -EINVAL; 1282 1283 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 1284 goto set_fec; 1285 1286 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) 1287 fec_none = 1; 1288 1289 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 1290 fec_baser = 1; 1291 1292 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 1293 fec_rs = 1; 1294 1295 set_fec: 1296 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps); 1297 if (ret != 0) 1298 return ret; 1299 1300 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 1301 new_caps |= FW_PORT_CAP32_FORCE_FEC; 1302 else 1303 new_caps &= ~FW_PORT_CAP32_FORCE_FEC; 1304 1305 if (new_caps != lc->admin_caps) { 1306 ret = t4_link_l1cfg(pi, new_caps); 1307 if (ret == 0) 1308 lc->admin_caps = new_caps; 1309 } 1310 1311 return ret; 1312 } 1313 1314 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1315 .dev_start = cxgbe_dev_start, 1316 .dev_stop = cxgbe_dev_stop, 1317 .dev_close = cxgbe_dev_close, 1318 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1319 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1320 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1321 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1322 .dev_configure = cxgbe_dev_configure, 1323 .dev_infos_get = cxgbe_dev_info_get, 1324 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1325 .link_update = cxgbe_dev_link_update, 1326 .dev_set_link_up = cxgbe_dev_set_link_up, 1327 .dev_set_link_down = cxgbe_dev_set_link_down, 1328 .mtu_set = cxgbe_dev_mtu_set, 1329 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1330 .tx_queue_start = cxgbe_dev_tx_queue_start, 1331 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1332 .tx_queue_release = cxgbe_dev_tx_queue_release, 1333 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1334 .rx_queue_start = cxgbe_dev_rx_queue_start, 1335 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1336 .rx_queue_release = cxgbe_dev_rx_queue_release, 1337 .flow_ops_get = cxgbe_dev_flow_ops_get, 1338 .stats_get = cxgbe_dev_stats_get, 1339 .stats_reset = cxgbe_dev_stats_reset, 1340 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1341 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1342 .get_eeprom_length = cxgbe_get_eeprom_length, 1343 .get_eeprom = cxgbe_get_eeprom, 1344 .set_eeprom = cxgbe_set_eeprom, 1345 .get_reg = cxgbe_get_regs, 1346 .rss_hash_update = cxgbe_dev_rss_hash_update, 1347 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1348 .mac_addr_set = cxgbe_mac_addr_set, 1349 .reta_update = cxgbe_dev_rss_reta_update, 1350 .reta_query = cxgbe_dev_rss_reta_query, 1351 .fec_get_capability = cxgbe_fec_get_capability, 1352 .fec_get = cxgbe_fec_get, 1353 .fec_set = cxgbe_fec_set, 1354 }; 1355 1356 /* 1357 * Initialize driver 1358 * It returns 0 on success. 1359 */ 1360 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1361 { 1362 struct rte_pci_device *pci_dev; 1363 struct port_info *pi = eth_dev->data->dev_private; 1364 struct adapter *adapter = NULL; 1365 char name[RTE_ETH_NAME_MAX_LEN]; 1366 int err = 0; 1367 1368 CXGBE_FUNC_TRACE(); 1369 1370 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1371 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1372 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1373 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1374 1375 /* for secondary processes, we attach to ethdevs allocated by primary 1376 * and do minimal initialization. 1377 */ 1378 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1379 int i; 1380 1381 for (i = 1; i < MAX_NPORTS; i++) { 1382 struct rte_eth_dev *rest_eth_dev; 1383 char namei[RTE_ETH_NAME_MAX_LEN]; 1384 1385 snprintf(namei, sizeof(namei), "%s_%d", 1386 pci_dev->device.name, i); 1387 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1388 if (rest_eth_dev) { 1389 rest_eth_dev->device = &pci_dev->device; 1390 rest_eth_dev->dev_ops = 1391 eth_dev->dev_ops; 1392 rest_eth_dev->rx_pkt_burst = 1393 eth_dev->rx_pkt_burst; 1394 rest_eth_dev->tx_pkt_burst = 1395 eth_dev->tx_pkt_burst; 1396 rte_eth_dev_probing_finish(rest_eth_dev); 1397 } 1398 } 1399 return 0; 1400 } 1401 1402 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 1403 1404 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1405 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1406 if (!adapter) 1407 return -1; 1408 1409 adapter->use_unpacked_mode = 1; 1410 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1411 if (!adapter->regs) { 1412 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1413 err = -ENOMEM; 1414 goto out_free_adapter; 1415 } 1416 adapter->pdev = pci_dev; 1417 adapter->eth_dev = eth_dev; 1418 pi->adapter = adapter; 1419 1420 cxgbe_process_devargs(adapter); 1421 1422 err = cxgbe_probe(adapter); 1423 if (err) { 1424 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1425 __func__, err); 1426 goto out_free_adapter; 1427 } 1428 1429 return 0; 1430 1431 out_free_adapter: 1432 rte_free(adapter); 1433 return err; 1434 } 1435 1436 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1437 { 1438 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1439 uint16_t port_id; 1440 int err = 0; 1441 1442 /* Free up other ports and all resources */ 1443 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1444 err |= rte_eth_dev_close(port_id); 1445 1446 return err == 0 ? 0 : -EIO; 1447 } 1448 1449 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1450 struct rte_pci_device *pci_dev) 1451 { 1452 return rte_eth_dev_pci_generic_probe(pci_dev, 1453 sizeof(struct port_info), eth_cxgbe_dev_init); 1454 } 1455 1456 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1457 { 1458 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1459 } 1460 1461 static struct rte_pci_driver rte_cxgbe_pmd = { 1462 .id_table = cxgb4_pci_tbl, 1463 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1464 .probe = eth_cxgbe_pci_probe, 1465 .remove = eth_cxgbe_pci_remove, 1466 }; 1467 1468 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1469 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1470 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1471 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1472 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1473 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1474 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1475 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1476 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE); 1477 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE); 1478