1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 int cxgbe_logtype; 42 int cxgbe_mbox_logtype; 43 44 /* 45 * Macros needed to support the PCI Device ID Table ... 46 */ 47 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 48 static const struct rte_pci_id cxgb4_pci_tbl[] = { 49 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 50 51 #define PCI_VENDOR_ID_CHELSIO 0x1425 52 53 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 55 56 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 57 { .vendor_id = 0, } \ 58 } 59 60 /* 61 *... and the PCI ID Table itself ... 62 */ 63 #include "base/t4_pci_id_tbl.h" 64 65 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 66 uint16_t nb_pkts) 67 { 68 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 69 uint16_t pkts_sent, pkts_remain; 70 uint16_t total_sent = 0; 71 uint16_t idx = 0; 72 int ret = 0; 73 74 t4_os_lock(&txq->txq_lock); 75 /* free up desc from already completed tx */ 76 reclaim_completed_tx(&txq->q); 77 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 78 while (total_sent < nb_pkts) { 79 pkts_remain = nb_pkts - total_sent; 80 81 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 82 idx = total_sent + pkts_sent; 83 if ((idx + 1) < nb_pkts) 84 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 85 volatile void *)); 86 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 87 if (ret < 0) 88 break; 89 } 90 if (!pkts_sent) 91 break; 92 total_sent += pkts_sent; 93 /* reclaim as much as possible */ 94 reclaim_completed_tx(&txq->q); 95 } 96 97 t4_os_unlock(&txq->txq_lock); 98 return total_sent; 99 } 100 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 102 uint16_t nb_pkts) 103 { 104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 105 unsigned int work_done; 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 return work_done; 111 } 112 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 114 struct rte_eth_dev_info *device_info) 115 { 116 struct port_info *pi = eth_dev->data->dev_private; 117 struct adapter *adapter = pi->adapter; 118 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 119 120 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 121 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 122 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 123 .nb_align = 1, 124 }; 125 126 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 127 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 128 device_info->max_rx_queues = max_queues; 129 device_info->max_tx_queues = max_queues; 130 device_info->max_mac_addrs = 1; 131 /* XXX: For now we support one MAC/port */ 132 device_info->max_vfs = adapter->params.arch.vfcount; 133 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 134 135 device_info->rx_queue_offload_capa = 0UL; 136 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 137 138 device_info->tx_queue_offload_capa = 0UL; 139 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 140 141 device_info->reta_size = pi->rss_size; 142 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 143 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 144 145 device_info->rx_desc_lim = cxgbe_desc_lim; 146 device_info->tx_desc_lim = cxgbe_desc_lim; 147 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 148 149 return 0; 150 } 151 152 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 153 { 154 struct port_info *pi = eth_dev->data->dev_private; 155 struct adapter *adapter = pi->adapter; 156 157 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 158 1, -1, 1, -1, false); 159 } 160 161 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 162 { 163 struct port_info *pi = eth_dev->data->dev_private; 164 struct adapter *adapter = pi->adapter; 165 166 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 167 0, -1, 1, -1, false); 168 } 169 170 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 171 { 172 struct port_info *pi = eth_dev->data->dev_private; 173 struct adapter *adapter = pi->adapter; 174 175 /* TODO: address filters ?? */ 176 177 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 178 -1, 1, 1, -1, false); 179 } 180 181 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 182 { 183 struct port_info *pi = eth_dev->data->dev_private; 184 struct adapter *adapter = pi->adapter; 185 186 /* TODO: address filters ?? */ 187 188 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 189 -1, 0, 1, -1, false); 190 } 191 192 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 193 int wait_to_complete) 194 { 195 struct port_info *pi = eth_dev->data->dev_private; 196 struct adapter *adapter = pi->adapter; 197 struct sge *s = &adapter->sge; 198 struct rte_eth_link new_link = { 0 }; 199 unsigned int i, work_done, budget = 32; 200 u8 old_link = pi->link_cfg.link_ok; 201 202 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 203 if (!s->fw_evtq.desc) 204 break; 205 206 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 207 208 /* Exit if link status changed or always forced up */ 209 if (pi->link_cfg.link_ok != old_link || 210 cxgbe_force_linkup(adapter)) 211 break; 212 213 if (!wait_to_complete) 214 break; 215 216 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 217 } 218 219 new_link.link_status = cxgbe_force_linkup(adapter) ? 220 ETH_LINK_UP : pi->link_cfg.link_ok; 221 new_link.link_autoneg = pi->link_cfg.autoneg; 222 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 223 new_link.link_speed = pi->link_cfg.speed; 224 225 return rte_eth_linkstatus_set(eth_dev, &new_link); 226 } 227 228 /** 229 * Set device link up. 230 */ 231 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 232 { 233 struct port_info *pi = dev->data->dev_private; 234 struct adapter *adapter = pi->adapter; 235 unsigned int work_done, budget = 32; 236 struct sge *s = &adapter->sge; 237 int ret; 238 239 if (!s->fw_evtq.desc) 240 return -ENOMEM; 241 242 /* Flush all link events */ 243 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 244 245 /* If link already up, nothing to do */ 246 if (pi->link_cfg.link_ok) 247 return 0; 248 249 ret = cxgbe_set_link_status(pi, true); 250 if (ret) 251 return ret; 252 253 cxgbe_dev_link_update(dev, 1); 254 return 0; 255 } 256 257 /** 258 * Set device link down. 259 */ 260 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 261 { 262 struct port_info *pi = dev->data->dev_private; 263 struct adapter *adapter = pi->adapter; 264 unsigned int work_done, budget = 32; 265 struct sge *s = &adapter->sge; 266 int ret; 267 268 if (!s->fw_evtq.desc) 269 return -ENOMEM; 270 271 /* Flush all link events */ 272 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 273 274 /* If link already down, nothing to do */ 275 if (!pi->link_cfg.link_ok) 276 return 0; 277 278 ret = cxgbe_set_link_status(pi, false); 279 if (ret) 280 return ret; 281 282 cxgbe_dev_link_update(dev, 0); 283 return 0; 284 } 285 286 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 287 { 288 struct port_info *pi = eth_dev->data->dev_private; 289 struct adapter *adapter = pi->adapter; 290 struct rte_eth_dev_info dev_info; 291 int err; 292 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 293 294 err = cxgbe_dev_info_get(eth_dev, &dev_info); 295 if (err != 0) 296 return err; 297 298 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 299 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 300 return -EINVAL; 301 302 /* set to jumbo mode if needed */ 303 if (new_mtu > RTE_ETHER_MAX_LEN) 304 eth_dev->data->dev_conf.rxmode.offloads |= 305 DEV_RX_OFFLOAD_JUMBO_FRAME; 306 else 307 eth_dev->data->dev_conf.rxmode.offloads &= 308 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 309 310 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 311 -1, -1, true); 312 if (!err) 313 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 314 315 return err; 316 } 317 318 /* 319 * Stop device. 320 */ 321 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 322 { 323 struct port_info *pi = eth_dev->data->dev_private; 324 struct adapter *adapter = pi->adapter; 325 326 CXGBE_FUNC_TRACE(); 327 328 if (!(adapter->flags & FULL_INIT_DONE)) 329 return; 330 331 cxgbe_down(pi); 332 333 /* 334 * We clear queues only if both tx and rx path of the port 335 * have been disabled 336 */ 337 t4_sge_eth_clear_queues(pi); 338 } 339 340 /* Start the device. 341 * It returns 0 on success. 342 */ 343 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 344 { 345 struct port_info *pi = eth_dev->data->dev_private; 346 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 347 struct adapter *adapter = pi->adapter; 348 int err = 0, i; 349 350 CXGBE_FUNC_TRACE(); 351 352 /* 353 * If we don't have a connection to the firmware there's nothing we 354 * can do. 355 */ 356 if (!(adapter->flags & FW_OK)) { 357 err = -ENXIO; 358 goto out; 359 } 360 361 if (!(adapter->flags & FULL_INIT_DONE)) { 362 err = cxgbe_up(adapter); 363 if (err < 0) 364 goto out; 365 } 366 367 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 368 eth_dev->data->scattered_rx = 1; 369 else 370 eth_dev->data->scattered_rx = 0; 371 372 cxgbe_enable_rx_queues(pi); 373 374 err = cxgbe_setup_rss(pi); 375 if (err) 376 goto out; 377 378 for (i = 0; i < pi->n_tx_qsets; i++) { 379 err = cxgbe_dev_tx_queue_start(eth_dev, i); 380 if (err) 381 goto out; 382 } 383 384 for (i = 0; i < pi->n_rx_qsets; i++) { 385 err = cxgbe_dev_rx_queue_start(eth_dev, i); 386 if (err) 387 goto out; 388 } 389 390 err = cxgbe_link_start(pi); 391 if (err) 392 goto out; 393 394 out: 395 return err; 396 } 397 398 /* 399 * Stop device: disable rx and tx functions to allow for reconfiguring. 400 */ 401 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 402 { 403 struct port_info *pi = eth_dev->data->dev_private; 404 struct adapter *adapter = pi->adapter; 405 406 CXGBE_FUNC_TRACE(); 407 408 if (!(adapter->flags & FULL_INIT_DONE)) 409 return; 410 411 cxgbe_down(pi); 412 413 /* 414 * We clear queues only if both tx and rx path of the port 415 * have been disabled 416 */ 417 t4_sge_eth_clear_queues(pi); 418 eth_dev->data->scattered_rx = 0; 419 } 420 421 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 422 { 423 struct port_info *pi = eth_dev->data->dev_private; 424 struct adapter *adapter = pi->adapter; 425 int err; 426 427 CXGBE_FUNC_TRACE(); 428 429 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 430 eth_dev->data->dev_conf.rxmode.offloads |= 431 DEV_RX_OFFLOAD_RSS_HASH; 432 433 if (!(adapter->flags & FW_QUEUE_BOUND)) { 434 err = cxgbe_setup_sge_fwevtq(adapter); 435 if (err) 436 return err; 437 adapter->flags |= FW_QUEUE_BOUND; 438 if (is_pf4(adapter)) { 439 err = cxgbe_setup_sge_ctrl_txq(adapter); 440 if (err) 441 return err; 442 } 443 } 444 445 err = cxgbe_cfg_queue_count(eth_dev); 446 if (err) 447 return err; 448 449 return 0; 450 } 451 452 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 453 { 454 int ret; 455 struct sge_eth_txq *txq = (struct sge_eth_txq *) 456 (eth_dev->data->tx_queues[tx_queue_id]); 457 458 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 459 460 ret = t4_sge_eth_txq_start(txq); 461 if (ret == 0) 462 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 463 464 return ret; 465 } 466 467 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 468 { 469 int ret; 470 struct sge_eth_txq *txq = (struct sge_eth_txq *) 471 (eth_dev->data->tx_queues[tx_queue_id]); 472 473 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 474 475 ret = t4_sge_eth_txq_stop(txq); 476 if (ret == 0) 477 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 478 479 return ret; 480 } 481 482 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 483 uint16_t queue_idx, uint16_t nb_desc, 484 unsigned int socket_id, 485 const struct rte_eth_txconf *tx_conf __rte_unused) 486 { 487 struct port_info *pi = eth_dev->data->dev_private; 488 struct adapter *adapter = pi->adapter; 489 struct sge *s = &adapter->sge; 490 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 491 int err = 0; 492 unsigned int temp_nb_desc; 493 494 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 495 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 496 socket_id, pi->first_qset); 497 498 /* Free up the existing queue */ 499 if (eth_dev->data->tx_queues[queue_idx]) { 500 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 501 eth_dev->data->tx_queues[queue_idx] = NULL; 502 } 503 504 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 505 506 /* Sanity Checking 507 * 508 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 509 */ 510 temp_nb_desc = nb_desc; 511 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 512 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 513 __func__, CXGBE_MIN_RING_DESC_SIZE, 514 CXGBE_DEFAULT_TX_DESC_SIZE); 515 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 516 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 517 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 518 __func__, CXGBE_MIN_RING_DESC_SIZE, 519 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 520 return -(EINVAL); 521 } 522 523 txq->q.size = temp_nb_desc; 524 525 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 526 s->fw_evtq.cntxt_id, socket_id); 527 528 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 529 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 530 return err; 531 } 532 533 void cxgbe_dev_tx_queue_release(void *q) 534 { 535 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 536 537 if (txq) { 538 struct port_info *pi = (struct port_info *) 539 (txq->eth_dev->data->dev_private); 540 struct adapter *adap = pi->adapter; 541 542 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 543 __func__, pi->port_id, txq->q.cntxt_id); 544 545 t4_sge_eth_txq_release(adap, txq); 546 } 547 } 548 549 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 550 { 551 int ret; 552 struct port_info *pi = eth_dev->data->dev_private; 553 struct adapter *adap = pi->adapter; 554 struct sge_rspq *q; 555 556 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 557 __func__, pi->port_id, rx_queue_id); 558 559 q = eth_dev->data->rx_queues[rx_queue_id]; 560 561 ret = t4_sge_eth_rxq_start(adap, q); 562 if (ret == 0) 563 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 564 565 return ret; 566 } 567 568 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 569 { 570 int ret; 571 struct port_info *pi = eth_dev->data->dev_private; 572 struct adapter *adap = pi->adapter; 573 struct sge_rspq *q; 574 575 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 576 __func__, pi->port_id, rx_queue_id); 577 578 q = eth_dev->data->rx_queues[rx_queue_id]; 579 ret = t4_sge_eth_rxq_stop(adap, q); 580 if (ret == 0) 581 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 582 583 return ret; 584 } 585 586 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 587 uint16_t queue_idx, uint16_t nb_desc, 588 unsigned int socket_id, 589 const struct rte_eth_rxconf *rx_conf __rte_unused, 590 struct rte_mempool *mp) 591 { 592 struct port_info *pi = eth_dev->data->dev_private; 593 struct adapter *adapter = pi->adapter; 594 struct sge *s = &adapter->sge; 595 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 596 int err = 0; 597 int msi_idx = 0; 598 unsigned int temp_nb_desc; 599 struct rte_eth_dev_info dev_info; 600 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 601 602 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 603 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 604 socket_id, mp); 605 606 err = cxgbe_dev_info_get(eth_dev, &dev_info); 607 if (err != 0) { 608 dev_err(adap, "%s: error during getting ethernet device info", 609 __func__); 610 return err; 611 } 612 613 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 614 if ((pkt_len < dev_info.min_rx_bufsize) || 615 (pkt_len > dev_info.max_rx_pktlen)) { 616 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 617 __func__, dev_info.min_rx_bufsize, 618 dev_info.max_rx_pktlen); 619 return -EINVAL; 620 } 621 622 /* Free up the existing queue */ 623 if (eth_dev->data->rx_queues[queue_idx]) { 624 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 625 eth_dev->data->rx_queues[queue_idx] = NULL; 626 } 627 628 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 629 630 /* Sanity Checking 631 * 632 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 633 */ 634 temp_nb_desc = nb_desc; 635 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 636 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 637 __func__, CXGBE_MIN_RING_DESC_SIZE, 638 CXGBE_DEFAULT_RX_DESC_SIZE); 639 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 640 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 641 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 642 __func__, CXGBE_MIN_RING_DESC_SIZE, 643 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 644 return -(EINVAL); 645 } 646 647 rxq->rspq.size = temp_nb_desc; 648 if ((&rxq->fl) != NULL) 649 rxq->fl.size = temp_nb_desc; 650 651 /* Set to jumbo mode if necessary */ 652 if (pkt_len > RTE_ETHER_MAX_LEN) 653 eth_dev->data->dev_conf.rxmode.offloads |= 654 DEV_RX_OFFLOAD_JUMBO_FRAME; 655 else 656 eth_dev->data->dev_conf.rxmode.offloads &= 657 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 658 659 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 660 &rxq->fl, NULL, 661 is_pf4(adapter) ? 662 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 663 queue_idx, socket_id); 664 665 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 666 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 667 rxq->rspq.abs_id); 668 return err; 669 } 670 671 void cxgbe_dev_rx_queue_release(void *q) 672 { 673 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 674 struct sge_rspq *rq = &rxq->rspq; 675 676 if (rq) { 677 struct port_info *pi = (struct port_info *) 678 (rq->eth_dev->data->dev_private); 679 struct adapter *adap = pi->adapter; 680 681 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 682 __func__, pi->port_id, rxq->rspq.cntxt_id); 683 684 t4_sge_eth_rxq_release(adap, rxq); 685 } 686 } 687 688 /* 689 * Get port statistics. 690 */ 691 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 692 struct rte_eth_stats *eth_stats) 693 { 694 struct port_info *pi = eth_dev->data->dev_private; 695 struct adapter *adapter = pi->adapter; 696 struct sge *s = &adapter->sge; 697 struct port_stats ps; 698 unsigned int i; 699 700 cxgbe_stats_get(pi, &ps); 701 702 /* RX Stats */ 703 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 704 ps.rx_ovflow2 + ps.rx_ovflow3 + 705 ps.rx_trunc0 + ps.rx_trunc1 + 706 ps.rx_trunc2 + ps.rx_trunc3; 707 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 708 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 709 ps.rx_len_err; 710 711 /* TX Stats */ 712 eth_stats->opackets = ps.tx_frames; 713 eth_stats->obytes = ps.tx_octets; 714 eth_stats->oerrors = ps.tx_error_frames; 715 716 for (i = 0; i < pi->n_rx_qsets; i++) { 717 struct sge_eth_rxq *rxq = 718 &s->ethrxq[pi->first_qset + i]; 719 720 eth_stats->q_ipackets[i] = rxq->stats.pkts; 721 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 722 eth_stats->ipackets += eth_stats->q_ipackets[i]; 723 eth_stats->ibytes += eth_stats->q_ibytes[i]; 724 } 725 726 for (i = 0; i < pi->n_tx_qsets; i++) { 727 struct sge_eth_txq *txq = 728 &s->ethtxq[pi->first_qset + i]; 729 730 eth_stats->q_opackets[i] = txq->stats.pkts; 731 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 732 } 733 return 0; 734 } 735 736 /* 737 * Reset port statistics. 738 */ 739 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 740 { 741 struct port_info *pi = eth_dev->data->dev_private; 742 struct adapter *adapter = pi->adapter; 743 struct sge *s = &adapter->sge; 744 unsigned int i; 745 746 cxgbe_stats_reset(pi); 747 for (i = 0; i < pi->n_rx_qsets; i++) { 748 struct sge_eth_rxq *rxq = 749 &s->ethrxq[pi->first_qset + i]; 750 751 rxq->stats.pkts = 0; 752 rxq->stats.rx_bytes = 0; 753 } 754 for (i = 0; i < pi->n_tx_qsets; i++) { 755 struct sge_eth_txq *txq = 756 &s->ethtxq[pi->first_qset + i]; 757 758 txq->stats.pkts = 0; 759 txq->stats.tx_bytes = 0; 760 txq->stats.mapping_err = 0; 761 } 762 763 return 0; 764 } 765 766 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 767 struct rte_eth_fc_conf *fc_conf) 768 { 769 struct port_info *pi = eth_dev->data->dev_private; 770 struct link_config *lc = &pi->link_cfg; 771 int rx_pause, tx_pause; 772 773 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 774 rx_pause = lc->fc & PAUSE_RX; 775 tx_pause = lc->fc & PAUSE_TX; 776 777 if (rx_pause && tx_pause) 778 fc_conf->mode = RTE_FC_FULL; 779 else if (rx_pause) 780 fc_conf->mode = RTE_FC_RX_PAUSE; 781 else if (tx_pause) 782 fc_conf->mode = RTE_FC_TX_PAUSE; 783 else 784 fc_conf->mode = RTE_FC_NONE; 785 return 0; 786 } 787 788 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 789 struct rte_eth_fc_conf *fc_conf) 790 { 791 struct port_info *pi = eth_dev->data->dev_private; 792 struct adapter *adapter = pi->adapter; 793 struct link_config *lc = &pi->link_cfg; 794 795 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 796 if (fc_conf->autoneg) 797 lc->requested_fc |= PAUSE_AUTONEG; 798 else 799 lc->requested_fc &= ~PAUSE_AUTONEG; 800 } 801 802 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 803 (fc_conf->mode & RTE_FC_RX_PAUSE)) 804 lc->requested_fc |= PAUSE_RX; 805 else 806 lc->requested_fc &= ~PAUSE_RX; 807 808 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 809 (fc_conf->mode & RTE_FC_TX_PAUSE)) 810 lc->requested_fc |= PAUSE_TX; 811 else 812 lc->requested_fc &= ~PAUSE_TX; 813 814 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 815 &pi->link_cfg); 816 } 817 818 const uint32_t * 819 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 820 { 821 static const uint32_t ptypes[] = { 822 RTE_PTYPE_L3_IPV4, 823 RTE_PTYPE_L3_IPV6, 824 RTE_PTYPE_UNKNOWN 825 }; 826 827 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 828 return ptypes; 829 return NULL; 830 } 831 832 /* Update RSS hash configuration 833 */ 834 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 835 struct rte_eth_rss_conf *rss_conf) 836 { 837 struct port_info *pi = dev->data->dev_private; 838 struct adapter *adapter = pi->adapter; 839 int err; 840 841 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 842 if (err) 843 return err; 844 845 pi->rss_hf = rss_conf->rss_hf; 846 847 if (rss_conf->rss_key) { 848 u32 key[10], mod_key[10]; 849 int i, j; 850 851 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 852 853 for (i = 9, j = 0; i >= 0; i--, j++) 854 mod_key[j] = cpu_to_be32(key[i]); 855 856 t4_write_rss_key(adapter, mod_key, -1); 857 } 858 859 return 0; 860 } 861 862 /* Get RSS hash configuration 863 */ 864 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 865 struct rte_eth_rss_conf *rss_conf) 866 { 867 struct port_info *pi = dev->data->dev_private; 868 struct adapter *adapter = pi->adapter; 869 u64 rss_hf = 0; 870 u64 flags = 0; 871 int err; 872 873 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 874 &flags, NULL); 875 876 if (err) 877 return err; 878 879 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 880 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 881 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 882 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 883 } 884 885 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 886 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 887 888 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 889 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 890 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 891 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 892 } 893 894 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 895 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 896 897 rss_conf->rss_hf = rss_hf; 898 899 if (rss_conf->rss_key) { 900 u32 key[10], mod_key[10]; 901 int i, j; 902 903 t4_read_rss_key(adapter, key); 904 905 for (i = 9, j = 0; i >= 0; i--, j++) 906 mod_key[j] = be32_to_cpu(key[i]); 907 908 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 909 } 910 911 return 0; 912 } 913 914 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 915 { 916 RTE_SET_USED(dev); 917 return EEPROMSIZE; 918 } 919 920 /** 921 * eeprom_ptov - translate a physical EEPROM address to virtual 922 * @phys_addr: the physical EEPROM address 923 * @fn: the PCI function number 924 * @sz: size of function-specific area 925 * 926 * Translate a physical EEPROM address to virtual. The first 1K is 927 * accessed through virtual addresses starting at 31K, the rest is 928 * accessed through virtual addresses starting at 0. 929 * 930 * The mapping is as follows: 931 * [0..1K) -> [31K..32K) 932 * [1K..1K+A) -> [31K-A..31K) 933 * [1K+A..ES) -> [0..ES-A-1K) 934 * 935 * where A = @fn * @sz, and ES = EEPROM size. 936 */ 937 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 938 { 939 fn *= sz; 940 if (phys_addr < 1024) 941 return phys_addr + (31 << 10); 942 if (phys_addr < 1024 + fn) 943 return fn + phys_addr - 1024; 944 if (phys_addr < EEPROMSIZE) 945 return phys_addr - 1024 - fn; 946 if (phys_addr < EEPROMVSIZE) 947 return phys_addr - 1024; 948 return -EINVAL; 949 } 950 951 /* The next two routines implement eeprom read/write from physical addresses. 952 */ 953 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 954 { 955 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 956 957 if (vaddr >= 0) 958 vaddr = t4_seeprom_read(adap, vaddr, v); 959 return vaddr < 0 ? vaddr : 0; 960 } 961 962 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 963 { 964 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 965 966 if (vaddr >= 0) 967 vaddr = t4_seeprom_write(adap, vaddr, v); 968 return vaddr < 0 ? vaddr : 0; 969 } 970 971 #define EEPROM_MAGIC 0x38E2F10C 972 973 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 974 struct rte_dev_eeprom_info *e) 975 { 976 struct port_info *pi = dev->data->dev_private; 977 struct adapter *adapter = pi->adapter; 978 u32 i, err = 0; 979 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 980 981 if (!buf) 982 return -ENOMEM; 983 984 e->magic = EEPROM_MAGIC; 985 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 986 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 987 988 if (!err) 989 rte_memcpy(e->data, buf + e->offset, e->length); 990 rte_free(buf); 991 return err; 992 } 993 994 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 995 struct rte_dev_eeprom_info *eeprom) 996 { 997 struct port_info *pi = dev->data->dev_private; 998 struct adapter *adapter = pi->adapter; 999 u8 *buf; 1000 int err = 0; 1001 u32 aligned_offset, aligned_len, *p; 1002 1003 if (eeprom->magic != EEPROM_MAGIC) 1004 return -EINVAL; 1005 1006 aligned_offset = eeprom->offset & ~3; 1007 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1008 1009 if (adapter->pf > 0) { 1010 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1011 1012 if (aligned_offset < start || 1013 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1014 return -EPERM; 1015 } 1016 1017 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1018 /* RMW possibly needed for first or last words. 1019 */ 1020 buf = rte_zmalloc(NULL, aligned_len, 0); 1021 if (!buf) 1022 return -ENOMEM; 1023 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1024 if (!err && aligned_len > 4) 1025 err = eeprom_rd_phys(adapter, 1026 aligned_offset + aligned_len - 4, 1027 (u32 *)&buf[aligned_len - 4]); 1028 if (err) 1029 goto out; 1030 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1031 eeprom->length); 1032 } else { 1033 buf = eeprom->data; 1034 } 1035 1036 err = t4_seeprom_wp(adapter, false); 1037 if (err) 1038 goto out; 1039 1040 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1041 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1042 aligned_offset += 4; 1043 } 1044 1045 if (!err) 1046 err = t4_seeprom_wp(adapter, true); 1047 out: 1048 if (buf != eeprom->data) 1049 rte_free(buf); 1050 return err; 1051 } 1052 1053 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1054 { 1055 struct port_info *pi = eth_dev->data->dev_private; 1056 struct adapter *adapter = pi->adapter; 1057 1058 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1059 } 1060 1061 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1062 struct rte_dev_reg_info *regs) 1063 { 1064 struct port_info *pi = eth_dev->data->dev_private; 1065 struct adapter *adapter = pi->adapter; 1066 1067 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1068 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1069 (1 << 16); 1070 1071 if (regs->data == NULL) { 1072 regs->length = cxgbe_get_regs_len(eth_dev); 1073 regs->width = sizeof(uint32_t); 1074 1075 return 0; 1076 } 1077 1078 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1079 1080 return 0; 1081 } 1082 1083 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1084 { 1085 struct port_info *pi = dev->data->dev_private; 1086 int ret; 1087 1088 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1089 if (ret < 0) { 1090 dev_err(adapter, "failed to set mac addr; err = %d\n", 1091 ret); 1092 return ret; 1093 } 1094 pi->xact_addr_filt = ret; 1095 return 0; 1096 } 1097 1098 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1099 .dev_start = cxgbe_dev_start, 1100 .dev_stop = cxgbe_dev_stop, 1101 .dev_close = cxgbe_dev_close, 1102 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1103 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1104 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1105 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1106 .dev_configure = cxgbe_dev_configure, 1107 .dev_infos_get = cxgbe_dev_info_get, 1108 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1109 .link_update = cxgbe_dev_link_update, 1110 .dev_set_link_up = cxgbe_dev_set_link_up, 1111 .dev_set_link_down = cxgbe_dev_set_link_down, 1112 .mtu_set = cxgbe_dev_mtu_set, 1113 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1114 .tx_queue_start = cxgbe_dev_tx_queue_start, 1115 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1116 .tx_queue_release = cxgbe_dev_tx_queue_release, 1117 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1118 .rx_queue_start = cxgbe_dev_rx_queue_start, 1119 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1120 .rx_queue_release = cxgbe_dev_rx_queue_release, 1121 .filter_ctrl = cxgbe_dev_filter_ctrl, 1122 .stats_get = cxgbe_dev_stats_get, 1123 .stats_reset = cxgbe_dev_stats_reset, 1124 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1125 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1126 .get_eeprom_length = cxgbe_get_eeprom_length, 1127 .get_eeprom = cxgbe_get_eeprom, 1128 .set_eeprom = cxgbe_set_eeprom, 1129 .get_reg = cxgbe_get_regs, 1130 .rss_hash_update = cxgbe_dev_rss_hash_update, 1131 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1132 .mac_addr_set = cxgbe_mac_addr_set, 1133 }; 1134 1135 /* 1136 * Initialize driver 1137 * It returns 0 on success. 1138 */ 1139 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1140 { 1141 struct rte_pci_device *pci_dev; 1142 struct port_info *pi = eth_dev->data->dev_private; 1143 struct adapter *adapter = NULL; 1144 char name[RTE_ETH_NAME_MAX_LEN]; 1145 int err = 0; 1146 1147 CXGBE_FUNC_TRACE(); 1148 1149 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1150 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1151 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1152 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1153 1154 /* for secondary processes, we attach to ethdevs allocated by primary 1155 * and do minimal initialization. 1156 */ 1157 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1158 int i; 1159 1160 for (i = 1; i < MAX_NPORTS; i++) { 1161 struct rte_eth_dev *rest_eth_dev; 1162 char namei[RTE_ETH_NAME_MAX_LEN]; 1163 1164 snprintf(namei, sizeof(namei), "%s_%d", 1165 pci_dev->device.name, i); 1166 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1167 if (rest_eth_dev) { 1168 rest_eth_dev->device = &pci_dev->device; 1169 rest_eth_dev->dev_ops = 1170 eth_dev->dev_ops; 1171 rest_eth_dev->rx_pkt_burst = 1172 eth_dev->rx_pkt_burst; 1173 rest_eth_dev->tx_pkt_burst = 1174 eth_dev->tx_pkt_burst; 1175 rte_eth_dev_probing_finish(rest_eth_dev); 1176 } 1177 } 1178 return 0; 1179 } 1180 1181 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1182 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1183 if (!adapter) 1184 return -1; 1185 1186 adapter->use_unpacked_mode = 1; 1187 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1188 if (!adapter->regs) { 1189 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1190 err = -ENOMEM; 1191 goto out_free_adapter; 1192 } 1193 adapter->pdev = pci_dev; 1194 adapter->eth_dev = eth_dev; 1195 pi->adapter = adapter; 1196 1197 cxgbe_process_devargs(adapter); 1198 1199 err = cxgbe_probe(adapter); 1200 if (err) { 1201 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1202 __func__, err); 1203 goto out_free_adapter; 1204 } 1205 1206 return 0; 1207 1208 out_free_adapter: 1209 rte_free(adapter); 1210 return err; 1211 } 1212 1213 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1214 { 1215 struct port_info *pi = eth_dev->data->dev_private; 1216 struct adapter *adap = pi->adapter; 1217 1218 /* Free up other ports and all resources */ 1219 cxgbe_close(adap); 1220 return 0; 1221 } 1222 1223 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1224 struct rte_pci_device *pci_dev) 1225 { 1226 return rte_eth_dev_pci_generic_probe(pci_dev, 1227 sizeof(struct port_info), eth_cxgbe_dev_init); 1228 } 1229 1230 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1231 { 1232 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1233 } 1234 1235 static struct rte_pci_driver rte_cxgbe_pmd = { 1236 .id_table = cxgb4_pci_tbl, 1237 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1238 .probe = eth_cxgbe_pci_probe, 1239 .remove = eth_cxgbe_pci_remove, 1240 }; 1241 1242 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1243 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1244 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1245 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1246 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1247 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1248 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1249 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1250 1251 RTE_INIT(cxgbe_init_log) 1252 { 1253 cxgbe_logtype = rte_log_register("pmd.net.cxgbe"); 1254 if (cxgbe_logtype >= 0) 1255 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE); 1256 cxgbe_mbox_logtype = rte_log_register("pmd.net.cxgbe.mbox"); 1257 if (cxgbe_mbox_logtype >= 0) 1258 rte_log_set_level(cxgbe_mbox_logtype, RTE_LOG_NOTICE); 1259 } 1260