1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2017 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 44 #include <rte_byteorder.h> 45 #include <rte_common.h> 46 #include <rte_cycles.h> 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_tailq.h> 56 #include <rte_eal.h> 57 #include <rte_alarm.h> 58 #include <rte_ether.h> 59 #include <rte_ethdev.h> 60 #include <rte_ethdev_pci.h> 61 #include <rte_malloc.h> 62 #include <rte_random.h> 63 #include <rte_dev.h> 64 65 #include "cxgbe.h" 66 67 /* 68 * Macros needed to support the PCI Device ID Table ... 69 */ 70 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 71 static const struct rte_pci_id cxgb4_pci_tbl[] = { 72 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 73 74 #define PCI_VENDOR_ID_CHELSIO 0x1425 75 76 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 78 79 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 80 { .vendor_id = 0, } \ 81 } 82 83 /* 84 *... and the PCI ID Table itself ... 85 */ 86 #include "t4_pci_id_tbl.h" 87 88 static uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 89 uint16_t nb_pkts) 90 { 91 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 92 uint16_t pkts_sent, pkts_remain; 93 uint16_t total_sent = 0; 94 int ret = 0; 95 96 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 97 __func__, txq, tx_pkts, nb_pkts); 98 99 t4_os_lock(&txq->txq_lock); 100 /* free up desc from already completed tx */ 101 reclaim_completed_tx(&txq->q); 102 while (total_sent < nb_pkts) { 103 pkts_remain = nb_pkts - total_sent; 104 105 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 106 ret = t4_eth_xmit(txq, tx_pkts[total_sent + pkts_sent], 107 nb_pkts); 108 if (ret < 0) 109 break; 110 } 111 if (!pkts_sent) 112 break; 113 total_sent += pkts_sent; 114 /* reclaim as much as possible */ 115 reclaim_completed_tx(&txq->q); 116 } 117 118 t4_os_unlock(&txq->txq_lock); 119 return total_sent; 120 } 121 122 static uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 123 uint16_t nb_pkts) 124 { 125 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 126 unsigned int work_done; 127 128 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 129 __func__, rxq->rspq.cntxt_id, nb_pkts); 130 131 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 132 dev_err(adapter, "error in cxgbe poll\n"); 133 134 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 135 return work_done; 136 } 137 138 static void cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 139 struct rte_eth_dev_info *device_info) 140 { 141 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 142 struct adapter *adapter = pi->adapter; 143 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 144 145 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 146 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 147 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 148 .nb_align = 1, 149 }; 150 151 device_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 152 153 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 154 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 155 device_info->max_rx_queues = max_queues; 156 device_info->max_tx_queues = max_queues; 157 device_info->max_mac_addrs = 1; 158 /* XXX: For now we support one MAC/port */ 159 device_info->max_vfs = adapter->params.arch.vfcount; 160 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 161 162 device_info->rx_offload_capa = DEV_RX_OFFLOAD_VLAN_STRIP | 163 DEV_RX_OFFLOAD_IPV4_CKSUM | 164 DEV_RX_OFFLOAD_UDP_CKSUM | 165 DEV_RX_OFFLOAD_TCP_CKSUM; 166 167 device_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 168 DEV_TX_OFFLOAD_IPV4_CKSUM | 169 DEV_TX_OFFLOAD_UDP_CKSUM | 170 DEV_TX_OFFLOAD_TCP_CKSUM | 171 DEV_TX_OFFLOAD_TCP_TSO; 172 173 device_info->reta_size = pi->rss_size; 174 175 device_info->rx_desc_lim = cxgbe_desc_lim; 176 device_info->tx_desc_lim = cxgbe_desc_lim; 177 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 178 } 179 180 static void cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 181 { 182 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 183 struct adapter *adapter = pi->adapter; 184 185 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 186 1, -1, 1, -1, false); 187 } 188 189 static void cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 190 { 191 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 192 struct adapter *adapter = pi->adapter; 193 194 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 195 0, -1, 1, -1, false); 196 } 197 198 static void cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 199 { 200 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 201 struct adapter *adapter = pi->adapter; 202 203 /* TODO: address filters ?? */ 204 205 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 206 -1, 1, 1, -1, false); 207 } 208 209 static void cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 210 { 211 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 212 struct adapter *adapter = pi->adapter; 213 214 /* TODO: address filters ?? */ 215 216 t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 217 -1, 0, 1, -1, false); 218 } 219 220 static int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 221 __rte_unused int wait_to_complete) 222 { 223 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 224 struct adapter *adapter = pi->adapter; 225 struct sge *s = &adapter->sge; 226 struct rte_eth_link *old_link = ð_dev->data->dev_link; 227 unsigned int work_done, budget = 4; 228 229 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 230 if (old_link->link_status == pi->link_cfg.link_ok) 231 return -1; /* link not changed */ 232 233 eth_dev->data->dev_link.link_status = pi->link_cfg.link_ok; 234 eth_dev->data->dev_link.link_duplex = ETH_LINK_FULL_DUPLEX; 235 eth_dev->data->dev_link.link_speed = pi->link_cfg.speed; 236 237 /* link has changed */ 238 return 0; 239 } 240 241 static int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 242 { 243 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 244 struct adapter *adapter = pi->adapter; 245 struct rte_eth_dev_info dev_info; 246 int err; 247 uint16_t new_mtu = mtu + ETHER_HDR_LEN + ETHER_CRC_LEN; 248 249 cxgbe_dev_info_get(eth_dev, &dev_info); 250 251 /* Must accommodate at least ETHER_MIN_MTU */ 252 if ((new_mtu < ETHER_MIN_MTU) || (new_mtu > dev_info.max_rx_pktlen)) 253 return -EINVAL; 254 255 /* set to jumbo mode if needed */ 256 if (new_mtu > ETHER_MAX_LEN) 257 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; 258 else 259 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; 260 261 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 262 -1, -1, true); 263 if (!err) 264 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 265 266 return err; 267 } 268 269 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 270 uint16_t tx_queue_id); 271 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 272 uint16_t tx_queue_id); 273 static void cxgbe_dev_tx_queue_release(void *q); 274 static void cxgbe_dev_rx_queue_release(void *q); 275 276 /* 277 * Stop device. 278 */ 279 static void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 280 { 281 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 282 struct adapter *adapter = pi->adapter; 283 int i, dev_down = 0; 284 285 CXGBE_FUNC_TRACE(); 286 287 if (!(adapter->flags & FULL_INIT_DONE)) 288 return; 289 290 cxgbe_down(pi); 291 292 /* 293 * We clear queues only if both tx and rx path of the port 294 * have been disabled 295 */ 296 t4_sge_eth_clear_queues(pi); 297 298 /* See if all ports are down */ 299 for_each_port(adapter, i) { 300 pi = adap2pinfo(adapter, i); 301 /* 302 * Skip first port of the adapter since it will be closed 303 * by DPDK 304 */ 305 if (i == 0) 306 continue; 307 dev_down += (pi->eth_dev->data->dev_started == 0) ? 1 : 0; 308 } 309 310 /* If rest of the ports are stopped, then free up resources */ 311 if (dev_down == (adapter->params.nports - 1)) 312 cxgbe_close(adapter); 313 } 314 315 /* Start the device. 316 * It returns 0 on success. 317 */ 318 static int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 319 { 320 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 321 struct adapter *adapter = pi->adapter; 322 int err = 0, i; 323 324 CXGBE_FUNC_TRACE(); 325 326 /* 327 * If we don't have a connection to the firmware there's nothing we 328 * can do. 329 */ 330 if (!(adapter->flags & FW_OK)) { 331 err = -ENXIO; 332 goto out; 333 } 334 335 if (!(adapter->flags & FULL_INIT_DONE)) { 336 err = cxgbe_up(adapter); 337 if (err < 0) 338 goto out; 339 } 340 341 cxgbe_enable_rx_queues(pi); 342 343 err = setup_rss(pi); 344 if (err) 345 goto out; 346 347 for (i = 0; i < pi->n_tx_qsets; i++) { 348 err = cxgbe_dev_tx_queue_start(eth_dev, i); 349 if (err) 350 goto out; 351 } 352 353 for (i = 0; i < pi->n_rx_qsets; i++) { 354 err = cxgbe_dev_rx_queue_start(eth_dev, i); 355 if (err) 356 goto out; 357 } 358 359 err = link_start(pi); 360 if (err) 361 goto out; 362 363 out: 364 return err; 365 } 366 367 /* 368 * Stop device: disable rx and tx functions to allow for reconfiguring. 369 */ 370 static void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 371 { 372 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 373 struct adapter *adapter = pi->adapter; 374 375 CXGBE_FUNC_TRACE(); 376 377 if (!(adapter->flags & FULL_INIT_DONE)) 378 return; 379 380 cxgbe_down(pi); 381 382 /* 383 * We clear queues only if both tx and rx path of the port 384 * have been disabled 385 */ 386 t4_sge_eth_clear_queues(pi); 387 } 388 389 static int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 390 { 391 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 392 struct adapter *adapter = pi->adapter; 393 int err; 394 395 CXGBE_FUNC_TRACE(); 396 397 if (!(adapter->flags & FW_QUEUE_BOUND)) { 398 err = setup_sge_fwevtq(adapter); 399 if (err) 400 return err; 401 adapter->flags |= FW_QUEUE_BOUND; 402 } 403 404 err = cfg_queue_count(eth_dev); 405 if (err) 406 return err; 407 408 return 0; 409 } 410 411 static int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, 412 uint16_t tx_queue_id) 413 { 414 int ret; 415 struct sge_eth_txq *txq = (struct sge_eth_txq *) 416 (eth_dev->data->tx_queues[tx_queue_id]); 417 418 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 419 420 ret = t4_sge_eth_txq_start(txq); 421 if (ret == 0) 422 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 423 424 return ret; 425 } 426 427 static int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, 428 uint16_t tx_queue_id) 429 { 430 int ret; 431 struct sge_eth_txq *txq = (struct sge_eth_txq *) 432 (eth_dev->data->tx_queues[tx_queue_id]); 433 434 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 435 436 ret = t4_sge_eth_txq_stop(txq); 437 if (ret == 0) 438 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 439 440 return ret; 441 } 442 443 static int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 444 uint16_t queue_idx, uint16_t nb_desc, 445 unsigned int socket_id, 446 const struct rte_eth_txconf *tx_conf) 447 { 448 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 449 struct adapter *adapter = pi->adapter; 450 struct sge *s = &adapter->sge; 451 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 452 int err = 0; 453 unsigned int temp_nb_desc; 454 455 RTE_SET_USED(tx_conf); 456 457 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 458 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 459 socket_id, pi->first_qset); 460 461 /* Free up the existing queue */ 462 if (eth_dev->data->tx_queues[queue_idx]) { 463 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 464 eth_dev->data->tx_queues[queue_idx] = NULL; 465 } 466 467 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 468 469 /* Sanity Checking 470 * 471 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 472 */ 473 temp_nb_desc = nb_desc; 474 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 475 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 476 __func__, CXGBE_MIN_RING_DESC_SIZE, 477 CXGBE_DEFAULT_TX_DESC_SIZE); 478 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 479 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 480 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 481 __func__, CXGBE_MIN_RING_DESC_SIZE, 482 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 483 return -(EINVAL); 484 } 485 486 txq->q.size = temp_nb_desc; 487 488 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 489 s->fw_evtq.cntxt_id, socket_id); 490 491 dev_debug(adapter, "%s: txq->q.cntxt_id= %d err = %d\n", 492 __func__, txq->q.cntxt_id, err); 493 494 return err; 495 } 496 497 static void cxgbe_dev_tx_queue_release(void *q) 498 { 499 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 500 501 if (txq) { 502 struct port_info *pi = (struct port_info *) 503 (txq->eth_dev->data->dev_private); 504 struct adapter *adap = pi->adapter; 505 506 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 507 __func__, pi->port_id, txq->q.cntxt_id); 508 509 t4_sge_eth_txq_release(adap, txq); 510 } 511 } 512 513 static int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, 514 uint16_t rx_queue_id) 515 { 516 int ret; 517 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 518 struct adapter *adap = pi->adapter; 519 struct sge_rspq *q; 520 521 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 522 __func__, pi->port_id, rx_queue_id); 523 524 q = eth_dev->data->rx_queues[rx_queue_id]; 525 526 ret = t4_sge_eth_rxq_start(adap, q); 527 if (ret == 0) 528 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 529 530 return ret; 531 } 532 533 static int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, 534 uint16_t rx_queue_id) 535 { 536 int ret; 537 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 538 struct adapter *adap = pi->adapter; 539 struct sge_rspq *q; 540 541 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 542 __func__, pi->port_id, rx_queue_id); 543 544 q = eth_dev->data->rx_queues[rx_queue_id]; 545 ret = t4_sge_eth_rxq_stop(adap, q); 546 if (ret == 0) 547 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 548 549 return ret; 550 } 551 552 static int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 553 uint16_t queue_idx, uint16_t nb_desc, 554 unsigned int socket_id, 555 const struct rte_eth_rxconf *rx_conf, 556 struct rte_mempool *mp) 557 { 558 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 559 struct adapter *adapter = pi->adapter; 560 struct sge *s = &adapter->sge; 561 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 562 int err = 0; 563 int msi_idx = 0; 564 unsigned int temp_nb_desc; 565 struct rte_eth_dev_info dev_info; 566 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 567 568 RTE_SET_USED(rx_conf); 569 570 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 571 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 572 socket_id, mp); 573 574 cxgbe_dev_info_get(eth_dev, &dev_info); 575 576 /* Must accommodate at least ETHER_MIN_MTU */ 577 if ((pkt_len < dev_info.min_rx_bufsize) || 578 (pkt_len > dev_info.max_rx_pktlen)) { 579 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 580 __func__, dev_info.min_rx_bufsize, 581 dev_info.max_rx_pktlen); 582 return -EINVAL; 583 } 584 585 /* Free up the existing queue */ 586 if (eth_dev->data->rx_queues[queue_idx]) { 587 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 588 eth_dev->data->rx_queues[queue_idx] = NULL; 589 } 590 591 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 592 593 /* Sanity Checking 594 * 595 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 596 */ 597 temp_nb_desc = nb_desc; 598 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 599 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 600 __func__, CXGBE_MIN_RING_DESC_SIZE, 601 CXGBE_DEFAULT_RX_DESC_SIZE); 602 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 603 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 604 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 605 __func__, CXGBE_MIN_RING_DESC_SIZE, 606 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 607 return -(EINVAL); 608 } 609 610 rxq->rspq.size = temp_nb_desc; 611 if ((&rxq->fl) != NULL) 612 rxq->fl.size = temp_nb_desc; 613 614 /* Set to jumbo mode if necessary */ 615 if (pkt_len > ETHER_MAX_LEN) 616 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; 617 else 618 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; 619 620 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 621 &rxq->fl, t4_ethrx_handler, 622 t4_get_tp_ch_map(adapter, pi->tx_chan), mp, 623 queue_idx, socket_id); 624 625 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u\n", 626 __func__, err, pi->port_id, rxq->rspq.cntxt_id); 627 return err; 628 } 629 630 static void cxgbe_dev_rx_queue_release(void *q) 631 { 632 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 633 struct sge_rspq *rq = &rxq->rspq; 634 635 if (rq) { 636 struct port_info *pi = (struct port_info *) 637 (rq->eth_dev->data->dev_private); 638 struct adapter *adap = pi->adapter; 639 640 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 641 __func__, pi->port_id, rxq->rspq.cntxt_id); 642 643 t4_sge_eth_rxq_release(adap, rxq); 644 } 645 } 646 647 /* 648 * Get port statistics. 649 */ 650 static void cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 651 struct rte_eth_stats *eth_stats) 652 { 653 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 654 struct adapter *adapter = pi->adapter; 655 struct sge *s = &adapter->sge; 656 struct port_stats ps; 657 unsigned int i; 658 659 cxgbe_stats_get(pi, &ps); 660 661 /* RX Stats */ 662 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 663 ps.rx_ovflow2 + ps.rx_ovflow3 + 664 ps.rx_trunc0 + ps.rx_trunc1 + 665 ps.rx_trunc2 + ps.rx_trunc3; 666 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 667 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 668 ps.rx_len_err; 669 670 /* TX Stats */ 671 eth_stats->opackets = ps.tx_frames; 672 eth_stats->obytes = ps.tx_octets; 673 eth_stats->oerrors = ps.tx_error_frames; 674 675 for (i = 0; i < pi->n_rx_qsets; i++) { 676 struct sge_eth_rxq *rxq = 677 &s->ethrxq[pi->first_qset + i]; 678 679 eth_stats->q_ipackets[i] = rxq->stats.pkts; 680 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 681 eth_stats->ipackets += eth_stats->q_ipackets[i]; 682 eth_stats->ibytes += eth_stats->q_ibytes[i]; 683 } 684 685 for (i = 0; i < pi->n_tx_qsets; i++) { 686 struct sge_eth_txq *txq = 687 &s->ethtxq[pi->first_qset + i]; 688 689 eth_stats->q_opackets[i] = txq->stats.pkts; 690 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 691 eth_stats->q_errors[i] = txq->stats.mapping_err; 692 } 693 } 694 695 /* 696 * Reset port statistics. 697 */ 698 static void cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 699 { 700 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 701 struct adapter *adapter = pi->adapter; 702 struct sge *s = &adapter->sge; 703 unsigned int i; 704 705 cxgbe_stats_reset(pi); 706 for (i = 0; i < pi->n_rx_qsets; i++) { 707 struct sge_eth_rxq *rxq = 708 &s->ethrxq[pi->first_qset + i]; 709 710 rxq->stats.pkts = 0; 711 rxq->stats.rx_bytes = 0; 712 } 713 for (i = 0; i < pi->n_tx_qsets; i++) { 714 struct sge_eth_txq *txq = 715 &s->ethtxq[pi->first_qset + i]; 716 717 txq->stats.pkts = 0; 718 txq->stats.tx_bytes = 0; 719 txq->stats.mapping_err = 0; 720 } 721 } 722 723 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 724 struct rte_eth_fc_conf *fc_conf) 725 { 726 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 727 struct link_config *lc = &pi->link_cfg; 728 int rx_pause, tx_pause; 729 730 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 731 rx_pause = lc->fc & PAUSE_RX; 732 tx_pause = lc->fc & PAUSE_TX; 733 734 if (rx_pause && tx_pause) 735 fc_conf->mode = RTE_FC_FULL; 736 else if (rx_pause) 737 fc_conf->mode = RTE_FC_RX_PAUSE; 738 else if (tx_pause) 739 fc_conf->mode = RTE_FC_TX_PAUSE; 740 else 741 fc_conf->mode = RTE_FC_NONE; 742 return 0; 743 } 744 745 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 746 struct rte_eth_fc_conf *fc_conf) 747 { 748 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 749 struct adapter *adapter = pi->adapter; 750 struct link_config *lc = &pi->link_cfg; 751 752 if (lc->supported & FW_PORT_CAP_ANEG) { 753 if (fc_conf->autoneg) 754 lc->requested_fc |= PAUSE_AUTONEG; 755 else 756 lc->requested_fc &= ~PAUSE_AUTONEG; 757 } 758 759 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 760 (fc_conf->mode & RTE_FC_RX_PAUSE)) 761 lc->requested_fc |= PAUSE_RX; 762 else 763 lc->requested_fc &= ~PAUSE_RX; 764 765 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 766 (fc_conf->mode & RTE_FC_TX_PAUSE)) 767 lc->requested_fc |= PAUSE_TX; 768 else 769 lc->requested_fc &= ~PAUSE_TX; 770 771 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 772 &pi->link_cfg); 773 } 774 775 static const uint32_t * 776 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 777 { 778 static const uint32_t ptypes[] = { 779 RTE_PTYPE_L3_IPV4, 780 RTE_PTYPE_L3_IPV6, 781 RTE_PTYPE_UNKNOWN 782 }; 783 784 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 785 return ptypes; 786 return NULL; 787 } 788 789 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 790 { 791 RTE_SET_USED(dev); 792 return EEPROMSIZE; 793 } 794 795 /** 796 * eeprom_ptov - translate a physical EEPROM address to virtual 797 * @phys_addr: the physical EEPROM address 798 * @fn: the PCI function number 799 * @sz: size of function-specific area 800 * 801 * Translate a physical EEPROM address to virtual. The first 1K is 802 * accessed through virtual addresses starting at 31K, the rest is 803 * accessed through virtual addresses starting at 0. 804 * 805 * The mapping is as follows: 806 * [0..1K) -> [31K..32K) 807 * [1K..1K+A) -> [31K-A..31K) 808 * [1K+A..ES) -> [0..ES-A-1K) 809 * 810 * where A = @fn * @sz, and ES = EEPROM size. 811 */ 812 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 813 { 814 fn *= sz; 815 if (phys_addr < 1024) 816 return phys_addr + (31 << 10); 817 if (phys_addr < 1024 + fn) 818 return fn + phys_addr - 1024; 819 if (phys_addr < EEPROMSIZE) 820 return phys_addr - 1024 - fn; 821 if (phys_addr < EEPROMVSIZE) 822 return phys_addr - 1024; 823 return -EINVAL; 824 } 825 826 /* The next two routines implement eeprom read/write from physical addresses. 827 */ 828 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 829 { 830 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 831 832 if (vaddr >= 0) 833 vaddr = t4_seeprom_read(adap, vaddr, v); 834 return vaddr < 0 ? vaddr : 0; 835 } 836 837 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 838 { 839 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 840 841 if (vaddr >= 0) 842 vaddr = t4_seeprom_write(adap, vaddr, v); 843 return vaddr < 0 ? vaddr : 0; 844 } 845 846 #define EEPROM_MAGIC 0x38E2F10C 847 848 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 849 struct rte_dev_eeprom_info *e) 850 { 851 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 852 struct adapter *adapter = pi->adapter; 853 u32 i, err = 0; 854 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 855 856 if (!buf) 857 return -ENOMEM; 858 859 e->magic = EEPROM_MAGIC; 860 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 861 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 862 863 if (!err) 864 rte_memcpy(e->data, buf + e->offset, e->length); 865 rte_free(buf); 866 return err; 867 } 868 869 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 870 struct rte_dev_eeprom_info *eeprom) 871 { 872 struct port_info *pi = (struct port_info *)(dev->data->dev_private); 873 struct adapter *adapter = pi->adapter; 874 u8 *buf; 875 int err = 0; 876 u32 aligned_offset, aligned_len, *p; 877 878 if (eeprom->magic != EEPROM_MAGIC) 879 return -EINVAL; 880 881 aligned_offset = eeprom->offset & ~3; 882 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 883 884 if (adapter->pf > 0) { 885 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 886 887 if (aligned_offset < start || 888 aligned_offset + aligned_len > start + EEPROMPFSIZE) 889 return -EPERM; 890 } 891 892 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 893 /* RMW possibly needed for first or last words. 894 */ 895 buf = rte_zmalloc(NULL, aligned_len, 0); 896 if (!buf) 897 return -ENOMEM; 898 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 899 if (!err && aligned_len > 4) 900 err = eeprom_rd_phys(adapter, 901 aligned_offset + aligned_len - 4, 902 (u32 *)&buf[aligned_len - 4]); 903 if (err) 904 goto out; 905 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 906 eeprom->length); 907 } else { 908 buf = eeprom->data; 909 } 910 911 err = t4_seeprom_wp(adapter, false); 912 if (err) 913 goto out; 914 915 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 916 err = eeprom_wr_phys(adapter, aligned_offset, *p); 917 aligned_offset += 4; 918 } 919 920 if (!err) 921 err = t4_seeprom_wp(adapter, true); 922 out: 923 if (buf != eeprom->data) 924 rte_free(buf); 925 return err; 926 } 927 928 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 929 { 930 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 931 struct adapter *adapter = pi->adapter; 932 933 return t4_get_regs_len(adapter) / sizeof(uint32_t); 934 } 935 936 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 937 struct rte_dev_reg_info *regs) 938 { 939 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 940 struct adapter *adapter = pi->adapter; 941 942 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 943 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 944 (1 << 16); 945 946 if (regs->data == NULL) { 947 regs->length = cxgbe_get_regs_len(eth_dev); 948 regs->width = sizeof(uint32_t); 949 950 return 0; 951 } 952 953 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 954 955 return 0; 956 } 957 958 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 959 .dev_start = cxgbe_dev_start, 960 .dev_stop = cxgbe_dev_stop, 961 .dev_close = cxgbe_dev_close, 962 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 963 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 964 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 965 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 966 .dev_configure = cxgbe_dev_configure, 967 .dev_infos_get = cxgbe_dev_info_get, 968 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 969 .link_update = cxgbe_dev_link_update, 970 .mtu_set = cxgbe_dev_mtu_set, 971 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 972 .tx_queue_start = cxgbe_dev_tx_queue_start, 973 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 974 .tx_queue_release = cxgbe_dev_tx_queue_release, 975 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 976 .rx_queue_start = cxgbe_dev_rx_queue_start, 977 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 978 .rx_queue_release = cxgbe_dev_rx_queue_release, 979 .stats_get = cxgbe_dev_stats_get, 980 .stats_reset = cxgbe_dev_stats_reset, 981 .flow_ctrl_get = cxgbe_flow_ctrl_get, 982 .flow_ctrl_set = cxgbe_flow_ctrl_set, 983 .get_eeprom_length = cxgbe_get_eeprom_length, 984 .get_eeprom = cxgbe_get_eeprom, 985 .set_eeprom = cxgbe_set_eeprom, 986 .get_reg = cxgbe_get_regs, 987 }; 988 989 /* 990 * Initialize driver 991 * It returns 0 on success. 992 */ 993 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 994 { 995 struct rte_pci_device *pci_dev; 996 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 997 struct adapter *adapter = NULL; 998 char name[RTE_ETH_NAME_MAX_LEN]; 999 int err = 0; 1000 1001 CXGBE_FUNC_TRACE(); 1002 1003 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1004 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1005 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1006 1007 /* for secondary processes, we don't initialise any further as primary 1008 * has already done this work. 1009 */ 1010 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1011 return 0; 1012 1013 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1014 1015 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1016 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1017 if (!adapter) 1018 return -1; 1019 1020 adapter->use_unpacked_mode = 1; 1021 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1022 if (!adapter->regs) { 1023 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1024 err = -ENOMEM; 1025 goto out_free_adapter; 1026 } 1027 adapter->pdev = pci_dev; 1028 adapter->eth_dev = eth_dev; 1029 pi->adapter = adapter; 1030 1031 err = cxgbe_probe(adapter); 1032 if (err) { 1033 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1034 __func__, err); 1035 goto out_free_adapter; 1036 } 1037 1038 return 0; 1039 1040 out_free_adapter: 1041 rte_free(adapter); 1042 return err; 1043 } 1044 1045 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1046 struct rte_pci_device *pci_dev) 1047 { 1048 return rte_eth_dev_pci_generic_probe(pci_dev, 1049 sizeof(struct port_info), eth_cxgbe_dev_init); 1050 } 1051 1052 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1053 { 1054 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 1055 } 1056 1057 static struct rte_pci_driver rte_cxgbe_pmd = { 1058 .id_table = cxgb4_pci_tbl, 1059 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1060 .probe = eth_cxgbe_pci_probe, 1061 .remove = eth_cxgbe_pci_remove, 1062 }; 1063 1064 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1065 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1066 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1067