1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <bus_pci_driver.h> 24 #include <rte_branch_prediction.h> 25 #include <rte_memory.h> 26 #include <rte_tailq.h> 27 #include <rte_eal.h> 28 #include <rte_alarm.h> 29 #include <rte_ether.h> 30 #include <ethdev_driver.h> 31 #include <ethdev_pci.h> 32 #include <rte_malloc.h> 33 #include <rte_random.h> 34 #include <dev_driver.h> 35 36 #include "cxgbe.h" 37 #include "cxgbe_pfvf.h" 38 #include "cxgbe_flow.h" 39 40 /* 41 * Macros needed to support the PCI Device ID Table ... 42 */ 43 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 44 static const struct rte_pci_id cxgb4_pci_tbl[] = { 45 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 46 47 #define PCI_VENDOR_ID_CHELSIO 0x1425 48 49 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 51 52 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 53 { .vendor_id = 0, } \ 54 } 55 56 /* 57 *... and the PCI ID Table itself ... 58 */ 59 #include "base/t4_pci_id_tbl.h" 60 61 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 62 uint16_t nb_pkts) 63 { 64 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 65 uint16_t pkts_sent, pkts_remain; 66 uint16_t total_sent = 0; 67 uint16_t idx = 0; 68 int ret = 0; 69 70 t4_os_lock(&txq->txq_lock); 71 /* free up desc from already completed tx */ 72 reclaim_completed_tx(&txq->q); 73 if (unlikely(!nb_pkts)) 74 goto out_unlock; 75 76 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 77 while (total_sent < nb_pkts) { 78 pkts_remain = nb_pkts - total_sent; 79 80 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 81 idx = total_sent + pkts_sent; 82 if ((idx + 1) < nb_pkts) 83 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 84 volatile void *)); 85 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 86 if (ret < 0) 87 break; 88 } 89 if (!pkts_sent) 90 break; 91 total_sent += pkts_sent; 92 /* reclaim as much as possible */ 93 reclaim_completed_tx(&txq->q); 94 } 95 96 out_unlock: 97 t4_os_unlock(&txq->txq_lock); 98 return total_sent; 99 } 100 101 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 102 uint16_t nb_pkts) 103 { 104 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 105 unsigned int work_done; 106 107 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 108 dev_err(adapter, "error in cxgbe poll\n"); 109 110 return work_done; 111 } 112 113 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 114 struct rte_eth_dev_info *device_info) 115 { 116 struct port_info *pi = eth_dev->data->dev_private; 117 struct adapter *adapter = pi->adapter; 118 119 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 120 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 121 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 122 .nb_align = 1, 123 }; 124 125 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 126 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 127 device_info->max_rx_queues = adapter->sge.max_ethqsets; 128 device_info->max_tx_queues = adapter->sge.max_ethqsets; 129 device_info->max_mac_addrs = 1; 130 /* XXX: For now we support one MAC/port */ 131 device_info->max_vfs = adapter->params.arch.vfcount; 132 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 133 134 device_info->dev_capa &= ~RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP; 135 136 device_info->rx_queue_offload_capa = 0UL; 137 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 138 139 device_info->tx_queue_offload_capa = 0UL; 140 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 141 142 device_info->reta_size = pi->rss_size; 143 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 144 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 145 146 device_info->rx_desc_lim = cxgbe_desc_lim; 147 device_info->tx_desc_lim = cxgbe_desc_lim; 148 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 149 150 return 0; 151 } 152 153 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 154 { 155 struct port_info *pi = eth_dev->data->dev_private; 156 struct adapter *adapter = pi->adapter; 157 int ret; 158 159 if (adapter->params.rawf_size != 0) { 160 ret = cxgbe_mpstcam_rawf_enable(pi); 161 if (ret < 0) 162 return ret; 163 } 164 165 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 166 1, -1, 1, -1, false); 167 } 168 169 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 170 { 171 struct port_info *pi = eth_dev->data->dev_private; 172 struct adapter *adapter = pi->adapter; 173 int ret; 174 175 if (adapter->params.rawf_size != 0) { 176 ret = cxgbe_mpstcam_rawf_disable(pi); 177 if (ret < 0) 178 return ret; 179 } 180 181 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 182 0, -1, 1, -1, false); 183 } 184 185 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 186 { 187 struct port_info *pi = eth_dev->data->dev_private; 188 struct adapter *adapter = pi->adapter; 189 190 /* TODO: address filters ?? */ 191 192 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 193 -1, 1, 1, -1, false); 194 } 195 196 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 197 { 198 struct port_info *pi = eth_dev->data->dev_private; 199 struct adapter *adapter = pi->adapter; 200 201 /* TODO: address filters ?? */ 202 203 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 204 -1, 0, 1, -1, false); 205 } 206 207 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 208 int wait_to_complete) 209 { 210 struct port_info *pi = eth_dev->data->dev_private; 211 unsigned int i, work_done, budget = 32; 212 struct link_config *lc = &pi->link_cfg; 213 struct adapter *adapter = pi->adapter; 214 u8 old_link = pi->link_cfg.link_ok; 215 struct sge *s = &adapter->sge; 216 struct rte_eth_link new_link; 217 218 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 219 if (!s->fw_evtq.desc) 220 break; 221 222 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 223 224 /* Exit if link status changed or always forced up */ 225 if (pi->link_cfg.link_ok != old_link || 226 cxgbe_force_linkup(adapter)) 227 break; 228 229 if (!wait_to_complete) 230 break; 231 232 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 233 } 234 235 memset(&new_link, 0, sizeof(new_link)); 236 new_link.link_status = cxgbe_force_linkup(adapter) ? 237 RTE_ETH_LINK_UP : pi->link_cfg.link_ok; 238 new_link.link_autoneg = (lc->link_caps & FW_PORT_CAP32_ANEG) ? 1 : 0; 239 new_link.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 240 new_link.link_speed = t4_fwcap_to_speed(lc->link_caps); 241 242 return rte_eth_linkstatus_set(eth_dev, &new_link); 243 } 244 245 /** 246 * Set device link up. 247 */ 248 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 249 { 250 struct port_info *pi = dev->data->dev_private; 251 struct adapter *adapter = pi->adapter; 252 unsigned int work_done, budget = 32; 253 struct sge *s = &adapter->sge; 254 int ret; 255 256 if (!s->fw_evtq.desc) 257 return -ENOMEM; 258 259 /* Flush all link events */ 260 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 261 262 /* If link already up, nothing to do */ 263 if (pi->link_cfg.link_ok) 264 return 0; 265 266 ret = cxgbe_set_link_status(pi, true); 267 if (ret) 268 return ret; 269 270 cxgbe_dev_link_update(dev, 1); 271 return 0; 272 } 273 274 /** 275 * Set device link down. 276 */ 277 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 278 { 279 struct port_info *pi = dev->data->dev_private; 280 struct adapter *adapter = pi->adapter; 281 unsigned int work_done, budget = 32; 282 struct sge *s = &adapter->sge; 283 int ret; 284 285 if (!s->fw_evtq.desc) 286 return -ENOMEM; 287 288 /* Flush all link events */ 289 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 290 291 /* If link already down, nothing to do */ 292 if (!pi->link_cfg.link_ok) 293 return 0; 294 295 ret = cxgbe_set_link_status(pi, false); 296 if (ret) 297 return ret; 298 299 cxgbe_dev_link_update(dev, 0); 300 return 0; 301 } 302 303 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 304 { 305 struct port_info *pi = eth_dev->data->dev_private; 306 struct adapter *adapter = pi->adapter; 307 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 308 309 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 310 -1, -1, true); 311 } 312 313 /* 314 * Stop device. 315 */ 316 int cxgbe_dev_close(struct rte_eth_dev *eth_dev) 317 { 318 struct port_info *temp_pi, *pi = eth_dev->data->dev_private; 319 struct adapter *adapter = pi->adapter; 320 u8 i; 321 322 CXGBE_FUNC_TRACE(); 323 324 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 325 return 0; 326 327 if (!(adapter->flags & FULL_INIT_DONE)) 328 return 0; 329 330 if (!pi->viid) 331 return 0; 332 333 cxgbe_down(pi); 334 t4_sge_eth_release_queues(pi); 335 t4_free_vi(adapter, adapter->mbox, adapter->pf, 0, pi->viid); 336 pi->viid = 0; 337 338 /* Free up the adapter-wide resources only after all the ports 339 * under this PF have been closed. 340 */ 341 for_each_port(adapter, i) { 342 temp_pi = adap2pinfo(adapter, i); 343 if (temp_pi->viid) 344 return 0; 345 } 346 347 cxgbe_close(adapter); 348 rte_free(adapter); 349 350 return 0; 351 } 352 353 /* Start the device. 354 * It returns 0 on success. 355 */ 356 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 357 { 358 struct port_info *pi = eth_dev->data->dev_private; 359 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 360 struct adapter *adapter = pi->adapter; 361 int err = 0, i; 362 363 CXGBE_FUNC_TRACE(); 364 365 /* 366 * If we don't have a connection to the firmware there's nothing we 367 * can do. 368 */ 369 if (!(adapter->flags & FW_OK)) { 370 err = -ENXIO; 371 goto out; 372 } 373 374 if (!(adapter->flags & FULL_INIT_DONE)) { 375 err = cxgbe_up(adapter); 376 if (err < 0) 377 goto out; 378 } 379 380 if (rx_conf->offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 381 eth_dev->data->scattered_rx = 1; 382 else 383 eth_dev->data->scattered_rx = 0; 384 385 cxgbe_enable_rx_queues(pi); 386 387 err = cxgbe_setup_rss(pi); 388 if (err) 389 goto out; 390 391 for (i = 0; i < pi->n_tx_qsets; i++) { 392 err = cxgbe_dev_tx_queue_start(eth_dev, i); 393 if (err) 394 goto out; 395 } 396 397 for (i = 0; i < pi->n_rx_qsets; i++) { 398 err = cxgbe_dev_rx_queue_start(eth_dev, i); 399 if (err) 400 goto out; 401 } 402 403 err = cxgbe_link_start(pi); 404 if (err) 405 goto out; 406 407 out: 408 return err; 409 } 410 411 /* 412 * Stop device: disable rx and tx functions to allow for reconfiguring. 413 */ 414 int cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 415 { 416 struct port_info *pi = eth_dev->data->dev_private; 417 struct adapter *adapter = pi->adapter; 418 uint16_t i; 419 420 CXGBE_FUNC_TRACE(); 421 422 if (!(adapter->flags & FULL_INIT_DONE)) 423 return 0; 424 425 cxgbe_down(pi); 426 427 /* 428 * We clear queues only if both tx and rx path of the port 429 * have been disabled 430 */ 431 t4_sge_eth_clear_queues(pi); 432 eth_dev->data->scattered_rx = 0; 433 434 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) 435 eth_dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 436 for (i = 0; i < eth_dev->data->nb_tx_queues; i++) 437 eth_dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 438 439 return 0; 440 } 441 442 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 443 { 444 struct port_info *pi = eth_dev->data->dev_private; 445 struct adapter *adapter = pi->adapter; 446 int err; 447 448 CXGBE_FUNC_TRACE(); 449 450 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 451 eth_dev->data->dev_conf.rxmode.offloads |= 452 RTE_ETH_RX_OFFLOAD_RSS_HASH; 453 454 if (!(adapter->flags & FW_QUEUE_BOUND)) { 455 err = cxgbe_setup_sge_fwevtq(adapter); 456 if (err) 457 return err; 458 adapter->flags |= FW_QUEUE_BOUND; 459 if (is_pf4(adapter)) { 460 err = cxgbe_setup_sge_ctrl_txq(adapter); 461 if (err) 462 return err; 463 } 464 } 465 466 err = cxgbe_cfg_queue_count(eth_dev); 467 if (err) 468 return err; 469 470 return 0; 471 } 472 473 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 474 { 475 int ret; 476 struct sge_eth_txq *txq = (struct sge_eth_txq *) 477 (eth_dev->data->tx_queues[tx_queue_id]); 478 479 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 480 481 ret = t4_sge_eth_txq_start(txq); 482 if (ret == 0) 483 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 484 485 return ret; 486 } 487 488 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 489 { 490 int ret; 491 struct sge_eth_txq *txq = (struct sge_eth_txq *) 492 (eth_dev->data->tx_queues[tx_queue_id]); 493 494 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 495 496 ret = t4_sge_eth_txq_stop(txq); 497 if (ret == 0) 498 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 499 500 return ret; 501 } 502 503 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 504 uint16_t queue_idx, uint16_t nb_desc, 505 unsigned int socket_id, 506 const struct rte_eth_txconf *tx_conf __rte_unused) 507 { 508 struct port_info *pi = eth_dev->data->dev_private; 509 struct adapter *adapter = pi->adapter; 510 struct sge *s = &adapter->sge; 511 unsigned int temp_nb_desc; 512 struct sge_eth_txq *txq; 513 int err = 0; 514 515 txq = &s->ethtxq[pi->first_txqset + queue_idx]; 516 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 517 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 518 socket_id, pi->first_txqset); 519 520 /* Free up the existing queue */ 521 if (eth_dev->data->tx_queues[queue_idx]) { 522 cxgbe_dev_tx_queue_release(eth_dev, queue_idx); 523 eth_dev->data->tx_queues[queue_idx] = NULL; 524 } 525 526 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 527 528 /* Sanity Checking 529 * 530 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 531 */ 532 temp_nb_desc = nb_desc; 533 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 534 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 535 __func__, CXGBE_MIN_RING_DESC_SIZE, 536 CXGBE_DEFAULT_TX_DESC_SIZE); 537 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 538 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 539 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 540 __func__, CXGBE_MIN_RING_DESC_SIZE, 541 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 542 return -(EINVAL); 543 } 544 545 txq->q.size = temp_nb_desc; 546 547 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 548 s->fw_evtq.cntxt_id, socket_id); 549 550 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 551 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 552 return err; 553 } 554 555 void cxgbe_dev_tx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 556 { 557 struct sge_eth_txq *txq = eth_dev->data->tx_queues[qid]; 558 559 if (txq) { 560 struct port_info *pi = (struct port_info *) 561 (txq->eth_dev->data->dev_private); 562 struct adapter *adap = pi->adapter; 563 564 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 565 __func__, pi->port_id, txq->q.cntxt_id); 566 567 t4_sge_eth_txq_release(adap, txq); 568 } 569 } 570 571 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 572 { 573 struct port_info *pi = eth_dev->data->dev_private; 574 struct adapter *adap = pi->adapter; 575 struct sge_eth_rxq *rxq; 576 int ret; 577 578 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 579 __func__, pi->port_id, rx_queue_id); 580 581 rxq = eth_dev->data->rx_queues[rx_queue_id]; 582 ret = t4_sge_eth_rxq_start(adap, rxq); 583 if (ret == 0) 584 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 585 586 return ret; 587 } 588 589 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 590 { 591 struct port_info *pi = eth_dev->data->dev_private; 592 struct adapter *adap = pi->adapter; 593 struct sge_eth_rxq *rxq; 594 int ret; 595 596 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 597 __func__, pi->port_id, rx_queue_id); 598 599 rxq = eth_dev->data->rx_queues[rx_queue_id]; 600 ret = t4_sge_eth_rxq_stop(adap, rxq); 601 if (ret == 0) 602 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 603 604 return ret; 605 } 606 607 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 608 uint16_t queue_idx, uint16_t nb_desc, 609 unsigned int socket_id, 610 const struct rte_eth_rxconf *rx_conf __rte_unused, 611 struct rte_mempool *mp) 612 { 613 unsigned int pkt_len = eth_dev->data->mtu + RTE_ETHER_HDR_LEN + 614 RTE_ETHER_CRC_LEN; 615 struct port_info *pi = eth_dev->data->dev_private; 616 struct adapter *adapter = pi->adapter; 617 struct rte_eth_dev_info dev_info; 618 struct sge *s = &adapter->sge; 619 unsigned int temp_nb_desc; 620 int err = 0, msi_idx = 0; 621 struct sge_eth_rxq *rxq; 622 623 rxq = &s->ethrxq[pi->first_rxqset + queue_idx]; 624 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 625 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 626 socket_id, mp); 627 628 err = cxgbe_dev_info_get(eth_dev, &dev_info); 629 if (err != 0) { 630 dev_err(adap, "%s: error during getting ethernet device info", 631 __func__); 632 return err; 633 } 634 635 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 636 if ((pkt_len < dev_info.min_rx_bufsize) || 637 (pkt_len > dev_info.max_rx_pktlen)) { 638 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 639 __func__, dev_info.min_rx_bufsize, 640 dev_info.max_rx_pktlen); 641 return -EINVAL; 642 } 643 644 /* Free up the existing queue */ 645 if (eth_dev->data->rx_queues[queue_idx]) { 646 cxgbe_dev_rx_queue_release(eth_dev, queue_idx); 647 eth_dev->data->rx_queues[queue_idx] = NULL; 648 } 649 650 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 651 652 /* Sanity Checking 653 * 654 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 655 */ 656 temp_nb_desc = nb_desc; 657 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 658 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 659 __func__, CXGBE_MIN_RING_DESC_SIZE, 660 CXGBE_DEFAULT_RX_DESC_SIZE); 661 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 662 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 663 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 664 __func__, CXGBE_MIN_RING_DESC_SIZE, 665 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 666 return -(EINVAL); 667 } 668 669 rxq->rspq.size = temp_nb_desc; 670 rxq->fl.size = temp_nb_desc; 671 672 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 673 &rxq->fl, NULL, 674 is_pf4(adapter) ? 675 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 676 queue_idx, socket_id); 677 678 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 679 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 680 rxq->rspq.abs_id); 681 return err; 682 } 683 684 void cxgbe_dev_rx_queue_release(struct rte_eth_dev *eth_dev, uint16_t qid) 685 { 686 struct sge_eth_rxq *rxq = eth_dev->data->rx_queues[qid]; 687 688 if (rxq) { 689 struct port_info *pi = (struct port_info *) 690 (rxq->rspq.eth_dev->data->dev_private); 691 struct adapter *adap = pi->adapter; 692 693 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 694 __func__, pi->port_id, rxq->rspq.cntxt_id); 695 696 t4_sge_eth_rxq_release(adap, rxq); 697 } 698 } 699 700 /* 701 * Get port statistics. 702 */ 703 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 704 struct rte_eth_stats *eth_stats) 705 { 706 struct port_info *pi = eth_dev->data->dev_private; 707 struct adapter *adapter = pi->adapter; 708 struct sge *s = &adapter->sge; 709 struct port_stats ps; 710 unsigned int i; 711 712 cxgbe_stats_get(pi, &ps); 713 714 /* RX Stats */ 715 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 716 ps.rx_ovflow2 + ps.rx_ovflow3 + 717 ps.rx_trunc0 + ps.rx_trunc1 + 718 ps.rx_trunc2 + ps.rx_trunc3; 719 for (i = 0; i < NCHAN; i++) 720 eth_stats->imissed += ps.rx_tp_tnl_cong_drops[i]; 721 722 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 723 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 724 ps.rx_len_err; 725 726 /* TX Stats */ 727 eth_stats->opackets = ps.tx_frames; 728 eth_stats->obytes = ps.tx_octets; 729 eth_stats->oerrors = ps.tx_error_frames; 730 731 for (i = 0; i < pi->n_rx_qsets; i++) { 732 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 733 734 eth_stats->ipackets += rxq->stats.pkts; 735 eth_stats->ibytes += rxq->stats.rx_bytes; 736 } 737 738 return 0; 739 } 740 741 /* 742 * Reset port statistics. 743 */ 744 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 745 { 746 struct port_info *pi = eth_dev->data->dev_private; 747 struct adapter *adapter = pi->adapter; 748 struct sge *s = &adapter->sge; 749 unsigned int i; 750 751 cxgbe_stats_reset(pi); 752 for (i = 0; i < pi->n_rx_qsets; i++) { 753 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + i]; 754 755 memset(&rxq->stats, 0, sizeof(rxq->stats)); 756 } 757 for (i = 0; i < pi->n_tx_qsets; i++) { 758 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + i]; 759 760 memset(&txq->stats, 0, sizeof(txq->stats)); 761 } 762 763 return 0; 764 } 765 766 /* Store extended statistics names and its offset in stats structure */ 767 struct cxgbe_dev_xstats_name_off { 768 char name[RTE_ETH_XSTATS_NAME_SIZE]; 769 unsigned int offset; 770 }; 771 772 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_rxq_stats_strings[] = { 773 {"packets", offsetof(struct sge_eth_rx_stats, pkts)}, 774 {"bytes", offsetof(struct sge_eth_rx_stats, rx_bytes)}, 775 {"checksum_offloads", offsetof(struct sge_eth_rx_stats, rx_cso)}, 776 {"vlan_extractions", offsetof(struct sge_eth_rx_stats, vlan_ex)}, 777 {"dropped_packets", offsetof(struct sge_eth_rx_stats, rx_drops)}, 778 }; 779 780 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_txq_stats_strings[] = { 781 {"packets", offsetof(struct sge_eth_tx_stats, pkts)}, 782 {"bytes", offsetof(struct sge_eth_tx_stats, tx_bytes)}, 783 {"tso_requests", offsetof(struct sge_eth_tx_stats, tso)}, 784 {"checksum_offloads", offsetof(struct sge_eth_tx_stats, tx_cso)}, 785 {"vlan_insertions", offsetof(struct sge_eth_tx_stats, vlan_ins)}, 786 {"packet_mapping_errors", 787 offsetof(struct sge_eth_tx_stats, mapping_err)}, 788 {"coalesced_wrs", offsetof(struct sge_eth_tx_stats, coal_wr)}, 789 {"coalesced_packets", offsetof(struct sge_eth_tx_stats, coal_pkts)}, 790 }; 791 792 static const struct cxgbe_dev_xstats_name_off cxgbe_dev_port_stats_strings[] = { 793 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 794 {"tx_packets", offsetof(struct port_stats, tx_frames)}, 795 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 796 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 797 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 798 {"tx_error_packets", offsetof(struct port_stats, tx_error_frames)}, 799 {"tx_size_64_packets", offsetof(struct port_stats, tx_frames_64)}, 800 {"tx_size_65_to_127_packets", 801 offsetof(struct port_stats, tx_frames_65_127)}, 802 {"tx_size_128_to_255_packets", 803 offsetof(struct port_stats, tx_frames_128_255)}, 804 {"tx_size_256_to_511_packets", 805 offsetof(struct port_stats, tx_frames_256_511)}, 806 {"tx_size_512_to_1023_packets", 807 offsetof(struct port_stats, tx_frames_512_1023)}, 808 {"tx_size_1024_to_1518_packets", 809 offsetof(struct port_stats, tx_frames_1024_1518)}, 810 {"tx_size_1519_to_max_packets", 811 offsetof(struct port_stats, tx_frames_1519_max)}, 812 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 813 {"tx_pause_frames", offsetof(struct port_stats, tx_pause)}, 814 {"tx_ppp_pri0_packets", offsetof(struct port_stats, tx_ppp0)}, 815 {"tx_ppp_pri1_packets", offsetof(struct port_stats, tx_ppp1)}, 816 {"tx_ppp_pri2_packets", offsetof(struct port_stats, tx_ppp2)}, 817 {"tx_ppp_pri3_packets", offsetof(struct port_stats, tx_ppp3)}, 818 {"tx_ppp_pri4_packets", offsetof(struct port_stats, tx_ppp4)}, 819 {"tx_ppp_pri5_packets", offsetof(struct port_stats, tx_ppp5)}, 820 {"tx_ppp_pri6_packets", offsetof(struct port_stats, tx_ppp6)}, 821 {"tx_ppp_pri7_packets", offsetof(struct port_stats, tx_ppp7)}, 822 {"rx_bytes", offsetof(struct port_stats, rx_octets)}, 823 {"rx_packets", offsetof(struct port_stats, rx_frames)}, 824 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 825 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 826 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 827 {"rx_too_long_packets", offsetof(struct port_stats, rx_too_long)}, 828 {"rx_jabber_packets", offsetof(struct port_stats, rx_jabber)}, 829 {"rx_fcs_error_packets", offsetof(struct port_stats, rx_fcs_err)}, 830 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 831 {"rx_symbol_error_packets", 832 offsetof(struct port_stats, rx_symbol_err)}, 833 {"rx_short_packets", offsetof(struct port_stats, rx_runt)}, 834 {"rx_size_64_packets", offsetof(struct port_stats, rx_frames_64)}, 835 {"rx_size_65_to_127_packets", 836 offsetof(struct port_stats, rx_frames_65_127)}, 837 {"rx_size_128_to_255_packets", 838 offsetof(struct port_stats, rx_frames_128_255)}, 839 {"rx_size_256_to_511_packets", 840 offsetof(struct port_stats, rx_frames_256_511)}, 841 {"rx_size_512_to_1023_packets", 842 offsetof(struct port_stats, rx_frames_512_1023)}, 843 {"rx_size_1024_to_1518_packets", 844 offsetof(struct port_stats, rx_frames_1024_1518)}, 845 {"rx_size_1519_to_max_packets", 846 offsetof(struct port_stats, rx_frames_1519_max)}, 847 {"rx_pause_packets", offsetof(struct port_stats, rx_pause)}, 848 {"rx_ppp_pri0_packets", offsetof(struct port_stats, rx_ppp0)}, 849 {"rx_ppp_pri1_packets", offsetof(struct port_stats, rx_ppp1)}, 850 {"rx_ppp_pri2_packets", offsetof(struct port_stats, rx_ppp2)}, 851 {"rx_ppp_pri3_packets", offsetof(struct port_stats, rx_ppp3)}, 852 {"rx_ppp_pri4_packets", offsetof(struct port_stats, rx_ppp4)}, 853 {"rx_ppp_pri5_packets", offsetof(struct port_stats, rx_ppp5)}, 854 {"rx_ppp_pri6_packets", offsetof(struct port_stats, rx_ppp6)}, 855 {"rx_ppp_pri7_packets", offsetof(struct port_stats, rx_ppp7)}, 856 {"rx_bg0_dropped_packets", offsetof(struct port_stats, rx_ovflow0)}, 857 {"rx_bg1_dropped_packets", offsetof(struct port_stats, rx_ovflow1)}, 858 {"rx_bg2_dropped_packets", offsetof(struct port_stats, rx_ovflow2)}, 859 {"rx_bg3_dropped_packets", offsetof(struct port_stats, rx_ovflow3)}, 860 {"rx_bg0_truncated_packets", offsetof(struct port_stats, rx_trunc0)}, 861 {"rx_bg1_truncated_packets", offsetof(struct port_stats, rx_trunc1)}, 862 {"rx_bg2_truncated_packets", offsetof(struct port_stats, rx_trunc2)}, 863 {"rx_bg3_truncated_packets", offsetof(struct port_stats, rx_trunc3)}, 864 {"rx_tp_tnl_cong_drops0", 865 offsetof(struct port_stats, rx_tp_tnl_cong_drops[0])}, 866 {"rx_tp_tnl_cong_drops1", 867 offsetof(struct port_stats, rx_tp_tnl_cong_drops[1])}, 868 {"rx_tp_tnl_cong_drops2", 869 offsetof(struct port_stats, rx_tp_tnl_cong_drops[2])}, 870 {"rx_tp_tnl_cong_drops3", 871 offsetof(struct port_stats, rx_tp_tnl_cong_drops[3])}, 872 }; 873 874 static const struct cxgbe_dev_xstats_name_off 875 cxgbevf_dev_port_stats_strings[] = { 876 {"tx_bytes", offsetof(struct port_stats, tx_octets)}, 877 {"tx_broadcast_packets", offsetof(struct port_stats, tx_bcast_frames)}, 878 {"tx_multicast_packets", offsetof(struct port_stats, tx_mcast_frames)}, 879 {"tx_unicast_packets", offsetof(struct port_stats, tx_ucast_frames)}, 880 {"tx_drop_packets", offsetof(struct port_stats, tx_drop)}, 881 {"rx_broadcast_packets", offsetof(struct port_stats, rx_bcast_frames)}, 882 {"rx_multicast_packets", offsetof(struct port_stats, rx_mcast_frames)}, 883 {"rx_unicast_packets", offsetof(struct port_stats, rx_ucast_frames)}, 884 {"rx_length_error_packets", offsetof(struct port_stats, rx_len_err)}, 885 }; 886 887 #define CXGBE_NB_RXQ_STATS RTE_DIM(cxgbe_dev_rxq_stats_strings) 888 #define CXGBE_NB_TXQ_STATS RTE_DIM(cxgbe_dev_txq_stats_strings) 889 #define CXGBE_NB_PORT_STATS RTE_DIM(cxgbe_dev_port_stats_strings) 890 #define CXGBEVF_NB_PORT_STATS RTE_DIM(cxgbevf_dev_port_stats_strings) 891 892 static u16 cxgbe_dev_xstats_count(struct port_info *pi) 893 { 894 u16 count; 895 896 count = (pi->n_tx_qsets * CXGBE_NB_TXQ_STATS) + 897 (pi->n_rx_qsets * CXGBE_NB_RXQ_STATS); 898 899 if (is_pf4(pi->adapter) != 0) 900 count += CXGBE_NB_PORT_STATS; 901 else 902 count += CXGBEVF_NB_PORT_STATS; 903 904 return count; 905 } 906 907 static int cxgbe_dev_xstats(struct rte_eth_dev *dev, 908 struct rte_eth_xstat_name *xstats_names, 909 struct rte_eth_xstat *xstats, unsigned int size) 910 { 911 const struct cxgbe_dev_xstats_name_off *xstats_str; 912 struct port_info *pi = dev->data->dev_private; 913 struct adapter *adap = pi->adapter; 914 struct sge *s = &adap->sge; 915 u16 count, i, qid, nstats; 916 struct port_stats ps; 917 u64 *stats_ptr; 918 919 count = cxgbe_dev_xstats_count(pi); 920 if (size < count) 921 return count; 922 923 if (is_pf4(adap) != 0) { 924 /* port stats for PF*/ 925 cxgbe_stats_get(pi, &ps); 926 xstats_str = cxgbe_dev_port_stats_strings; 927 nstats = CXGBE_NB_PORT_STATS; 928 } else { 929 /* port stats for VF*/ 930 cxgbevf_stats_get(pi, &ps); 931 xstats_str = cxgbevf_dev_port_stats_strings; 932 nstats = CXGBEVF_NB_PORT_STATS; 933 } 934 935 count = 0; 936 for (i = 0; i < nstats; i++, count++) { 937 if (xstats_names != NULL) 938 snprintf(xstats_names[count].name, 939 sizeof(xstats_names[count].name), 940 "%s", xstats_str[i].name); 941 if (xstats != NULL) { 942 stats_ptr = RTE_PTR_ADD(&ps, 943 xstats_str[i].offset); 944 xstats[count].value = *stats_ptr; 945 xstats[count].id = count; 946 } 947 } 948 949 /* per-txq stats */ 950 xstats_str = cxgbe_dev_txq_stats_strings; 951 for (qid = 0; qid < pi->n_tx_qsets; qid++) { 952 struct sge_eth_txq *txq = &s->ethtxq[pi->first_txqset + qid]; 953 954 for (i = 0; i < CXGBE_NB_TXQ_STATS; i++, count++) { 955 if (xstats_names != NULL) 956 snprintf(xstats_names[count].name, 957 sizeof(xstats_names[count].name), 958 "tx_q%u_%s", 959 qid, xstats_str[i].name); 960 if (xstats != NULL) { 961 stats_ptr = RTE_PTR_ADD(&txq->stats, 962 xstats_str[i].offset); 963 xstats[count].value = *stats_ptr; 964 xstats[count].id = count; 965 } 966 } 967 } 968 969 /* per-rxq stats */ 970 xstats_str = cxgbe_dev_rxq_stats_strings; 971 for (qid = 0; qid < pi->n_rx_qsets; qid++) { 972 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_rxqset + qid]; 973 974 for (i = 0; i < CXGBE_NB_RXQ_STATS; i++, count++) { 975 if (xstats_names != NULL) 976 snprintf(xstats_names[count].name, 977 sizeof(xstats_names[count].name), 978 "rx_q%u_%s", 979 qid, xstats_str[i].name); 980 if (xstats != NULL) { 981 stats_ptr = RTE_PTR_ADD(&rxq->stats, 982 xstats_str[i].offset); 983 xstats[count].value = *stats_ptr; 984 xstats[count].id = count; 985 } 986 } 987 } 988 989 return count; 990 } 991 992 /* Get port extended statistics by ID. */ 993 int cxgbe_dev_xstats_get_by_id(struct rte_eth_dev *dev, 994 const uint64_t *ids, uint64_t *values, 995 unsigned int n) 996 { 997 struct port_info *pi = dev->data->dev_private; 998 struct rte_eth_xstat *xstats_copy; 999 u16 count, i; 1000 int ret = 0; 1001 1002 count = cxgbe_dev_xstats_count(pi); 1003 if (ids == NULL || values == NULL) 1004 return count; 1005 1006 xstats_copy = rte_calloc(NULL, count, sizeof(*xstats_copy), 0); 1007 if (xstats_copy == NULL) 1008 return -ENOMEM; 1009 1010 cxgbe_dev_xstats(dev, NULL, xstats_copy, count); 1011 1012 for (i = 0; i < n; i++) { 1013 if (ids[i] >= count) { 1014 ret = -EINVAL; 1015 goto out_err; 1016 } 1017 values[i] = xstats_copy[ids[i]].value; 1018 } 1019 1020 ret = n; 1021 1022 out_err: 1023 rte_free(xstats_copy); 1024 return ret; 1025 } 1026 1027 /* Get names of port extended statistics by ID. */ 1028 int cxgbe_dev_xstats_get_names_by_id(struct rte_eth_dev *dev, 1029 const uint64_t *ids, 1030 struct rte_eth_xstat_name *xnames, 1031 unsigned int n) 1032 { 1033 struct port_info *pi = dev->data->dev_private; 1034 struct rte_eth_xstat_name *xnames_copy; 1035 u16 count, i; 1036 int ret = 0; 1037 1038 count = cxgbe_dev_xstats_count(pi); 1039 if (ids == NULL || xnames == NULL) 1040 return count; 1041 1042 xnames_copy = rte_calloc(NULL, count, sizeof(*xnames_copy), 0); 1043 if (xnames_copy == NULL) 1044 return -ENOMEM; 1045 1046 cxgbe_dev_xstats(dev, xnames_copy, NULL, count); 1047 1048 for (i = 0; i < n; i++) { 1049 if (ids[i] >= count) { 1050 ret = -EINVAL; 1051 goto out_err; 1052 } 1053 rte_strlcpy(xnames[i].name, xnames_copy[ids[i]].name, 1054 sizeof(xnames[i].name)); 1055 } 1056 1057 ret = n; 1058 1059 out_err: 1060 rte_free(xnames_copy); 1061 return ret; 1062 } 1063 1064 /* Get port extended statistics. */ 1065 int cxgbe_dev_xstats_get(struct rte_eth_dev *dev, 1066 struct rte_eth_xstat *xstats, unsigned int n) 1067 { 1068 return cxgbe_dev_xstats(dev, NULL, xstats, n); 1069 } 1070 1071 /* Get names of port extended statistics. */ 1072 int cxgbe_dev_xstats_get_names(struct rte_eth_dev *dev, 1073 struct rte_eth_xstat_name *xstats_names, 1074 unsigned int n) 1075 { 1076 return cxgbe_dev_xstats(dev, xstats_names, NULL, n); 1077 } 1078 1079 /* Reset port extended statistics. */ 1080 static int cxgbe_dev_xstats_reset(struct rte_eth_dev *dev) 1081 { 1082 return cxgbe_dev_stats_reset(dev); 1083 } 1084 1085 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 1086 struct rte_eth_fc_conf *fc_conf) 1087 { 1088 struct port_info *pi = eth_dev->data->dev_private; 1089 struct link_config *lc = &pi->link_cfg; 1090 u8 rx_pause = 0, tx_pause = 0; 1091 u32 caps = lc->link_caps; 1092 1093 if (caps & FW_PORT_CAP32_ANEG) 1094 fc_conf->autoneg = 1; 1095 1096 if (caps & FW_PORT_CAP32_FC_TX) 1097 tx_pause = 1; 1098 1099 if (caps & FW_PORT_CAP32_FC_RX) 1100 rx_pause = 1; 1101 1102 if (rx_pause && tx_pause) 1103 fc_conf->mode = RTE_ETH_FC_FULL; 1104 else if (rx_pause) 1105 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 1106 else if (tx_pause) 1107 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1108 else 1109 fc_conf->mode = RTE_ETH_FC_NONE; 1110 return 0; 1111 } 1112 1113 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 1114 struct rte_eth_fc_conf *fc_conf) 1115 { 1116 struct port_info *pi = eth_dev->data->dev_private; 1117 struct link_config *lc = &pi->link_cfg; 1118 u32 new_caps = lc->admin_caps; 1119 u8 tx_pause = 0, rx_pause = 0; 1120 int ret; 1121 1122 if (fc_conf->mode == RTE_ETH_FC_FULL) { 1123 tx_pause = 1; 1124 rx_pause = 1; 1125 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE) { 1126 tx_pause = 1; 1127 } else if (fc_conf->mode == RTE_ETH_FC_RX_PAUSE) { 1128 rx_pause = 1; 1129 } 1130 1131 ret = t4_set_link_pause(pi, fc_conf->autoneg, tx_pause, 1132 rx_pause, &new_caps); 1133 if (ret != 0) 1134 return ret; 1135 1136 if (!fc_conf->autoneg) { 1137 if (lc->pcaps & FW_PORT_CAP32_FORCE_PAUSE) 1138 new_caps |= FW_PORT_CAP32_FORCE_PAUSE; 1139 } else { 1140 new_caps &= ~FW_PORT_CAP32_FORCE_PAUSE; 1141 } 1142 1143 if (new_caps != lc->admin_caps) { 1144 ret = t4_link_l1cfg(pi, new_caps); 1145 if (ret == 0) 1146 lc->admin_caps = new_caps; 1147 } 1148 1149 return ret; 1150 } 1151 1152 const uint32_t * 1153 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev, 1154 size_t *no_of_elements) 1155 { 1156 static const uint32_t ptypes[] = { 1157 RTE_PTYPE_L3_IPV4, 1158 RTE_PTYPE_L3_IPV6, 1159 }; 1160 1161 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) { 1162 *no_of_elements = RTE_DIM(ptypes); 1163 return ptypes; 1164 } 1165 return NULL; 1166 } 1167 1168 /* Update RSS hash configuration 1169 */ 1170 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 1171 struct rte_eth_rss_conf *rss_conf) 1172 { 1173 struct port_info *pi = dev->data->dev_private; 1174 struct adapter *adapter = pi->adapter; 1175 int err; 1176 1177 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 1178 if (err) 1179 return err; 1180 1181 pi->rss_hf = rss_conf->rss_hf; 1182 1183 if (rss_conf->rss_key) { 1184 u32 key[10], mod_key[10]; 1185 int i, j; 1186 1187 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1188 1189 for (i = 9, j = 0; i >= 0; i--, j++) 1190 mod_key[j] = cpu_to_be32(key[i]); 1191 1192 t4_write_rss_key(adapter, mod_key, -1); 1193 } 1194 1195 return 0; 1196 } 1197 1198 /* Get RSS hash configuration 1199 */ 1200 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1201 struct rte_eth_rss_conf *rss_conf) 1202 { 1203 struct port_info *pi = dev->data->dev_private; 1204 struct adapter *adapter = pi->adapter; 1205 u64 rss_hf = 0; 1206 u64 flags = 0; 1207 int err; 1208 1209 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 1210 &flags, NULL); 1211 1212 if (err) 1213 return err; 1214 1215 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 1216 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 1217 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1218 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 1219 } 1220 1221 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1222 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 1223 1224 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 1225 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 1226 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 1227 rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 1228 } 1229 1230 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1231 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 1232 1233 rss_conf->rss_hf = rss_hf; 1234 1235 if (rss_conf->rss_key) { 1236 u32 key[10], mod_key[10]; 1237 int i, j; 1238 1239 t4_read_rss_key(adapter, key); 1240 1241 for (i = 9, j = 0; i >= 0; i--, j++) 1242 mod_key[j] = be32_to_cpu(key[i]); 1243 1244 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int cxgbe_dev_rss_reta_update(struct rte_eth_dev *dev, 1251 struct rte_eth_rss_reta_entry64 *reta_conf, 1252 uint16_t reta_size) 1253 { 1254 struct port_info *pi = dev->data->dev_private; 1255 struct adapter *adapter = pi->adapter; 1256 u16 i, idx, shift, *rss; 1257 int ret; 1258 1259 if (!(adapter->flags & FULL_INIT_DONE)) 1260 return -ENOMEM; 1261 1262 if (!reta_size || reta_size > pi->rss_size) 1263 return -EINVAL; 1264 1265 rss = rte_calloc(NULL, pi->rss_size, sizeof(u16), 0); 1266 if (!rss) 1267 return -ENOMEM; 1268 1269 rte_memcpy(rss, pi->rss, pi->rss_size * sizeof(u16)); 1270 for (i = 0; i < reta_size; i++) { 1271 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1272 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1273 if (!(reta_conf[idx].mask & (1ULL << shift))) 1274 continue; 1275 1276 rss[i] = reta_conf[idx].reta[shift]; 1277 } 1278 1279 ret = cxgbe_write_rss(pi, rss); 1280 if (!ret) 1281 rte_memcpy(pi->rss, rss, pi->rss_size * sizeof(u16)); 1282 1283 rte_free(rss); 1284 return ret; 1285 } 1286 1287 static int cxgbe_dev_rss_reta_query(struct rte_eth_dev *dev, 1288 struct rte_eth_rss_reta_entry64 *reta_conf, 1289 uint16_t reta_size) 1290 { 1291 struct port_info *pi = dev->data->dev_private; 1292 struct adapter *adapter = pi->adapter; 1293 u16 i, idx, shift; 1294 1295 if (!(adapter->flags & FULL_INIT_DONE)) 1296 return -ENOMEM; 1297 1298 if (!reta_size || reta_size > pi->rss_size) 1299 return -EINVAL; 1300 1301 for (i = 0; i < reta_size; i++) { 1302 idx = i / RTE_ETH_RETA_GROUP_SIZE; 1303 shift = i % RTE_ETH_RETA_GROUP_SIZE; 1304 if (!(reta_conf[idx].mask & (1ULL << shift))) 1305 continue; 1306 1307 reta_conf[idx].reta[shift] = pi->rss[i]; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 1314 { 1315 RTE_SET_USED(dev); 1316 return EEPROMSIZE; 1317 } 1318 1319 /** 1320 * eeprom_ptov - translate a physical EEPROM address to virtual 1321 * @phys_addr: the physical EEPROM address 1322 * @fn: the PCI function number 1323 * @sz: size of function-specific area 1324 * 1325 * Translate a physical EEPROM address to virtual. The first 1K is 1326 * accessed through virtual addresses starting at 31K, the rest is 1327 * accessed through virtual addresses starting at 0. 1328 * 1329 * The mapping is as follows: 1330 * [0..1K) -> [31K..32K) 1331 * [1K..1K+A) -> [31K-A..31K) 1332 * [1K+A..ES) -> [0..ES-A-1K) 1333 * 1334 * where A = @fn * @sz, and ES = EEPROM size. 1335 */ 1336 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 1337 { 1338 fn *= sz; 1339 if (phys_addr < 1024) 1340 return phys_addr + (31 << 10); 1341 if (phys_addr < 1024 + fn) 1342 return fn + phys_addr - 1024; 1343 if (phys_addr < EEPROMSIZE) 1344 return phys_addr - 1024 - fn; 1345 if (phys_addr < EEPROMVSIZE) 1346 return phys_addr - 1024; 1347 return -EINVAL; 1348 } 1349 1350 /* The next two routines implement eeprom read/write from physical addresses. 1351 */ 1352 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 1353 { 1354 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1355 1356 if (vaddr >= 0) 1357 vaddr = t4_seeprom_read(adap, vaddr, v); 1358 return vaddr < 0 ? vaddr : 0; 1359 } 1360 1361 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 1362 { 1363 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 1364 1365 if (vaddr >= 0) 1366 vaddr = t4_seeprom_write(adap, vaddr, v); 1367 return vaddr < 0 ? vaddr : 0; 1368 } 1369 1370 #define EEPROM_MAGIC 0x38E2F10C 1371 1372 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 1373 struct rte_dev_eeprom_info *e) 1374 { 1375 struct port_info *pi = dev->data->dev_private; 1376 struct adapter *adapter = pi->adapter; 1377 u32 i, err = 0; 1378 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 1379 1380 if (!buf) 1381 return -ENOMEM; 1382 1383 e->magic = EEPROM_MAGIC; 1384 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 1385 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 1386 1387 if (!err) 1388 rte_memcpy(e->data, buf + e->offset, e->length); 1389 rte_free(buf); 1390 return err; 1391 } 1392 1393 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 1394 struct rte_dev_eeprom_info *eeprom) 1395 { 1396 struct port_info *pi = dev->data->dev_private; 1397 struct adapter *adapter = pi->adapter; 1398 u8 *buf; 1399 int err = 0; 1400 u32 aligned_offset, aligned_len, *p; 1401 1402 if (eeprom->magic != EEPROM_MAGIC) 1403 return -EINVAL; 1404 1405 aligned_offset = eeprom->offset & ~3; 1406 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1407 1408 if (adapter->pf > 0) { 1409 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1410 1411 if (aligned_offset < start || 1412 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1413 return -EPERM; 1414 } 1415 1416 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1417 /* RMW possibly needed for first or last words. 1418 */ 1419 buf = rte_zmalloc(NULL, aligned_len, 0); 1420 if (!buf) 1421 return -ENOMEM; 1422 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1423 if (!err && aligned_len > 4) 1424 err = eeprom_rd_phys(adapter, 1425 aligned_offset + aligned_len - 4, 1426 (u32 *)&buf[aligned_len - 4]); 1427 if (err) 1428 goto out; 1429 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1430 eeprom->length); 1431 } else { 1432 buf = eeprom->data; 1433 } 1434 1435 err = t4_seeprom_wp(adapter, false); 1436 if (err) 1437 goto out; 1438 1439 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1440 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1441 aligned_offset += 4; 1442 } 1443 1444 if (!err) 1445 err = t4_seeprom_wp(adapter, true); 1446 out: 1447 if (buf != eeprom->data) 1448 rte_free(buf); 1449 return err; 1450 } 1451 1452 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1453 { 1454 struct port_info *pi = eth_dev->data->dev_private; 1455 struct adapter *adapter = pi->adapter; 1456 1457 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1458 } 1459 1460 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1461 struct rte_dev_reg_info *regs) 1462 { 1463 struct port_info *pi = eth_dev->data->dev_private; 1464 struct adapter *adapter = pi->adapter; 1465 1466 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1467 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1468 (1 << 16); 1469 1470 if (regs->data == NULL) { 1471 regs->length = cxgbe_get_regs_len(eth_dev); 1472 regs->width = sizeof(uint32_t); 1473 1474 return 0; 1475 } 1476 1477 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1478 1479 return 0; 1480 } 1481 1482 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1483 { 1484 struct port_info *pi = dev->data->dev_private; 1485 int ret; 1486 1487 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1488 if (ret < 0) { 1489 dev_err(adapter, "failed to set mac addr; err = %d\n", 1490 ret); 1491 return ret; 1492 } 1493 pi->xact_addr_filt = ret; 1494 return 0; 1495 } 1496 1497 static int cxgbe_fec_get_capa_speed_to_fec(struct link_config *lc, 1498 struct rte_eth_fec_capa *capa_arr) 1499 { 1500 int num = 0; 1501 1502 if (lc->pcaps & FW_PORT_CAP32_SPEED_100G) { 1503 if (capa_arr) { 1504 capa_arr[num].speed = RTE_ETH_SPEED_NUM_100G; 1505 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1506 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1507 } 1508 num++; 1509 } 1510 1511 if (lc->pcaps & FW_PORT_CAP32_SPEED_50G) { 1512 if (capa_arr) { 1513 capa_arr[num].speed = RTE_ETH_SPEED_NUM_50G; 1514 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1515 RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1516 } 1517 num++; 1518 } 1519 1520 if (lc->pcaps & FW_PORT_CAP32_SPEED_25G) { 1521 if (capa_arr) { 1522 capa_arr[num].speed = RTE_ETH_SPEED_NUM_25G; 1523 capa_arr[num].capa = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC) | 1524 RTE_ETH_FEC_MODE_CAPA_MASK(BASER) | 1525 RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1526 } 1527 num++; 1528 } 1529 1530 return num; 1531 } 1532 1533 static int cxgbe_fec_get_capability(struct rte_eth_dev *dev, 1534 struct rte_eth_fec_capa *speed_fec_capa, 1535 unsigned int num) 1536 { 1537 struct port_info *pi = dev->data->dev_private; 1538 struct link_config *lc = &pi->link_cfg; 1539 u8 num_entries; 1540 1541 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1542 return -EOPNOTSUPP; 1543 1544 num_entries = cxgbe_fec_get_capa_speed_to_fec(lc, NULL); 1545 if (!speed_fec_capa || num < num_entries) 1546 return num_entries; 1547 1548 return cxgbe_fec_get_capa_speed_to_fec(lc, speed_fec_capa); 1549 } 1550 1551 static int cxgbe_fec_get(struct rte_eth_dev *dev, uint32_t *fec_capa) 1552 { 1553 struct port_info *pi = dev->data->dev_private; 1554 struct link_config *lc = &pi->link_cfg; 1555 u32 fec_caps = 0, caps = lc->link_caps; 1556 1557 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1558 return -EOPNOTSUPP; 1559 1560 if (caps & FW_PORT_CAP32_FEC_RS) 1561 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(RS); 1562 else if (caps & FW_PORT_CAP32_FEC_BASER_RS) 1563 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(BASER); 1564 else 1565 fec_caps = RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC); 1566 1567 *fec_capa = fec_caps; 1568 return 0; 1569 } 1570 1571 static int cxgbe_fec_set(struct rte_eth_dev *dev, uint32_t fec_capa) 1572 { 1573 struct port_info *pi = dev->data->dev_private; 1574 u8 fec_rs = 0, fec_baser = 0, fec_none = 0; 1575 struct link_config *lc = &pi->link_cfg; 1576 u32 new_caps = lc->admin_caps; 1577 int ret; 1578 1579 if (!(lc->pcaps & V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC))) 1580 return -EOPNOTSUPP; 1581 1582 if (!fec_capa) 1583 return -EINVAL; 1584 1585 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(AUTO)) 1586 goto set_fec; 1587 1588 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(NOFEC)) 1589 fec_none = 1; 1590 1591 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(BASER)) 1592 fec_baser = 1; 1593 1594 if (fec_capa & RTE_ETH_FEC_MODE_CAPA_MASK(RS)) 1595 fec_rs = 1; 1596 1597 set_fec: 1598 ret = t4_set_link_fec(pi, fec_rs, fec_baser, fec_none, &new_caps); 1599 if (ret != 0) 1600 return ret; 1601 1602 if (lc->pcaps & FW_PORT_CAP32_FORCE_FEC) 1603 new_caps |= FW_PORT_CAP32_FORCE_FEC; 1604 else 1605 new_caps &= ~FW_PORT_CAP32_FORCE_FEC; 1606 1607 if (new_caps != lc->admin_caps) { 1608 ret = t4_link_l1cfg(pi, new_caps); 1609 if (ret == 0) 1610 lc->admin_caps = new_caps; 1611 } 1612 1613 return ret; 1614 } 1615 1616 int cxgbe_fw_version_get(struct rte_eth_dev *dev, char *fw_version, 1617 size_t fw_size) 1618 { 1619 struct port_info *pi = dev->data->dev_private; 1620 struct adapter *adapter = pi->adapter; 1621 int ret; 1622 1623 if (adapter->params.fw_vers == 0) 1624 return -EIO; 1625 1626 ret = snprintf(fw_version, fw_size, "%u.%u.%u.%u", 1627 G_FW_HDR_FW_VER_MAJOR(adapter->params.fw_vers), 1628 G_FW_HDR_FW_VER_MINOR(adapter->params.fw_vers), 1629 G_FW_HDR_FW_VER_MICRO(adapter->params.fw_vers), 1630 G_FW_HDR_FW_VER_BUILD(adapter->params.fw_vers)); 1631 if (ret < 0) 1632 return -EINVAL; 1633 1634 ret += 1; 1635 if (fw_size < (size_t)ret) 1636 return ret; 1637 1638 return 0; 1639 } 1640 1641 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1642 .dev_start = cxgbe_dev_start, 1643 .dev_stop = cxgbe_dev_stop, 1644 .dev_close = cxgbe_dev_close, 1645 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1646 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1647 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1648 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1649 .dev_configure = cxgbe_dev_configure, 1650 .dev_infos_get = cxgbe_dev_info_get, 1651 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1652 .link_update = cxgbe_dev_link_update, 1653 .dev_set_link_up = cxgbe_dev_set_link_up, 1654 .dev_set_link_down = cxgbe_dev_set_link_down, 1655 .mtu_set = cxgbe_dev_mtu_set, 1656 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1657 .tx_queue_start = cxgbe_dev_tx_queue_start, 1658 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1659 .tx_queue_release = cxgbe_dev_tx_queue_release, 1660 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1661 .rx_queue_start = cxgbe_dev_rx_queue_start, 1662 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1663 .rx_queue_release = cxgbe_dev_rx_queue_release, 1664 .flow_ops_get = cxgbe_dev_flow_ops_get, 1665 .stats_get = cxgbe_dev_stats_get, 1666 .stats_reset = cxgbe_dev_stats_reset, 1667 .xstats_get = cxgbe_dev_xstats_get, 1668 .xstats_get_by_id = cxgbe_dev_xstats_get_by_id, 1669 .xstats_get_names = cxgbe_dev_xstats_get_names, 1670 .xstats_get_names_by_id = cxgbe_dev_xstats_get_names_by_id, 1671 .xstats_reset = cxgbe_dev_xstats_reset, 1672 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1673 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1674 .get_eeprom_length = cxgbe_get_eeprom_length, 1675 .get_eeprom = cxgbe_get_eeprom, 1676 .set_eeprom = cxgbe_set_eeprom, 1677 .get_reg = cxgbe_get_regs, 1678 .rss_hash_update = cxgbe_dev_rss_hash_update, 1679 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1680 .mac_addr_set = cxgbe_mac_addr_set, 1681 .reta_update = cxgbe_dev_rss_reta_update, 1682 .reta_query = cxgbe_dev_rss_reta_query, 1683 .fec_get_capability = cxgbe_fec_get_capability, 1684 .fec_get = cxgbe_fec_get, 1685 .fec_set = cxgbe_fec_set, 1686 .fw_version_get = cxgbe_fw_version_get, 1687 }; 1688 1689 /* 1690 * Initialize driver 1691 * It returns 0 on success. 1692 */ 1693 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1694 { 1695 struct rte_pci_device *pci_dev; 1696 struct port_info *pi = eth_dev->data->dev_private; 1697 struct adapter *adapter = NULL; 1698 char name[RTE_ETH_NAME_MAX_LEN]; 1699 int err = 0; 1700 1701 CXGBE_FUNC_TRACE(); 1702 1703 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1704 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1705 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1706 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1707 1708 /* for secondary processes, we attach to ethdevs allocated by primary 1709 * and do minimal initialization. 1710 */ 1711 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1712 int i; 1713 1714 for (i = 1; i < MAX_NPORTS; i++) { 1715 struct rte_eth_dev *rest_eth_dev; 1716 char namei[RTE_ETH_NAME_MAX_LEN]; 1717 1718 snprintf(namei, sizeof(namei), "%s_%d", 1719 pci_dev->device.name, i); 1720 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1721 if (rest_eth_dev) { 1722 rest_eth_dev->device = &pci_dev->device; 1723 rest_eth_dev->dev_ops = 1724 eth_dev->dev_ops; 1725 rest_eth_dev->rx_pkt_burst = 1726 eth_dev->rx_pkt_burst; 1727 rest_eth_dev->tx_pkt_burst = 1728 eth_dev->tx_pkt_burst; 1729 rte_eth_dev_probing_finish(rest_eth_dev); 1730 } 1731 } 1732 return 0; 1733 } 1734 1735 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1736 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1737 if (!adapter) 1738 return -1; 1739 1740 adapter->use_unpacked_mode = 1; 1741 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1742 if (!adapter->regs) { 1743 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1744 err = -ENOMEM; 1745 goto out_free_adapter; 1746 } 1747 adapter->pdev = pci_dev; 1748 adapter->eth_dev = eth_dev; 1749 pi->adapter = adapter; 1750 1751 cxgbe_process_devargs(adapter); 1752 1753 err = cxgbe_probe(adapter); 1754 if (err) { 1755 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1756 __func__, err); 1757 goto out_free_adapter; 1758 } 1759 1760 return 0; 1761 1762 out_free_adapter: 1763 rte_free(adapter); 1764 return err; 1765 } 1766 1767 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1768 { 1769 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1770 uint16_t port_id; 1771 int err = 0; 1772 1773 /* Free up other ports and all resources */ 1774 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 1775 err |= rte_eth_dev_close(port_id); 1776 1777 return err == 0 ? 0 : -EIO; 1778 } 1779 1780 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1781 struct rte_pci_device *pci_dev) 1782 { 1783 return rte_eth_dev_pci_generic_probe(pci_dev, 1784 sizeof(struct port_info), eth_cxgbe_dev_init); 1785 } 1786 1787 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1788 { 1789 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1790 } 1791 1792 static struct rte_pci_driver rte_cxgbe_pmd = { 1793 .id_table = cxgb4_pci_tbl, 1794 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1795 .probe = eth_cxgbe_pci_probe, 1796 .remove = eth_cxgbe_pci_remove, 1797 }; 1798 1799 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1800 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1801 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1802 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1803 CXGBE_DEVARG_CMN_KEEP_OVLAN "=<0|1> " 1804 CXGBE_DEVARG_CMN_TX_MODE_LATENCY "=<0|1> " 1805 CXGBE_DEVARG_PF_FILTER_MODE "=<uint32> " 1806 CXGBE_DEVARG_PF_FILTER_MASK "=<uint32> "); 1807 RTE_LOG_REGISTER_DEFAULT(cxgbe_logtype, NOTICE); 1808 RTE_LOG_REGISTER_SUFFIX(cxgbe_mbox_logtype, mbox, NOTICE); 1809