1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #include <sys/queue.h> 7 #include <stdio.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <unistd.h> 12 #include <stdarg.h> 13 #include <inttypes.h> 14 #include <netinet/in.h> 15 16 #include <rte_byteorder.h> 17 #include <rte_common.h> 18 #include <rte_cycles.h> 19 #include <rte_interrupts.h> 20 #include <rte_log.h> 21 #include <rte_debug.h> 22 #include <rte_pci.h> 23 #include <rte_bus_pci.h> 24 #include <rte_atomic.h> 25 #include <rte_branch_prediction.h> 26 #include <rte_memory.h> 27 #include <rte_tailq.h> 28 #include <rte_eal.h> 29 #include <rte_alarm.h> 30 #include <rte_ether.h> 31 #include <rte_ethdev_driver.h> 32 #include <rte_ethdev_pci.h> 33 #include <rte_malloc.h> 34 #include <rte_random.h> 35 #include <rte_dev.h> 36 37 #include "cxgbe.h" 38 #include "cxgbe_pfvf.h" 39 #include "cxgbe_flow.h" 40 41 int cxgbe_logtype; 42 43 /* 44 * Macros needed to support the PCI Device ID Table ... 45 */ 46 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 47 static const struct rte_pci_id cxgb4_pci_tbl[] = { 48 #define CH_PCI_DEVICE_ID_FUNCTION 0x4 49 50 #define PCI_VENDOR_ID_CHELSIO 0x1425 51 52 #define CH_PCI_ID_TABLE_ENTRY(devid) \ 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_CHELSIO, (devid)) } 54 55 #define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \ 56 { .vendor_id = 0, } \ 57 } 58 59 /* 60 *... and the PCI ID Table itself ... 61 */ 62 #include "base/t4_pci_id_tbl.h" 63 64 uint16_t cxgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 65 uint16_t nb_pkts) 66 { 67 struct sge_eth_txq *txq = (struct sge_eth_txq *)tx_queue; 68 uint16_t pkts_sent, pkts_remain; 69 uint16_t total_sent = 0; 70 uint16_t idx = 0; 71 int ret = 0; 72 73 CXGBE_DEBUG_TX(adapter, "%s: txq = %p; tx_pkts = %p; nb_pkts = %d\n", 74 __func__, txq, tx_pkts, nb_pkts); 75 76 t4_os_lock(&txq->txq_lock); 77 /* free up desc from already completed tx */ 78 reclaim_completed_tx(&txq->q); 79 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[0], volatile void *)); 80 while (total_sent < nb_pkts) { 81 pkts_remain = nb_pkts - total_sent; 82 83 for (pkts_sent = 0; pkts_sent < pkts_remain; pkts_sent++) { 84 idx = total_sent + pkts_sent; 85 if ((idx + 1) < nb_pkts) 86 rte_prefetch0(rte_pktmbuf_mtod(tx_pkts[idx + 1], 87 volatile void *)); 88 ret = t4_eth_xmit(txq, tx_pkts[idx], nb_pkts); 89 if (ret < 0) 90 break; 91 } 92 if (!pkts_sent) 93 break; 94 total_sent += pkts_sent; 95 /* reclaim as much as possible */ 96 reclaim_completed_tx(&txq->q); 97 } 98 99 t4_os_unlock(&txq->txq_lock); 100 return total_sent; 101 } 102 103 uint16_t cxgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 104 uint16_t nb_pkts) 105 { 106 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)rx_queue; 107 unsigned int work_done; 108 109 CXGBE_DEBUG_RX(adapter, "%s: rxq->rspq.cntxt_id = %u; nb_pkts = %d\n", 110 __func__, rxq->rspq.cntxt_id, nb_pkts); 111 112 if (cxgbe_poll(&rxq->rspq, rx_pkts, (unsigned int)nb_pkts, &work_done)) 113 dev_err(adapter, "error in cxgbe poll\n"); 114 115 CXGBE_DEBUG_RX(adapter, "%s: work_done = %u\n", __func__, work_done); 116 return work_done; 117 } 118 119 int cxgbe_dev_info_get(struct rte_eth_dev *eth_dev, 120 struct rte_eth_dev_info *device_info) 121 { 122 struct port_info *pi = eth_dev->data->dev_private; 123 struct adapter *adapter = pi->adapter; 124 int max_queues = adapter->sge.max_ethqsets / adapter->params.nports; 125 126 static const struct rte_eth_desc_lim cxgbe_desc_lim = { 127 .nb_max = CXGBE_MAX_RING_DESC_SIZE, 128 .nb_min = CXGBE_MIN_RING_DESC_SIZE, 129 .nb_align = 1, 130 }; 131 132 device_info->min_rx_bufsize = CXGBE_MIN_RX_BUFSIZE; 133 device_info->max_rx_pktlen = CXGBE_MAX_RX_PKTLEN; 134 device_info->max_rx_queues = max_queues; 135 device_info->max_tx_queues = max_queues; 136 device_info->max_mac_addrs = 1; 137 /* XXX: For now we support one MAC/port */ 138 device_info->max_vfs = adapter->params.arch.vfcount; 139 device_info->max_vmdq_pools = 0; /* XXX: For now no support for VMDQ */ 140 141 device_info->rx_queue_offload_capa = 0UL; 142 device_info->rx_offload_capa = CXGBE_RX_OFFLOADS; 143 144 device_info->tx_queue_offload_capa = 0UL; 145 device_info->tx_offload_capa = CXGBE_TX_OFFLOADS; 146 147 device_info->reta_size = pi->rss_size; 148 device_info->hash_key_size = CXGBE_DEFAULT_RSS_KEY_LEN; 149 device_info->flow_type_rss_offloads = CXGBE_RSS_HF_ALL; 150 151 device_info->rx_desc_lim = cxgbe_desc_lim; 152 device_info->tx_desc_lim = cxgbe_desc_lim; 153 cxgbe_get_speed_caps(pi, &device_info->speed_capa); 154 155 return 0; 156 } 157 158 int cxgbe_dev_promiscuous_enable(struct rte_eth_dev *eth_dev) 159 { 160 struct port_info *pi = eth_dev->data->dev_private; 161 struct adapter *adapter = pi->adapter; 162 163 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 164 1, -1, 1, -1, false); 165 } 166 167 int cxgbe_dev_promiscuous_disable(struct rte_eth_dev *eth_dev) 168 { 169 struct port_info *pi = eth_dev->data->dev_private; 170 struct adapter *adapter = pi->adapter; 171 172 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 173 0, -1, 1, -1, false); 174 } 175 176 int cxgbe_dev_allmulticast_enable(struct rte_eth_dev *eth_dev) 177 { 178 struct port_info *pi = eth_dev->data->dev_private; 179 struct adapter *adapter = pi->adapter; 180 181 /* TODO: address filters ?? */ 182 183 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 184 -1, 1, 1, -1, false); 185 } 186 187 int cxgbe_dev_allmulticast_disable(struct rte_eth_dev *eth_dev) 188 { 189 struct port_info *pi = eth_dev->data->dev_private; 190 struct adapter *adapter = pi->adapter; 191 192 /* TODO: address filters ?? */ 193 194 return t4_set_rxmode(adapter, adapter->mbox, pi->viid, -1, 195 -1, 0, 1, -1, false); 196 } 197 198 int cxgbe_dev_link_update(struct rte_eth_dev *eth_dev, 199 int wait_to_complete) 200 { 201 struct port_info *pi = eth_dev->data->dev_private; 202 struct adapter *adapter = pi->adapter; 203 struct sge *s = &adapter->sge; 204 struct rte_eth_link new_link = { 0 }; 205 unsigned int i, work_done, budget = 32; 206 u8 old_link = pi->link_cfg.link_ok; 207 208 for (i = 0; i < CXGBE_LINK_STATUS_POLL_CNT; i++) { 209 if (!s->fw_evtq.desc) 210 break; 211 212 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 213 214 /* Exit if link status changed or always forced up */ 215 if (pi->link_cfg.link_ok != old_link || 216 cxgbe_force_linkup(adapter)) 217 break; 218 219 if (!wait_to_complete) 220 break; 221 222 rte_delay_ms(CXGBE_LINK_STATUS_POLL_MS); 223 } 224 225 new_link.link_status = cxgbe_force_linkup(adapter) ? 226 ETH_LINK_UP : pi->link_cfg.link_ok; 227 new_link.link_autoneg = pi->link_cfg.autoneg; 228 new_link.link_duplex = ETH_LINK_FULL_DUPLEX; 229 new_link.link_speed = pi->link_cfg.speed; 230 231 return rte_eth_linkstatus_set(eth_dev, &new_link); 232 } 233 234 /** 235 * Set device link up. 236 */ 237 int cxgbe_dev_set_link_up(struct rte_eth_dev *dev) 238 { 239 struct port_info *pi = dev->data->dev_private; 240 struct adapter *adapter = pi->adapter; 241 unsigned int work_done, budget = 32; 242 struct sge *s = &adapter->sge; 243 int ret; 244 245 if (!s->fw_evtq.desc) 246 return -ENOMEM; 247 248 /* Flush all link events */ 249 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 250 251 /* If link already up, nothing to do */ 252 if (pi->link_cfg.link_ok) 253 return 0; 254 255 ret = cxgbe_set_link_status(pi, true); 256 if (ret) 257 return ret; 258 259 cxgbe_dev_link_update(dev, 1); 260 return 0; 261 } 262 263 /** 264 * Set device link down. 265 */ 266 int cxgbe_dev_set_link_down(struct rte_eth_dev *dev) 267 { 268 struct port_info *pi = dev->data->dev_private; 269 struct adapter *adapter = pi->adapter; 270 unsigned int work_done, budget = 32; 271 struct sge *s = &adapter->sge; 272 int ret; 273 274 if (!s->fw_evtq.desc) 275 return -ENOMEM; 276 277 /* Flush all link events */ 278 cxgbe_poll(&s->fw_evtq, NULL, budget, &work_done); 279 280 /* If link already down, nothing to do */ 281 if (!pi->link_cfg.link_ok) 282 return 0; 283 284 ret = cxgbe_set_link_status(pi, false); 285 if (ret) 286 return ret; 287 288 cxgbe_dev_link_update(dev, 0); 289 return 0; 290 } 291 292 int cxgbe_dev_mtu_set(struct rte_eth_dev *eth_dev, uint16_t mtu) 293 { 294 struct port_info *pi = eth_dev->data->dev_private; 295 struct adapter *adapter = pi->adapter; 296 struct rte_eth_dev_info dev_info; 297 int err; 298 uint16_t new_mtu = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN; 299 300 err = cxgbe_dev_info_get(eth_dev, &dev_info); 301 if (err != 0) 302 return err; 303 304 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 305 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > dev_info.max_rx_pktlen) 306 return -EINVAL; 307 308 /* set to jumbo mode if needed */ 309 if (new_mtu > RTE_ETHER_MAX_LEN) 310 eth_dev->data->dev_conf.rxmode.offloads |= 311 DEV_RX_OFFLOAD_JUMBO_FRAME; 312 else 313 eth_dev->data->dev_conf.rxmode.offloads &= 314 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 315 316 err = t4_set_rxmode(adapter, adapter->mbox, pi->viid, new_mtu, -1, -1, 317 -1, -1, true); 318 if (!err) 319 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_mtu; 320 321 return err; 322 } 323 324 /* 325 * Stop device. 326 */ 327 void cxgbe_dev_close(struct rte_eth_dev *eth_dev) 328 { 329 struct port_info *pi = eth_dev->data->dev_private; 330 struct adapter *adapter = pi->adapter; 331 332 CXGBE_FUNC_TRACE(); 333 334 if (!(adapter->flags & FULL_INIT_DONE)) 335 return; 336 337 cxgbe_down(pi); 338 339 /* 340 * We clear queues only if both tx and rx path of the port 341 * have been disabled 342 */ 343 t4_sge_eth_clear_queues(pi); 344 } 345 346 /* Start the device. 347 * It returns 0 on success. 348 */ 349 int cxgbe_dev_start(struct rte_eth_dev *eth_dev) 350 { 351 struct port_info *pi = eth_dev->data->dev_private; 352 struct rte_eth_rxmode *rx_conf = ð_dev->data->dev_conf.rxmode; 353 struct adapter *adapter = pi->adapter; 354 int err = 0, i; 355 356 CXGBE_FUNC_TRACE(); 357 358 /* 359 * If we don't have a connection to the firmware there's nothing we 360 * can do. 361 */ 362 if (!(adapter->flags & FW_OK)) { 363 err = -ENXIO; 364 goto out; 365 } 366 367 if (!(adapter->flags & FULL_INIT_DONE)) { 368 err = cxgbe_up(adapter); 369 if (err < 0) 370 goto out; 371 } 372 373 if (rx_conf->offloads & DEV_RX_OFFLOAD_SCATTER) 374 eth_dev->data->scattered_rx = 1; 375 else 376 eth_dev->data->scattered_rx = 0; 377 378 cxgbe_enable_rx_queues(pi); 379 380 err = cxgbe_setup_rss(pi); 381 if (err) 382 goto out; 383 384 for (i = 0; i < pi->n_tx_qsets; i++) { 385 err = cxgbe_dev_tx_queue_start(eth_dev, i); 386 if (err) 387 goto out; 388 } 389 390 for (i = 0; i < pi->n_rx_qsets; i++) { 391 err = cxgbe_dev_rx_queue_start(eth_dev, i); 392 if (err) 393 goto out; 394 } 395 396 err = cxgbe_link_start(pi); 397 if (err) 398 goto out; 399 400 out: 401 return err; 402 } 403 404 /* 405 * Stop device: disable rx and tx functions to allow for reconfiguring. 406 */ 407 void cxgbe_dev_stop(struct rte_eth_dev *eth_dev) 408 { 409 struct port_info *pi = eth_dev->data->dev_private; 410 struct adapter *adapter = pi->adapter; 411 412 CXGBE_FUNC_TRACE(); 413 414 if (!(adapter->flags & FULL_INIT_DONE)) 415 return; 416 417 cxgbe_down(pi); 418 419 /* 420 * We clear queues only if both tx and rx path of the port 421 * have been disabled 422 */ 423 t4_sge_eth_clear_queues(pi); 424 eth_dev->data->scattered_rx = 0; 425 } 426 427 int cxgbe_dev_configure(struct rte_eth_dev *eth_dev) 428 { 429 struct port_info *pi = eth_dev->data->dev_private; 430 struct adapter *adapter = pi->adapter; 431 int err; 432 433 CXGBE_FUNC_TRACE(); 434 435 if (!(adapter->flags & FW_QUEUE_BOUND)) { 436 err = cxgbe_setup_sge_fwevtq(adapter); 437 if (err) 438 return err; 439 adapter->flags |= FW_QUEUE_BOUND; 440 if (is_pf4(adapter)) { 441 err = cxgbe_setup_sge_ctrl_txq(adapter); 442 if (err) 443 return err; 444 } 445 } 446 447 err = cxgbe_cfg_queue_count(eth_dev); 448 if (err) 449 return err; 450 451 return 0; 452 } 453 454 int cxgbe_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 455 { 456 int ret; 457 struct sge_eth_txq *txq = (struct sge_eth_txq *) 458 (eth_dev->data->tx_queues[tx_queue_id]); 459 460 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 461 462 ret = t4_sge_eth_txq_start(txq); 463 if (ret == 0) 464 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 465 466 return ret; 467 } 468 469 int cxgbe_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id) 470 { 471 int ret; 472 struct sge_eth_txq *txq = (struct sge_eth_txq *) 473 (eth_dev->data->tx_queues[tx_queue_id]); 474 475 dev_debug(NULL, "%s: tx_queue_id = %d\n", __func__, tx_queue_id); 476 477 ret = t4_sge_eth_txq_stop(txq); 478 if (ret == 0) 479 eth_dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 480 481 return ret; 482 } 483 484 int cxgbe_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, 485 uint16_t queue_idx, uint16_t nb_desc, 486 unsigned int socket_id, 487 const struct rte_eth_txconf *tx_conf __rte_unused) 488 { 489 struct port_info *pi = eth_dev->data->dev_private; 490 struct adapter *adapter = pi->adapter; 491 struct sge *s = &adapter->sge; 492 struct sge_eth_txq *txq = &s->ethtxq[pi->first_qset + queue_idx]; 493 int err = 0; 494 unsigned int temp_nb_desc; 495 496 dev_debug(adapter, "%s: eth_dev->data->nb_tx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; pi->first_qset = %u\n", 497 __func__, eth_dev->data->nb_tx_queues, queue_idx, nb_desc, 498 socket_id, pi->first_qset); 499 500 /* Free up the existing queue */ 501 if (eth_dev->data->tx_queues[queue_idx]) { 502 cxgbe_dev_tx_queue_release(eth_dev->data->tx_queues[queue_idx]); 503 eth_dev->data->tx_queues[queue_idx] = NULL; 504 } 505 506 eth_dev->data->tx_queues[queue_idx] = (void *)txq; 507 508 /* Sanity Checking 509 * 510 * nb_desc should be > 1023 and <= CXGBE_MAX_RING_DESC_SIZE 511 */ 512 temp_nb_desc = nb_desc; 513 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 514 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 515 __func__, CXGBE_MIN_RING_DESC_SIZE, 516 CXGBE_DEFAULT_TX_DESC_SIZE); 517 temp_nb_desc = CXGBE_DEFAULT_TX_DESC_SIZE; 518 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 519 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 520 __func__, CXGBE_MIN_RING_DESC_SIZE, 521 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_TX_DESC_SIZE); 522 return -(EINVAL); 523 } 524 525 txq->q.size = temp_nb_desc; 526 527 err = t4_sge_alloc_eth_txq(adapter, txq, eth_dev, queue_idx, 528 s->fw_evtq.cntxt_id, socket_id); 529 530 dev_debug(adapter, "%s: txq->q.cntxt_id= %u txq->q.abs_id= %u err = %d\n", 531 __func__, txq->q.cntxt_id, txq->q.abs_id, err); 532 return err; 533 } 534 535 void cxgbe_dev_tx_queue_release(void *q) 536 { 537 struct sge_eth_txq *txq = (struct sge_eth_txq *)q; 538 539 if (txq) { 540 struct port_info *pi = (struct port_info *) 541 (txq->eth_dev->data->dev_private); 542 struct adapter *adap = pi->adapter; 543 544 dev_debug(adapter, "%s: pi->port_id = %d; tx_queue_id = %d\n", 545 __func__, pi->port_id, txq->q.cntxt_id); 546 547 t4_sge_eth_txq_release(adap, txq); 548 } 549 } 550 551 int cxgbe_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 552 { 553 int ret; 554 struct port_info *pi = eth_dev->data->dev_private; 555 struct adapter *adap = pi->adapter; 556 struct sge_rspq *q; 557 558 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 559 __func__, pi->port_id, rx_queue_id); 560 561 q = eth_dev->data->rx_queues[rx_queue_id]; 562 563 ret = t4_sge_eth_rxq_start(adap, q); 564 if (ret == 0) 565 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED; 566 567 return ret; 568 } 569 570 int cxgbe_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id) 571 { 572 int ret; 573 struct port_info *pi = eth_dev->data->dev_private; 574 struct adapter *adap = pi->adapter; 575 struct sge_rspq *q; 576 577 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 578 __func__, pi->port_id, rx_queue_id); 579 580 q = eth_dev->data->rx_queues[rx_queue_id]; 581 ret = t4_sge_eth_rxq_stop(adap, q); 582 if (ret == 0) 583 eth_dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED; 584 585 return ret; 586 } 587 588 int cxgbe_dev_rx_queue_setup(struct rte_eth_dev *eth_dev, 589 uint16_t queue_idx, uint16_t nb_desc, 590 unsigned int socket_id, 591 const struct rte_eth_rxconf *rx_conf __rte_unused, 592 struct rte_mempool *mp) 593 { 594 struct port_info *pi = eth_dev->data->dev_private; 595 struct adapter *adapter = pi->adapter; 596 struct sge *s = &adapter->sge; 597 struct sge_eth_rxq *rxq = &s->ethrxq[pi->first_qset + queue_idx]; 598 int err = 0; 599 int msi_idx = 0; 600 unsigned int temp_nb_desc; 601 struct rte_eth_dev_info dev_info; 602 unsigned int pkt_len = eth_dev->data->dev_conf.rxmode.max_rx_pkt_len; 603 604 dev_debug(adapter, "%s: eth_dev->data->nb_rx_queues = %d; queue_idx = %d; nb_desc = %d; socket_id = %d; mp = %p\n", 605 __func__, eth_dev->data->nb_rx_queues, queue_idx, nb_desc, 606 socket_id, mp); 607 608 err = cxgbe_dev_info_get(eth_dev, &dev_info); 609 if (err != 0) { 610 dev_err(adap, "%s: error during getting ethernet device info", 611 __func__); 612 return err; 613 } 614 615 /* Must accommodate at least RTE_ETHER_MIN_MTU */ 616 if ((pkt_len < dev_info.min_rx_bufsize) || 617 (pkt_len > dev_info.max_rx_pktlen)) { 618 dev_err(adap, "%s: max pkt len must be > %d and <= %d\n", 619 __func__, dev_info.min_rx_bufsize, 620 dev_info.max_rx_pktlen); 621 return -EINVAL; 622 } 623 624 /* Free up the existing queue */ 625 if (eth_dev->data->rx_queues[queue_idx]) { 626 cxgbe_dev_rx_queue_release(eth_dev->data->rx_queues[queue_idx]); 627 eth_dev->data->rx_queues[queue_idx] = NULL; 628 } 629 630 eth_dev->data->rx_queues[queue_idx] = (void *)rxq; 631 632 /* Sanity Checking 633 * 634 * nb_desc should be > 0 and <= CXGBE_MAX_RING_DESC_SIZE 635 */ 636 temp_nb_desc = nb_desc; 637 if (nb_desc < CXGBE_MIN_RING_DESC_SIZE) { 638 dev_warn(adapter, "%s: number of descriptors must be >= %d. Using default [%d]\n", 639 __func__, CXGBE_MIN_RING_DESC_SIZE, 640 CXGBE_DEFAULT_RX_DESC_SIZE); 641 temp_nb_desc = CXGBE_DEFAULT_RX_DESC_SIZE; 642 } else if (nb_desc > CXGBE_MAX_RING_DESC_SIZE) { 643 dev_err(adapter, "%s: number of descriptors must be between %d and %d inclusive. Default [%d]\n", 644 __func__, CXGBE_MIN_RING_DESC_SIZE, 645 CXGBE_MAX_RING_DESC_SIZE, CXGBE_DEFAULT_RX_DESC_SIZE); 646 return -(EINVAL); 647 } 648 649 rxq->rspq.size = temp_nb_desc; 650 if ((&rxq->fl) != NULL) 651 rxq->fl.size = temp_nb_desc; 652 653 /* Set to jumbo mode if necessary */ 654 if (pkt_len > RTE_ETHER_MAX_LEN) 655 eth_dev->data->dev_conf.rxmode.offloads |= 656 DEV_RX_OFFLOAD_JUMBO_FRAME; 657 else 658 eth_dev->data->dev_conf.rxmode.offloads &= 659 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 660 661 err = t4_sge_alloc_rxq(adapter, &rxq->rspq, false, eth_dev, msi_idx, 662 &rxq->fl, NULL, 663 is_pf4(adapter) ? 664 t4_get_tp_ch_map(adapter, pi->tx_chan) : 0, mp, 665 queue_idx, socket_id); 666 667 dev_debug(adapter, "%s: err = %d; port_id = %d; cntxt_id = %u; abs_id = %u\n", 668 __func__, err, pi->port_id, rxq->rspq.cntxt_id, 669 rxq->rspq.abs_id); 670 return err; 671 } 672 673 void cxgbe_dev_rx_queue_release(void *q) 674 { 675 struct sge_eth_rxq *rxq = (struct sge_eth_rxq *)q; 676 struct sge_rspq *rq = &rxq->rspq; 677 678 if (rq) { 679 struct port_info *pi = (struct port_info *) 680 (rq->eth_dev->data->dev_private); 681 struct adapter *adap = pi->adapter; 682 683 dev_debug(adapter, "%s: pi->port_id = %d; rx_queue_id = %d\n", 684 __func__, pi->port_id, rxq->rspq.cntxt_id); 685 686 t4_sge_eth_rxq_release(adap, rxq); 687 } 688 } 689 690 /* 691 * Get port statistics. 692 */ 693 static int cxgbe_dev_stats_get(struct rte_eth_dev *eth_dev, 694 struct rte_eth_stats *eth_stats) 695 { 696 struct port_info *pi = eth_dev->data->dev_private; 697 struct adapter *adapter = pi->adapter; 698 struct sge *s = &adapter->sge; 699 struct port_stats ps; 700 unsigned int i; 701 702 cxgbe_stats_get(pi, &ps); 703 704 /* RX Stats */ 705 eth_stats->imissed = ps.rx_ovflow0 + ps.rx_ovflow1 + 706 ps.rx_ovflow2 + ps.rx_ovflow3 + 707 ps.rx_trunc0 + ps.rx_trunc1 + 708 ps.rx_trunc2 + ps.rx_trunc3; 709 eth_stats->ierrors = ps.rx_symbol_err + ps.rx_fcs_err + 710 ps.rx_jabber + ps.rx_too_long + ps.rx_runt + 711 ps.rx_len_err; 712 713 /* TX Stats */ 714 eth_stats->opackets = ps.tx_frames; 715 eth_stats->obytes = ps.tx_octets; 716 eth_stats->oerrors = ps.tx_error_frames; 717 718 for (i = 0; i < pi->n_rx_qsets; i++) { 719 struct sge_eth_rxq *rxq = 720 &s->ethrxq[pi->first_qset + i]; 721 722 eth_stats->q_ipackets[i] = rxq->stats.pkts; 723 eth_stats->q_ibytes[i] = rxq->stats.rx_bytes; 724 eth_stats->ipackets += eth_stats->q_ipackets[i]; 725 eth_stats->ibytes += eth_stats->q_ibytes[i]; 726 } 727 728 for (i = 0; i < pi->n_tx_qsets; i++) { 729 struct sge_eth_txq *txq = 730 &s->ethtxq[pi->first_qset + i]; 731 732 eth_stats->q_opackets[i] = txq->stats.pkts; 733 eth_stats->q_obytes[i] = txq->stats.tx_bytes; 734 } 735 return 0; 736 } 737 738 /* 739 * Reset port statistics. 740 */ 741 static int cxgbe_dev_stats_reset(struct rte_eth_dev *eth_dev) 742 { 743 struct port_info *pi = eth_dev->data->dev_private; 744 struct adapter *adapter = pi->adapter; 745 struct sge *s = &adapter->sge; 746 unsigned int i; 747 748 cxgbe_stats_reset(pi); 749 for (i = 0; i < pi->n_rx_qsets; i++) { 750 struct sge_eth_rxq *rxq = 751 &s->ethrxq[pi->first_qset + i]; 752 753 rxq->stats.pkts = 0; 754 rxq->stats.rx_bytes = 0; 755 } 756 for (i = 0; i < pi->n_tx_qsets; i++) { 757 struct sge_eth_txq *txq = 758 &s->ethtxq[pi->first_qset + i]; 759 760 txq->stats.pkts = 0; 761 txq->stats.tx_bytes = 0; 762 txq->stats.mapping_err = 0; 763 } 764 765 return 0; 766 } 767 768 static int cxgbe_flow_ctrl_get(struct rte_eth_dev *eth_dev, 769 struct rte_eth_fc_conf *fc_conf) 770 { 771 struct port_info *pi = eth_dev->data->dev_private; 772 struct link_config *lc = &pi->link_cfg; 773 int rx_pause, tx_pause; 774 775 fc_conf->autoneg = lc->fc & PAUSE_AUTONEG; 776 rx_pause = lc->fc & PAUSE_RX; 777 tx_pause = lc->fc & PAUSE_TX; 778 779 if (rx_pause && tx_pause) 780 fc_conf->mode = RTE_FC_FULL; 781 else if (rx_pause) 782 fc_conf->mode = RTE_FC_RX_PAUSE; 783 else if (tx_pause) 784 fc_conf->mode = RTE_FC_TX_PAUSE; 785 else 786 fc_conf->mode = RTE_FC_NONE; 787 return 0; 788 } 789 790 static int cxgbe_flow_ctrl_set(struct rte_eth_dev *eth_dev, 791 struct rte_eth_fc_conf *fc_conf) 792 { 793 struct port_info *pi = eth_dev->data->dev_private; 794 struct adapter *adapter = pi->adapter; 795 struct link_config *lc = &pi->link_cfg; 796 797 if (lc->pcaps & FW_PORT_CAP32_ANEG) { 798 if (fc_conf->autoneg) 799 lc->requested_fc |= PAUSE_AUTONEG; 800 else 801 lc->requested_fc &= ~PAUSE_AUTONEG; 802 } 803 804 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 805 (fc_conf->mode & RTE_FC_RX_PAUSE)) 806 lc->requested_fc |= PAUSE_RX; 807 else 808 lc->requested_fc &= ~PAUSE_RX; 809 810 if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) || 811 (fc_conf->mode & RTE_FC_TX_PAUSE)) 812 lc->requested_fc |= PAUSE_TX; 813 else 814 lc->requested_fc &= ~PAUSE_TX; 815 816 return t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 817 &pi->link_cfg); 818 } 819 820 const uint32_t * 821 cxgbe_dev_supported_ptypes_get(struct rte_eth_dev *eth_dev) 822 { 823 static const uint32_t ptypes[] = { 824 RTE_PTYPE_L3_IPV4, 825 RTE_PTYPE_L3_IPV6, 826 RTE_PTYPE_UNKNOWN 827 }; 828 829 if (eth_dev->rx_pkt_burst == cxgbe_recv_pkts) 830 return ptypes; 831 return NULL; 832 } 833 834 /* Update RSS hash configuration 835 */ 836 static int cxgbe_dev_rss_hash_update(struct rte_eth_dev *dev, 837 struct rte_eth_rss_conf *rss_conf) 838 { 839 struct port_info *pi = dev->data->dev_private; 840 struct adapter *adapter = pi->adapter; 841 int err; 842 843 err = cxgbe_write_rss_conf(pi, rss_conf->rss_hf); 844 if (err) 845 return err; 846 847 pi->rss_hf = rss_conf->rss_hf; 848 849 if (rss_conf->rss_key) { 850 u32 key[10], mod_key[10]; 851 int i, j; 852 853 memcpy(key, rss_conf->rss_key, CXGBE_DEFAULT_RSS_KEY_LEN); 854 855 for (i = 9, j = 0; i >= 0; i--, j++) 856 mod_key[j] = cpu_to_be32(key[i]); 857 858 t4_write_rss_key(adapter, mod_key, -1); 859 } 860 861 return 0; 862 } 863 864 /* Get RSS hash configuration 865 */ 866 static int cxgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 867 struct rte_eth_rss_conf *rss_conf) 868 { 869 struct port_info *pi = dev->data->dev_private; 870 struct adapter *adapter = pi->adapter; 871 u64 rss_hf = 0; 872 u64 flags = 0; 873 int err; 874 875 err = t4_read_config_vi_rss(adapter, adapter->mbox, pi->viid, 876 &flags, NULL); 877 878 if (err) 879 return err; 880 881 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) { 882 rss_hf |= CXGBE_RSS_HF_TCP_IPV6_MASK; 883 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 884 rss_hf |= CXGBE_RSS_HF_UDP_IPV6_MASK; 885 } 886 887 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 888 rss_hf |= CXGBE_RSS_HF_IPV6_MASK; 889 890 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) { 891 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 892 if (flags & F_FW_RSS_VI_CONFIG_CMD_UDPEN) 893 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 894 } 895 896 if (flags & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 897 rss_hf |= CXGBE_RSS_HF_IPV4_MASK; 898 899 rss_conf->rss_hf = rss_hf; 900 901 if (rss_conf->rss_key) { 902 u32 key[10], mod_key[10]; 903 int i, j; 904 905 t4_read_rss_key(adapter, key); 906 907 for (i = 9, j = 0; i >= 0; i--, j++) 908 mod_key[j] = be32_to_cpu(key[i]); 909 910 memcpy(rss_conf->rss_key, mod_key, CXGBE_DEFAULT_RSS_KEY_LEN); 911 } 912 913 return 0; 914 } 915 916 static int cxgbe_get_eeprom_length(struct rte_eth_dev *dev) 917 { 918 RTE_SET_USED(dev); 919 return EEPROMSIZE; 920 } 921 922 /** 923 * eeprom_ptov - translate a physical EEPROM address to virtual 924 * @phys_addr: the physical EEPROM address 925 * @fn: the PCI function number 926 * @sz: size of function-specific area 927 * 928 * Translate a physical EEPROM address to virtual. The first 1K is 929 * accessed through virtual addresses starting at 31K, the rest is 930 * accessed through virtual addresses starting at 0. 931 * 932 * The mapping is as follows: 933 * [0..1K) -> [31K..32K) 934 * [1K..1K+A) -> [31K-A..31K) 935 * [1K+A..ES) -> [0..ES-A-1K) 936 * 937 * where A = @fn * @sz, and ES = EEPROM size. 938 */ 939 static int eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz) 940 { 941 fn *= sz; 942 if (phys_addr < 1024) 943 return phys_addr + (31 << 10); 944 if (phys_addr < 1024 + fn) 945 return fn + phys_addr - 1024; 946 if (phys_addr < EEPROMSIZE) 947 return phys_addr - 1024 - fn; 948 if (phys_addr < EEPROMVSIZE) 949 return phys_addr - 1024; 950 return -EINVAL; 951 } 952 953 /* The next two routines implement eeprom read/write from physical addresses. 954 */ 955 static int eeprom_rd_phys(struct adapter *adap, unsigned int phys_addr, u32 *v) 956 { 957 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 958 959 if (vaddr >= 0) 960 vaddr = t4_seeprom_read(adap, vaddr, v); 961 return vaddr < 0 ? vaddr : 0; 962 } 963 964 static int eeprom_wr_phys(struct adapter *adap, unsigned int phys_addr, u32 v) 965 { 966 int vaddr = eeprom_ptov(phys_addr, adap->pf, EEPROMPFSIZE); 967 968 if (vaddr >= 0) 969 vaddr = t4_seeprom_write(adap, vaddr, v); 970 return vaddr < 0 ? vaddr : 0; 971 } 972 973 #define EEPROM_MAGIC 0x38E2F10C 974 975 static int cxgbe_get_eeprom(struct rte_eth_dev *dev, 976 struct rte_dev_eeprom_info *e) 977 { 978 struct port_info *pi = dev->data->dev_private; 979 struct adapter *adapter = pi->adapter; 980 u32 i, err = 0; 981 u8 *buf = rte_zmalloc(NULL, EEPROMSIZE, 0); 982 983 if (!buf) 984 return -ENOMEM; 985 986 e->magic = EEPROM_MAGIC; 987 for (i = e->offset & ~3; !err && i < e->offset + e->length; i += 4) 988 err = eeprom_rd_phys(adapter, i, (u32 *)&buf[i]); 989 990 if (!err) 991 rte_memcpy(e->data, buf + e->offset, e->length); 992 rte_free(buf); 993 return err; 994 } 995 996 static int cxgbe_set_eeprom(struct rte_eth_dev *dev, 997 struct rte_dev_eeprom_info *eeprom) 998 { 999 struct port_info *pi = dev->data->dev_private; 1000 struct adapter *adapter = pi->adapter; 1001 u8 *buf; 1002 int err = 0; 1003 u32 aligned_offset, aligned_len, *p; 1004 1005 if (eeprom->magic != EEPROM_MAGIC) 1006 return -EINVAL; 1007 1008 aligned_offset = eeprom->offset & ~3; 1009 aligned_len = (eeprom->length + (eeprom->offset & 3) + 3) & ~3; 1010 1011 if (adapter->pf > 0) { 1012 u32 start = 1024 + adapter->pf * EEPROMPFSIZE; 1013 1014 if (aligned_offset < start || 1015 aligned_offset + aligned_len > start + EEPROMPFSIZE) 1016 return -EPERM; 1017 } 1018 1019 if (aligned_offset != eeprom->offset || aligned_len != eeprom->length) { 1020 /* RMW possibly needed for first or last words. 1021 */ 1022 buf = rte_zmalloc(NULL, aligned_len, 0); 1023 if (!buf) 1024 return -ENOMEM; 1025 err = eeprom_rd_phys(adapter, aligned_offset, (u32 *)buf); 1026 if (!err && aligned_len > 4) 1027 err = eeprom_rd_phys(adapter, 1028 aligned_offset + aligned_len - 4, 1029 (u32 *)&buf[aligned_len - 4]); 1030 if (err) 1031 goto out; 1032 rte_memcpy(buf + (eeprom->offset & 3), eeprom->data, 1033 eeprom->length); 1034 } else { 1035 buf = eeprom->data; 1036 } 1037 1038 err = t4_seeprom_wp(adapter, false); 1039 if (err) 1040 goto out; 1041 1042 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) { 1043 err = eeprom_wr_phys(adapter, aligned_offset, *p); 1044 aligned_offset += 4; 1045 } 1046 1047 if (!err) 1048 err = t4_seeprom_wp(adapter, true); 1049 out: 1050 if (buf != eeprom->data) 1051 rte_free(buf); 1052 return err; 1053 } 1054 1055 static int cxgbe_get_regs_len(struct rte_eth_dev *eth_dev) 1056 { 1057 struct port_info *pi = eth_dev->data->dev_private; 1058 struct adapter *adapter = pi->adapter; 1059 1060 return t4_get_regs_len(adapter) / sizeof(uint32_t); 1061 } 1062 1063 static int cxgbe_get_regs(struct rte_eth_dev *eth_dev, 1064 struct rte_dev_reg_info *regs) 1065 { 1066 struct port_info *pi = eth_dev->data->dev_private; 1067 struct adapter *adapter = pi->adapter; 1068 1069 regs->version = CHELSIO_CHIP_VERSION(adapter->params.chip) | 1070 (CHELSIO_CHIP_RELEASE(adapter->params.chip) << 10) | 1071 (1 << 16); 1072 1073 if (regs->data == NULL) { 1074 regs->length = cxgbe_get_regs_len(eth_dev); 1075 regs->width = sizeof(uint32_t); 1076 1077 return 0; 1078 } 1079 1080 t4_get_regs(adapter, regs->data, (regs->length * sizeof(uint32_t))); 1081 1082 return 0; 1083 } 1084 1085 int cxgbe_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *addr) 1086 { 1087 struct port_info *pi = dev->data->dev_private; 1088 int ret; 1089 1090 ret = cxgbe_mpstcam_modify(pi, (int)pi->xact_addr_filt, (u8 *)addr); 1091 if (ret < 0) { 1092 dev_err(adapter, "failed to set mac addr; err = %d\n", 1093 ret); 1094 return ret; 1095 } 1096 pi->xact_addr_filt = ret; 1097 return 0; 1098 } 1099 1100 static const struct eth_dev_ops cxgbe_eth_dev_ops = { 1101 .dev_start = cxgbe_dev_start, 1102 .dev_stop = cxgbe_dev_stop, 1103 .dev_close = cxgbe_dev_close, 1104 .promiscuous_enable = cxgbe_dev_promiscuous_enable, 1105 .promiscuous_disable = cxgbe_dev_promiscuous_disable, 1106 .allmulticast_enable = cxgbe_dev_allmulticast_enable, 1107 .allmulticast_disable = cxgbe_dev_allmulticast_disable, 1108 .dev_configure = cxgbe_dev_configure, 1109 .dev_infos_get = cxgbe_dev_info_get, 1110 .dev_supported_ptypes_get = cxgbe_dev_supported_ptypes_get, 1111 .link_update = cxgbe_dev_link_update, 1112 .dev_set_link_up = cxgbe_dev_set_link_up, 1113 .dev_set_link_down = cxgbe_dev_set_link_down, 1114 .mtu_set = cxgbe_dev_mtu_set, 1115 .tx_queue_setup = cxgbe_dev_tx_queue_setup, 1116 .tx_queue_start = cxgbe_dev_tx_queue_start, 1117 .tx_queue_stop = cxgbe_dev_tx_queue_stop, 1118 .tx_queue_release = cxgbe_dev_tx_queue_release, 1119 .rx_queue_setup = cxgbe_dev_rx_queue_setup, 1120 .rx_queue_start = cxgbe_dev_rx_queue_start, 1121 .rx_queue_stop = cxgbe_dev_rx_queue_stop, 1122 .rx_queue_release = cxgbe_dev_rx_queue_release, 1123 .filter_ctrl = cxgbe_dev_filter_ctrl, 1124 .stats_get = cxgbe_dev_stats_get, 1125 .stats_reset = cxgbe_dev_stats_reset, 1126 .flow_ctrl_get = cxgbe_flow_ctrl_get, 1127 .flow_ctrl_set = cxgbe_flow_ctrl_set, 1128 .get_eeprom_length = cxgbe_get_eeprom_length, 1129 .get_eeprom = cxgbe_get_eeprom, 1130 .set_eeprom = cxgbe_set_eeprom, 1131 .get_reg = cxgbe_get_regs, 1132 .rss_hash_update = cxgbe_dev_rss_hash_update, 1133 .rss_hash_conf_get = cxgbe_dev_rss_hash_conf_get, 1134 .mac_addr_set = cxgbe_mac_addr_set, 1135 }; 1136 1137 /* 1138 * Initialize driver 1139 * It returns 0 on success. 1140 */ 1141 static int eth_cxgbe_dev_init(struct rte_eth_dev *eth_dev) 1142 { 1143 struct rte_pci_device *pci_dev; 1144 struct port_info *pi = eth_dev->data->dev_private; 1145 struct adapter *adapter = NULL; 1146 char name[RTE_ETH_NAME_MAX_LEN]; 1147 int err = 0; 1148 1149 CXGBE_FUNC_TRACE(); 1150 1151 eth_dev->dev_ops = &cxgbe_eth_dev_ops; 1152 eth_dev->rx_pkt_burst = &cxgbe_recv_pkts; 1153 eth_dev->tx_pkt_burst = &cxgbe_xmit_pkts; 1154 pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1155 1156 /* for secondary processes, we attach to ethdevs allocated by primary 1157 * and do minimal initialization. 1158 */ 1159 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 1160 int i; 1161 1162 for (i = 1; i < MAX_NPORTS; i++) { 1163 struct rte_eth_dev *rest_eth_dev; 1164 char namei[RTE_ETH_NAME_MAX_LEN]; 1165 1166 snprintf(namei, sizeof(namei), "%s_%d", 1167 pci_dev->device.name, i); 1168 rest_eth_dev = rte_eth_dev_attach_secondary(namei); 1169 if (rest_eth_dev) { 1170 rest_eth_dev->device = &pci_dev->device; 1171 rest_eth_dev->dev_ops = 1172 eth_dev->dev_ops; 1173 rest_eth_dev->rx_pkt_burst = 1174 eth_dev->rx_pkt_burst; 1175 rest_eth_dev->tx_pkt_burst = 1176 eth_dev->tx_pkt_burst; 1177 rte_eth_dev_probing_finish(rest_eth_dev); 1178 } 1179 } 1180 return 0; 1181 } 1182 1183 snprintf(name, sizeof(name), "cxgbeadapter%d", eth_dev->data->port_id); 1184 adapter = rte_zmalloc(name, sizeof(*adapter), 0); 1185 if (!adapter) 1186 return -1; 1187 1188 adapter->use_unpacked_mode = 1; 1189 adapter->regs = (void *)pci_dev->mem_resource[0].addr; 1190 if (!adapter->regs) { 1191 dev_err(adapter, "%s: cannot map device registers\n", __func__); 1192 err = -ENOMEM; 1193 goto out_free_adapter; 1194 } 1195 adapter->pdev = pci_dev; 1196 adapter->eth_dev = eth_dev; 1197 pi->adapter = adapter; 1198 1199 err = cxgbe_probe(adapter); 1200 if (err) { 1201 dev_err(adapter, "%s: cxgbe probe failed with err %d\n", 1202 __func__, err); 1203 goto out_free_adapter; 1204 } 1205 1206 return 0; 1207 1208 out_free_adapter: 1209 rte_free(adapter); 1210 return err; 1211 } 1212 1213 static int eth_cxgbe_dev_uninit(struct rte_eth_dev *eth_dev) 1214 { 1215 struct port_info *pi = eth_dev->data->dev_private; 1216 struct adapter *adap = pi->adapter; 1217 1218 /* Free up other ports and all resources */ 1219 cxgbe_close(adap); 1220 return 0; 1221 } 1222 1223 static int eth_cxgbe_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1224 struct rte_pci_device *pci_dev) 1225 { 1226 return rte_eth_dev_pci_generic_probe(pci_dev, 1227 sizeof(struct port_info), eth_cxgbe_dev_init); 1228 } 1229 1230 static int eth_cxgbe_pci_remove(struct rte_pci_device *pci_dev) 1231 { 1232 return rte_eth_dev_pci_generic_remove(pci_dev, eth_cxgbe_dev_uninit); 1233 } 1234 1235 static struct rte_pci_driver rte_cxgbe_pmd = { 1236 .id_table = cxgb4_pci_tbl, 1237 .drv_flags = RTE_PCI_DRV_NEED_MAPPING, 1238 .probe = eth_cxgbe_pci_probe, 1239 .remove = eth_cxgbe_pci_remove, 1240 }; 1241 1242 RTE_PMD_REGISTER_PCI(net_cxgbe, rte_cxgbe_pmd); 1243 RTE_PMD_REGISTER_PCI_TABLE(net_cxgbe, cxgb4_pci_tbl); 1244 RTE_PMD_REGISTER_KMOD_DEP(net_cxgbe, "* igb_uio | uio_pci_generic | vfio-pci"); 1245 RTE_PMD_REGISTER_PARAM_STRING(net_cxgbe, 1246 CXGBE_DEVARG_KEEP_OVLAN "=<0|1> " 1247 CXGBE_DEVARG_FORCE_LINK_UP "=<0|1> "); 1248 1249 RTE_INIT(cxgbe_init_log) 1250 { 1251 cxgbe_logtype = rte_log_register("pmd.net.cxgbe"); 1252 if (cxgbe_logtype >= 0) 1253 rte_log_set_level(cxgbe_logtype, RTE_LOG_NOTICE); 1254 } 1255