1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2017 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _T4FW_INTERFACE_H_ 35 #define _T4FW_INTERFACE_H_ 36 37 /****************************************************************************** 38 * R E T U R N V A L U E S 39 ********************************/ 40 41 enum fw_retval { 42 FW_SUCCESS = 0, /* completed successfully */ 43 FW_EPERM = 1, /* operation not permitted */ 44 FW_ENOENT = 2, /* no such file or directory */ 45 FW_EIO = 5, /* input/output error; hw bad */ 46 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 47 FW_EAGAIN = 11, /* try again */ 48 FW_ENOMEM = 12, /* out of memory */ 49 FW_EFAULT = 14, /* bad address; fw bad */ 50 FW_EBUSY = 16, /* resource busy */ 51 FW_EEXIST = 17, /* file exists */ 52 FW_ENODEV = 19, /* no such device */ 53 FW_EINVAL = 22, /* invalid argument */ 54 FW_ENOSPC = 28, /* no space left on device */ 55 FW_ENOSYS = 38, /* functionality not implemented */ 56 FW_ENODATA = 61, /* no data available */ 57 FW_EPROTO = 71, /* protocol error */ 58 FW_EADDRINUSE = 98, /* address already in use */ 59 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 60 FW_ENETDOWN = 100, /* network is down */ 61 FW_ENETUNREACH = 101, /* network is unreachable */ 62 FW_ENOBUFS = 105, /* no buffer space available */ 63 FW_ETIMEDOUT = 110, /* timeout */ 64 FW_EINPROGRESS = 115, /* fw internal */ 65 }; 66 67 /****************************************************************************** 68 * M E M O R Y T Y P E s 69 ******************************/ 70 71 enum fw_memtype { 72 FW_MEMTYPE_EDC0 = 0x0, 73 FW_MEMTYPE_EDC1 = 0x1, 74 FW_MEMTYPE_EXTMEM = 0x2, 75 FW_MEMTYPE_FLASH = 0x4, 76 FW_MEMTYPE_INTERNAL = 0x5, 77 FW_MEMTYPE_EXTMEM1 = 0x6, 78 }; 79 80 /****************************************************************************** 81 * W O R K R E Q U E S T s 82 ********************************/ 83 84 enum fw_wr_opcodes { 85 FW_ETH_TX_PKT_WR = 0x08, 86 FW_ETH_TX_PKTS_WR = 0x09, 87 FW_ETH_TX_PKT_VM_WR = 0x11, 88 FW_ETH_TX_PKTS_VM_WR = 0x12, 89 FW_ETH_TX_PKTS2_WR = 0x78, 90 }; 91 92 /* 93 * Generic work request header flit0 94 */ 95 struct fw_wr_hdr { 96 __be32 hi; 97 __be32 lo; 98 }; 99 100 /* work request opcode (hi) 101 */ 102 #define S_FW_WR_OP 24 103 #define M_FW_WR_OP 0xff 104 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 105 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 106 107 /* work request immediate data length (hi) 108 */ 109 #define S_FW_WR_IMMDLEN 0 110 #define M_FW_WR_IMMDLEN 0xff 111 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 112 #define G_FW_WR_IMMDLEN(x) \ 113 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 114 115 /* egress queue status update to egress queue status entry (lo) 116 */ 117 #define S_FW_WR_EQUEQ 30 118 #define M_FW_WR_EQUEQ 0x1 119 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 120 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 121 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 122 123 /* length in units of 16-bytes (lo) 124 */ 125 #define S_FW_WR_LEN16 0 126 #define M_FW_WR_LEN16 0xff 127 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 128 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 129 130 struct fw_eth_tx_pkt_wr { 131 __be32 op_immdlen; 132 __be32 equiq_to_len16; 133 __be64 r3; 134 }; 135 136 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 137 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 138 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 139 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 140 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 141 142 struct fw_eth_tx_pkts_wr { 143 __be32 op_pkd; 144 __be32 equiq_to_len16; 145 __be32 r3; 146 __be16 plen; 147 __u8 npkt; 148 __u8 type; 149 }; 150 151 struct fw_eth_tx_pkt_vm_wr { 152 __be32 op_immdlen; 153 __be32 equiq_to_len16; 154 __be32 r3[2]; 155 __u8 ethmacdst[6]; 156 __u8 ethmacsrc[6]; 157 __be16 ethtype; 158 __be16 vlantci; 159 }; 160 161 struct fw_eth_tx_pkts_vm_wr { 162 __be32 op_pkd; 163 __be32 equiq_to_len16; 164 __be32 r3; 165 __be16 plen; 166 __u8 npkt; 167 __u8 r4; 168 __u8 ethmacdst[6]; 169 __u8 ethmacsrc[6]; 170 __be16 ethtype; 171 __be16 vlantci; 172 }; 173 174 /****************************************************************************** 175 * C O M M A N D s 176 *********************/ 177 178 /* 179 * The maximum length of time, in miliseconds, that we expect any firmware 180 * command to take to execute and return a reply to the host. The RESET 181 * and INITIALIZE commands can take a fair amount of time to execute but 182 * most execute in far less time than this maximum. This constant is used 183 * by host software to determine how long to wait for a firmware command 184 * reply before declaring the firmware as dead/unreachable ... 185 */ 186 #define FW_CMD_MAX_TIMEOUT 10000 187 188 /* 189 * If a host driver does a HELLO and discovers that there's already a MASTER 190 * selected, we may have to wait for that MASTER to finish issuing RESET, 191 * configuration and INITIALIZE commands. Also, there's a possibility that 192 * our own HELLO may get lost if it happens right as the MASTER is issuign a 193 * RESET command, so we need to be willing to make a few retries of our HELLO. 194 */ 195 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 196 #define FW_CMD_HELLO_RETRIES 3 197 198 enum fw_cmd_opcodes { 199 FW_LDST_CMD = 0x01, 200 FW_RESET_CMD = 0x03, 201 FW_HELLO_CMD = 0x04, 202 FW_BYE_CMD = 0x05, 203 FW_INITIALIZE_CMD = 0x06, 204 FW_CAPS_CONFIG_CMD = 0x07, 205 FW_PARAMS_CMD = 0x08, 206 FW_PFVF_CMD = 0x09, 207 FW_IQ_CMD = 0x10, 208 FW_EQ_ETH_CMD = 0x12, 209 FW_VI_CMD = 0x14, 210 FW_VI_MAC_CMD = 0x15, 211 FW_VI_RXMODE_CMD = 0x16, 212 FW_VI_ENABLE_CMD = 0x17, 213 FW_VI_STATS_CMD = 0x1a, 214 FW_PORT_CMD = 0x1b, 215 FW_RSS_IND_TBL_CMD = 0x20, 216 FW_RSS_GLB_CONFIG_CMD = 0x22, 217 FW_RSS_VI_CONFIG_CMD = 0x23, 218 FW_DEBUG_CMD = 0x81, 219 }; 220 221 enum fw_cmd_cap { 222 FW_CMD_CAP_PORT = 0x04, 223 }; 224 225 /* 226 * Generic command header flit0 227 */ 228 struct fw_cmd_hdr { 229 __be32 hi; 230 __be32 lo; 231 }; 232 233 #define S_FW_CMD_OP 24 234 #define M_FW_CMD_OP 0xff 235 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 236 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 237 238 #define S_FW_CMD_REQUEST 23 239 #define M_FW_CMD_REQUEST 0x1 240 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 241 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 242 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 243 244 #define S_FW_CMD_READ 22 245 #define M_FW_CMD_READ 0x1 246 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 247 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 248 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 249 250 #define S_FW_CMD_WRITE 21 251 #define M_FW_CMD_WRITE 0x1 252 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 253 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 254 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 255 256 #define S_FW_CMD_EXEC 20 257 #define M_FW_CMD_EXEC 0x1 258 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 259 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 260 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 261 262 #define S_FW_CMD_RETVAL 8 263 #define M_FW_CMD_RETVAL 0xff 264 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 265 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 266 267 #define S_FW_CMD_LEN16 0 268 #define M_FW_CMD_LEN16 0xff 269 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 270 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 271 272 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 273 274 /* address spaces 275 */ 276 enum fw_ldst_addrspc { 277 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 278 }; 279 280 struct fw_ldst_cmd { 281 __be32 op_to_addrspace; 282 __be32 cycles_to_len16; 283 union fw_ldst { 284 struct fw_ldst_addrval { 285 __be32 addr; 286 __be32 val; 287 } addrval; 288 struct fw_ldst_idctxt { 289 __be32 physid; 290 __be32 msg_ctxtflush; 291 __be32 ctxt_data7; 292 __be32 ctxt_data6; 293 __be32 ctxt_data5; 294 __be32 ctxt_data4; 295 __be32 ctxt_data3; 296 __be32 ctxt_data2; 297 __be32 ctxt_data1; 298 __be32 ctxt_data0; 299 } idctxt; 300 struct fw_ldst_mdio { 301 __be16 paddr_mmd; 302 __be16 raddr; 303 __be16 vctl; 304 __be16 rval; 305 } mdio; 306 struct fw_ldst_mps { 307 __be16 fid_ctl; 308 __be16 rplcpf_pkd; 309 __be32 rplc127_96; 310 __be32 rplc95_64; 311 __be32 rplc63_32; 312 __be32 rplc31_0; 313 __be32 atrb; 314 __be16 vlan[16]; 315 } mps; 316 struct fw_ldst_func { 317 __u8 access_ctl; 318 __u8 mod_index; 319 __be16 ctl_id; 320 __be32 offset; 321 __be64 data0; 322 __be64 data1; 323 } func; 324 struct fw_ldst_pcie { 325 __u8 ctrl_to_fn; 326 __u8 bnum; 327 __u8 r; 328 __u8 ext_r; 329 __u8 select_naccess; 330 __u8 pcie_fn; 331 __be16 nset_pkd; 332 __be32 data[12]; 333 } pcie; 334 struct fw_ldst_i2c_deprecated { 335 __u8 pid_pkd; 336 __u8 base; 337 __u8 boffset; 338 __u8 data; 339 __be32 r9; 340 } i2c_deprecated; 341 struct fw_ldst_i2c { 342 __u8 pid; 343 __u8 did; 344 __u8 boffset; 345 __u8 blen; 346 __be32 r9; 347 __u8 data[48]; 348 } i2c; 349 struct fw_ldst_le { 350 __be32 index; 351 __be32 r9; 352 __u8 val[33]; 353 __u8 r11[7]; 354 } le; 355 } u; 356 }; 357 358 #define S_FW_LDST_CMD_ADDRSPACE 0 359 #define M_FW_LDST_CMD_ADDRSPACE 0xff 360 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 361 362 struct fw_reset_cmd { 363 __be32 op_to_write; 364 __be32 retval_len16; 365 __be32 val; 366 __be32 halt_pkd; 367 }; 368 369 #define S_FW_RESET_CMD_HALT 31 370 #define M_FW_RESET_CMD_HALT 0x1 371 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 372 #define G_FW_RESET_CMD_HALT(x) \ 373 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 374 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 375 376 enum { 377 FW_HELLO_CMD_STAGE_OS = 0, 378 }; 379 380 struct fw_hello_cmd { 381 __be32 op_to_write; 382 __be32 retval_len16; 383 __be32 err_to_clearinit; 384 __be32 fwrev; 385 }; 386 387 #define S_FW_HELLO_CMD_ERR 31 388 #define M_FW_HELLO_CMD_ERR 0x1 389 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 390 #define G_FW_HELLO_CMD_ERR(x) \ 391 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 392 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 393 394 #define S_FW_HELLO_CMD_INIT 30 395 #define M_FW_HELLO_CMD_INIT 0x1 396 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 397 #define G_FW_HELLO_CMD_INIT(x) \ 398 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 399 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 400 401 #define S_FW_HELLO_CMD_MASTERDIS 29 402 #define M_FW_HELLO_CMD_MASTERDIS 0x1 403 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 404 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 405 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 406 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 407 408 #define S_FW_HELLO_CMD_MASTERFORCE 28 409 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 410 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 411 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 412 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 413 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 414 415 #define S_FW_HELLO_CMD_MBMASTER 24 416 #define M_FW_HELLO_CMD_MBMASTER 0xf 417 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 418 #define G_FW_HELLO_CMD_MBMASTER(x) \ 419 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 420 421 #define S_FW_HELLO_CMD_MBASYNCNOT 20 422 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 423 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 424 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 425 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 426 427 #define S_FW_HELLO_CMD_STAGE 17 428 #define M_FW_HELLO_CMD_STAGE 0x7 429 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 430 #define G_FW_HELLO_CMD_STAGE(x) \ 431 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 432 433 #define S_FW_HELLO_CMD_CLEARINIT 16 434 #define M_FW_HELLO_CMD_CLEARINIT 0x1 435 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 436 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 437 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 438 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 439 440 struct fw_bye_cmd { 441 __be32 op_to_write; 442 __be32 retval_len16; 443 __be64 r3; 444 }; 445 446 struct fw_initialize_cmd { 447 __be32 op_to_write; 448 __be32 retval_len16; 449 __be64 r3; 450 }; 451 452 enum fw_caps_config_nic { 453 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 454 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 455 }; 456 457 enum fw_memtype_cf { 458 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 459 }; 460 461 struct fw_caps_config_cmd { 462 __be32 op_to_write; 463 __be32 cfvalid_to_len16; 464 __be32 r2; 465 __be32 hwmbitmap; 466 __be16 nbmcaps; 467 __be16 linkcaps; 468 __be16 switchcaps; 469 __be16 r3; 470 __be16 niccaps; 471 __be16 toecaps; 472 __be16 rdmacaps; 473 __be16 r4; 474 __be16 iscsicaps; 475 __be16 fcoecaps; 476 __be32 cfcsum; 477 __be32 finiver; 478 __be32 finicsum; 479 }; 480 481 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 482 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 483 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 484 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 485 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 486 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 487 488 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 489 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 490 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 491 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 492 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 493 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 494 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 495 496 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 497 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 498 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 499 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 500 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 501 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 502 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 503 504 /* 505 * params command mnemonics 506 */ 507 enum fw_params_mnem { 508 FW_PARAMS_MNEM_DEV = 1, /* device params */ 509 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 510 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 511 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 512 }; 513 514 /* 515 * device parameters 516 */ 517 enum fw_params_param_dev { 518 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 519 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 520 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */ 521 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */ 522 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 523 }; 524 525 /* 526 * physical and virtual function parameters 527 */ 528 enum fw_params_param_pfvf { 529 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 530 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A 531 }; 532 533 /* 534 * dma queue parameters 535 */ 536 enum fw_params_param_dmaq { 537 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 538 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 539 }; 540 541 #define S_FW_PARAMS_MNEM 24 542 #define M_FW_PARAMS_MNEM 0xff 543 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 544 #define G_FW_PARAMS_MNEM(x) \ 545 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 546 547 #define S_FW_PARAMS_PARAM_X 16 548 #define M_FW_PARAMS_PARAM_X 0xff 549 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 550 #define G_FW_PARAMS_PARAM_X(x) \ 551 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 552 553 #define S_FW_PARAMS_PARAM_Y 8 554 #define M_FW_PARAMS_PARAM_Y 0xff 555 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 556 #define G_FW_PARAMS_PARAM_Y(x) \ 557 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 558 559 #define S_FW_PARAMS_PARAM_Z 0 560 #define M_FW_PARAMS_PARAM_Z 0xff 561 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 562 #define G_FW_PARAMS_PARAM_Z(x) \ 563 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 564 565 #define S_FW_PARAMS_PARAM_YZ 0 566 #define M_FW_PARAMS_PARAM_YZ 0xffff 567 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 568 #define G_FW_PARAMS_PARAM_YZ(x) \ 569 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 570 571 #define S_FW_PARAMS_PARAM_XYZ 0 572 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 573 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 574 575 struct fw_params_cmd { 576 __be32 op_to_vfn; 577 __be32 retval_len16; 578 struct fw_params_param { 579 __be32 mnem; 580 __be32 val; 581 } param[7]; 582 }; 583 584 #define S_FW_PARAMS_CMD_PFN 8 585 #define M_FW_PARAMS_CMD_PFN 0x7 586 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 587 #define G_FW_PARAMS_CMD_PFN(x) \ 588 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 589 590 #define S_FW_PARAMS_CMD_VFN 0 591 #define M_FW_PARAMS_CMD_VFN 0xff 592 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 593 #define G_FW_PARAMS_CMD_VFN(x) \ 594 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 595 596 struct fw_pfvf_cmd { 597 __be32 op_to_vfn; 598 __be32 retval_len16; 599 __be32 niqflint_niq; 600 __be32 type_to_neq; 601 __be32 tc_to_nexactf; 602 __be32 r_caps_to_nethctrl; 603 __be16 nricq; 604 __be16 nriqp; 605 __be32 r4; 606 }; 607 608 #define S_FW_PFVF_CMD_NIQFLINT 20 609 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 610 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 611 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 612 613 #define S_FW_PFVF_CMD_NIQ 0 614 #define M_FW_PFVF_CMD_NIQ 0xfffff 615 #define G_FW_PFVF_CMD_NIQ(x) \ 616 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 617 618 #define S_FW_PFVF_CMD_PMASK 20 619 #define M_FW_PFVF_CMD_PMASK 0xf 620 #define G_FW_PFVF_CMD_PMASK(x) \ 621 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 622 623 #define S_FW_PFVF_CMD_NEQ 0 624 #define M_FW_PFVF_CMD_NEQ 0xfffff 625 #define G_FW_PFVF_CMD_NEQ(x) \ 626 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 627 628 #define S_FW_PFVF_CMD_TC 24 629 #define M_FW_PFVF_CMD_TC 0xff 630 #define G_FW_PFVF_CMD_TC(x) \ 631 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 632 633 #define S_FW_PFVF_CMD_NVI 16 634 #define M_FW_PFVF_CMD_NVI 0xff 635 #define G_FW_PFVF_CMD_NVI(x) \ 636 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 637 638 #define S_FW_PFVF_CMD_NEXACTF 0 639 #define M_FW_PFVF_CMD_NEXACTF 0xffff 640 #define G_FW_PFVF_CMD_NEXACTF(x) \ 641 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 642 643 #define S_FW_PFVF_CMD_R_CAPS 24 644 #define M_FW_PFVF_CMD_R_CAPS 0xff 645 #define G_FW_PFVF_CMD_R_CAPS(x) \ 646 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 647 648 #define S_FW_PFVF_CMD_WX_CAPS 16 649 #define M_FW_PFVF_CMD_WX_CAPS 0xff 650 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 651 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 652 653 #define S_FW_PFVF_CMD_NETHCTRL 0 654 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 655 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 656 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 657 658 /* 659 * ingress queue type; the first 1K ingress queues can have associated 0, 660 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 661 * capabilities 662 */ 663 enum fw_iq_type { 664 FW_IQ_TYPE_FL_INT_CAP, 665 }; 666 667 struct fw_iq_cmd { 668 __be32 op_to_vfn; 669 __be32 alloc_to_len16; 670 __be16 physiqid; 671 __be16 iqid; 672 __be16 fl0id; 673 __be16 fl1id; 674 __be32 type_to_iqandstindex; 675 __be16 iqdroprss_to_iqesize; 676 __be16 iqsize; 677 __be64 iqaddr; 678 __be32 iqns_to_fl0congen; 679 __be16 fl0dcaen_to_fl0cidxfthresh; 680 __be16 fl0size; 681 __be64 fl0addr; 682 __be32 fl1cngchmap_to_fl1congen; 683 __be16 fl1dcaen_to_fl1cidxfthresh; 684 __be16 fl1size; 685 __be64 fl1addr; 686 }; 687 688 #define S_FW_IQ_CMD_PFN 8 689 #define M_FW_IQ_CMD_PFN 0x7 690 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 691 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 692 693 #define S_FW_IQ_CMD_VFN 0 694 #define M_FW_IQ_CMD_VFN 0xff 695 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 696 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 697 698 #define S_FW_IQ_CMD_ALLOC 31 699 #define M_FW_IQ_CMD_ALLOC 0x1 700 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 701 #define G_FW_IQ_CMD_ALLOC(x) \ 702 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 703 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 704 705 #define S_FW_IQ_CMD_FREE 30 706 #define M_FW_IQ_CMD_FREE 0x1 707 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 708 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 709 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 710 711 #define S_FW_IQ_CMD_IQSTART 28 712 #define M_FW_IQ_CMD_IQSTART 0x1 713 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 714 #define G_FW_IQ_CMD_IQSTART(x) \ 715 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 716 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 717 718 #define S_FW_IQ_CMD_IQSTOP 27 719 #define M_FW_IQ_CMD_IQSTOP 0x1 720 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 721 #define G_FW_IQ_CMD_IQSTOP(x) \ 722 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 723 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 724 725 #define S_FW_IQ_CMD_TYPE 29 726 #define M_FW_IQ_CMD_TYPE 0x7 727 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 728 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 729 730 #define S_FW_IQ_CMD_IQASYNCH 28 731 #define M_FW_IQ_CMD_IQASYNCH 0x1 732 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 733 #define G_FW_IQ_CMD_IQASYNCH(x) \ 734 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 735 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 736 737 #define S_FW_IQ_CMD_VIID 16 738 #define M_FW_IQ_CMD_VIID 0xfff 739 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 740 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 741 742 #define S_FW_IQ_CMD_IQANDST 15 743 #define M_FW_IQ_CMD_IQANDST 0x1 744 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 745 #define G_FW_IQ_CMD_IQANDST(x) \ 746 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 747 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 748 749 #define S_FW_IQ_CMD_IQANUD 12 750 #define M_FW_IQ_CMD_IQANUD 0x3 751 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 752 #define G_FW_IQ_CMD_IQANUD(x) \ 753 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 754 755 #define S_FW_IQ_CMD_IQANDSTINDEX 0 756 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 757 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 758 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 759 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 760 761 #define S_FW_IQ_CMD_IQGTSMODE 14 762 #define M_FW_IQ_CMD_IQGTSMODE 0x1 763 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 764 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 765 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 766 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 767 768 #define S_FW_IQ_CMD_IQPCIECH 12 769 #define M_FW_IQ_CMD_IQPCIECH 0x3 770 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 771 #define G_FW_IQ_CMD_IQPCIECH(x) \ 772 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 773 774 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 775 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 776 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 777 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 778 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 779 780 #define S_FW_IQ_CMD_IQESIZE 0 781 #define M_FW_IQ_CMD_IQESIZE 0x3 782 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 783 #define G_FW_IQ_CMD_IQESIZE(x) \ 784 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 785 786 #define S_FW_IQ_CMD_IQRO 30 787 #define M_FW_IQ_CMD_IQRO 0x1 788 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 789 #define G_FW_IQ_CMD_IQRO(x) \ 790 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 791 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 792 793 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 794 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 795 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 796 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 797 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 798 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 799 800 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 801 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 802 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 803 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 804 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 805 806 #define S_FW_IQ_CMD_FL0DATARO 12 807 #define M_FW_IQ_CMD_FL0DATARO 0x1 808 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 809 #define G_FW_IQ_CMD_FL0DATARO(x) \ 810 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 811 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 812 813 #define S_FW_IQ_CMD_FL0CONGCIF 11 814 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 815 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 816 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 817 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 818 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 819 820 #define S_FW_IQ_CMD_FL0FETCHRO 6 821 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 822 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 823 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 824 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 825 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 826 827 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 828 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 829 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 830 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 831 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 832 833 #define S_FW_IQ_CMD_FL0PADEN 2 834 #define M_FW_IQ_CMD_FL0PADEN 0x1 835 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 836 #define G_FW_IQ_CMD_FL0PADEN(x) \ 837 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 838 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 839 840 #define S_FW_IQ_CMD_FL0PACKEN 1 841 #define M_FW_IQ_CMD_FL0PACKEN 0x1 842 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 843 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 844 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 845 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 846 847 #define S_FW_IQ_CMD_FL0CONGEN 0 848 #define M_FW_IQ_CMD_FL0CONGEN 0x1 849 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 850 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 851 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 852 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 853 854 #define S_FW_IQ_CMD_FL0FBMIN 7 855 #define M_FW_IQ_CMD_FL0FBMIN 0x7 856 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 857 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 858 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 859 860 #define S_FW_IQ_CMD_FL0FBMAX 4 861 #define M_FW_IQ_CMD_FL0FBMAX 0x7 862 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 863 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 864 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 865 866 struct fw_eq_eth_cmd { 867 __be32 op_to_vfn; 868 __be32 alloc_to_len16; 869 __be32 eqid_pkd; 870 __be32 physeqid_pkd; 871 __be32 fetchszm_to_iqid; 872 __be32 dcaen_to_eqsize; 873 __be64 eqaddr; 874 __be32 autoequiqe_to_viid; 875 __be32 r8_lo; 876 __be64 r9; 877 }; 878 879 #define S_FW_EQ_ETH_CMD_PFN 8 880 #define M_FW_EQ_ETH_CMD_PFN 0x7 881 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 882 #define G_FW_EQ_ETH_CMD_PFN(x) \ 883 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 884 885 #define S_FW_EQ_ETH_CMD_VFN 0 886 #define M_FW_EQ_ETH_CMD_VFN 0xff 887 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 888 #define G_FW_EQ_ETH_CMD_VFN(x) \ 889 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 890 891 #define S_FW_EQ_ETH_CMD_ALLOC 31 892 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 893 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 894 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 895 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 896 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 897 898 #define S_FW_EQ_ETH_CMD_FREE 30 899 #define M_FW_EQ_ETH_CMD_FREE 0x1 900 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 901 #define G_FW_EQ_ETH_CMD_FREE(x) \ 902 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 903 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 904 905 #define S_FW_EQ_ETH_CMD_EQSTART 28 906 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 907 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 908 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 909 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 910 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 911 912 #define S_FW_EQ_ETH_CMD_EQID 0 913 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 914 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 915 #define G_FW_EQ_ETH_CMD_EQID(x) \ 916 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 917 918 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 919 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 920 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 921 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 922 923 #define S_FW_EQ_ETH_CMD_FETCHRO 22 924 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 925 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 926 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 927 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 928 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 929 930 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 931 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 932 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 933 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 934 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 935 936 #define S_FW_EQ_ETH_CMD_PCIECHN 16 937 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 938 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 939 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 940 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 941 942 #define S_FW_EQ_ETH_CMD_IQID 0 943 #define M_FW_EQ_ETH_CMD_IQID 0xffff 944 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 945 #define G_FW_EQ_ETH_CMD_IQID(x) \ 946 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 947 948 #define S_FW_EQ_ETH_CMD_FBMIN 23 949 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 950 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 951 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 952 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 953 954 #define S_FW_EQ_ETH_CMD_FBMAX 20 955 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 956 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 957 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 958 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 959 960 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 961 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 962 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 963 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 964 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 965 966 #define S_FW_EQ_ETH_CMD_EQSIZE 0 967 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 968 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 969 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 970 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 971 972 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 973 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 974 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 975 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 976 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 977 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 978 979 #define S_FW_EQ_ETH_CMD_VIID 16 980 #define M_FW_EQ_ETH_CMD_VIID 0xfff 981 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 982 #define G_FW_EQ_ETH_CMD_VIID(x) \ 983 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 984 985 enum fw_vi_func { 986 FW_VI_FUNC_ETH, 987 }; 988 989 struct fw_vi_cmd { 990 __be32 op_to_vfn; 991 __be32 alloc_to_len16; 992 __be16 type_to_viid; 993 __u8 mac[6]; 994 __u8 portid_pkd; 995 __u8 nmac; 996 __u8 nmac0[6]; 997 __be16 norss_rsssize; 998 __u8 nmac1[6]; 999 __be16 idsiiq_pkd; 1000 __u8 nmac2[6]; 1001 __be16 idseiq_pkd; 1002 __u8 nmac3[6]; 1003 __be64 r9; 1004 __be64 r10; 1005 }; 1006 1007 #define S_FW_VI_CMD_PFN 8 1008 #define M_FW_VI_CMD_PFN 0x7 1009 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 1010 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 1011 1012 #define S_FW_VI_CMD_VFN 0 1013 #define M_FW_VI_CMD_VFN 0xff 1014 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 1015 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 1016 1017 #define S_FW_VI_CMD_ALLOC 31 1018 #define M_FW_VI_CMD_ALLOC 0x1 1019 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 1020 #define G_FW_VI_CMD_ALLOC(x) \ 1021 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 1022 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 1023 1024 #define S_FW_VI_CMD_FREE 30 1025 #define M_FW_VI_CMD_FREE 0x1 1026 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 1027 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 1028 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 1029 1030 #define S_FW_VI_CMD_TYPE 15 1031 #define M_FW_VI_CMD_TYPE 0x1 1032 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 1033 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 1034 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 1035 1036 #define S_FW_VI_CMD_FUNC 12 1037 #define M_FW_VI_CMD_FUNC 0x7 1038 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 1039 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 1040 1041 #define S_FW_VI_CMD_VIID 0 1042 #define M_FW_VI_CMD_VIID 0xfff 1043 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 1044 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 1045 1046 #define S_FW_VI_CMD_PORTID 4 1047 #define M_FW_VI_CMD_PORTID 0xf 1048 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 1049 #define G_FW_VI_CMD_PORTID(x) \ 1050 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 1051 1052 #define S_FW_VI_CMD_RSSSIZE 0 1053 #define M_FW_VI_CMD_RSSSIZE 0x7ff 1054 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 1055 #define G_FW_VI_CMD_RSSSIZE(x) \ 1056 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 1057 1058 /* Special VI_MAC command index ids */ 1059 #define FW_VI_MAC_ADD_MAC 0x3FF 1060 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1061 1062 enum fw_vi_mac_smac { 1063 FW_VI_MAC_MPS_TCAM_ENTRY, 1064 FW_VI_MAC_SMT_AND_MPSTCAM 1065 }; 1066 1067 struct fw_vi_mac_cmd { 1068 __be32 op_to_viid; 1069 __be32 freemacs_to_len16; 1070 union fw_vi_mac { 1071 struct fw_vi_mac_exact { 1072 __be16 valid_to_idx; 1073 __u8 macaddr[6]; 1074 } exact[7]; 1075 struct fw_vi_mac_hash { 1076 __be64 hashvec; 1077 } hash; 1078 } u; 1079 }; 1080 1081 #define S_FW_VI_MAC_CMD_VIID 0 1082 #define M_FW_VI_MAC_CMD_VIID 0xfff 1083 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 1084 #define G_FW_VI_MAC_CMD_VIID(x) \ 1085 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 1086 1087 #define S_FW_VI_MAC_CMD_VALID 15 1088 #define M_FW_VI_MAC_CMD_VALID 0x1 1089 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 1090 #define G_FW_VI_MAC_CMD_VALID(x) \ 1091 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 1092 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 1093 1094 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 1095 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 1096 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 1097 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 1098 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 1099 1100 #define S_FW_VI_MAC_CMD_IDX 0 1101 #define M_FW_VI_MAC_CMD_IDX 0x3ff 1102 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 1103 #define G_FW_VI_MAC_CMD_IDX(x) \ 1104 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 1105 1106 struct fw_vi_rxmode_cmd { 1107 __be32 op_to_viid; 1108 __be32 retval_len16; 1109 __be32 mtu_to_vlanexen; 1110 __be32 r4_lo; 1111 }; 1112 1113 #define S_FW_VI_RXMODE_CMD_VIID 0 1114 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 1115 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 1116 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 1117 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 1118 1119 #define S_FW_VI_RXMODE_CMD_MTU 16 1120 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 1121 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 1122 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 1123 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 1124 1125 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 1126 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 1127 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 1128 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 1129 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 1130 1131 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 1132 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 1133 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1134 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 1135 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1136 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 1137 1138 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 1139 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 1140 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1141 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 1142 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1143 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 1144 M_FW_VI_RXMODE_CMD_BROADCASTEN) 1145 1146 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 1147 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 1148 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 1149 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 1150 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 1151 1152 struct fw_vi_enable_cmd { 1153 __be32 op_to_viid; 1154 __be32 ien_to_len16; 1155 __be16 blinkdur; 1156 __be16 r3; 1157 __be32 r4; 1158 }; 1159 1160 #define S_FW_VI_ENABLE_CMD_VIID 0 1161 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 1162 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 1163 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 1164 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 1165 1166 #define S_FW_VI_ENABLE_CMD_IEN 31 1167 #define M_FW_VI_ENABLE_CMD_IEN 0x1 1168 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 1169 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 1170 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 1171 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 1172 1173 #define S_FW_VI_ENABLE_CMD_EEN 30 1174 #define M_FW_VI_ENABLE_CMD_EEN 0x1 1175 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 1176 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 1177 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 1178 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 1179 1180 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 1181 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 1182 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 1183 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 1184 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 1185 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 1186 1187 /* VI VF stats offset definitions */ 1188 #define VI_VF_NUM_STATS 16 1189 1190 /* VI PF stats offset definitions */ 1191 #define VI_PF_NUM_STATS 17 1192 enum fw_vi_stats_pf_index { 1193 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 1194 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 1195 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 1196 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 1197 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 1198 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 1199 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 1200 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 1201 FW_VI_PF_STAT_RX_BYTES_IX, 1202 FW_VI_PF_STAT_RX_FRAMES_IX, 1203 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 1204 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 1205 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 1206 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1207 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1208 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1209 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1210 }; 1211 1212 struct fw_vi_stats_cmd { 1213 __be32 op_to_viid; 1214 __be32 retval_len16; 1215 union fw_vi_stats { 1216 struct fw_vi_stats_ctl { 1217 __be16 nstats_ix; 1218 __be16 r6; 1219 __be32 r7; 1220 __be64 stat0; 1221 __be64 stat1; 1222 __be64 stat2; 1223 __be64 stat3; 1224 __be64 stat4; 1225 __be64 stat5; 1226 } ctl; 1227 struct fw_vi_stats_pf { 1228 __be64 tx_bcast_bytes; 1229 __be64 tx_bcast_frames; 1230 __be64 tx_mcast_bytes; 1231 __be64 tx_mcast_frames; 1232 __be64 tx_ucast_bytes; 1233 __be64 tx_ucast_frames; 1234 __be64 tx_offload_bytes; 1235 __be64 tx_offload_frames; 1236 __be64 rx_pf_bytes; 1237 __be64 rx_pf_frames; 1238 __be64 rx_bcast_bytes; 1239 __be64 rx_bcast_frames; 1240 __be64 rx_mcast_bytes; 1241 __be64 rx_mcast_frames; 1242 __be64 rx_ucast_bytes; 1243 __be64 rx_ucast_frames; 1244 __be64 rx_err_frames; 1245 } pf; 1246 struct fw_vi_stats_vf { 1247 __be64 tx_bcast_bytes; 1248 __be64 tx_bcast_frames; 1249 __be64 tx_mcast_bytes; 1250 __be64 tx_mcast_frames; 1251 __be64 tx_ucast_bytes; 1252 __be64 tx_ucast_frames; 1253 __be64 tx_drop_frames; 1254 __be64 tx_offload_bytes; 1255 __be64 tx_offload_frames; 1256 __be64 rx_bcast_bytes; 1257 __be64 rx_bcast_frames; 1258 __be64 rx_mcast_bytes; 1259 __be64 rx_mcast_frames; 1260 __be64 rx_ucast_bytes; 1261 __be64 rx_ucast_frames; 1262 __be64 rx_err_frames; 1263 } vf; 1264 } u; 1265 }; 1266 1267 #define S_FW_VI_STATS_CMD_VIID 0 1268 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 1269 1270 #define S_FW_VI_STATS_CMD_NSTATS 12 1271 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 1272 1273 #define S_FW_VI_STATS_CMD_IX 0 1274 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 1275 1276 /* old 16-bit port capabilities bitmap */ 1277 enum fw_port_cap { 1278 FW_PORT_CAP_SPEED_100M = 0x0001, 1279 FW_PORT_CAP_SPEED_1G = 0x0002, 1280 FW_PORT_CAP_SPEED_25G = 0x0004, 1281 FW_PORT_CAP_SPEED_10G = 0x0008, 1282 FW_PORT_CAP_SPEED_40G = 0x0010, 1283 FW_PORT_CAP_SPEED_100G = 0x0020, 1284 FW_PORT_CAP_FC_RX = 0x0040, 1285 FW_PORT_CAP_FC_TX = 0x0080, 1286 FW_PORT_CAP_ANEG = 0x0100, 1287 FW_PORT_CAP_MDIX = 0x0200, 1288 FW_PORT_CAP_MDIAUTO = 0x0400, 1289 FW_PORT_CAP_FEC_RS = 0x0800, 1290 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 1291 FW_PORT_CAP_FEC_RESERVED = 0x2000, 1292 FW_PORT_CAP_802_3_PAUSE = 0x4000, 1293 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 1294 }; 1295 1296 #define S_FW_PORT_CAP_SPEED 0 1297 #define M_FW_PORT_CAP_SPEED 0x3f 1298 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 1299 #define G_FW_PORT_CAP_SPEED(x) \ 1300 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 1301 1302 enum fw_port_mdi { 1303 FW_PORT_CAP_MDI_AUTO, 1304 }; 1305 1306 #define S_FW_PORT_CAP_MDI 9 1307 #define M_FW_PORT_CAP_MDI 3 1308 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 1309 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 1310 1311 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 1312 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 1313 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 1314 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 1315 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 1316 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 1317 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 1318 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 1319 #define FW_PORT_CAP32_FC_RX 0x00010000UL 1320 #define FW_PORT_CAP32_FC_TX 0x00020000UL 1321 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 1322 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 1323 #define FW_PORT_CAP32_ANEG 0x00100000UL 1324 #define FW_PORT_CAP32_MDIX 0x00200000UL 1325 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 1326 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 1327 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 1328 1329 #define S_FW_PORT_CAP32_SPEED 0 1330 #define M_FW_PORT_CAP32_SPEED 0xfff 1331 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 1332 #define G_FW_PORT_CAP32_SPEED(x) \ 1333 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 1334 1335 enum fw_port_mdi32 { 1336 FW_PORT_CAP32_MDI_AUTO, 1337 }; 1338 1339 #define S_FW_PORT_CAP32_MDI 21 1340 #define M_FW_PORT_CAP32_MDI 3 1341 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 1342 #define G_FW_PORT_CAP32_MDI(x) \ 1343 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 1344 1345 enum fw_port_action { 1346 FW_PORT_ACTION_L1_CFG = 0x0001, 1347 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 1348 FW_PORT_ACTION_L1_CFG32 = 0x0009, 1349 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 1350 }; 1351 1352 struct fw_port_cmd { 1353 __be32 op_to_portid; 1354 __be32 action_to_len16; 1355 union fw_port { 1356 struct fw_port_l1cfg { 1357 __be32 rcap; 1358 __be32 r; 1359 } l1cfg; 1360 struct fw_port_l2cfg { 1361 __u8 ctlbf; 1362 __u8 ovlan3_to_ivlan0; 1363 __be16 ivlantype; 1364 __be16 txipg_force_pinfo; 1365 __be16 mtu; 1366 __be16 ovlan0mask; 1367 __be16 ovlan0type; 1368 __be16 ovlan1mask; 1369 __be16 ovlan1type; 1370 __be16 ovlan2mask; 1371 __be16 ovlan2type; 1372 __be16 ovlan3mask; 1373 __be16 ovlan3type; 1374 } l2cfg; 1375 struct fw_port_info { 1376 __be32 lstatus_to_modtype; 1377 __be16 pcap; 1378 __be16 acap; 1379 __be16 mtu; 1380 __u8 cbllen; 1381 __u8 auxlinfo; 1382 __u8 dcbxdis_pkd; 1383 __u8 r8_lo; 1384 __be16 lpacap; 1385 __be64 r9; 1386 } info; 1387 struct fw_port_diags { 1388 __u8 diagop; 1389 __u8 r[3]; 1390 __be32 diagval; 1391 } diags; 1392 union fw_port_dcb { 1393 struct fw_port_dcb_pgid { 1394 __u8 type; 1395 __u8 apply_pkd; 1396 __u8 r10_lo[2]; 1397 __be32 pgid; 1398 __be64 r11; 1399 } pgid; 1400 struct fw_port_dcb_pgrate { 1401 __u8 type; 1402 __u8 apply_pkd; 1403 __u8 r10_lo[5]; 1404 __u8 num_tcs_supported; 1405 __u8 pgrate[8]; 1406 __u8 tsa[8]; 1407 } pgrate; 1408 struct fw_port_dcb_priorate { 1409 __u8 type; 1410 __u8 apply_pkd; 1411 __u8 r10_lo[6]; 1412 __u8 strict_priorate[8]; 1413 } priorate; 1414 struct fw_port_dcb_pfc { 1415 __u8 type; 1416 __u8 pfcen; 1417 __u8 r10[5]; 1418 __u8 max_pfc_tcs; 1419 __be64 r11; 1420 } pfc; 1421 struct fw_port_app_priority { 1422 __u8 type; 1423 __u8 r10[2]; 1424 __u8 idx; 1425 __u8 user_prio_map; 1426 __u8 sel_field; 1427 __be16 protocolid; 1428 __be64 r12; 1429 } app_priority; 1430 struct fw_port_dcb_control { 1431 __u8 type; 1432 __u8 all_syncd_pkd; 1433 __be16 dcb_version_to_app_state; 1434 __be32 r11; 1435 __be64 r12; 1436 } control; 1437 } dcb; 1438 struct fw_port_l1cfg32 { 1439 __be32 rcap32; 1440 __be32 r; 1441 } l1cfg32; 1442 struct fw_port_info32 { 1443 __be32 lstatus32_to_cbllen32; 1444 __be32 auxlinfo32_mtu32; 1445 __be32 linkattr32; 1446 __be32 pcaps32; 1447 __be32 acaps32; 1448 __be32 lpacaps32; 1449 } info32; 1450 } u; 1451 }; 1452 1453 #define S_FW_PORT_CMD_PORTID 0 1454 #define M_FW_PORT_CMD_PORTID 0xf 1455 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 1456 #define G_FW_PORT_CMD_PORTID(x) \ 1457 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 1458 1459 #define S_FW_PORT_CMD_ACTION 16 1460 #define M_FW_PORT_CMD_ACTION 0xffff 1461 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 1462 #define G_FW_PORT_CMD_ACTION(x) \ 1463 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 1464 1465 #define S_FW_PORT_CMD_LSTATUS 31 1466 #define M_FW_PORT_CMD_LSTATUS 0x1 1467 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 1468 #define G_FW_PORT_CMD_LSTATUS(x) \ 1469 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 1470 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 1471 1472 #define S_FW_PORT_CMD_LSPEED 24 1473 #define M_FW_PORT_CMD_LSPEED 0x3f 1474 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 1475 #define G_FW_PORT_CMD_LSPEED(x) \ 1476 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 1477 1478 #define S_FW_PORT_CMD_TXPAUSE 23 1479 #define M_FW_PORT_CMD_TXPAUSE 0x1 1480 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 1481 #define G_FW_PORT_CMD_TXPAUSE(x) \ 1482 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 1483 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 1484 1485 #define S_FW_PORT_CMD_RXPAUSE 22 1486 #define M_FW_PORT_CMD_RXPAUSE 0x1 1487 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 1488 #define G_FW_PORT_CMD_RXPAUSE(x) \ 1489 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 1490 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 1491 1492 #define S_FW_PORT_CMD_MDIOCAP 21 1493 #define M_FW_PORT_CMD_MDIOCAP 0x1 1494 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 1495 #define G_FW_PORT_CMD_MDIOCAP(x) \ 1496 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 1497 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 1498 1499 #define S_FW_PORT_CMD_MDIOADDR 16 1500 #define M_FW_PORT_CMD_MDIOADDR 0x1f 1501 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 1502 #define G_FW_PORT_CMD_MDIOADDR(x) \ 1503 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 1504 1505 #define S_FW_PORT_CMD_PTYPE 8 1506 #define M_FW_PORT_CMD_PTYPE 0x1f 1507 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 1508 #define G_FW_PORT_CMD_PTYPE(x) \ 1509 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 1510 1511 #define S_FW_PORT_CMD_LINKDNRC 5 1512 #define M_FW_PORT_CMD_LINKDNRC 0x7 1513 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 1514 #define G_FW_PORT_CMD_LINKDNRC(x) \ 1515 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 1516 1517 #define S_FW_PORT_CMD_MODTYPE 0 1518 #define M_FW_PORT_CMD_MODTYPE 0x1f 1519 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 1520 #define G_FW_PORT_CMD_MODTYPE(x) \ 1521 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 1522 1523 #define S_FW_PORT_CMD_LSTATUS32 31 1524 #define M_FW_PORT_CMD_LSTATUS32 0x1 1525 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 1526 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 1527 1528 #define S_FW_PORT_CMD_LINKDNRC32 28 1529 #define M_FW_PORT_CMD_LINKDNRC32 0x7 1530 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 1531 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 1532 1533 #define S_FW_PORT_CMD_MDIOCAP32 26 1534 #define M_FW_PORT_CMD_MDIOCAP32 0x1 1535 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 1536 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 1537 1538 #define S_FW_PORT_CMD_MDIOADDR32 21 1539 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 1540 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 1541 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 1542 1543 #define S_FW_PORT_CMD_PORTTYPE32 13 1544 #define M_FW_PORT_CMD_PORTTYPE32 0xff 1545 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 1546 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 1547 1548 #define S_FW_PORT_CMD_MODTYPE32 8 1549 #define M_FW_PORT_CMD_MODTYPE32 0x1f 1550 #define G_FW_PORT_CMD_MODTYPE32(x) \ 1551 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 1552 1553 /* 1554 * These are configured into the VPD and hence tools that generate 1555 * VPD may use this enumeration. 1556 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 1557 * 1558 * REMEMBER: 1559 * Update the Common Code t4_hw.c:t4_get_port_type_description() 1560 * with any new Firmware Port Technology Types! 1561 */ 1562 enum fw_port_type { 1563 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 1564 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 1565 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 1566 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 1567 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 1568 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 1569 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 1570 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 1571 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 1572 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 1573 FW_PORT_TYPE_BP_AP = 10, 1574 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 1575 FW_PORT_TYPE_BP4_AP = 11, 1576 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 1577 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 1578 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 1579 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 1580 FW_PORT_TYPE_BP40_BA = 15, 1581 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 1582 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 1583 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 1584 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 1585 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 1586 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 1587 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 1588 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 1589 }; 1590 1591 /* These are read from module's EEPROM and determined once the 1592 * module is inserted. 1593 */ 1594 enum fw_port_module_type { 1595 FW_PORT_MOD_TYPE_NA = 0x0, 1596 FW_PORT_MOD_TYPE_LR = 0x1, 1597 FW_PORT_MOD_TYPE_SR = 0x2, 1598 FW_PORT_MOD_TYPE_ER = 0x3, 1599 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 1600 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 1601 FW_PORT_MOD_TYPE_LRM = 0x6, 1602 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 1603 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 1604 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 1605 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 1606 }; 1607 1608 /* used by FW and tools may use this to generate VPD */ 1609 enum fw_port_mod_sub_type { 1610 FW_PORT_MOD_SUB_TYPE_NA, 1611 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 1612 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 1613 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 1614 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 1615 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 1616 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6, 1617 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7, 1618 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 1619 1620 /* 1621 * The following will never been in the VPD. They are TWINAX cable 1622 * lengths decoded from SFP+ module i2c PROMs. These should almost 1623 * certainly go somewhere else ... 1624 */ 1625 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 1626 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 1627 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 1628 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 1629 }; 1630 1631 /* link down reason codes (3b) */ 1632 enum fw_port_link_dn_rc { 1633 FW_PORT_LINK_DN_RC_NONE, 1634 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 1635 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 1636 FW_PORT_LINK_DN_RESERVED3, 1637 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 1638 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 1639 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 1640 FW_PORT_LINK_DN_RESERVED7 1641 }; 1642 1643 /* port stats */ 1644 #define FW_NUM_PORT_STATS 50 1645 #define FW_NUM_PORT_TX_STATS 23 1646 #define FW_NUM_PORT_RX_STATS 27 1647 1648 enum fw_port_stats_tx_index { 1649 FW_STAT_TX_PORT_BYTES_IX, 1650 FW_STAT_TX_PORT_FRAMES_IX, 1651 FW_STAT_TX_PORT_BCAST_IX, 1652 FW_STAT_TX_PORT_MCAST_IX, 1653 FW_STAT_TX_PORT_UCAST_IX, 1654 FW_STAT_TX_PORT_ERROR_IX, 1655 FW_STAT_TX_PORT_64B_IX, 1656 FW_STAT_TX_PORT_65B_127B_IX, 1657 FW_STAT_TX_PORT_128B_255B_IX, 1658 FW_STAT_TX_PORT_256B_511B_IX, 1659 FW_STAT_TX_PORT_512B_1023B_IX, 1660 FW_STAT_TX_PORT_1024B_1518B_IX, 1661 FW_STAT_TX_PORT_1519B_MAX_IX, 1662 FW_STAT_TX_PORT_DROP_IX, 1663 FW_STAT_TX_PORT_PAUSE_IX, 1664 FW_STAT_TX_PORT_PPP0_IX, 1665 FW_STAT_TX_PORT_PPP1_IX, 1666 FW_STAT_TX_PORT_PPP2_IX, 1667 FW_STAT_TX_PORT_PPP3_IX, 1668 FW_STAT_TX_PORT_PPP4_IX, 1669 FW_STAT_TX_PORT_PPP5_IX, 1670 FW_STAT_TX_PORT_PPP6_IX, 1671 FW_STAT_TX_PORT_PPP7_IX 1672 }; 1673 1674 enum fw_port_stat_rx_index { 1675 FW_STAT_RX_PORT_BYTES_IX, 1676 FW_STAT_RX_PORT_FRAMES_IX, 1677 FW_STAT_RX_PORT_BCAST_IX, 1678 FW_STAT_RX_PORT_MCAST_IX, 1679 FW_STAT_RX_PORT_UCAST_IX, 1680 FW_STAT_RX_PORT_MTU_ERROR_IX, 1681 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 1682 FW_STAT_RX_PORT_CRC_ERROR_IX, 1683 FW_STAT_RX_PORT_LEN_ERROR_IX, 1684 FW_STAT_RX_PORT_SYM_ERROR_IX, 1685 FW_STAT_RX_PORT_64B_IX, 1686 FW_STAT_RX_PORT_65B_127B_IX, 1687 FW_STAT_RX_PORT_128B_255B_IX, 1688 FW_STAT_RX_PORT_256B_511B_IX, 1689 FW_STAT_RX_PORT_512B_1023B_IX, 1690 FW_STAT_RX_PORT_1024B_1518B_IX, 1691 FW_STAT_RX_PORT_1519B_MAX_IX, 1692 FW_STAT_RX_PORT_PAUSE_IX, 1693 FW_STAT_RX_PORT_PPP0_IX, 1694 FW_STAT_RX_PORT_PPP1_IX, 1695 FW_STAT_RX_PORT_PPP2_IX, 1696 FW_STAT_RX_PORT_PPP3_IX, 1697 FW_STAT_RX_PORT_PPP4_IX, 1698 FW_STAT_RX_PORT_PPP5_IX, 1699 FW_STAT_RX_PORT_PPP6_IX, 1700 FW_STAT_RX_PORT_PPP7_IX, 1701 FW_STAT_RX_PORT_LESS_64B_IX 1702 }; 1703 1704 struct fw_port_stats_cmd { 1705 __be32 op_to_portid; 1706 __be32 retval_len16; 1707 union fw_port_stats { 1708 struct fw_port_stats_ctl { 1709 __u8 nstats_bg_bm; 1710 __u8 tx_ix; 1711 __be16 r6; 1712 __be32 r7; 1713 __be64 stat0; 1714 __be64 stat1; 1715 __be64 stat2; 1716 __be64 stat3; 1717 __be64 stat4; 1718 __be64 stat5; 1719 } ctl; 1720 struct fw_port_stats_all { 1721 __be64 tx_bytes; 1722 __be64 tx_frames; 1723 __be64 tx_bcast; 1724 __be64 tx_mcast; 1725 __be64 tx_ucast; 1726 __be64 tx_error; 1727 __be64 tx_64b; 1728 __be64 tx_65b_127b; 1729 __be64 tx_128b_255b; 1730 __be64 tx_256b_511b; 1731 __be64 tx_512b_1023b; 1732 __be64 tx_1024b_1518b; 1733 __be64 tx_1519b_max; 1734 __be64 tx_drop; 1735 __be64 tx_pause; 1736 __be64 tx_ppp0; 1737 __be64 tx_ppp1; 1738 __be64 tx_ppp2; 1739 __be64 tx_ppp3; 1740 __be64 tx_ppp4; 1741 __be64 tx_ppp5; 1742 __be64 tx_ppp6; 1743 __be64 tx_ppp7; 1744 __be64 rx_bytes; 1745 __be64 rx_frames; 1746 __be64 rx_bcast; 1747 __be64 rx_mcast; 1748 __be64 rx_ucast; 1749 __be64 rx_mtu_error; 1750 __be64 rx_mtu_crc_error; 1751 __be64 rx_crc_error; 1752 __be64 rx_len_error; 1753 __be64 rx_sym_error; 1754 __be64 rx_64b; 1755 __be64 rx_65b_127b; 1756 __be64 rx_128b_255b; 1757 __be64 rx_256b_511b; 1758 __be64 rx_512b_1023b; 1759 __be64 rx_1024b_1518b; 1760 __be64 rx_1519b_max; 1761 __be64 rx_pause; 1762 __be64 rx_ppp0; 1763 __be64 rx_ppp1; 1764 __be64 rx_ppp2; 1765 __be64 rx_ppp3; 1766 __be64 rx_ppp4; 1767 __be64 rx_ppp5; 1768 __be64 rx_ppp6; 1769 __be64 rx_ppp7; 1770 __be64 rx_less_64b; 1771 __be64 rx_bg_drop; 1772 __be64 rx_bg_trunc; 1773 } all; 1774 } u; 1775 }; 1776 1777 struct fw_rss_ind_tbl_cmd { 1778 __be32 op_to_viid; 1779 __be32 retval_len16; 1780 __be16 niqid; 1781 __be16 startidx; 1782 __be32 r3; 1783 __be32 iq0_to_iq2; 1784 __be32 iq3_to_iq5; 1785 __be32 iq6_to_iq8; 1786 __be32 iq9_to_iq11; 1787 __be32 iq12_to_iq14; 1788 __be32 iq15_to_iq17; 1789 __be32 iq18_to_iq20; 1790 __be32 iq21_to_iq23; 1791 __be32 iq24_to_iq26; 1792 __be32 iq27_to_iq29; 1793 __be32 iq30_iq31; 1794 __be32 r15_lo; 1795 }; 1796 1797 #define S_FW_RSS_IND_TBL_CMD_VIID 0 1798 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 1799 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 1800 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 1801 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 1802 1803 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 1804 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 1805 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 1806 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 1807 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 1808 1809 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 1810 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 1811 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 1812 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 1813 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 1814 1815 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 1816 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 1817 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 1818 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 1819 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 1820 1821 struct fw_rss_glb_config_cmd { 1822 __be32 op_to_write; 1823 __be32 retval_len16; 1824 union fw_rss_glb_config { 1825 struct fw_rss_glb_config_manual { 1826 __be32 mode_pkd; 1827 __be32 r3; 1828 __be64 r4; 1829 __be64 r5; 1830 } manual; 1831 struct fw_rss_glb_config_basicvirtual { 1832 __be32 mode_keymode; 1833 __be32 synmapen_to_hashtoeplitz; 1834 __be64 r8; 1835 __be64 r9; 1836 } basicvirtual; 1837 } u; 1838 }; 1839 1840 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 1841 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 1842 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 1843 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 1844 1845 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 1846 1847 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 1848 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 1849 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 1850 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 1851 1852 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 1853 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 1854 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 1855 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 1856 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 1857 1858 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 1859 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 1860 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 1861 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 1862 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 1863 1864 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 1865 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 1866 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 1867 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 1868 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 1869 1870 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 1871 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 1872 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 1873 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 1874 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 1875 1876 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 1877 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 1878 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 1879 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 1880 1881 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 1882 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 1883 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 1884 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 1885 1886 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 1887 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 1888 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 1889 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 1890 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 1891 1892 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 1893 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 1894 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 1895 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 1896 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 1897 1898 struct fw_rss_vi_config_cmd { 1899 __be32 op_to_viid; 1900 __be32 retval_len16; 1901 union fw_rss_vi_config { 1902 struct fw_rss_vi_config_manual { 1903 __be64 r3; 1904 __be64 r4; 1905 __be64 r5; 1906 } manual; 1907 struct fw_rss_vi_config_basicvirtual { 1908 __be32 r6; 1909 __be32 defaultq_to_udpen; 1910 __be64 r9; 1911 __be64 r10; 1912 } basicvirtual; 1913 } u; 1914 }; 1915 1916 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 1917 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 1918 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 1919 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 1920 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 1921 1922 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 1923 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 1924 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 1925 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 1926 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 1927 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 1928 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 1929 1930 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 1931 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 1932 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 1933 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 1934 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 1935 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 1936 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 1937 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 1938 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 1939 1940 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 1941 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 1942 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 1943 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1944 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 1945 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 1946 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1947 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 1948 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 1949 1950 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 1951 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 1952 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 1953 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 1954 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 1955 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 1956 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 1957 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 1958 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 1959 1960 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 1961 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 1962 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 1963 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1964 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 1965 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 1966 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1967 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 1968 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 1969 1970 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 1971 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 1972 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 1973 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 1974 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 1975 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 1976 1977 /****************************************************************************** 1978 * D E B U G C O M M A N D s 1979 ******************************************************/ 1980 1981 struct fw_debug_cmd { 1982 __be32 op_type; 1983 __be32 len16_pkd; 1984 union fw_debug { 1985 struct fw_debug_assert { 1986 __be32 fcid; 1987 __be32 line; 1988 __be32 x; 1989 __be32 y; 1990 __u8 filename_0_7[8]; 1991 __u8 filename_8_15[8]; 1992 __be64 r3; 1993 } assert; 1994 struct fw_debug_prt { 1995 __be16 dprtstridx; 1996 __be16 r3[3]; 1997 __be32 dprtstrparam0; 1998 __be32 dprtstrparam1; 1999 __be32 dprtstrparam2; 2000 __be32 dprtstrparam3; 2001 } prt; 2002 } u; 2003 }; 2004 2005 #define S_FW_DEBUG_CMD_TYPE 0 2006 #define M_FW_DEBUG_CMD_TYPE 0xff 2007 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 2008 #define G_FW_DEBUG_CMD_TYPE(x) \ 2009 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 2010 2011 /****************************************************************************** 2012 * P C I E F W R E G I S T E R 2013 **************************************/ 2014 2015 /* 2016 * Register definitions for the PCIE_FW register which the firmware uses 2017 * to retain status across RESETs. This register should be considered 2018 * as a READ-ONLY register for Host Software and only to be used to 2019 * track firmware initialization/error state, etc. 2020 */ 2021 #define S_PCIE_FW_ERR 31 2022 #define M_PCIE_FW_ERR 0x1 2023 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 2024 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 2025 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 2026 2027 #define S_PCIE_FW_INIT 30 2028 #define M_PCIE_FW_INIT 0x1 2029 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 2030 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 2031 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 2032 2033 #define S_PCIE_FW_HALT 29 2034 #define M_PCIE_FW_HALT 0x1 2035 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 2036 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 2037 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 2038 2039 #define S_PCIE_FW_EVAL 24 2040 #define M_PCIE_FW_EVAL 0x7 2041 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 2042 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 2043 2044 #define S_PCIE_FW_MASTER_VLD 15 2045 #define M_PCIE_FW_MASTER_VLD 0x1 2046 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 2047 #define G_PCIE_FW_MASTER_VLD(x) \ 2048 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 2049 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 2050 2051 #define S_PCIE_FW_MASTER 12 2052 #define M_PCIE_FW_MASTER 0x7 2053 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 2054 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 2055 2056 /****************************************************************************** 2057 * B I N A R Y H E A D E R F O R M A T 2058 **********************************************/ 2059 2060 /* 2061 * firmware binary header format 2062 */ 2063 struct fw_hdr { 2064 __u8 ver; 2065 __u8 chip; /* terminator chip family */ 2066 __be16 len512; /* bin length in units of 512-bytes */ 2067 __be32 fw_ver; /* firmware version */ 2068 __be32 tp_microcode_ver; /* tcp processor microcode version */ 2069 __u8 intfver_nic; 2070 __u8 intfver_vnic; 2071 __u8 intfver_ofld; 2072 __u8 intfver_ri; 2073 __u8 intfver_iscsipdu; 2074 __u8 intfver_iscsi; 2075 __u8 intfver_fcoepdu; 2076 __u8 intfver_fcoe; 2077 __u32 reserved2; 2078 __u32 reserved3; 2079 __u32 magic; /* runtime or bootstrap fw */ 2080 __be32 flags; 2081 __be32 reserved6[23]; 2082 }; 2083 2084 #define S_FW_HDR_FW_VER_MAJOR 24 2085 #define M_FW_HDR_FW_VER_MAJOR 0xff 2086 #define V_FW_HDR_FW_VER_MAJOR(x) \ 2087 ((x) << S_FW_HDR_FW_VER_MAJOR) 2088 #define G_FW_HDR_FW_VER_MAJOR(x) \ 2089 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 2090 2091 #define S_FW_HDR_FW_VER_MINOR 16 2092 #define M_FW_HDR_FW_VER_MINOR 0xff 2093 #define V_FW_HDR_FW_VER_MINOR(x) \ 2094 ((x) << S_FW_HDR_FW_VER_MINOR) 2095 #define G_FW_HDR_FW_VER_MINOR(x) \ 2096 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 2097 2098 #define S_FW_HDR_FW_VER_MICRO 8 2099 #define M_FW_HDR_FW_VER_MICRO 0xff 2100 #define V_FW_HDR_FW_VER_MICRO(x) \ 2101 ((x) << S_FW_HDR_FW_VER_MICRO) 2102 #define G_FW_HDR_FW_VER_MICRO(x) \ 2103 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 2104 2105 #define S_FW_HDR_FW_VER_BUILD 0 2106 #define M_FW_HDR_FW_VER_BUILD 0xff 2107 #define V_FW_HDR_FW_VER_BUILD(x) \ 2108 ((x) << S_FW_HDR_FW_VER_BUILD) 2109 #define G_FW_HDR_FW_VER_BUILD(x) \ 2110 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 2111 2112 #endif /* _T4FW_INTERFACE_H_ */ 2113