1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef _T4FW_INTERFACE_H_ 7 #define _T4FW_INTERFACE_H_ 8 9 /****************************************************************************** 10 * R E T U R N V A L U E S 11 ********************************/ 12 13 enum fw_retval { 14 FW_SUCCESS = 0, /* completed successfully */ 15 FW_EPERM = 1, /* operation not permitted */ 16 FW_ENOENT = 2, /* no such file or directory */ 17 FW_EIO = 5, /* input/output error; hw bad */ 18 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 19 FW_EAGAIN = 11, /* try again */ 20 FW_ENOMEM = 12, /* out of memory */ 21 FW_EFAULT = 14, /* bad address; fw bad */ 22 FW_EBUSY = 16, /* resource busy */ 23 FW_EEXIST = 17, /* file exists */ 24 FW_ENODEV = 19, /* no such device */ 25 FW_EINVAL = 22, /* invalid argument */ 26 FW_ENOSPC = 28, /* no space left on device */ 27 FW_ENOSYS = 38, /* functionality not implemented */ 28 FW_ENODATA = 61, /* no data available */ 29 FW_EPROTO = 71, /* protocol error */ 30 FW_EADDRINUSE = 98, /* address already in use */ 31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 32 FW_ENETDOWN = 100, /* network is down */ 33 FW_ENETUNREACH = 101, /* network is unreachable */ 34 FW_ENOBUFS = 105, /* no buffer space available */ 35 FW_ETIMEDOUT = 110, /* timeout */ 36 FW_EINPROGRESS = 115, /* fw internal */ 37 }; 38 39 /****************************************************************************** 40 * M E M O R Y T Y P E s 41 ******************************/ 42 43 enum fw_memtype { 44 FW_MEMTYPE_EDC0 = 0x0, 45 FW_MEMTYPE_EDC1 = 0x1, 46 FW_MEMTYPE_EXTMEM = 0x2, 47 FW_MEMTYPE_FLASH = 0x4, 48 FW_MEMTYPE_INTERNAL = 0x5, 49 FW_MEMTYPE_EXTMEM1 = 0x6, 50 }; 51 52 /****************************************************************************** 53 * W O R K R E Q U E S T s 54 ********************************/ 55 56 enum fw_wr_opcodes { 57 FW_FILTER_WR = 0x02, 58 FW_ULPTX_WR = 0x04, 59 FW_TP_WR = 0x05, 60 FW_ETH_TX_PKT_WR = 0x08, 61 FW_ETH_TX_PKTS_WR = 0x09, 62 FW_ETH_TX_PKT_VM_WR = 0x11, 63 FW_ETH_TX_PKTS_VM_WR = 0x12, 64 FW_FILTER2_WR = 0x77, 65 FW_ETH_TX_PKTS2_WR = 0x78, 66 }; 67 68 /* 69 * Generic work request header flit0 70 */ 71 struct fw_wr_hdr { 72 __be32 hi; 73 __be32 lo; 74 }; 75 76 /* work request opcode (hi) 77 */ 78 #define S_FW_WR_OP 24 79 #define M_FW_WR_OP 0xff 80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 82 83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 84 */ 85 #define S_FW_WR_ATOMIC 23 86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 87 88 /* work request immediate data length (hi) 89 */ 90 #define S_FW_WR_IMMDLEN 0 91 #define M_FW_WR_IMMDLEN 0xff 92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 93 #define G_FW_WR_IMMDLEN(x) \ 94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 95 96 /* egress queue status update to egress queue status entry (lo) 97 */ 98 #define S_FW_WR_EQUEQ 30 99 #define M_FW_WR_EQUEQ 0x1 100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 103 104 /* flow context identifier (lo) 105 */ 106 #define S_FW_WR_FLOWID 8 107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 108 109 /* length in units of 16-bytes (lo) 110 */ 111 #define S_FW_WR_LEN16 0 112 #define M_FW_WR_LEN16 0xff 113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 115 116 struct fw_eth_tx_pkt_wr { 117 __be32 op_immdlen; 118 __be32 equiq_to_len16; 119 __be64 r3; 120 }; 121 122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 127 128 struct fw_eth_tx_pkts_wr { 129 __be32 op_pkd; 130 __be32 equiq_to_len16; 131 __be32 r3; 132 __be16 plen; 133 __u8 npkt; 134 __u8 type; 135 }; 136 137 struct fw_eth_tx_pkt_vm_wr { 138 __be32 op_immdlen; 139 __be32 equiq_to_len16; 140 __be32 r3[2]; 141 __u8 ethmacdst[6]; 142 __u8 ethmacsrc[6]; 143 __be16 ethtype; 144 __be16 vlantci; 145 }; 146 147 struct fw_eth_tx_pkts_vm_wr { 148 __be32 op_pkd; 149 __be32 equiq_to_len16; 150 __be32 r3; 151 __be16 plen; 152 __u8 npkt; 153 __u8 r4; 154 __u8 ethmacdst[6]; 155 __u8 ethmacsrc[6]; 156 __be16 ethtype; 157 __be16 vlantci; 158 }; 159 160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 161 enum fw_filter_wr_cookie { 162 FW_FILTER_WR_SUCCESS, 163 FW_FILTER_WR_FLT_ADDED, 164 FW_FILTER_WR_FLT_DELETED, 165 FW_FILTER_WR_SMT_TBL_FULL, 166 FW_FILTER_WR_EINVAL, 167 }; 168 169 struct fw_filter2_wr { 170 __be32 op_pkd; 171 __be32 len16_pkd; 172 __be64 r3; 173 __be32 tid_to_iq; 174 __be32 del_filter_to_l2tix; 175 __be16 ethtype; 176 __be16 ethtypem; 177 __u8 frag_to_ovlan_vldm; 178 __u8 smac_sel; 179 __be16 rx_chan_rx_rpl_iq; 180 __be32 maci_to_matchtypem; 181 __u8 ptcl; 182 __u8 ptclm; 183 __u8 ttyp; 184 __u8 ttypm; 185 __be16 ivlan; 186 __be16 ivlanm; 187 __be16 ovlan; 188 __be16 ovlanm; 189 __u8 lip[16]; 190 __u8 lipm[16]; 191 __u8 fip[16]; 192 __u8 fipm[16]; 193 __be16 lp; 194 __be16 lpm; 195 __be16 fp; 196 __be16 fpm; 197 __be16 r7; 198 __u8 sma[6]; 199 __be16 r8; 200 __u8 filter_type_swapmac; 201 __u8 natmode_to_ulp_type; 202 __be16 newlport; 203 __be16 newfport; 204 __u8 newlip[16]; 205 __u8 newfip[16]; 206 __be32 natseqcheck; 207 __be32 r9; 208 __be64 r10; 209 __be64 r11; 210 __be64 r12; 211 __be64 r13; 212 }; 213 214 #define S_FW_FILTER_WR_TID 12 215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 216 217 #define S_FW_FILTER_WR_RQTYPE 11 218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 219 220 #define S_FW_FILTER_WR_NOREPLY 10 221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 222 223 #define S_FW_FILTER_WR_IQ 0 224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 225 226 #define S_FW_FILTER_WR_DEL_FILTER 31 227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 229 230 #define S_FW_FILTER_WR_RPTTID 25 231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 232 233 #define S_FW_FILTER_WR_DROP 24 234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 235 236 #define S_FW_FILTER_WR_DIRSTEER 23 237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 238 239 #define S_FW_FILTER_WR_MASKHASH 22 240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 241 242 #define S_FW_FILTER_WR_DIRSTEERHASH 21 243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 244 245 #define S_FW_FILTER_WR_LPBK 20 246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 247 248 #define S_FW_FILTER_WR_DMAC 19 249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 250 251 #define S_FW_FILTER_WR_SMAC 18 252 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 253 254 #define S_FW_FILTER_WR_INSVLAN 17 255 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 256 257 #define S_FW_FILTER_WR_RMVLAN 16 258 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 259 260 #define S_FW_FILTER_WR_HITCNTS 15 261 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 262 263 #define S_FW_FILTER_WR_TXCHAN 13 264 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 265 266 #define S_FW_FILTER_WR_PRIO 12 267 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 268 269 #define S_FW_FILTER_WR_L2TIX 0 270 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 271 272 #define S_FW_FILTER_WR_FRAG 7 273 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 274 275 #define S_FW_FILTER_WR_FRAGM 6 276 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 277 278 #define S_FW_FILTER_WR_IVLAN_VLD 5 279 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 280 281 #define S_FW_FILTER_WR_OVLAN_VLD 4 282 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 283 284 #define S_FW_FILTER_WR_IVLAN_VLDM 3 285 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 286 287 #define S_FW_FILTER_WR_OVLAN_VLDM 2 288 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 289 290 #define S_FW_FILTER_WR_RX_CHAN 15 291 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 292 293 #define S_FW_FILTER_WR_RX_RPL_IQ 0 294 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 295 296 #define S_FW_FILTER_WR_MACI 23 297 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 298 299 #define S_FW_FILTER_WR_MACIM 14 300 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 301 302 #define S_FW_FILTER_WR_FCOE 13 303 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 304 305 #define S_FW_FILTER_WR_FCOEM 12 306 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 307 308 #define S_FW_FILTER_WR_PORT 9 309 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 310 311 #define S_FW_FILTER_WR_PORTM 6 312 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 313 314 #define S_FW_FILTER_WR_MATCHTYPE 3 315 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 316 317 #define S_FW_FILTER_WR_MATCHTYPEM 0 318 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 319 320 #define S_FW_FILTER2_WR_SWAPMAC 0 321 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 322 323 #define S_FW_FILTER2_WR_NATMODE 5 324 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 325 326 #define S_FW_FILTER2_WR_ULP_TYPE 0 327 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 328 329 /****************************************************************************** 330 * C O M M A N D s 331 *********************/ 332 333 /* 334 * The maximum length of time, in miliseconds, that we expect any firmware 335 * command to take to execute and return a reply to the host. The RESET 336 * and INITIALIZE commands can take a fair amount of time to execute but 337 * most execute in far less time than this maximum. This constant is used 338 * by host software to determine how long to wait for a firmware command 339 * reply before declaring the firmware as dead/unreachable ... 340 */ 341 #define FW_CMD_MAX_TIMEOUT 10000 342 343 /* 344 * If a host driver does a HELLO and discovers that there's already a MASTER 345 * selected, we may have to wait for that MASTER to finish issuing RESET, 346 * configuration and INITIALIZE commands. Also, there's a possibility that 347 * our own HELLO may get lost if it happens right as the MASTER is issuign a 348 * RESET command, so we need to be willing to make a few retries of our HELLO. 349 */ 350 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 351 #define FW_CMD_HELLO_RETRIES 3 352 353 enum fw_cmd_opcodes { 354 FW_LDST_CMD = 0x01, 355 FW_RESET_CMD = 0x03, 356 FW_HELLO_CMD = 0x04, 357 FW_BYE_CMD = 0x05, 358 FW_INITIALIZE_CMD = 0x06, 359 FW_CAPS_CONFIG_CMD = 0x07, 360 FW_PARAMS_CMD = 0x08, 361 FW_PFVF_CMD = 0x09, 362 FW_IQ_CMD = 0x10, 363 FW_EQ_ETH_CMD = 0x12, 364 FW_EQ_CTRL_CMD = 0x13, 365 FW_VI_CMD = 0x14, 366 FW_VI_MAC_CMD = 0x15, 367 FW_VI_RXMODE_CMD = 0x16, 368 FW_VI_ENABLE_CMD = 0x17, 369 FW_VI_STATS_CMD = 0x1a, 370 FW_PORT_CMD = 0x1b, 371 FW_RSS_IND_TBL_CMD = 0x20, 372 FW_RSS_GLB_CONFIG_CMD = 0x22, 373 FW_RSS_VI_CONFIG_CMD = 0x23, 374 FW_CLIP_CMD = 0x28, 375 FW_DEBUG_CMD = 0x81, 376 }; 377 378 enum fw_cmd_cap { 379 FW_CMD_CAP_PORT = 0x04, 380 }; 381 382 /* 383 * Generic command header flit0 384 */ 385 struct fw_cmd_hdr { 386 __be32 hi; 387 __be32 lo; 388 }; 389 390 #define S_FW_CMD_OP 24 391 #define M_FW_CMD_OP 0xff 392 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 393 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 394 395 #define S_FW_CMD_REQUEST 23 396 #define M_FW_CMD_REQUEST 0x1 397 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 398 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 399 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 400 401 #define S_FW_CMD_READ 22 402 #define M_FW_CMD_READ 0x1 403 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 404 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 405 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 406 407 #define S_FW_CMD_WRITE 21 408 #define M_FW_CMD_WRITE 0x1 409 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 410 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 411 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 412 413 #define S_FW_CMD_EXEC 20 414 #define M_FW_CMD_EXEC 0x1 415 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 416 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 417 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 418 419 #define S_FW_CMD_RETVAL 8 420 #define M_FW_CMD_RETVAL 0xff 421 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 422 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 423 424 #define S_FW_CMD_LEN16 0 425 #define M_FW_CMD_LEN16 0xff 426 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 427 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 428 429 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 430 431 /* address spaces 432 */ 433 enum fw_ldst_addrspc { 434 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 435 }; 436 437 struct fw_ldst_cmd { 438 __be32 op_to_addrspace; 439 __be32 cycles_to_len16; 440 union fw_ldst { 441 struct fw_ldst_addrval { 442 __be32 addr; 443 __be32 val; 444 } addrval; 445 struct fw_ldst_idctxt { 446 __be32 physid; 447 __be32 msg_ctxtflush; 448 __be32 ctxt_data7; 449 __be32 ctxt_data6; 450 __be32 ctxt_data5; 451 __be32 ctxt_data4; 452 __be32 ctxt_data3; 453 __be32 ctxt_data2; 454 __be32 ctxt_data1; 455 __be32 ctxt_data0; 456 } idctxt; 457 struct fw_ldst_mdio { 458 __be16 paddr_mmd; 459 __be16 raddr; 460 __be16 vctl; 461 __be16 rval; 462 } mdio; 463 struct fw_ldst_mps { 464 __be16 fid_ctl; 465 __be16 rplcpf_pkd; 466 __be32 rplc127_96; 467 __be32 rplc95_64; 468 __be32 rplc63_32; 469 __be32 rplc31_0; 470 __be32 atrb; 471 __be16 vlan[16]; 472 } mps; 473 struct fw_ldst_func { 474 __u8 access_ctl; 475 __u8 mod_index; 476 __be16 ctl_id; 477 __be32 offset; 478 __be64 data0; 479 __be64 data1; 480 } func; 481 struct fw_ldst_pcie { 482 __u8 ctrl_to_fn; 483 __u8 bnum; 484 __u8 r; 485 __u8 ext_r; 486 __u8 select_naccess; 487 __u8 pcie_fn; 488 __be16 nset_pkd; 489 __be32 data[12]; 490 } pcie; 491 struct fw_ldst_i2c_deprecated { 492 __u8 pid_pkd; 493 __u8 base; 494 __u8 boffset; 495 __u8 data; 496 __be32 r9; 497 } i2c_deprecated; 498 struct fw_ldst_i2c { 499 __u8 pid; 500 __u8 did; 501 __u8 boffset; 502 __u8 blen; 503 __be32 r9; 504 __u8 data[48]; 505 } i2c; 506 struct fw_ldst_le { 507 __be32 index; 508 __be32 r9; 509 __u8 val[33]; 510 __u8 r11[7]; 511 } le; 512 } u; 513 }; 514 515 #define S_FW_LDST_CMD_ADDRSPACE 0 516 #define M_FW_LDST_CMD_ADDRSPACE 0xff 517 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 518 519 struct fw_reset_cmd { 520 __be32 op_to_write; 521 __be32 retval_len16; 522 __be32 val; 523 __be32 halt_pkd; 524 }; 525 526 #define S_FW_RESET_CMD_HALT 31 527 #define M_FW_RESET_CMD_HALT 0x1 528 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 529 #define G_FW_RESET_CMD_HALT(x) \ 530 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 531 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 532 533 enum { 534 FW_HELLO_CMD_STAGE_OS = 0, 535 }; 536 537 struct fw_hello_cmd { 538 __be32 op_to_write; 539 __be32 retval_len16; 540 __be32 err_to_clearinit; 541 __be32 fwrev; 542 }; 543 544 #define S_FW_HELLO_CMD_ERR 31 545 #define M_FW_HELLO_CMD_ERR 0x1 546 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 547 #define G_FW_HELLO_CMD_ERR(x) \ 548 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 549 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 550 551 #define S_FW_HELLO_CMD_INIT 30 552 #define M_FW_HELLO_CMD_INIT 0x1 553 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 554 #define G_FW_HELLO_CMD_INIT(x) \ 555 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 556 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 557 558 #define S_FW_HELLO_CMD_MASTERDIS 29 559 #define M_FW_HELLO_CMD_MASTERDIS 0x1 560 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 561 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 562 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 563 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 564 565 #define S_FW_HELLO_CMD_MASTERFORCE 28 566 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 567 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 568 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 569 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 570 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 571 572 #define S_FW_HELLO_CMD_MBMASTER 24 573 #define M_FW_HELLO_CMD_MBMASTER 0xf 574 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 575 #define G_FW_HELLO_CMD_MBMASTER(x) \ 576 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 577 578 #define S_FW_HELLO_CMD_MBASYNCNOT 20 579 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 580 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 581 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 582 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 583 584 #define S_FW_HELLO_CMD_STAGE 17 585 #define M_FW_HELLO_CMD_STAGE 0x7 586 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 587 #define G_FW_HELLO_CMD_STAGE(x) \ 588 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 589 590 #define S_FW_HELLO_CMD_CLEARINIT 16 591 #define M_FW_HELLO_CMD_CLEARINIT 0x1 592 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 593 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 594 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 595 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 596 597 struct fw_bye_cmd { 598 __be32 op_to_write; 599 __be32 retval_len16; 600 __be64 r3; 601 }; 602 603 struct fw_initialize_cmd { 604 __be32 op_to_write; 605 __be32 retval_len16; 606 __be64 r3; 607 }; 608 609 enum fw_caps_config_nic { 610 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 611 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 612 }; 613 614 enum fw_memtype_cf { 615 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 616 }; 617 618 struct fw_caps_config_cmd { 619 __be32 op_to_write; 620 __be32 cfvalid_to_len16; 621 __be32 r2; 622 __be32 hwmbitmap; 623 __be16 nbmcaps; 624 __be16 linkcaps; 625 __be16 switchcaps; 626 __be16 r3; 627 __be16 niccaps; 628 __be16 toecaps; 629 __be16 rdmacaps; 630 __be16 cryptocaps; 631 __be16 iscsicaps; 632 __be16 fcoecaps; 633 __be32 cfcsum; 634 __be32 finiver; 635 __be32 finicsum; 636 }; 637 638 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 639 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 640 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 641 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 642 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 643 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 644 645 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 646 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 647 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 648 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 649 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 650 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 651 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 652 653 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 654 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 655 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 656 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 657 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 658 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 659 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 660 661 /* 662 * params command mnemonics 663 */ 664 enum fw_params_mnem { 665 FW_PARAMS_MNEM_DEV = 1, /* device params */ 666 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 667 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 668 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 669 }; 670 671 /* 672 * device parameters 673 */ 674 675 #define S_FW_PARAMS_PARAM_FILTER_MODE 16 676 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 677 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 678 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 679 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 680 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 681 M_FW_PARAMS_PARAM_FILTER_MODE) 682 683 #define S_FW_PARAMS_PARAM_FILTER_MASK 0 684 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 685 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 686 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 687 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 688 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 689 M_FW_PARAMS_PARAM_FILTER_MASK) 690 691 enum fw_params_param_dev { 692 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 693 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 694 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 695 * allocated by the device's 696 * Lookup Engine 697 */ 698 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */ 699 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */ 700 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 701 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 702 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 703 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 704 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 705 FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32, 706 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 707 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 708 }; 709 710 /* 711 * physical and virtual function parameters 712 */ 713 enum fw_params_param_pfvf { 714 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 715 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 716 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 717 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 718 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 719 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 720 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 721 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 722 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 723 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 724 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 725 }; 726 727 /* 728 * dma queue parameters 729 */ 730 enum fw_params_param_dmaq { 731 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 732 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 733 }; 734 735 enum fw_params_param_dev_filter { 736 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 737 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 738 }; 739 740 #define S_FW_PARAMS_MNEM 24 741 #define M_FW_PARAMS_MNEM 0xff 742 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 743 #define G_FW_PARAMS_MNEM(x) \ 744 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 745 746 #define S_FW_PARAMS_PARAM_X 16 747 #define M_FW_PARAMS_PARAM_X 0xff 748 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 749 #define G_FW_PARAMS_PARAM_X(x) \ 750 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 751 752 #define S_FW_PARAMS_PARAM_Y 8 753 #define M_FW_PARAMS_PARAM_Y 0xff 754 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 755 #define G_FW_PARAMS_PARAM_Y(x) \ 756 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 757 758 #define S_FW_PARAMS_PARAM_Z 0 759 #define M_FW_PARAMS_PARAM_Z 0xff 760 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 761 #define G_FW_PARAMS_PARAM_Z(x) \ 762 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 763 764 #define S_FW_PARAMS_PARAM_YZ 0 765 #define M_FW_PARAMS_PARAM_YZ 0xffff 766 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 767 #define G_FW_PARAMS_PARAM_YZ(x) \ 768 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 769 770 #define S_FW_PARAMS_PARAM_XYZ 0 771 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 772 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 773 774 struct fw_params_cmd { 775 __be32 op_to_vfn; 776 __be32 retval_len16; 777 struct fw_params_param { 778 __be32 mnem; 779 __be32 val; 780 } param[7]; 781 }; 782 783 #define S_FW_PARAMS_CMD_PFN 8 784 #define M_FW_PARAMS_CMD_PFN 0x7 785 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 786 #define G_FW_PARAMS_CMD_PFN(x) \ 787 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 788 789 #define S_FW_PARAMS_CMD_VFN 0 790 #define M_FW_PARAMS_CMD_VFN 0xff 791 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 792 #define G_FW_PARAMS_CMD_VFN(x) \ 793 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 794 795 struct fw_pfvf_cmd { 796 __be32 op_to_vfn; 797 __be32 retval_len16; 798 __be32 niqflint_niq; 799 __be32 type_to_neq; 800 __be32 tc_to_nexactf; 801 __be32 r_caps_to_nethctrl; 802 __be16 nricq; 803 __be16 nriqp; 804 __be32 r4; 805 }; 806 807 #define S_FW_PFVF_CMD_PFN 8 808 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 809 810 #define S_FW_PFVF_CMD_VFN 0 811 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 812 813 #define S_FW_PFVF_CMD_NIQFLINT 20 814 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 815 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 816 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 817 818 #define S_FW_PFVF_CMD_NIQ 0 819 #define M_FW_PFVF_CMD_NIQ 0xfffff 820 #define G_FW_PFVF_CMD_NIQ(x) \ 821 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 822 823 #define S_FW_PFVF_CMD_PMASK 20 824 #define M_FW_PFVF_CMD_PMASK 0xf 825 #define G_FW_PFVF_CMD_PMASK(x) \ 826 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 827 828 #define S_FW_PFVF_CMD_NEQ 0 829 #define M_FW_PFVF_CMD_NEQ 0xfffff 830 #define G_FW_PFVF_CMD_NEQ(x) \ 831 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 832 833 #define S_FW_PFVF_CMD_TC 24 834 #define M_FW_PFVF_CMD_TC 0xff 835 #define G_FW_PFVF_CMD_TC(x) \ 836 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 837 838 #define S_FW_PFVF_CMD_NVI 16 839 #define M_FW_PFVF_CMD_NVI 0xff 840 #define G_FW_PFVF_CMD_NVI(x) \ 841 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 842 843 #define S_FW_PFVF_CMD_NEXACTF 0 844 #define M_FW_PFVF_CMD_NEXACTF 0xffff 845 #define G_FW_PFVF_CMD_NEXACTF(x) \ 846 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 847 848 #define S_FW_PFVF_CMD_R_CAPS 24 849 #define M_FW_PFVF_CMD_R_CAPS 0xff 850 #define G_FW_PFVF_CMD_R_CAPS(x) \ 851 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 852 853 #define S_FW_PFVF_CMD_WX_CAPS 16 854 #define M_FW_PFVF_CMD_WX_CAPS 0xff 855 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 856 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 857 858 #define S_FW_PFVF_CMD_NETHCTRL 0 859 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 860 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 861 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 862 863 /* 864 * ingress queue type; the first 1K ingress queues can have associated 0, 865 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 866 * capabilities 867 */ 868 enum fw_iq_type { 869 FW_IQ_TYPE_FL_INT_CAP, 870 }; 871 872 enum fw_iq_iqtype { 873 FW_IQ_IQTYPE_NIC = 1, 874 FW_IQ_IQTYPE_OFLD, 875 }; 876 877 struct fw_iq_cmd { 878 __be32 op_to_vfn; 879 __be32 alloc_to_len16; 880 __be16 physiqid; 881 __be16 iqid; 882 __be16 fl0id; 883 __be16 fl1id; 884 __be32 type_to_iqandstindex; 885 __be16 iqdroprss_to_iqesize; 886 __be16 iqsize; 887 __be64 iqaddr; 888 __be32 iqns_to_fl0congen; 889 __be16 fl0dcaen_to_fl0cidxfthresh; 890 __be16 fl0size; 891 __be64 fl0addr; 892 __be32 fl1cngchmap_to_fl1congen; 893 __be16 fl1dcaen_to_fl1cidxfthresh; 894 __be16 fl1size; 895 __be64 fl1addr; 896 }; 897 898 #define S_FW_IQ_CMD_PFN 8 899 #define M_FW_IQ_CMD_PFN 0x7 900 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 901 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 902 903 #define S_FW_IQ_CMD_VFN 0 904 #define M_FW_IQ_CMD_VFN 0xff 905 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 906 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 907 908 #define S_FW_IQ_CMD_ALLOC 31 909 #define M_FW_IQ_CMD_ALLOC 0x1 910 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 911 #define G_FW_IQ_CMD_ALLOC(x) \ 912 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 913 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 914 915 #define S_FW_IQ_CMD_FREE 30 916 #define M_FW_IQ_CMD_FREE 0x1 917 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 918 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 919 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 920 921 #define S_FW_IQ_CMD_IQSTART 28 922 #define M_FW_IQ_CMD_IQSTART 0x1 923 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 924 #define G_FW_IQ_CMD_IQSTART(x) \ 925 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 926 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 927 928 #define S_FW_IQ_CMD_IQSTOP 27 929 #define M_FW_IQ_CMD_IQSTOP 0x1 930 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 931 #define G_FW_IQ_CMD_IQSTOP(x) \ 932 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 933 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 934 935 #define S_FW_IQ_CMD_TYPE 29 936 #define M_FW_IQ_CMD_TYPE 0x7 937 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 938 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 939 940 #define S_FW_IQ_CMD_IQASYNCH 28 941 #define M_FW_IQ_CMD_IQASYNCH 0x1 942 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 943 #define G_FW_IQ_CMD_IQASYNCH(x) \ 944 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 945 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 946 947 #define S_FW_IQ_CMD_VIID 16 948 #define M_FW_IQ_CMD_VIID 0xfff 949 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 950 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 951 952 #define S_FW_IQ_CMD_IQANDST 15 953 #define M_FW_IQ_CMD_IQANDST 0x1 954 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 955 #define G_FW_IQ_CMD_IQANDST(x) \ 956 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 957 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 958 959 #define S_FW_IQ_CMD_IQANUD 12 960 #define M_FW_IQ_CMD_IQANUD 0x3 961 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 962 #define G_FW_IQ_CMD_IQANUD(x) \ 963 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 964 965 #define S_FW_IQ_CMD_IQANDSTINDEX 0 966 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 967 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 968 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 969 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 970 971 #define S_FW_IQ_CMD_IQGTSMODE 14 972 #define M_FW_IQ_CMD_IQGTSMODE 0x1 973 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 974 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 975 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 976 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 977 978 #define S_FW_IQ_CMD_IQPCIECH 12 979 #define M_FW_IQ_CMD_IQPCIECH 0x3 980 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 981 #define G_FW_IQ_CMD_IQPCIECH(x) \ 982 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 983 984 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 985 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 986 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 987 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 988 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 989 990 #define S_FW_IQ_CMD_IQESIZE 0 991 #define M_FW_IQ_CMD_IQESIZE 0x3 992 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 993 #define G_FW_IQ_CMD_IQESIZE(x) \ 994 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 995 996 #define S_FW_IQ_CMD_IQRO 30 997 #define M_FW_IQ_CMD_IQRO 0x1 998 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 999 #define G_FW_IQ_CMD_IQRO(x) \ 1000 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 1001 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 1002 1003 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 1004 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 1005 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 1006 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 1007 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 1008 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 1009 1010 #define S_FW_IQ_CMD_IQTYPE 24 1011 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 1012 1013 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 1014 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 1015 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 1016 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 1017 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 1018 1019 #define S_FW_IQ_CMD_FL0DATARO 12 1020 #define M_FW_IQ_CMD_FL0DATARO 0x1 1021 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 1022 #define G_FW_IQ_CMD_FL0DATARO(x) \ 1023 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 1024 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 1025 1026 #define S_FW_IQ_CMD_FL0CONGCIF 11 1027 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 1028 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 1029 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 1030 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 1031 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 1032 1033 #define S_FW_IQ_CMD_FL0FETCHRO 6 1034 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 1035 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 1036 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 1037 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 1038 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 1039 1040 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 1041 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 1042 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 1043 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 1044 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 1045 1046 #define S_FW_IQ_CMD_FL0PADEN 2 1047 #define M_FW_IQ_CMD_FL0PADEN 0x1 1048 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 1049 #define G_FW_IQ_CMD_FL0PADEN(x) \ 1050 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 1051 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 1052 1053 #define S_FW_IQ_CMD_FL0PACKEN 1 1054 #define M_FW_IQ_CMD_FL0PACKEN 0x1 1055 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 1056 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 1057 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 1058 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 1059 1060 #define S_FW_IQ_CMD_FL0CONGEN 0 1061 #define M_FW_IQ_CMD_FL0CONGEN 0x1 1062 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 1063 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 1064 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 1065 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 1066 1067 #define S_FW_IQ_CMD_FL0FBMIN 7 1068 #define M_FW_IQ_CMD_FL0FBMIN 0x7 1069 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 1070 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 1071 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 1072 1073 #define S_FW_IQ_CMD_FL0FBMAX 4 1074 #define M_FW_IQ_CMD_FL0FBMAX 0x7 1075 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 1076 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 1077 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 1078 1079 struct fw_eq_eth_cmd { 1080 __be32 op_to_vfn; 1081 __be32 alloc_to_len16; 1082 __be32 eqid_pkd; 1083 __be32 physeqid_pkd; 1084 __be32 fetchszm_to_iqid; 1085 __be32 dcaen_to_eqsize; 1086 __be64 eqaddr; 1087 __be32 autoequiqe_to_viid; 1088 __be32 r8_lo; 1089 __be64 r9; 1090 }; 1091 1092 #define S_FW_EQ_ETH_CMD_PFN 8 1093 #define M_FW_EQ_ETH_CMD_PFN 0x7 1094 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 1095 #define G_FW_EQ_ETH_CMD_PFN(x) \ 1096 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 1097 1098 #define S_FW_EQ_ETH_CMD_VFN 0 1099 #define M_FW_EQ_ETH_CMD_VFN 0xff 1100 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 1101 #define G_FW_EQ_ETH_CMD_VFN(x) \ 1102 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 1103 1104 #define S_FW_EQ_ETH_CMD_ALLOC 31 1105 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 1106 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 1107 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 1108 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 1109 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 1110 1111 #define S_FW_EQ_ETH_CMD_FREE 30 1112 #define M_FW_EQ_ETH_CMD_FREE 0x1 1113 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 1114 #define G_FW_EQ_ETH_CMD_FREE(x) \ 1115 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 1116 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 1117 1118 #define S_FW_EQ_ETH_CMD_EQSTART 28 1119 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 1120 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 1121 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 1122 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 1123 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 1124 1125 #define S_FW_EQ_ETH_CMD_EQID 0 1126 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 1127 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 1128 #define G_FW_EQ_ETH_CMD_EQID(x) \ 1129 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 1130 1131 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 1132 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 1133 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 1134 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 1135 1136 #define S_FW_EQ_ETH_CMD_FETCHRO 22 1137 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 1138 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 1139 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 1140 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 1141 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 1142 1143 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 1144 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 1145 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 1146 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 1147 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 1148 1149 #define S_FW_EQ_ETH_CMD_PCIECHN 16 1150 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 1151 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 1152 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 1153 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 1154 1155 #define S_FW_EQ_ETH_CMD_IQID 0 1156 #define M_FW_EQ_ETH_CMD_IQID 0xffff 1157 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 1158 #define G_FW_EQ_ETH_CMD_IQID(x) \ 1159 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 1160 1161 #define S_FW_EQ_ETH_CMD_FBMIN 23 1162 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 1163 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 1164 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 1165 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 1166 1167 #define S_FW_EQ_ETH_CMD_FBMAX 20 1168 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 1169 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 1170 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 1171 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 1172 1173 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 1174 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 1175 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 1176 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 1177 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 1178 1179 #define S_FW_EQ_ETH_CMD_EQSIZE 0 1180 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 1181 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 1182 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 1183 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 1184 1185 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 1186 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 1187 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 1188 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 1189 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 1190 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 1191 1192 #define S_FW_EQ_ETH_CMD_VIID 16 1193 #define M_FW_EQ_ETH_CMD_VIID 0xfff 1194 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 1195 #define G_FW_EQ_ETH_CMD_VIID(x) \ 1196 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 1197 1198 struct fw_eq_ctrl_cmd { 1199 __be32 op_to_vfn; 1200 __be32 alloc_to_len16; 1201 __be32 cmpliqid_eqid; 1202 __be32 physeqid_pkd; 1203 __be32 fetchszm_to_iqid; 1204 __be32 dcaen_to_eqsize; 1205 __be64 eqaddr; 1206 }; 1207 1208 #define S_FW_EQ_CTRL_CMD_PFN 8 1209 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 1210 1211 #define S_FW_EQ_CTRL_CMD_VFN 0 1212 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 1213 1214 #define S_FW_EQ_CTRL_CMD_ALLOC 31 1215 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 1216 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 1217 1218 #define S_FW_EQ_CTRL_CMD_FREE 30 1219 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 1220 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 1221 1222 #define S_FW_EQ_CTRL_CMD_EQSTART 28 1223 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 1224 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 1225 1226 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 1227 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 1228 1229 #define S_FW_EQ_CTRL_CMD_EQID 0 1230 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 1231 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 1232 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 1233 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 1234 1235 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 1236 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 1237 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 1238 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 1239 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 1240 1241 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 1242 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 1243 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 1244 1245 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 1246 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 1247 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 1248 1249 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 1250 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 1251 1252 #define S_FW_EQ_CTRL_CMD_IQID 0 1253 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 1254 1255 #define S_FW_EQ_CTRL_CMD_FBMIN 23 1256 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 1257 1258 #define S_FW_EQ_CTRL_CMD_FBMAX 20 1259 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 1260 1261 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 1262 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 1263 1264 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 1265 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 1266 1267 enum fw_vi_func { 1268 FW_VI_FUNC_ETH, 1269 }; 1270 1271 /* Macros for VIID parsing: 1272 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 1273 */ 1274 1275 #define S_FW_VIID_VIVLD 7 1276 #define M_FW_VIID_VIVLD 0x1 1277 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 1278 1279 #define S_FW_VIID_VIN 0 1280 #define M_FW_VIID_VIN 0x7F 1281 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 1282 1283 struct fw_vi_cmd { 1284 __be32 op_to_vfn; 1285 __be32 alloc_to_len16; 1286 __be16 type_to_viid; 1287 __u8 mac[6]; 1288 __u8 portid_pkd; 1289 __u8 nmac; 1290 __u8 nmac0[6]; 1291 __be16 norss_rsssize; 1292 __u8 nmac1[6]; 1293 __be16 idsiiq_pkd; 1294 __u8 nmac2[6]; 1295 __be16 idseiq_pkd; 1296 __u8 nmac3[6]; 1297 __be64 r9; 1298 __be64 r10; 1299 }; 1300 1301 #define S_FW_VI_CMD_PFN 8 1302 #define M_FW_VI_CMD_PFN 0x7 1303 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 1304 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 1305 1306 #define S_FW_VI_CMD_VFN 0 1307 #define M_FW_VI_CMD_VFN 0xff 1308 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 1309 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 1310 1311 #define S_FW_VI_CMD_ALLOC 31 1312 #define M_FW_VI_CMD_ALLOC 0x1 1313 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 1314 #define G_FW_VI_CMD_ALLOC(x) \ 1315 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 1316 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 1317 1318 #define S_FW_VI_CMD_FREE 30 1319 #define M_FW_VI_CMD_FREE 0x1 1320 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 1321 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 1322 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 1323 1324 #define S_FW_VI_CMD_VFVLD 24 1325 #define M_FW_VI_CMD_VFVLD 0x1 1326 #define G_FW_VI_CMD_VFVLD(x) \ 1327 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 1328 1329 #define S_FW_VI_CMD_VIN 16 1330 #define M_FW_VI_CMD_VIN 0xff 1331 #define G_FW_VI_CMD_VIN(x) \ 1332 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 1333 1334 #define S_FW_VI_CMD_TYPE 15 1335 #define M_FW_VI_CMD_TYPE 0x1 1336 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 1337 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 1338 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 1339 1340 #define S_FW_VI_CMD_FUNC 12 1341 #define M_FW_VI_CMD_FUNC 0x7 1342 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 1343 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 1344 1345 #define S_FW_VI_CMD_VIID 0 1346 #define M_FW_VI_CMD_VIID 0xfff 1347 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 1348 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 1349 1350 #define S_FW_VI_CMD_PORTID 4 1351 #define M_FW_VI_CMD_PORTID 0xf 1352 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 1353 #define G_FW_VI_CMD_PORTID(x) \ 1354 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 1355 1356 #define S_FW_VI_CMD_RSSSIZE 0 1357 #define M_FW_VI_CMD_RSSSIZE 0x7ff 1358 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 1359 #define G_FW_VI_CMD_RSSSIZE(x) \ 1360 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 1361 1362 /* Special VI_MAC command index ids */ 1363 #define FW_VI_MAC_ADD_MAC 0x3FF 1364 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1365 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 1366 1367 enum fw_vi_mac_smac { 1368 FW_VI_MAC_MPS_TCAM_ENTRY = 0x0, 1369 FW_VI_MAC_SMT_AND_MPSTCAM = 0x3 1370 }; 1371 1372 enum fw_vi_mac_entry_types { 1373 FW_VI_MAC_TYPE_RAW = 0x2, 1374 }; 1375 1376 struct fw_vi_mac_cmd { 1377 __be32 op_to_viid; 1378 __be32 freemacs_to_len16; 1379 union fw_vi_mac { 1380 struct fw_vi_mac_exact { 1381 __be16 valid_to_idx; 1382 __u8 macaddr[6]; 1383 } exact[7]; 1384 struct fw_vi_mac_hash { 1385 __be64 hashvec; 1386 } hash; 1387 struct fw_vi_mac_raw { 1388 __be32 raw_idx_pkd; 1389 __be32 data0_pkd; 1390 __be32 data1[2]; 1391 __be64 data0m_pkd; 1392 __be32 data1m[2]; 1393 } raw; 1394 } u; 1395 }; 1396 1397 #define S_FW_VI_MAC_CMD_VIID 0 1398 #define M_FW_VI_MAC_CMD_VIID 0xfff 1399 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 1400 #define G_FW_VI_MAC_CMD_VIID(x) \ 1401 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 1402 1403 #define S_FW_VI_MAC_CMD_FREEMACS 31 1404 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 1405 1406 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 1407 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 1408 1409 #define S_FW_VI_MAC_CMD_VALID 15 1410 #define M_FW_VI_MAC_CMD_VALID 0x1 1411 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 1412 #define G_FW_VI_MAC_CMD_VALID(x) \ 1413 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 1414 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 1415 1416 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 1417 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 1418 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 1419 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 1420 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 1421 1422 #define S_FW_VI_MAC_CMD_IDX 0 1423 #define M_FW_VI_MAC_CMD_IDX 0x3ff 1424 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 1425 #define G_FW_VI_MAC_CMD_IDX(x) \ 1426 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 1427 1428 #define S_FW_VI_MAC_CMD_RAW_IDX 16 1429 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 1430 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 1431 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 1432 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 1433 1434 struct fw_vi_rxmode_cmd { 1435 __be32 op_to_viid; 1436 __be32 retval_len16; 1437 __be32 mtu_to_vlanexen; 1438 __be32 r4_lo; 1439 }; 1440 1441 #define S_FW_VI_RXMODE_CMD_VIID 0 1442 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 1443 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 1444 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 1445 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 1446 1447 #define S_FW_VI_RXMODE_CMD_MTU 16 1448 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 1449 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 1450 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 1451 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 1452 1453 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 1454 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 1455 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 1456 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 1457 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 1458 1459 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 1460 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 1461 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1462 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 1463 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1464 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 1465 1466 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 1467 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 1468 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1469 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 1470 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1471 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 1472 M_FW_VI_RXMODE_CMD_BROADCASTEN) 1473 1474 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 1475 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 1476 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 1477 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 1478 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 1479 1480 struct fw_vi_enable_cmd { 1481 __be32 op_to_viid; 1482 __be32 ien_to_len16; 1483 __be16 blinkdur; 1484 __be16 r3; 1485 __be32 r4; 1486 }; 1487 1488 #define S_FW_VI_ENABLE_CMD_VIID 0 1489 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 1490 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 1491 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 1492 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 1493 1494 #define S_FW_VI_ENABLE_CMD_IEN 31 1495 #define M_FW_VI_ENABLE_CMD_IEN 0x1 1496 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 1497 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 1498 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 1499 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 1500 1501 #define S_FW_VI_ENABLE_CMD_EEN 30 1502 #define M_FW_VI_ENABLE_CMD_EEN 0x1 1503 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 1504 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 1505 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 1506 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 1507 1508 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 1509 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 1510 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 1511 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 1512 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 1513 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 1514 1515 /* VI VF stats offset definitions */ 1516 #define VI_VF_NUM_STATS 16 1517 1518 /* VI PF stats offset definitions */ 1519 #define VI_PF_NUM_STATS 17 1520 enum fw_vi_stats_pf_index { 1521 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 1522 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 1523 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 1524 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 1525 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 1526 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 1527 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 1528 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 1529 FW_VI_PF_STAT_RX_BYTES_IX, 1530 FW_VI_PF_STAT_RX_FRAMES_IX, 1531 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 1532 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 1533 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 1534 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1535 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1536 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1537 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1538 }; 1539 1540 struct fw_vi_stats_cmd { 1541 __be32 op_to_viid; 1542 __be32 retval_len16; 1543 union fw_vi_stats { 1544 struct fw_vi_stats_ctl { 1545 __be16 nstats_ix; 1546 __be16 r6; 1547 __be32 r7; 1548 __be64 stat0; 1549 __be64 stat1; 1550 __be64 stat2; 1551 __be64 stat3; 1552 __be64 stat4; 1553 __be64 stat5; 1554 } ctl; 1555 struct fw_vi_stats_pf { 1556 __be64 tx_bcast_bytes; 1557 __be64 tx_bcast_frames; 1558 __be64 tx_mcast_bytes; 1559 __be64 tx_mcast_frames; 1560 __be64 tx_ucast_bytes; 1561 __be64 tx_ucast_frames; 1562 __be64 tx_offload_bytes; 1563 __be64 tx_offload_frames; 1564 __be64 rx_pf_bytes; 1565 __be64 rx_pf_frames; 1566 __be64 rx_bcast_bytes; 1567 __be64 rx_bcast_frames; 1568 __be64 rx_mcast_bytes; 1569 __be64 rx_mcast_frames; 1570 __be64 rx_ucast_bytes; 1571 __be64 rx_ucast_frames; 1572 __be64 rx_err_frames; 1573 } pf; 1574 struct fw_vi_stats_vf { 1575 __be64 tx_bcast_bytes; 1576 __be64 tx_bcast_frames; 1577 __be64 tx_mcast_bytes; 1578 __be64 tx_mcast_frames; 1579 __be64 tx_ucast_bytes; 1580 __be64 tx_ucast_frames; 1581 __be64 tx_drop_frames; 1582 __be64 tx_offload_bytes; 1583 __be64 tx_offload_frames; 1584 __be64 rx_bcast_bytes; 1585 __be64 rx_bcast_frames; 1586 __be64 rx_mcast_bytes; 1587 __be64 rx_mcast_frames; 1588 __be64 rx_ucast_bytes; 1589 __be64 rx_ucast_frames; 1590 __be64 rx_err_frames; 1591 } vf; 1592 } u; 1593 }; 1594 1595 #define S_FW_VI_STATS_CMD_VIID 0 1596 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 1597 1598 #define S_FW_VI_STATS_CMD_NSTATS 12 1599 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 1600 1601 #define S_FW_VI_STATS_CMD_IX 0 1602 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 1603 1604 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 1605 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 1606 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 1607 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 1608 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 1609 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 1610 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 1611 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 1612 #define FW_PORT_CAP32_FC_RX 0x00010000UL 1613 #define FW_PORT_CAP32_FC_TX 0x00020000UL 1614 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 1615 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 1616 #define FW_PORT_CAP32_ANEG 0x00100000UL 1617 #define FW_PORT_CAP32_MDIX 0x00200000UL 1618 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 1619 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 1620 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 1621 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL 1622 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 1623 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL 1624 1625 #define S_FW_PORT_CAP32_SPEED 0 1626 #define M_FW_PORT_CAP32_SPEED 0xfff 1627 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 1628 #define G_FW_PORT_CAP32_SPEED(x) \ 1629 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 1630 1631 #define S_FW_PORT_CAP32_FC 16 1632 #define M_FW_PORT_CAP32_FC 0x3 1633 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 1634 1635 #define S_FW_PORT_CAP32_802_3 18 1636 #define M_FW_PORT_CAP32_802_3 0x3 1637 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 1638 1639 enum fw_port_mdi32 { 1640 FW_PORT_CAP32_MDI_AUTO = 1, 1641 }; 1642 1643 #define S_FW_PORT_CAP32_MDI 21 1644 #define M_FW_PORT_CAP32_MDI 3 1645 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 1646 #define G_FW_PORT_CAP32_MDI(x) \ 1647 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 1648 1649 #define S_FW_PORT_CAP32_FEC 23 1650 #define M_FW_PORT_CAP32_FEC 0x1f 1651 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 1652 1653 enum fw_port_action { 1654 FW_PORT_ACTION_L1_CFG32 = 0x0009, 1655 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 1656 }; 1657 1658 struct fw_port_cmd { 1659 __be32 op_to_portid; 1660 __be32 action_to_len16; 1661 union fw_port { 1662 struct fw_port_l1cfg { 1663 __be32 rcap; 1664 __be32 r; 1665 } l1cfg; 1666 struct fw_port_l2cfg { 1667 __u8 ctlbf; 1668 __u8 ovlan3_to_ivlan0; 1669 __be16 ivlantype; 1670 __be16 txipg_force_pinfo; 1671 __be16 mtu; 1672 __be16 ovlan0mask; 1673 __be16 ovlan0type; 1674 __be16 ovlan1mask; 1675 __be16 ovlan1type; 1676 __be16 ovlan2mask; 1677 __be16 ovlan2type; 1678 __be16 ovlan3mask; 1679 __be16 ovlan3type; 1680 } l2cfg; 1681 struct fw_port_info { 1682 __be32 lstatus_to_modtype; 1683 __be16 pcap; 1684 __be16 acap; 1685 __be16 mtu; 1686 __u8 cbllen; 1687 __u8 auxlinfo; 1688 __u8 dcbxdis_pkd; 1689 __u8 r8_lo; 1690 __be16 lpacap; 1691 __be64 r9; 1692 } info; 1693 struct fw_port_diags { 1694 __u8 diagop; 1695 __u8 r[3]; 1696 __be32 diagval; 1697 } diags; 1698 union fw_port_dcb { 1699 struct fw_port_dcb_pgid { 1700 __u8 type; 1701 __u8 apply_pkd; 1702 __u8 r10_lo[2]; 1703 __be32 pgid; 1704 __be64 r11; 1705 } pgid; 1706 struct fw_port_dcb_pgrate { 1707 __u8 type; 1708 __u8 apply_pkd; 1709 __u8 r10_lo[5]; 1710 __u8 num_tcs_supported; 1711 __u8 pgrate[8]; 1712 __u8 tsa[8]; 1713 } pgrate; 1714 struct fw_port_dcb_priorate { 1715 __u8 type; 1716 __u8 apply_pkd; 1717 __u8 r10_lo[6]; 1718 __u8 strict_priorate[8]; 1719 } priorate; 1720 struct fw_port_dcb_pfc { 1721 __u8 type; 1722 __u8 pfcen; 1723 __u8 r10[5]; 1724 __u8 max_pfc_tcs; 1725 __be64 r11; 1726 } pfc; 1727 struct fw_port_app_priority { 1728 __u8 type; 1729 __u8 r10[2]; 1730 __u8 idx; 1731 __u8 user_prio_map; 1732 __u8 sel_field; 1733 __be16 protocolid; 1734 __be64 r12; 1735 } app_priority; 1736 struct fw_port_dcb_control { 1737 __u8 type; 1738 __u8 all_syncd_pkd; 1739 __be16 dcb_version_to_app_state; 1740 __be32 r11; 1741 __be64 r12; 1742 } control; 1743 } dcb; 1744 struct fw_port_l1cfg32 { 1745 __be32 rcap32; 1746 __be32 r; 1747 } l1cfg32; 1748 struct fw_port_info32 { 1749 __be32 lstatus32_to_cbllen32; 1750 __be32 auxlinfo32_mtu32; 1751 __be32 linkattr32; 1752 __be32 pcaps32; 1753 __be32 acaps32; 1754 __be32 lpacaps32; 1755 } info32; 1756 } u; 1757 }; 1758 1759 #define S_FW_PORT_CMD_PORTID 0 1760 #define M_FW_PORT_CMD_PORTID 0xf 1761 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 1762 #define G_FW_PORT_CMD_PORTID(x) \ 1763 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 1764 1765 #define S_FW_PORT_CMD_ACTION 16 1766 #define M_FW_PORT_CMD_ACTION 0xffff 1767 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 1768 #define G_FW_PORT_CMD_ACTION(x) \ 1769 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 1770 1771 #define S_FW_PORT_CMD_LSTATUS 31 1772 #define M_FW_PORT_CMD_LSTATUS 0x1 1773 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 1774 #define G_FW_PORT_CMD_LSTATUS(x) \ 1775 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 1776 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 1777 1778 #define S_FW_PORT_CMD_LSPEED 24 1779 #define M_FW_PORT_CMD_LSPEED 0x3f 1780 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 1781 #define G_FW_PORT_CMD_LSPEED(x) \ 1782 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 1783 1784 #define S_FW_PORT_CMD_TXPAUSE 23 1785 #define M_FW_PORT_CMD_TXPAUSE 0x1 1786 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 1787 #define G_FW_PORT_CMD_TXPAUSE(x) \ 1788 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 1789 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 1790 1791 #define S_FW_PORT_CMD_RXPAUSE 22 1792 #define M_FW_PORT_CMD_RXPAUSE 0x1 1793 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 1794 #define G_FW_PORT_CMD_RXPAUSE(x) \ 1795 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 1796 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 1797 1798 #define S_FW_PORT_CMD_PTYPE 8 1799 #define M_FW_PORT_CMD_PTYPE 0x1f 1800 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 1801 #define G_FW_PORT_CMD_PTYPE(x) \ 1802 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 1803 1804 #define S_FW_PORT_CMD_LSTATUS32 31 1805 #define M_FW_PORT_CMD_LSTATUS32 0x1 1806 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 1807 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 1808 1809 #define S_FW_PORT_CMD_LINKDNRC32 28 1810 #define M_FW_PORT_CMD_LINKDNRC32 0x7 1811 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 1812 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 1813 1814 #define S_FW_PORT_CMD_MDIOCAP32 26 1815 #define M_FW_PORT_CMD_MDIOCAP32 0x1 1816 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 1817 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 1818 1819 #define S_FW_PORT_CMD_MDIOADDR32 21 1820 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 1821 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 1822 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 1823 1824 #define S_FW_PORT_CMD_PORTTYPE32 13 1825 #define M_FW_PORT_CMD_PORTTYPE32 0xff 1826 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 1827 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 1828 1829 #define S_FW_PORT_CMD_MODTYPE32 8 1830 #define M_FW_PORT_CMD_MODTYPE32 0x1f 1831 #define G_FW_PORT_CMD_MODTYPE32(x) \ 1832 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 1833 1834 /* 1835 * These are configured into the VPD and hence tools that generate 1836 * VPD may use this enumeration. 1837 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 1838 * 1839 * REMEMBER: 1840 * Update the Common Code t4_hw.c:t4_get_port_type_description() 1841 * with any new Firmware Port Technology Types! 1842 */ 1843 enum fw_port_type { 1844 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 1845 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 1846 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 1847 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 1848 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 1849 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 1850 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 1851 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 1852 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 1853 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 1854 FW_PORT_TYPE_BP_AP = 10, 1855 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 1856 FW_PORT_TYPE_BP4_AP = 11, 1857 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 1858 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 1859 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 1860 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 1861 FW_PORT_TYPE_BP40_BA = 15, 1862 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 1863 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 1864 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 1865 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 1866 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 1867 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 1868 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 1869 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 1870 }; 1871 1872 /* These are read from module's EEPROM and determined once the 1873 * module is inserted. 1874 */ 1875 enum fw_port_module_type { 1876 FW_PORT_MOD_TYPE_NA = 0x0, 1877 FW_PORT_MOD_TYPE_LR = 0x1, 1878 FW_PORT_MOD_TYPE_SR = 0x2, 1879 FW_PORT_MOD_TYPE_ER = 0x3, 1880 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 1881 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 1882 FW_PORT_MOD_TYPE_LRM = 0x6, 1883 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE32 - 3, 1884 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE32 - 2, 1885 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE32 - 1, 1886 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE32 1887 }; 1888 1889 /* used by FW and tools may use this to generate VPD */ 1890 enum fw_port_mod_sub_type { 1891 FW_PORT_MOD_SUB_TYPE_NA, 1892 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 1893 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 1894 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 1895 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 1896 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 1897 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6, 1898 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7, 1899 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 1900 1901 /* 1902 * The following will never been in the VPD. They are TWINAX cable 1903 * lengths decoded from SFP+ module i2c PROMs. These should almost 1904 * certainly go somewhere else ... 1905 */ 1906 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 1907 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 1908 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 1909 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 1910 }; 1911 1912 /* link down reason codes (3b) */ 1913 enum fw_port_link_dn_rc { 1914 FW_PORT_LINK_DN_RC_NONE, 1915 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 1916 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 1917 FW_PORT_LINK_DN_RESERVED3, 1918 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 1919 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 1920 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 1921 FW_PORT_LINK_DN_RESERVED7 1922 }; 1923 1924 /* port stats */ 1925 #define FW_NUM_PORT_STATS 50 1926 #define FW_NUM_PORT_TX_STATS 23 1927 #define FW_NUM_PORT_RX_STATS 27 1928 1929 enum fw_port_stats_tx_index { 1930 FW_STAT_TX_PORT_BYTES_IX, 1931 FW_STAT_TX_PORT_FRAMES_IX, 1932 FW_STAT_TX_PORT_BCAST_IX, 1933 FW_STAT_TX_PORT_MCAST_IX, 1934 FW_STAT_TX_PORT_UCAST_IX, 1935 FW_STAT_TX_PORT_ERROR_IX, 1936 FW_STAT_TX_PORT_64B_IX, 1937 FW_STAT_TX_PORT_65B_127B_IX, 1938 FW_STAT_TX_PORT_128B_255B_IX, 1939 FW_STAT_TX_PORT_256B_511B_IX, 1940 FW_STAT_TX_PORT_512B_1023B_IX, 1941 FW_STAT_TX_PORT_1024B_1518B_IX, 1942 FW_STAT_TX_PORT_1519B_MAX_IX, 1943 FW_STAT_TX_PORT_DROP_IX, 1944 FW_STAT_TX_PORT_PAUSE_IX, 1945 FW_STAT_TX_PORT_PPP0_IX, 1946 FW_STAT_TX_PORT_PPP1_IX, 1947 FW_STAT_TX_PORT_PPP2_IX, 1948 FW_STAT_TX_PORT_PPP3_IX, 1949 FW_STAT_TX_PORT_PPP4_IX, 1950 FW_STAT_TX_PORT_PPP5_IX, 1951 FW_STAT_TX_PORT_PPP6_IX, 1952 FW_STAT_TX_PORT_PPP7_IX 1953 }; 1954 1955 enum fw_port_stat_rx_index { 1956 FW_STAT_RX_PORT_BYTES_IX, 1957 FW_STAT_RX_PORT_FRAMES_IX, 1958 FW_STAT_RX_PORT_BCAST_IX, 1959 FW_STAT_RX_PORT_MCAST_IX, 1960 FW_STAT_RX_PORT_UCAST_IX, 1961 FW_STAT_RX_PORT_MTU_ERROR_IX, 1962 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 1963 FW_STAT_RX_PORT_CRC_ERROR_IX, 1964 FW_STAT_RX_PORT_LEN_ERROR_IX, 1965 FW_STAT_RX_PORT_SYM_ERROR_IX, 1966 FW_STAT_RX_PORT_64B_IX, 1967 FW_STAT_RX_PORT_65B_127B_IX, 1968 FW_STAT_RX_PORT_128B_255B_IX, 1969 FW_STAT_RX_PORT_256B_511B_IX, 1970 FW_STAT_RX_PORT_512B_1023B_IX, 1971 FW_STAT_RX_PORT_1024B_1518B_IX, 1972 FW_STAT_RX_PORT_1519B_MAX_IX, 1973 FW_STAT_RX_PORT_PAUSE_IX, 1974 FW_STAT_RX_PORT_PPP0_IX, 1975 FW_STAT_RX_PORT_PPP1_IX, 1976 FW_STAT_RX_PORT_PPP2_IX, 1977 FW_STAT_RX_PORT_PPP3_IX, 1978 FW_STAT_RX_PORT_PPP4_IX, 1979 FW_STAT_RX_PORT_PPP5_IX, 1980 FW_STAT_RX_PORT_PPP6_IX, 1981 FW_STAT_RX_PORT_PPP7_IX, 1982 FW_STAT_RX_PORT_LESS_64B_IX 1983 }; 1984 1985 struct fw_port_stats_cmd { 1986 __be32 op_to_portid; 1987 __be32 retval_len16; 1988 union fw_port_stats { 1989 struct fw_port_stats_ctl { 1990 __u8 nstats_bg_bm; 1991 __u8 tx_ix; 1992 __be16 r6; 1993 __be32 r7; 1994 __be64 stat0; 1995 __be64 stat1; 1996 __be64 stat2; 1997 __be64 stat3; 1998 __be64 stat4; 1999 __be64 stat5; 2000 } ctl; 2001 struct fw_port_stats_all { 2002 __be64 tx_bytes; 2003 __be64 tx_frames; 2004 __be64 tx_bcast; 2005 __be64 tx_mcast; 2006 __be64 tx_ucast; 2007 __be64 tx_error; 2008 __be64 tx_64b; 2009 __be64 tx_65b_127b; 2010 __be64 tx_128b_255b; 2011 __be64 tx_256b_511b; 2012 __be64 tx_512b_1023b; 2013 __be64 tx_1024b_1518b; 2014 __be64 tx_1519b_max; 2015 __be64 tx_drop; 2016 __be64 tx_pause; 2017 __be64 tx_ppp0; 2018 __be64 tx_ppp1; 2019 __be64 tx_ppp2; 2020 __be64 tx_ppp3; 2021 __be64 tx_ppp4; 2022 __be64 tx_ppp5; 2023 __be64 tx_ppp6; 2024 __be64 tx_ppp7; 2025 __be64 rx_bytes; 2026 __be64 rx_frames; 2027 __be64 rx_bcast; 2028 __be64 rx_mcast; 2029 __be64 rx_ucast; 2030 __be64 rx_mtu_error; 2031 __be64 rx_mtu_crc_error; 2032 __be64 rx_crc_error; 2033 __be64 rx_len_error; 2034 __be64 rx_sym_error; 2035 __be64 rx_64b; 2036 __be64 rx_65b_127b; 2037 __be64 rx_128b_255b; 2038 __be64 rx_256b_511b; 2039 __be64 rx_512b_1023b; 2040 __be64 rx_1024b_1518b; 2041 __be64 rx_1519b_max; 2042 __be64 rx_pause; 2043 __be64 rx_ppp0; 2044 __be64 rx_ppp1; 2045 __be64 rx_ppp2; 2046 __be64 rx_ppp3; 2047 __be64 rx_ppp4; 2048 __be64 rx_ppp5; 2049 __be64 rx_ppp6; 2050 __be64 rx_ppp7; 2051 __be64 rx_less_64b; 2052 __be64 rx_bg_drop; 2053 __be64 rx_bg_trunc; 2054 } all; 2055 } u; 2056 }; 2057 2058 struct fw_rss_ind_tbl_cmd { 2059 __be32 op_to_viid; 2060 __be32 retval_len16; 2061 __be16 niqid; 2062 __be16 startidx; 2063 __be32 r3; 2064 __be32 iq0_to_iq2; 2065 __be32 iq3_to_iq5; 2066 __be32 iq6_to_iq8; 2067 __be32 iq9_to_iq11; 2068 __be32 iq12_to_iq14; 2069 __be32 iq15_to_iq17; 2070 __be32 iq18_to_iq20; 2071 __be32 iq21_to_iq23; 2072 __be32 iq24_to_iq26; 2073 __be32 iq27_to_iq29; 2074 __be32 iq30_iq31; 2075 __be32 r15_lo; 2076 }; 2077 2078 #define S_FW_RSS_IND_TBL_CMD_VIID 0 2079 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 2080 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 2081 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 2082 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 2083 2084 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 2085 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 2086 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 2087 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 2088 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 2089 2090 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 2091 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 2092 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 2093 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 2094 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 2095 2096 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 2097 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 2098 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 2099 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 2100 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 2101 2102 struct fw_rss_glb_config_cmd { 2103 __be32 op_to_write; 2104 __be32 retval_len16; 2105 union fw_rss_glb_config { 2106 struct fw_rss_glb_config_manual { 2107 __be32 mode_pkd; 2108 __be32 r3; 2109 __be64 r4; 2110 __be64 r5; 2111 } manual; 2112 struct fw_rss_glb_config_basicvirtual { 2113 __be32 mode_keymode; 2114 __be32 synmapen_to_hashtoeplitz; 2115 __be64 r8; 2116 __be64 r9; 2117 } basicvirtual; 2118 } u; 2119 }; 2120 2121 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 2122 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 2123 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 2124 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 2125 2126 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 2127 2128 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 2129 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 2130 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 2131 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 2132 2133 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 2134 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 2135 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 2136 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 2137 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 2138 2139 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 2140 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 2141 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 2142 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 2143 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 2144 2145 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 2146 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 2147 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 2148 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 2149 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 2150 2151 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 2152 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 2153 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 2154 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 2155 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 2156 2157 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 2158 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 2159 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 2160 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 2161 2162 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 2163 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 2164 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 2165 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 2166 2167 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 2168 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 2169 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 2170 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 2171 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 2172 2173 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 2174 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 2175 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 2176 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 2177 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 2178 2179 struct fw_rss_vi_config_cmd { 2180 __be32 op_to_viid; 2181 __be32 retval_len16; 2182 union fw_rss_vi_config { 2183 struct fw_rss_vi_config_manual { 2184 __be64 r3; 2185 __be64 r4; 2186 __be64 r5; 2187 } manual; 2188 struct fw_rss_vi_config_basicvirtual { 2189 __be32 r6; 2190 __be32 defaultq_to_udpen; 2191 __be64 r9; 2192 __be64 r10; 2193 } basicvirtual; 2194 } u; 2195 }; 2196 2197 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 2198 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 2199 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 2200 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 2201 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 2202 2203 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 2204 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 2205 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 2206 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 2207 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 2208 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 2209 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 2210 2211 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 2212 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 2213 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 2214 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 2215 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 2216 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 2217 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 2218 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 2219 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 2220 2221 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 2222 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 2223 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 2224 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 2225 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 2226 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 2227 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 2228 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 2229 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 2230 2231 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 2232 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 2233 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 2234 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 2235 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 2236 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 2237 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 2238 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 2239 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 2240 2241 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 2242 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 2243 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 2244 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 2245 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 2246 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 2247 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 2248 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 2249 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 2250 2251 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 2252 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 2253 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 2254 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 2255 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 2256 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 2257 2258 struct fw_clip_cmd { 2259 __be32 op_to_write; 2260 __be32 alloc_to_len16; 2261 __be64 ip_hi; 2262 __be64 ip_lo; 2263 __be32 r4[2]; 2264 }; 2265 2266 #define S_FW_CLIP_CMD_ALLOC 31 2267 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 2268 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 2269 2270 #define S_FW_CLIP_CMD_FREE 30 2271 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 2272 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 2273 2274 /****************************************************************************** 2275 * D E B U G C O M M A N D s 2276 ******************************************************/ 2277 2278 struct fw_debug_cmd { 2279 __be32 op_type; 2280 __be32 len16_pkd; 2281 union fw_debug { 2282 struct fw_debug_assert { 2283 __be32 fcid; 2284 __be32 line; 2285 __be32 x; 2286 __be32 y; 2287 __u8 filename_0_7[8]; 2288 __u8 filename_8_15[8]; 2289 __be64 r3; 2290 } assert; 2291 struct fw_debug_prt { 2292 __be16 dprtstridx; 2293 __be16 r3[3]; 2294 __be32 dprtstrparam0; 2295 __be32 dprtstrparam1; 2296 __be32 dprtstrparam2; 2297 __be32 dprtstrparam3; 2298 } prt; 2299 } u; 2300 }; 2301 2302 #define S_FW_DEBUG_CMD_TYPE 0 2303 #define M_FW_DEBUG_CMD_TYPE 0xff 2304 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 2305 #define G_FW_DEBUG_CMD_TYPE(x) \ 2306 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 2307 2308 /****************************************************************************** 2309 * P C I E F W R E G I S T E R 2310 **************************************/ 2311 2312 /* 2313 * Register definitions for the PCIE_FW register which the firmware uses 2314 * to retain status across RESETs. This register should be considered 2315 * as a READ-ONLY register for Host Software and only to be used to 2316 * track firmware initialization/error state, etc. 2317 */ 2318 #define S_PCIE_FW_ERR 31 2319 #define M_PCIE_FW_ERR 0x1 2320 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 2321 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 2322 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 2323 2324 #define S_PCIE_FW_INIT 30 2325 #define M_PCIE_FW_INIT 0x1 2326 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 2327 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 2328 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 2329 2330 #define S_PCIE_FW_HALT 29 2331 #define M_PCIE_FW_HALT 0x1 2332 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 2333 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 2334 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 2335 2336 #define S_PCIE_FW_EVAL 24 2337 #define M_PCIE_FW_EVAL 0x7 2338 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 2339 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 2340 2341 #define S_PCIE_FW_MASTER_VLD 15 2342 #define M_PCIE_FW_MASTER_VLD 0x1 2343 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 2344 #define G_PCIE_FW_MASTER_VLD(x) \ 2345 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 2346 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 2347 2348 #define S_PCIE_FW_MASTER 12 2349 #define M_PCIE_FW_MASTER 0x7 2350 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 2351 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 2352 2353 /****************************************************************************** 2354 * B I N A R Y H E A D E R F O R M A T 2355 **********************************************/ 2356 2357 /* 2358 * firmware binary header format 2359 */ 2360 struct fw_hdr { 2361 __u8 ver; 2362 __u8 chip; /* terminator chip family */ 2363 __be16 len512; /* bin length in units of 512-bytes */ 2364 __be32 fw_ver; /* firmware version */ 2365 __be32 tp_microcode_ver; /* tcp processor microcode version */ 2366 __u8 intfver_nic; 2367 __u8 intfver_vnic; 2368 __u8 intfver_ofld; 2369 __u8 intfver_ri; 2370 __u8 intfver_iscsipdu; 2371 __u8 intfver_iscsi; 2372 __u8 intfver_fcoepdu; 2373 __u8 intfver_fcoe; 2374 __u32 reserved2; 2375 __u32 reserved3; 2376 __u32 magic; /* runtime or bootstrap fw */ 2377 __be32 flags; 2378 __be32 reserved6[23]; 2379 }; 2380 2381 #define S_FW_HDR_FW_VER_MAJOR 24 2382 #define M_FW_HDR_FW_VER_MAJOR 0xff 2383 #define V_FW_HDR_FW_VER_MAJOR(x) \ 2384 ((x) << S_FW_HDR_FW_VER_MAJOR) 2385 #define G_FW_HDR_FW_VER_MAJOR(x) \ 2386 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 2387 2388 #define S_FW_HDR_FW_VER_MINOR 16 2389 #define M_FW_HDR_FW_VER_MINOR 0xff 2390 #define V_FW_HDR_FW_VER_MINOR(x) \ 2391 ((x) << S_FW_HDR_FW_VER_MINOR) 2392 #define G_FW_HDR_FW_VER_MINOR(x) \ 2393 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 2394 2395 #define S_FW_HDR_FW_VER_MICRO 8 2396 #define M_FW_HDR_FW_VER_MICRO 0xff 2397 #define V_FW_HDR_FW_VER_MICRO(x) \ 2398 ((x) << S_FW_HDR_FW_VER_MICRO) 2399 #define G_FW_HDR_FW_VER_MICRO(x) \ 2400 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 2401 2402 #define S_FW_HDR_FW_VER_BUILD 0 2403 #define M_FW_HDR_FW_VER_BUILD 0xff 2404 #define V_FW_HDR_FW_VER_BUILD(x) \ 2405 ((x) << S_FW_HDR_FW_VER_BUILD) 2406 #define G_FW_HDR_FW_VER_BUILD(x) \ 2407 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 2408 2409 #endif /* _T4FW_INTERFACE_H_ */ 2410