1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2015 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _T4FW_INTERFACE_H_ 35 #define _T4FW_INTERFACE_H_ 36 37 /****************************************************************************** 38 * R E T U R N V A L U E S 39 ********************************/ 40 41 enum fw_retval { 42 FW_SUCCESS = 0, /* completed successfully */ 43 FW_EPERM = 1, /* operation not permitted */ 44 FW_ENOENT = 2, /* no such file or directory */ 45 FW_EIO = 5, /* input/output error; hw bad */ 46 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 47 FW_EAGAIN = 11, /* try again */ 48 FW_ENOMEM = 12, /* out of memory */ 49 FW_EFAULT = 14, /* bad address; fw bad */ 50 FW_EBUSY = 16, /* resource busy */ 51 FW_EEXIST = 17, /* file exists */ 52 FW_ENODEV = 19, /* no such device */ 53 FW_EINVAL = 22, /* invalid argument */ 54 FW_ENOSPC = 28, /* no space left on device */ 55 FW_ENOSYS = 38, /* functionality not implemented */ 56 FW_ENODATA = 61, /* no data available */ 57 FW_EPROTO = 71, /* protocol error */ 58 FW_EADDRINUSE = 98, /* address already in use */ 59 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 60 FW_ENETDOWN = 100, /* network is down */ 61 FW_ENETUNREACH = 101, /* network is unreachable */ 62 FW_ENOBUFS = 105, /* no buffer space available */ 63 FW_ETIMEDOUT = 110, /* timeout */ 64 FW_EINPROGRESS = 115, /* fw internal */ 65 }; 66 67 /****************************************************************************** 68 * M E M O R Y T Y P E s 69 ******************************/ 70 71 enum fw_memtype { 72 FW_MEMTYPE_EDC0 = 0x0, 73 FW_MEMTYPE_EDC1 = 0x1, 74 FW_MEMTYPE_EXTMEM = 0x2, 75 FW_MEMTYPE_FLASH = 0x4, 76 FW_MEMTYPE_INTERNAL = 0x5, 77 FW_MEMTYPE_EXTMEM1 = 0x6, 78 }; 79 80 /****************************************************************************** 81 * W O R K R E Q U E S T s 82 ********************************/ 83 84 enum fw_wr_opcodes { 85 FW_ETH_TX_PKT_WR = 0x08, 86 FW_ETH_TX_PKTS_WR = 0x09, 87 }; 88 89 /* 90 * Generic work request header flit0 91 */ 92 struct fw_wr_hdr { 93 __be32 hi; 94 __be32 lo; 95 }; 96 97 /* work request opcode (hi) 98 */ 99 #define S_FW_WR_OP 24 100 #define M_FW_WR_OP 0xff 101 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 102 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 103 104 /* work request immediate data length (hi) 105 */ 106 #define S_FW_WR_IMMDLEN 0 107 #define M_FW_WR_IMMDLEN 0xff 108 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 109 #define G_FW_WR_IMMDLEN(x) \ 110 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 111 112 /* egress queue status update to egress queue status entry (lo) 113 */ 114 #define S_FW_WR_EQUEQ 30 115 #define M_FW_WR_EQUEQ 0x1 116 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 117 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 118 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 119 120 /* length in units of 16-bytes (lo) 121 */ 122 #define S_FW_WR_LEN16 0 123 #define M_FW_WR_LEN16 0xff 124 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 125 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 126 127 struct fw_eth_tx_pkt_wr { 128 __be32 op_immdlen; 129 __be32 equiq_to_len16; 130 __be64 r3; 131 }; 132 133 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 134 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 135 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 136 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 137 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 138 139 struct fw_eth_tx_pkts_wr { 140 __be32 op_pkd; 141 __be32 equiq_to_len16; 142 __be32 r3; 143 __be16 plen; 144 __u8 npkt; 145 __u8 type; 146 }; 147 148 /****************************************************************************** 149 * C O M M A N D s 150 *********************/ 151 152 /* 153 * The maximum length of time, in miliseconds, that we expect any firmware 154 * command to take to execute and return a reply to the host. The RESET 155 * and INITIALIZE commands can take a fair amount of time to execute but 156 * most execute in far less time than this maximum. This constant is used 157 * by host software to determine how long to wait for a firmware command 158 * reply before declaring the firmware as dead/unreachable ... 159 */ 160 #define FW_CMD_MAX_TIMEOUT 10000 161 162 /* 163 * If a host driver does a HELLO and discovers that there's already a MASTER 164 * selected, we may have to wait for that MASTER to finish issuing RESET, 165 * configuration and INITIALIZE commands. Also, there's a possibility that 166 * our own HELLO may get lost if it happens right as the MASTER is issuign a 167 * RESET command, so we need to be willing to make a few retries of our HELLO. 168 */ 169 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 170 #define FW_CMD_HELLO_RETRIES 3 171 172 enum fw_cmd_opcodes { 173 FW_RESET_CMD = 0x03, 174 FW_HELLO_CMD = 0x04, 175 FW_BYE_CMD = 0x05, 176 FW_INITIALIZE_CMD = 0x06, 177 FW_CAPS_CONFIG_CMD = 0x07, 178 FW_PARAMS_CMD = 0x08, 179 FW_IQ_CMD = 0x10, 180 FW_EQ_ETH_CMD = 0x12, 181 FW_VI_CMD = 0x14, 182 FW_VI_MAC_CMD = 0x15, 183 FW_VI_RXMODE_CMD = 0x16, 184 FW_VI_ENABLE_CMD = 0x17, 185 FW_PORT_CMD = 0x1b, 186 FW_RSS_IND_TBL_CMD = 0x20, 187 FW_RSS_VI_CONFIG_CMD = 0x23, 188 FW_DEBUG_CMD = 0x81, 189 }; 190 191 /* 192 * Generic command header flit0 193 */ 194 struct fw_cmd_hdr { 195 __be32 hi; 196 __be32 lo; 197 }; 198 199 #define S_FW_CMD_OP 24 200 #define M_FW_CMD_OP 0xff 201 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 202 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 203 204 #define S_FW_CMD_REQUEST 23 205 #define M_FW_CMD_REQUEST 0x1 206 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 207 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 208 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 209 210 #define S_FW_CMD_READ 22 211 #define M_FW_CMD_READ 0x1 212 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 213 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 214 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 215 216 #define S_FW_CMD_WRITE 21 217 #define M_FW_CMD_WRITE 0x1 218 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 219 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 220 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 221 222 #define S_FW_CMD_EXEC 20 223 #define M_FW_CMD_EXEC 0x1 224 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 225 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 226 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 227 228 #define S_FW_CMD_RETVAL 8 229 #define M_FW_CMD_RETVAL 0xff 230 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 231 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 232 233 #define S_FW_CMD_LEN16 0 234 #define M_FW_CMD_LEN16 0xff 235 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 236 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 237 238 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 239 240 struct fw_reset_cmd { 241 __be32 op_to_write; 242 __be32 retval_len16; 243 __be32 val; 244 __be32 halt_pkd; 245 }; 246 247 #define S_FW_RESET_CMD_HALT 31 248 #define M_FW_RESET_CMD_HALT 0x1 249 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 250 #define G_FW_RESET_CMD_HALT(x) \ 251 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 252 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 253 254 enum { 255 FW_HELLO_CMD_STAGE_OS = 0, 256 }; 257 258 struct fw_hello_cmd { 259 __be32 op_to_write; 260 __be32 retval_len16; 261 __be32 err_to_clearinit; 262 __be32 fwrev; 263 }; 264 265 #define S_FW_HELLO_CMD_ERR 31 266 #define M_FW_HELLO_CMD_ERR 0x1 267 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 268 #define G_FW_HELLO_CMD_ERR(x) \ 269 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 270 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 271 272 #define S_FW_HELLO_CMD_INIT 30 273 #define M_FW_HELLO_CMD_INIT 0x1 274 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 275 #define G_FW_HELLO_CMD_INIT(x) \ 276 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 277 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 278 279 #define S_FW_HELLO_CMD_MASTERDIS 29 280 #define M_FW_HELLO_CMD_MASTERDIS 0x1 281 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 282 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 283 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 284 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 285 286 #define S_FW_HELLO_CMD_MASTERFORCE 28 287 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 288 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 289 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 290 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 291 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 292 293 #define S_FW_HELLO_CMD_MBMASTER 24 294 #define M_FW_HELLO_CMD_MBMASTER 0xf 295 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 296 #define G_FW_HELLO_CMD_MBMASTER(x) \ 297 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 298 299 #define S_FW_HELLO_CMD_MBASYNCNOT 20 300 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 301 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 302 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 303 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 304 305 #define S_FW_HELLO_CMD_STAGE 17 306 #define M_FW_HELLO_CMD_STAGE 0x7 307 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 308 #define G_FW_HELLO_CMD_STAGE(x) \ 309 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 310 311 #define S_FW_HELLO_CMD_CLEARINIT 16 312 #define M_FW_HELLO_CMD_CLEARINIT 0x1 313 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 314 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 315 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 316 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 317 318 struct fw_bye_cmd { 319 __be32 op_to_write; 320 __be32 retval_len16; 321 __be64 r3; 322 }; 323 324 struct fw_initialize_cmd { 325 __be32 op_to_write; 326 __be32 retval_len16; 327 __be64 r3; 328 }; 329 330 enum fw_caps_config_nic { 331 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 332 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 333 }; 334 335 enum fw_memtype_cf { 336 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 337 }; 338 339 struct fw_caps_config_cmd { 340 __be32 op_to_write; 341 __be32 cfvalid_to_len16; 342 __be32 r2; 343 __be32 hwmbitmap; 344 __be16 nbmcaps; 345 __be16 linkcaps; 346 __be16 switchcaps; 347 __be16 r3; 348 __be16 niccaps; 349 __be16 toecaps; 350 __be16 rdmacaps; 351 __be16 r4; 352 __be16 iscsicaps; 353 __be16 fcoecaps; 354 __be32 cfcsum; 355 __be32 finiver; 356 __be32 finicsum; 357 }; 358 359 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 360 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 361 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 362 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 363 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 364 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 365 366 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 367 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 368 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 369 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 370 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 371 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 372 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 373 374 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 375 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 376 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 377 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 378 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 379 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 380 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 381 382 /* 383 * params command mnemonics 384 */ 385 enum fw_params_mnem { 386 FW_PARAMS_MNEM_DEV = 1, /* device params */ 387 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 388 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 389 }; 390 391 /* 392 * device parameters 393 */ 394 enum fw_params_param_dev { 395 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 396 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 397 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 398 }; 399 400 /* 401 * physical and virtual function parameters 402 */ 403 enum fw_params_param_pfvf { 404 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 405 }; 406 407 /* 408 * dma queue parameters 409 */ 410 enum fw_params_param_dmaq { 411 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 412 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 413 }; 414 415 #define S_FW_PARAMS_MNEM 24 416 #define M_FW_PARAMS_MNEM 0xff 417 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 418 #define G_FW_PARAMS_MNEM(x) \ 419 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 420 421 #define S_FW_PARAMS_PARAM_X 16 422 #define M_FW_PARAMS_PARAM_X 0xff 423 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 424 #define G_FW_PARAMS_PARAM_X(x) \ 425 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 426 427 #define S_FW_PARAMS_PARAM_Y 8 428 #define M_FW_PARAMS_PARAM_Y 0xff 429 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 430 #define G_FW_PARAMS_PARAM_Y(x) \ 431 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 432 433 #define S_FW_PARAMS_PARAM_Z 0 434 #define M_FW_PARAMS_PARAM_Z 0xff 435 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 436 #define G_FW_PARAMS_PARAM_Z(x) \ 437 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 438 439 #define S_FW_PARAMS_PARAM_YZ 0 440 #define M_FW_PARAMS_PARAM_YZ 0xffff 441 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 442 #define G_FW_PARAMS_PARAM_YZ(x) \ 443 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 444 445 struct fw_params_cmd { 446 __be32 op_to_vfn; 447 __be32 retval_len16; 448 struct fw_params_param { 449 __be32 mnem; 450 __be32 val; 451 } param[7]; 452 }; 453 454 #define S_FW_PARAMS_CMD_PFN 8 455 #define M_FW_PARAMS_CMD_PFN 0x7 456 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 457 #define G_FW_PARAMS_CMD_PFN(x) \ 458 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 459 460 #define S_FW_PARAMS_CMD_VFN 0 461 #define M_FW_PARAMS_CMD_VFN 0xff 462 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 463 #define G_FW_PARAMS_CMD_VFN(x) \ 464 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 465 466 /* 467 * ingress queue type; the first 1K ingress queues can have associated 0, 468 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 469 * capabilities 470 */ 471 enum fw_iq_type { 472 FW_IQ_TYPE_FL_INT_CAP, 473 }; 474 475 struct fw_iq_cmd { 476 __be32 op_to_vfn; 477 __be32 alloc_to_len16; 478 __be16 physiqid; 479 __be16 iqid; 480 __be16 fl0id; 481 __be16 fl1id; 482 __be32 type_to_iqandstindex; 483 __be16 iqdroprss_to_iqesize; 484 __be16 iqsize; 485 __be64 iqaddr; 486 __be32 iqns_to_fl0congen; 487 __be16 fl0dcaen_to_fl0cidxfthresh; 488 __be16 fl0size; 489 __be64 fl0addr; 490 __be32 fl1cngchmap_to_fl1congen; 491 __be16 fl1dcaen_to_fl1cidxfthresh; 492 __be16 fl1size; 493 __be64 fl1addr; 494 }; 495 496 #define S_FW_IQ_CMD_PFN 8 497 #define M_FW_IQ_CMD_PFN 0x7 498 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 499 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 500 501 #define S_FW_IQ_CMD_VFN 0 502 #define M_FW_IQ_CMD_VFN 0xff 503 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 504 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 505 506 #define S_FW_IQ_CMD_ALLOC 31 507 #define M_FW_IQ_CMD_ALLOC 0x1 508 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 509 #define G_FW_IQ_CMD_ALLOC(x) \ 510 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 511 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 512 513 #define S_FW_IQ_CMD_FREE 30 514 #define M_FW_IQ_CMD_FREE 0x1 515 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 516 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 517 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 518 519 #define S_FW_IQ_CMD_IQSTART 28 520 #define M_FW_IQ_CMD_IQSTART 0x1 521 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 522 #define G_FW_IQ_CMD_IQSTART(x) \ 523 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 524 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 525 526 #define S_FW_IQ_CMD_IQSTOP 27 527 #define M_FW_IQ_CMD_IQSTOP 0x1 528 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 529 #define G_FW_IQ_CMD_IQSTOP(x) \ 530 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 531 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 532 533 #define S_FW_IQ_CMD_TYPE 29 534 #define M_FW_IQ_CMD_TYPE 0x7 535 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 536 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 537 538 #define S_FW_IQ_CMD_IQASYNCH 28 539 #define M_FW_IQ_CMD_IQASYNCH 0x1 540 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 541 #define G_FW_IQ_CMD_IQASYNCH(x) \ 542 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 543 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 544 545 #define S_FW_IQ_CMD_VIID 16 546 #define M_FW_IQ_CMD_VIID 0xfff 547 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 548 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 549 550 #define S_FW_IQ_CMD_IQANDST 15 551 #define M_FW_IQ_CMD_IQANDST 0x1 552 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 553 #define G_FW_IQ_CMD_IQANDST(x) \ 554 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 555 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 556 557 #define S_FW_IQ_CMD_IQANUD 12 558 #define M_FW_IQ_CMD_IQANUD 0x3 559 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 560 #define G_FW_IQ_CMD_IQANUD(x) \ 561 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 562 563 #define S_FW_IQ_CMD_IQANDSTINDEX 0 564 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 565 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 566 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 567 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 568 569 #define S_FW_IQ_CMD_IQGTSMODE 14 570 #define M_FW_IQ_CMD_IQGTSMODE 0x1 571 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 572 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 573 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 574 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 575 576 #define S_FW_IQ_CMD_IQPCIECH 12 577 #define M_FW_IQ_CMD_IQPCIECH 0x3 578 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 579 #define G_FW_IQ_CMD_IQPCIECH(x) \ 580 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 581 582 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 583 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 584 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 585 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 586 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 587 588 #define S_FW_IQ_CMD_IQESIZE 0 589 #define M_FW_IQ_CMD_IQESIZE 0x3 590 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 591 #define G_FW_IQ_CMD_IQESIZE(x) \ 592 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 593 594 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 595 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 596 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 597 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 598 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 599 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 600 601 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 602 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 603 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 604 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 605 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 606 607 #define S_FW_IQ_CMD_FL0DATARO 12 608 #define M_FW_IQ_CMD_FL0DATARO 0x1 609 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 610 #define G_FW_IQ_CMD_FL0DATARO(x) \ 611 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 612 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 613 614 #define S_FW_IQ_CMD_FL0CONGCIF 11 615 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 616 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 617 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 618 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 619 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 620 621 #define S_FW_IQ_CMD_FL0FETCHRO 6 622 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 623 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 624 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 625 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 626 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 627 628 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 629 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 630 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 631 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 632 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 633 634 #define S_FW_IQ_CMD_FL0PADEN 2 635 #define M_FW_IQ_CMD_FL0PADEN 0x1 636 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 637 #define G_FW_IQ_CMD_FL0PADEN(x) \ 638 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 639 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 640 641 #define S_FW_IQ_CMD_FL0PACKEN 1 642 #define M_FW_IQ_CMD_FL0PACKEN 0x1 643 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 644 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 645 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 646 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 647 648 #define S_FW_IQ_CMD_FL0CONGEN 0 649 #define M_FW_IQ_CMD_FL0CONGEN 0x1 650 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 651 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 652 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 653 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 654 655 #define S_FW_IQ_CMD_FL0FBMIN 7 656 #define M_FW_IQ_CMD_FL0FBMIN 0x7 657 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 658 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 659 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 660 661 #define S_FW_IQ_CMD_FL0FBMAX 4 662 #define M_FW_IQ_CMD_FL0FBMAX 0x7 663 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 664 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 665 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 666 667 struct fw_eq_eth_cmd { 668 __be32 op_to_vfn; 669 __be32 alloc_to_len16; 670 __be32 eqid_pkd; 671 __be32 physeqid_pkd; 672 __be32 fetchszm_to_iqid; 673 __be32 dcaen_to_eqsize; 674 __be64 eqaddr; 675 __be32 autoequiqe_to_viid; 676 __be32 r8_lo; 677 __be64 r9; 678 }; 679 680 #define S_FW_EQ_ETH_CMD_PFN 8 681 #define M_FW_EQ_ETH_CMD_PFN 0x7 682 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 683 #define G_FW_EQ_ETH_CMD_PFN(x) \ 684 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 685 686 #define S_FW_EQ_ETH_CMD_VFN 0 687 #define M_FW_EQ_ETH_CMD_VFN 0xff 688 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 689 #define G_FW_EQ_ETH_CMD_VFN(x) \ 690 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 691 692 #define S_FW_EQ_ETH_CMD_ALLOC 31 693 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 694 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 695 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 696 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 697 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 698 699 #define S_FW_EQ_ETH_CMD_FREE 30 700 #define M_FW_EQ_ETH_CMD_FREE 0x1 701 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 702 #define G_FW_EQ_ETH_CMD_FREE(x) \ 703 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 704 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 705 706 #define S_FW_EQ_ETH_CMD_EQSTART 28 707 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 708 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 709 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 710 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 711 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 712 713 #define S_FW_EQ_ETH_CMD_EQID 0 714 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 715 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 716 #define G_FW_EQ_ETH_CMD_EQID(x) \ 717 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 718 719 #define S_FW_EQ_ETH_CMD_FETCHRO 22 720 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 721 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 722 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 723 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 724 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 725 726 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 727 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 728 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 729 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 730 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 731 732 #define S_FW_EQ_ETH_CMD_PCIECHN 16 733 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 734 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 735 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 736 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 737 738 #define S_FW_EQ_ETH_CMD_IQID 0 739 #define M_FW_EQ_ETH_CMD_IQID 0xffff 740 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 741 #define G_FW_EQ_ETH_CMD_IQID(x) \ 742 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 743 744 #define S_FW_EQ_ETH_CMD_FBMIN 23 745 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 746 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 747 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 748 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 749 750 #define S_FW_EQ_ETH_CMD_FBMAX 20 751 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 752 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 753 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 754 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 755 756 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 757 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 758 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 759 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 760 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 761 762 #define S_FW_EQ_ETH_CMD_EQSIZE 0 763 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 764 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 765 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 766 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 767 768 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 769 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 770 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 771 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 772 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 773 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 774 775 #define S_FW_EQ_ETH_CMD_VIID 16 776 #define M_FW_EQ_ETH_CMD_VIID 0xfff 777 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 778 #define G_FW_EQ_ETH_CMD_VIID(x) \ 779 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 780 781 enum fw_vi_func { 782 FW_VI_FUNC_ETH, 783 }; 784 785 struct fw_vi_cmd { 786 __be32 op_to_vfn; 787 __be32 alloc_to_len16; 788 __be16 type_to_viid; 789 __u8 mac[6]; 790 __u8 portid_pkd; 791 __u8 nmac; 792 __u8 nmac0[6]; 793 __be16 norss_rsssize; 794 __u8 nmac1[6]; 795 __be16 idsiiq_pkd; 796 __u8 nmac2[6]; 797 __be16 idseiq_pkd; 798 __u8 nmac3[6]; 799 __be64 r9; 800 __be64 r10; 801 }; 802 803 #define S_FW_VI_CMD_PFN 8 804 #define M_FW_VI_CMD_PFN 0x7 805 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 806 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 807 808 #define S_FW_VI_CMD_VFN 0 809 #define M_FW_VI_CMD_VFN 0xff 810 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 811 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 812 813 #define S_FW_VI_CMD_ALLOC 31 814 #define M_FW_VI_CMD_ALLOC 0x1 815 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 816 #define G_FW_VI_CMD_ALLOC(x) \ 817 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 818 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 819 820 #define S_FW_VI_CMD_FREE 30 821 #define M_FW_VI_CMD_FREE 0x1 822 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 823 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 824 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 825 826 #define S_FW_VI_CMD_TYPE 15 827 #define M_FW_VI_CMD_TYPE 0x1 828 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 829 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 830 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 831 832 #define S_FW_VI_CMD_FUNC 12 833 #define M_FW_VI_CMD_FUNC 0x7 834 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 835 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 836 837 #define S_FW_VI_CMD_VIID 0 838 #define M_FW_VI_CMD_VIID 0xfff 839 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 840 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 841 842 #define S_FW_VI_CMD_PORTID 4 843 #define M_FW_VI_CMD_PORTID 0xf 844 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 845 #define G_FW_VI_CMD_PORTID(x) \ 846 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 847 848 #define S_FW_VI_CMD_RSSSIZE 0 849 #define M_FW_VI_CMD_RSSSIZE 0x7ff 850 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 851 #define G_FW_VI_CMD_RSSSIZE(x) \ 852 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 853 854 /* Special VI_MAC command index ids */ 855 #define FW_VI_MAC_ADD_MAC 0x3FF 856 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 857 858 enum fw_vi_mac_smac { 859 FW_VI_MAC_MPS_TCAM_ENTRY, 860 FW_VI_MAC_SMT_AND_MPSTCAM 861 }; 862 863 struct fw_vi_mac_cmd { 864 __be32 op_to_viid; 865 __be32 freemacs_to_len16; 866 union fw_vi_mac { 867 struct fw_vi_mac_exact { 868 __be16 valid_to_idx; 869 __u8 macaddr[6]; 870 } exact[7]; 871 struct fw_vi_mac_hash { 872 __be64 hashvec; 873 } hash; 874 } u; 875 }; 876 877 #define S_FW_VI_MAC_CMD_VIID 0 878 #define M_FW_VI_MAC_CMD_VIID 0xfff 879 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 880 #define G_FW_VI_MAC_CMD_VIID(x) \ 881 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 882 883 #define S_FW_VI_MAC_CMD_VALID 15 884 #define M_FW_VI_MAC_CMD_VALID 0x1 885 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 886 #define G_FW_VI_MAC_CMD_VALID(x) \ 887 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 888 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 889 890 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 891 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 892 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 893 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 894 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 895 896 #define S_FW_VI_MAC_CMD_IDX 0 897 #define M_FW_VI_MAC_CMD_IDX 0x3ff 898 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 899 #define G_FW_VI_MAC_CMD_IDX(x) \ 900 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 901 902 struct fw_vi_rxmode_cmd { 903 __be32 op_to_viid; 904 __be32 retval_len16; 905 __be32 mtu_to_vlanexen; 906 __be32 r4_lo; 907 }; 908 909 #define S_FW_VI_RXMODE_CMD_VIID 0 910 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 911 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 912 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 913 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 914 915 #define S_FW_VI_RXMODE_CMD_MTU 16 916 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 917 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 918 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 919 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 920 921 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 922 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 923 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 924 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 925 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 926 927 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 928 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 929 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 930 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 931 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 932 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 933 934 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 935 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 936 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 937 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 938 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 939 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 940 M_FW_VI_RXMODE_CMD_BROADCASTEN) 941 942 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 943 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 944 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 945 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 946 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 947 948 struct fw_vi_enable_cmd { 949 __be32 op_to_viid; 950 __be32 ien_to_len16; 951 __be16 blinkdur; 952 __be16 r3; 953 __be32 r4; 954 }; 955 956 #define S_FW_VI_ENABLE_CMD_VIID 0 957 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 958 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 959 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 960 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 961 962 #define S_FW_VI_ENABLE_CMD_IEN 31 963 #define M_FW_VI_ENABLE_CMD_IEN 0x1 964 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 965 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 966 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 967 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 968 969 #define S_FW_VI_ENABLE_CMD_EEN 30 970 #define M_FW_VI_ENABLE_CMD_EEN 0x1 971 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 972 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 973 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 974 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 975 976 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 977 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 978 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 979 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 980 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 981 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 982 983 /* VI PF stats offset definitions */ 984 #define VI_PF_NUM_STATS 17 985 enum fw_vi_stats_pf_index { 986 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 987 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 988 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 989 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 990 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 991 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 992 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 993 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 994 FW_VI_PF_STAT_RX_BYTES_IX, 995 FW_VI_PF_STAT_RX_FRAMES_IX, 996 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 997 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 998 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 999 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1000 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1001 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1002 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1003 }; 1004 1005 struct fw_vi_stats_cmd { 1006 __be32 op_to_viid; 1007 __be32 retval_len16; 1008 union fw_vi_stats { 1009 struct fw_vi_stats_ctl { 1010 __be16 nstats_ix; 1011 __be16 r6; 1012 __be32 r7; 1013 __be64 stat0; 1014 __be64 stat1; 1015 __be64 stat2; 1016 __be64 stat3; 1017 __be64 stat4; 1018 __be64 stat5; 1019 } ctl; 1020 struct fw_vi_stats_pf { 1021 __be64 tx_bcast_bytes; 1022 __be64 tx_bcast_frames; 1023 __be64 tx_mcast_bytes; 1024 __be64 tx_mcast_frames; 1025 __be64 tx_ucast_bytes; 1026 __be64 tx_ucast_frames; 1027 __be64 tx_offload_bytes; 1028 __be64 tx_offload_frames; 1029 __be64 rx_pf_bytes; 1030 __be64 rx_pf_frames; 1031 __be64 rx_bcast_bytes; 1032 __be64 rx_bcast_frames; 1033 __be64 rx_mcast_bytes; 1034 __be64 rx_mcast_frames; 1035 __be64 rx_ucast_bytes; 1036 __be64 rx_ucast_frames; 1037 __be64 rx_err_frames; 1038 } pf; 1039 struct fw_vi_stats_vf { 1040 __be64 tx_bcast_bytes; 1041 __be64 tx_bcast_frames; 1042 __be64 tx_mcast_bytes; 1043 __be64 tx_mcast_frames; 1044 __be64 tx_ucast_bytes; 1045 __be64 tx_ucast_frames; 1046 __be64 tx_drop_frames; 1047 __be64 tx_offload_bytes; 1048 __be64 tx_offload_frames; 1049 __be64 rx_bcast_bytes; 1050 __be64 rx_bcast_frames; 1051 __be64 rx_mcast_bytes; 1052 __be64 rx_mcast_frames; 1053 __be64 rx_ucast_bytes; 1054 __be64 rx_ucast_frames; 1055 __be64 rx_err_frames; 1056 } vf; 1057 } u; 1058 }; 1059 1060 /* port capabilities bitmap */ 1061 enum fw_port_cap { 1062 FW_PORT_CAP_SPEED_100M = 0x0001, 1063 FW_PORT_CAP_SPEED_1G = 0x0002, 1064 FW_PORT_CAP_SPEED_2_5G = 0x0004, 1065 FW_PORT_CAP_SPEED_10G = 0x0008, 1066 FW_PORT_CAP_SPEED_40G = 0x0010, 1067 FW_PORT_CAP_SPEED_100G = 0x0020, 1068 FW_PORT_CAP_FC_RX = 0x0040, 1069 FW_PORT_CAP_FC_TX = 0x0080, 1070 FW_PORT_CAP_ANEG = 0x0100, 1071 FW_PORT_CAP_MDIX = 0x0200, 1072 FW_PORT_CAP_MDIAUTO = 0x0400, 1073 FW_PORT_CAP_FEC = 0x0800, 1074 FW_PORT_CAP_TECHKR = 0x1000, 1075 FW_PORT_CAP_TECHKX4 = 0x2000, 1076 FW_PORT_CAP_802_3_PAUSE = 0x4000, 1077 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 1078 }; 1079 1080 enum fw_port_mdi { 1081 FW_PORT_CAP_MDI_AUTO, 1082 }; 1083 1084 #define S_FW_PORT_CAP_MDI 9 1085 #define M_FW_PORT_CAP_MDI 3 1086 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 1087 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 1088 1089 enum fw_port_action { 1090 FW_PORT_ACTION_L1_CFG = 0x0001, 1091 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 1092 }; 1093 1094 struct fw_port_cmd { 1095 __be32 op_to_portid; 1096 __be32 action_to_len16; 1097 union fw_port { 1098 struct fw_port_l1cfg { 1099 __be32 rcap; 1100 __be32 r; 1101 } l1cfg; 1102 struct fw_port_l2cfg { 1103 __u8 ctlbf; 1104 __u8 ovlan3_to_ivlan0; 1105 __be16 ivlantype; 1106 __be16 txipg_force_pinfo; 1107 __be16 mtu; 1108 __be16 ovlan0mask; 1109 __be16 ovlan0type; 1110 __be16 ovlan1mask; 1111 __be16 ovlan1type; 1112 __be16 ovlan2mask; 1113 __be16 ovlan2type; 1114 __be16 ovlan3mask; 1115 __be16 ovlan3type; 1116 } l2cfg; 1117 struct fw_port_info { 1118 __be32 lstatus_to_modtype; 1119 __be16 pcap; 1120 __be16 acap; 1121 __be16 mtu; 1122 __u8 cbllen; 1123 __u8 auxlinfo; 1124 __u8 dcbxdis_pkd; 1125 __u8 r8_lo; 1126 __be16 lpacap; 1127 __be64 r9; 1128 } info; 1129 struct fw_port_diags { 1130 __u8 diagop; 1131 __u8 r[3]; 1132 __be32 diagval; 1133 } diags; 1134 union fw_port_dcb { 1135 struct fw_port_dcb_pgid { 1136 __u8 type; 1137 __u8 apply_pkd; 1138 __u8 r10_lo[2]; 1139 __be32 pgid; 1140 __be64 r11; 1141 } pgid; 1142 struct fw_port_dcb_pgrate { 1143 __u8 type; 1144 __u8 apply_pkd; 1145 __u8 r10_lo[5]; 1146 __u8 num_tcs_supported; 1147 __u8 pgrate[8]; 1148 __u8 tsa[8]; 1149 } pgrate; 1150 struct fw_port_dcb_priorate { 1151 __u8 type; 1152 __u8 apply_pkd; 1153 __u8 r10_lo[6]; 1154 __u8 strict_priorate[8]; 1155 } priorate; 1156 struct fw_port_dcb_pfc { 1157 __u8 type; 1158 __u8 pfcen; 1159 __u8 r10[5]; 1160 __u8 max_pfc_tcs; 1161 __be64 r11; 1162 } pfc; 1163 struct fw_port_app_priority { 1164 __u8 type; 1165 __u8 r10[2]; 1166 __u8 idx; 1167 __u8 user_prio_map; 1168 __u8 sel_field; 1169 __be16 protocolid; 1170 __be64 r12; 1171 } app_priority; 1172 struct fw_port_dcb_control { 1173 __u8 type; 1174 __u8 all_syncd_pkd; 1175 __be16 dcb_version_to_app_state; 1176 __be32 r11; 1177 __be64 r12; 1178 } control; 1179 } dcb; 1180 } u; 1181 }; 1182 1183 #define S_FW_PORT_CMD_PORTID 0 1184 #define M_FW_PORT_CMD_PORTID 0xf 1185 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 1186 #define G_FW_PORT_CMD_PORTID(x) \ 1187 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 1188 1189 #define S_FW_PORT_CMD_ACTION 16 1190 #define M_FW_PORT_CMD_ACTION 0xffff 1191 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 1192 #define G_FW_PORT_CMD_ACTION(x) \ 1193 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 1194 1195 #define S_FW_PORT_CMD_LSTATUS 31 1196 #define M_FW_PORT_CMD_LSTATUS 0x1 1197 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 1198 #define G_FW_PORT_CMD_LSTATUS(x) \ 1199 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 1200 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 1201 1202 #define S_FW_PORT_CMD_LSPEED 24 1203 #define M_FW_PORT_CMD_LSPEED 0x3f 1204 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 1205 #define G_FW_PORT_CMD_LSPEED(x) \ 1206 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 1207 1208 #define S_FW_PORT_CMD_TXPAUSE 23 1209 #define M_FW_PORT_CMD_TXPAUSE 0x1 1210 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 1211 #define G_FW_PORT_CMD_TXPAUSE(x) \ 1212 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 1213 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 1214 1215 #define S_FW_PORT_CMD_RXPAUSE 22 1216 #define M_FW_PORT_CMD_RXPAUSE 0x1 1217 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 1218 #define G_FW_PORT_CMD_RXPAUSE(x) \ 1219 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 1220 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 1221 1222 #define S_FW_PORT_CMD_MDIOCAP 21 1223 #define M_FW_PORT_CMD_MDIOCAP 0x1 1224 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 1225 #define G_FW_PORT_CMD_MDIOCAP(x) \ 1226 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 1227 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 1228 1229 #define S_FW_PORT_CMD_MDIOADDR 16 1230 #define M_FW_PORT_CMD_MDIOADDR 0x1f 1231 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 1232 #define G_FW_PORT_CMD_MDIOADDR(x) \ 1233 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 1234 1235 #define S_FW_PORT_CMD_PTYPE 8 1236 #define M_FW_PORT_CMD_PTYPE 0x1f 1237 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 1238 #define G_FW_PORT_CMD_PTYPE(x) \ 1239 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 1240 1241 #define S_FW_PORT_CMD_LINKDNRC 5 1242 #define M_FW_PORT_CMD_LINKDNRC 0x7 1243 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 1244 #define G_FW_PORT_CMD_LINKDNRC(x) \ 1245 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 1246 1247 #define S_FW_PORT_CMD_MODTYPE 0 1248 #define M_FW_PORT_CMD_MODTYPE 0x1f 1249 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 1250 #define G_FW_PORT_CMD_MODTYPE(x) \ 1251 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 1252 1253 /* 1254 * These are configured into the VPD and hence tools that generate 1255 * VPD may use this enumeration. 1256 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 1257 * 1258 * REMEMBER: 1259 * Update the Common Code t4_hw.c:t4_get_port_type_description() 1260 * with any new Firmware Port Technology Types! 1261 */ 1262 enum fw_port_type { 1263 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 1264 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 1265 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 1266 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 1267 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 1268 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 1269 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 1270 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 1271 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 1272 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 1273 FW_PORT_TYPE_BP_AP = 10, 1274 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 1275 FW_PORT_TYPE_BP4_AP = 11, 1276 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 1277 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 1278 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 1279 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 1280 FW_PORT_TYPE_BP40_BA = 15, 1281 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 1282 1283 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 1284 }; 1285 1286 /* These are read from module's EEPROM and determined once the 1287 * module is inserted. 1288 */ 1289 enum fw_port_module_type { 1290 FW_PORT_MOD_TYPE_NA = 0x0, 1291 FW_PORT_MOD_TYPE_LR = 0x1, 1292 FW_PORT_MOD_TYPE_SR = 0x2, 1293 FW_PORT_MOD_TYPE_ER = 0x3, 1294 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 1295 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 1296 FW_PORT_MOD_TYPE_LRM = 0x6, 1297 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 1298 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 1299 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 1300 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 1301 }; 1302 1303 /* used by FW and tools may use this to generate VPD */ 1304 enum fw_port_mod_sub_type { 1305 FW_PORT_MOD_SUB_TYPE_NA, 1306 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 1307 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 1308 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 1309 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 1310 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 1311 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6, 1312 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7, 1313 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 1314 1315 /* 1316 * The following will never been in the VPD. They are TWINAX cable 1317 * lengths decoded from SFP+ module i2c PROMs. These should almost 1318 * certainly go somewhere else ... 1319 */ 1320 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 1321 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 1322 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 1323 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 1324 }; 1325 1326 /* link down reason codes (3b) */ 1327 enum fw_port_link_dn_rc { 1328 FW_PORT_LINK_DN_RC_NONE, 1329 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 1330 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 1331 FW_PORT_LINK_DN_RESERVED3, 1332 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 1333 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 1334 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 1335 FW_PORT_LINK_DN_RESERVED7 1336 }; 1337 1338 /* port stats */ 1339 #define FW_NUM_PORT_STATS 50 1340 #define FW_NUM_PORT_TX_STATS 23 1341 #define FW_NUM_PORT_RX_STATS 27 1342 1343 enum fw_port_stats_tx_index { 1344 FW_STAT_TX_PORT_BYTES_IX, 1345 FW_STAT_TX_PORT_FRAMES_IX, 1346 FW_STAT_TX_PORT_BCAST_IX, 1347 FW_STAT_TX_PORT_MCAST_IX, 1348 FW_STAT_TX_PORT_UCAST_IX, 1349 FW_STAT_TX_PORT_ERROR_IX, 1350 FW_STAT_TX_PORT_64B_IX, 1351 FW_STAT_TX_PORT_65B_127B_IX, 1352 FW_STAT_TX_PORT_128B_255B_IX, 1353 FW_STAT_TX_PORT_256B_511B_IX, 1354 FW_STAT_TX_PORT_512B_1023B_IX, 1355 FW_STAT_TX_PORT_1024B_1518B_IX, 1356 FW_STAT_TX_PORT_1519B_MAX_IX, 1357 FW_STAT_TX_PORT_DROP_IX, 1358 FW_STAT_TX_PORT_PAUSE_IX, 1359 FW_STAT_TX_PORT_PPP0_IX, 1360 FW_STAT_TX_PORT_PPP1_IX, 1361 FW_STAT_TX_PORT_PPP2_IX, 1362 FW_STAT_TX_PORT_PPP3_IX, 1363 FW_STAT_TX_PORT_PPP4_IX, 1364 FW_STAT_TX_PORT_PPP5_IX, 1365 FW_STAT_TX_PORT_PPP6_IX, 1366 FW_STAT_TX_PORT_PPP7_IX 1367 }; 1368 1369 enum fw_port_stat_rx_index { 1370 FW_STAT_RX_PORT_BYTES_IX, 1371 FW_STAT_RX_PORT_FRAMES_IX, 1372 FW_STAT_RX_PORT_BCAST_IX, 1373 FW_STAT_RX_PORT_MCAST_IX, 1374 FW_STAT_RX_PORT_UCAST_IX, 1375 FW_STAT_RX_PORT_MTU_ERROR_IX, 1376 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 1377 FW_STAT_RX_PORT_CRC_ERROR_IX, 1378 FW_STAT_RX_PORT_LEN_ERROR_IX, 1379 FW_STAT_RX_PORT_SYM_ERROR_IX, 1380 FW_STAT_RX_PORT_64B_IX, 1381 FW_STAT_RX_PORT_65B_127B_IX, 1382 FW_STAT_RX_PORT_128B_255B_IX, 1383 FW_STAT_RX_PORT_256B_511B_IX, 1384 FW_STAT_RX_PORT_512B_1023B_IX, 1385 FW_STAT_RX_PORT_1024B_1518B_IX, 1386 FW_STAT_RX_PORT_1519B_MAX_IX, 1387 FW_STAT_RX_PORT_PAUSE_IX, 1388 FW_STAT_RX_PORT_PPP0_IX, 1389 FW_STAT_RX_PORT_PPP1_IX, 1390 FW_STAT_RX_PORT_PPP2_IX, 1391 FW_STAT_RX_PORT_PPP3_IX, 1392 FW_STAT_RX_PORT_PPP4_IX, 1393 FW_STAT_RX_PORT_PPP5_IX, 1394 FW_STAT_RX_PORT_PPP6_IX, 1395 FW_STAT_RX_PORT_PPP7_IX, 1396 FW_STAT_RX_PORT_LESS_64B_IX 1397 }; 1398 1399 struct fw_port_stats_cmd { 1400 __be32 op_to_portid; 1401 __be32 retval_len16; 1402 union fw_port_stats { 1403 struct fw_port_stats_ctl { 1404 __u8 nstats_bg_bm; 1405 __u8 tx_ix; 1406 __be16 r6; 1407 __be32 r7; 1408 __be64 stat0; 1409 __be64 stat1; 1410 __be64 stat2; 1411 __be64 stat3; 1412 __be64 stat4; 1413 __be64 stat5; 1414 } ctl; 1415 struct fw_port_stats_all { 1416 __be64 tx_bytes; 1417 __be64 tx_frames; 1418 __be64 tx_bcast; 1419 __be64 tx_mcast; 1420 __be64 tx_ucast; 1421 __be64 tx_error; 1422 __be64 tx_64b; 1423 __be64 tx_65b_127b; 1424 __be64 tx_128b_255b; 1425 __be64 tx_256b_511b; 1426 __be64 tx_512b_1023b; 1427 __be64 tx_1024b_1518b; 1428 __be64 tx_1519b_max; 1429 __be64 tx_drop; 1430 __be64 tx_pause; 1431 __be64 tx_ppp0; 1432 __be64 tx_ppp1; 1433 __be64 tx_ppp2; 1434 __be64 tx_ppp3; 1435 __be64 tx_ppp4; 1436 __be64 tx_ppp5; 1437 __be64 tx_ppp6; 1438 __be64 tx_ppp7; 1439 __be64 rx_bytes; 1440 __be64 rx_frames; 1441 __be64 rx_bcast; 1442 __be64 rx_mcast; 1443 __be64 rx_ucast; 1444 __be64 rx_mtu_error; 1445 __be64 rx_mtu_crc_error; 1446 __be64 rx_crc_error; 1447 __be64 rx_len_error; 1448 __be64 rx_sym_error; 1449 __be64 rx_64b; 1450 __be64 rx_65b_127b; 1451 __be64 rx_128b_255b; 1452 __be64 rx_256b_511b; 1453 __be64 rx_512b_1023b; 1454 __be64 rx_1024b_1518b; 1455 __be64 rx_1519b_max; 1456 __be64 rx_pause; 1457 __be64 rx_ppp0; 1458 __be64 rx_ppp1; 1459 __be64 rx_ppp2; 1460 __be64 rx_ppp3; 1461 __be64 rx_ppp4; 1462 __be64 rx_ppp5; 1463 __be64 rx_ppp6; 1464 __be64 rx_ppp7; 1465 __be64 rx_less_64b; 1466 __be64 rx_bg_drop; 1467 __be64 rx_bg_trunc; 1468 } all; 1469 } u; 1470 }; 1471 1472 struct fw_rss_ind_tbl_cmd { 1473 __be32 op_to_viid; 1474 __be32 retval_len16; 1475 __be16 niqid; 1476 __be16 startidx; 1477 __be32 r3; 1478 __be32 iq0_to_iq2; 1479 __be32 iq3_to_iq5; 1480 __be32 iq6_to_iq8; 1481 __be32 iq9_to_iq11; 1482 __be32 iq12_to_iq14; 1483 __be32 iq15_to_iq17; 1484 __be32 iq18_to_iq20; 1485 __be32 iq21_to_iq23; 1486 __be32 iq24_to_iq26; 1487 __be32 iq27_to_iq29; 1488 __be32 iq30_iq31; 1489 __be32 r15_lo; 1490 }; 1491 1492 #define S_FW_RSS_IND_TBL_CMD_VIID 0 1493 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 1494 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 1495 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 1496 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 1497 1498 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 1499 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 1500 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 1501 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 1502 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 1503 1504 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 1505 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 1506 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 1507 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 1508 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 1509 1510 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 1511 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 1512 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 1513 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 1514 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 1515 1516 struct fw_rss_vi_config_cmd { 1517 __be32 op_to_viid; 1518 __be32 retval_len16; 1519 union fw_rss_vi_config { 1520 struct fw_rss_vi_config_manual { 1521 __be64 r3; 1522 __be64 r4; 1523 __be64 r5; 1524 } manual; 1525 struct fw_rss_vi_config_basicvirtual { 1526 __be32 r6; 1527 __be32 defaultq_to_udpen; 1528 __be64 r9; 1529 __be64 r10; 1530 } basicvirtual; 1531 } u; 1532 }; 1533 1534 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 1535 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 1536 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 1537 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 1538 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 1539 1540 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 1541 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 1542 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 1543 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 1544 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 1545 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 1546 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 1547 1548 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 1549 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 1550 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 1551 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 1552 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 1553 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 1554 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 1555 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 1556 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 1557 1558 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 1559 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 1560 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 1561 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1562 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 1563 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 1564 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 1565 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 1566 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 1567 1568 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 1569 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 1570 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 1571 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 1572 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 1573 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 1574 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 1575 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 1576 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 1577 1578 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 1579 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 1580 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 1581 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1582 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 1583 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 1584 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 1585 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 1586 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 1587 1588 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 1589 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 1590 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 1591 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 1592 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 1593 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 1594 1595 /****************************************************************************** 1596 * D E B U G C O M M A N D s 1597 ******************************************************/ 1598 1599 struct fw_debug_cmd { 1600 __be32 op_type; 1601 __be32 len16_pkd; 1602 union fw_debug { 1603 struct fw_debug_assert { 1604 __be32 fcid; 1605 __be32 line; 1606 __be32 x; 1607 __be32 y; 1608 __u8 filename_0_7[8]; 1609 __u8 filename_8_15[8]; 1610 __be64 r3; 1611 } assert; 1612 struct fw_debug_prt { 1613 __be16 dprtstridx; 1614 __be16 r3[3]; 1615 __be32 dprtstrparam0; 1616 __be32 dprtstrparam1; 1617 __be32 dprtstrparam2; 1618 __be32 dprtstrparam3; 1619 } prt; 1620 } u; 1621 }; 1622 1623 #define S_FW_DEBUG_CMD_TYPE 0 1624 #define M_FW_DEBUG_CMD_TYPE 0xff 1625 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 1626 #define G_FW_DEBUG_CMD_TYPE(x) \ 1627 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 1628 1629 /****************************************************************************** 1630 * P C I E F W R E G I S T E R 1631 **************************************/ 1632 1633 /* 1634 * Register definitions for the PCIE_FW register which the firmware uses 1635 * to retain status across RESETs. This register should be considered 1636 * as a READ-ONLY register for Host Software and only to be used to 1637 * track firmware initialization/error state, etc. 1638 */ 1639 #define S_PCIE_FW_ERR 31 1640 #define M_PCIE_FW_ERR 0x1 1641 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 1642 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 1643 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 1644 1645 #define S_PCIE_FW_INIT 30 1646 #define M_PCIE_FW_INIT 0x1 1647 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 1648 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 1649 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 1650 1651 #define S_PCIE_FW_HALT 29 1652 #define M_PCIE_FW_HALT 0x1 1653 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 1654 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 1655 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 1656 1657 #define S_PCIE_FW_EVAL 24 1658 #define M_PCIE_FW_EVAL 0x7 1659 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 1660 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 1661 1662 #define S_PCIE_FW_MASTER_VLD 15 1663 #define M_PCIE_FW_MASTER_VLD 0x1 1664 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 1665 #define G_PCIE_FW_MASTER_VLD(x) \ 1666 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 1667 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 1668 1669 #define S_PCIE_FW_MASTER 12 1670 #define M_PCIE_FW_MASTER 0x7 1671 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 1672 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 1673 1674 /****************************************************************************** 1675 * B I N A R Y H E A D E R F O R M A T 1676 **********************************************/ 1677 1678 /* 1679 * firmware binary header format 1680 */ 1681 struct fw_hdr { 1682 __u8 ver; 1683 __u8 chip; /* terminator chip family */ 1684 __be16 len512; /* bin length in units of 512-bytes */ 1685 __be32 fw_ver; /* firmware version */ 1686 __be32 tp_microcode_ver; /* tcp processor microcode version */ 1687 __u8 intfver_nic; 1688 __u8 intfver_vnic; 1689 __u8 intfver_ofld; 1690 __u8 intfver_ri; 1691 __u8 intfver_iscsipdu; 1692 __u8 intfver_iscsi; 1693 __u8 intfver_fcoepdu; 1694 __u8 intfver_fcoe; 1695 __u32 reserved2; 1696 __u32 reserved3; 1697 __u32 magic; /* runtime or bootstrap fw */ 1698 __be32 flags; 1699 __be32 reserved6[23]; 1700 }; 1701 1702 #define S_FW_HDR_FW_VER_MAJOR 24 1703 #define M_FW_HDR_FW_VER_MAJOR 0xff 1704 #define V_FW_HDR_FW_VER_MAJOR(x) \ 1705 ((x) << S_FW_HDR_FW_VER_MAJOR) 1706 #define G_FW_HDR_FW_VER_MAJOR(x) \ 1707 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 1708 1709 #define S_FW_HDR_FW_VER_MINOR 16 1710 #define M_FW_HDR_FW_VER_MINOR 0xff 1711 #define V_FW_HDR_FW_VER_MINOR(x) \ 1712 ((x) << S_FW_HDR_FW_VER_MINOR) 1713 #define G_FW_HDR_FW_VER_MINOR(x) \ 1714 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 1715 1716 #define S_FW_HDR_FW_VER_MICRO 8 1717 #define M_FW_HDR_FW_VER_MICRO 0xff 1718 #define V_FW_HDR_FW_VER_MICRO(x) \ 1719 ((x) << S_FW_HDR_FW_VER_MICRO) 1720 #define G_FW_HDR_FW_VER_MICRO(x) \ 1721 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 1722 1723 #define S_FW_HDR_FW_VER_BUILD 0 1724 #define M_FW_HDR_FW_VER_BUILD 0xff 1725 #define V_FW_HDR_FW_VER_BUILD(x) \ 1726 ((x) << S_FW_HDR_FW_VER_BUILD) 1727 #define G_FW_HDR_FW_VER_BUILD(x) \ 1728 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 1729 1730 #endif /* _T4FW_INTERFACE_H_ */ 1731