1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef _T4FW_INTERFACE_H_ 7 #define _T4FW_INTERFACE_H_ 8 9 /****************************************************************************** 10 * R E T U R N V A L U E S 11 ********************************/ 12 13 enum fw_retval { 14 FW_SUCCESS = 0, /* completed successfully */ 15 FW_EPERM = 1, /* operation not permitted */ 16 FW_ENOENT = 2, /* no such file or directory */ 17 FW_EIO = 5, /* input/output error; hw bad */ 18 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 19 FW_EAGAIN = 11, /* try again */ 20 FW_ENOMEM = 12, /* out of memory */ 21 FW_EFAULT = 14, /* bad address; fw bad */ 22 FW_EBUSY = 16, /* resource busy */ 23 FW_EEXIST = 17, /* file exists */ 24 FW_ENODEV = 19, /* no such device */ 25 FW_EINVAL = 22, /* invalid argument */ 26 FW_ENOSPC = 28, /* no space left on device */ 27 FW_ENOSYS = 38, /* functionality not implemented */ 28 FW_ENODATA = 61, /* no data available */ 29 FW_EPROTO = 71, /* protocol error */ 30 FW_EADDRINUSE = 98, /* address already in use */ 31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 32 FW_ENETDOWN = 100, /* network is down */ 33 FW_ENETUNREACH = 101, /* network is unreachable */ 34 FW_ENOBUFS = 105, /* no buffer space available */ 35 FW_ETIMEDOUT = 110, /* timeout */ 36 FW_EINPROGRESS = 115, /* fw internal */ 37 }; 38 39 /****************************************************************************** 40 * M E M O R Y T Y P E s 41 ******************************/ 42 43 enum fw_memtype { 44 FW_MEMTYPE_EDC0 = 0x0, 45 FW_MEMTYPE_EDC1 = 0x1, 46 FW_MEMTYPE_EXTMEM = 0x2, 47 FW_MEMTYPE_FLASH = 0x4, 48 FW_MEMTYPE_INTERNAL = 0x5, 49 FW_MEMTYPE_EXTMEM1 = 0x6, 50 }; 51 52 /****************************************************************************** 53 * W O R K R E Q U E S T s 54 ********************************/ 55 56 enum fw_wr_opcodes { 57 FW_FILTER_WR = 0x02, 58 FW_ULPTX_WR = 0x04, 59 FW_TP_WR = 0x05, 60 FW_ETH_TX_PKT_WR = 0x08, 61 FW_ETH_TX_PKTS_WR = 0x09, 62 FW_ETH_TX_PKT_VM_WR = 0x11, 63 FW_ETH_TX_PKTS_VM_WR = 0x12, 64 FW_FILTER2_WR = 0x77, 65 FW_ETH_TX_PKTS2_WR = 0x78, 66 }; 67 68 /* 69 * Generic work request header flit0 70 */ 71 struct fw_wr_hdr { 72 __be32 hi; 73 __be32 lo; 74 }; 75 76 /* work request opcode (hi) 77 */ 78 #define S_FW_WR_OP 24 79 #define M_FW_WR_OP 0xff 80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 82 83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 84 */ 85 #define S_FW_WR_ATOMIC 23 86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 87 88 /* work request immediate data length (hi) 89 */ 90 #define S_FW_WR_IMMDLEN 0 91 #define M_FW_WR_IMMDLEN 0xff 92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 93 #define G_FW_WR_IMMDLEN(x) \ 94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 95 96 /* egress queue status update to egress queue status entry (lo) 97 */ 98 #define S_FW_WR_EQUEQ 30 99 #define M_FW_WR_EQUEQ 0x1 100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 103 104 /* flow context identifier (lo) 105 */ 106 #define S_FW_WR_FLOWID 8 107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 108 109 /* length in units of 16-bytes (lo) 110 */ 111 #define S_FW_WR_LEN16 0 112 #define M_FW_WR_LEN16 0xff 113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 115 116 struct fw_eth_tx_pkt_wr { 117 __be32 op_immdlen; 118 __be32 equiq_to_len16; 119 __be64 r3; 120 }; 121 122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 127 128 struct fw_eth_tx_pkts_wr { 129 __be32 op_pkd; 130 __be32 equiq_to_len16; 131 __be32 r3; 132 __be16 plen; 133 __u8 npkt; 134 __u8 type; 135 }; 136 137 struct fw_eth_tx_pkt_vm_wr { 138 __be32 op_immdlen; 139 __be32 equiq_to_len16; 140 __be32 r3[2]; 141 __u8 ethmacdst[6]; 142 __u8 ethmacsrc[6]; 143 __be16 ethtype; 144 __be16 vlantci; 145 }; 146 147 struct fw_eth_tx_pkts_vm_wr { 148 __be32 op_pkd; 149 __be32 equiq_to_len16; 150 __be32 r3; 151 __be16 plen; 152 __u8 npkt; 153 __u8 r4; 154 __u8 ethmacdst[6]; 155 __u8 ethmacsrc[6]; 156 __be16 ethtype; 157 __be16 vlantci; 158 }; 159 160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 161 enum fw_filter_wr_cookie { 162 FW_FILTER_WR_SUCCESS, 163 FW_FILTER_WR_FLT_ADDED, 164 FW_FILTER_WR_FLT_DELETED, 165 FW_FILTER_WR_SMT_TBL_FULL, 166 FW_FILTER_WR_EINVAL, 167 }; 168 169 struct fw_filter2_wr { 170 __be32 op_pkd; 171 __be32 len16_pkd; 172 __be64 r3; 173 __be32 tid_to_iq; 174 __be32 del_filter_to_l2tix; 175 __be16 ethtype; 176 __be16 ethtypem; 177 __u8 frag_to_ovlan_vldm; 178 __u8 smac_sel; 179 __be16 rx_chan_rx_rpl_iq; 180 __be32 maci_to_matchtypem; 181 __u8 ptcl; 182 __u8 ptclm; 183 __u8 ttyp; 184 __u8 ttypm; 185 __be16 ivlan; 186 __be16 ivlanm; 187 __be16 ovlan; 188 __be16 ovlanm; 189 __u8 lip[16]; 190 __u8 lipm[16]; 191 __u8 fip[16]; 192 __u8 fipm[16]; 193 __be16 lp; 194 __be16 lpm; 195 __be16 fp; 196 __be16 fpm; 197 __be16 r7; 198 __u8 sma[6]; 199 __be16 r8; 200 __u8 filter_type_swapmac; 201 __u8 natmode_to_ulp_type; 202 __be16 newlport; 203 __be16 newfport; 204 __u8 newlip[16]; 205 __u8 newfip[16]; 206 __be32 natseqcheck; 207 __be32 r9; 208 __be64 r10; 209 __be64 r11; 210 __be64 r12; 211 __be64 r13; 212 }; 213 214 #define S_FW_FILTER_WR_TID 12 215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 216 217 #define S_FW_FILTER_WR_RQTYPE 11 218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 219 220 #define S_FW_FILTER_WR_NOREPLY 10 221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 222 223 #define S_FW_FILTER_WR_IQ 0 224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 225 226 #define S_FW_FILTER_WR_DEL_FILTER 31 227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 229 230 #define S_FW_FILTER_WR_RPTTID 25 231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 232 233 #define S_FW_FILTER_WR_DROP 24 234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 235 236 #define S_FW_FILTER_WR_DIRSTEER 23 237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 238 239 #define S_FW_FILTER_WR_MASKHASH 22 240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 241 242 #define S_FW_FILTER_WR_DIRSTEERHASH 21 243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 244 245 #define S_FW_FILTER_WR_LPBK 20 246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 247 248 #define S_FW_FILTER_WR_DMAC 19 249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 250 251 #define S_FW_FILTER_WR_SMAC 18 252 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 253 254 #define S_FW_FILTER_WR_INSVLAN 17 255 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 256 257 #define S_FW_FILTER_WR_RMVLAN 16 258 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 259 260 #define S_FW_FILTER_WR_HITCNTS 15 261 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 262 263 #define S_FW_FILTER_WR_TXCHAN 13 264 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 265 266 #define S_FW_FILTER_WR_PRIO 12 267 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 268 269 #define S_FW_FILTER_WR_L2TIX 0 270 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 271 272 #define S_FW_FILTER_WR_FRAG 7 273 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 274 275 #define S_FW_FILTER_WR_FRAGM 6 276 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 277 278 #define S_FW_FILTER_WR_IVLAN_VLD 5 279 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 280 281 #define S_FW_FILTER_WR_OVLAN_VLD 4 282 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 283 284 #define S_FW_FILTER_WR_IVLAN_VLDM 3 285 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 286 287 #define S_FW_FILTER_WR_OVLAN_VLDM 2 288 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 289 290 #define S_FW_FILTER_WR_RX_CHAN 15 291 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 292 293 #define S_FW_FILTER_WR_RX_RPL_IQ 0 294 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 295 296 #define S_FW_FILTER_WR_MACI 23 297 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 298 299 #define S_FW_FILTER_WR_MACIM 14 300 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 301 302 #define S_FW_FILTER_WR_FCOE 13 303 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 304 305 #define S_FW_FILTER_WR_FCOEM 12 306 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 307 308 #define S_FW_FILTER_WR_PORT 9 309 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 310 311 #define S_FW_FILTER_WR_PORTM 6 312 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 313 314 #define S_FW_FILTER_WR_MATCHTYPE 3 315 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 316 317 #define S_FW_FILTER_WR_MATCHTYPEM 0 318 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 319 320 #define S_FW_FILTER2_WR_SWAPMAC 0 321 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 322 323 #define S_FW_FILTER2_WR_NATMODE 5 324 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 325 326 #define S_FW_FILTER2_WR_ULP_TYPE 0 327 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 328 329 /****************************************************************************** 330 * C O M M A N D s 331 *********************/ 332 333 /* 334 * The maximum length of time, in miliseconds, that we expect any firmware 335 * command to take to execute and return a reply to the host. The RESET 336 * and INITIALIZE commands can take a fair amount of time to execute but 337 * most execute in far less time than this maximum. This constant is used 338 * by host software to determine how long to wait for a firmware command 339 * reply before declaring the firmware as dead/unreachable ... 340 */ 341 #define FW_CMD_MAX_TIMEOUT 10000 342 343 /* 344 * If a host driver does a HELLO and discovers that there's already a MASTER 345 * selected, we may have to wait for that MASTER to finish issuing RESET, 346 * configuration and INITIALIZE commands. Also, there's a possibility that 347 * our own HELLO may get lost if it happens right as the MASTER is issuign a 348 * RESET command, so we need to be willing to make a few retries of our HELLO. 349 */ 350 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 351 #define FW_CMD_HELLO_RETRIES 3 352 353 enum fw_cmd_opcodes { 354 FW_LDST_CMD = 0x01, 355 FW_RESET_CMD = 0x03, 356 FW_HELLO_CMD = 0x04, 357 FW_BYE_CMD = 0x05, 358 FW_INITIALIZE_CMD = 0x06, 359 FW_CAPS_CONFIG_CMD = 0x07, 360 FW_PARAMS_CMD = 0x08, 361 FW_PFVF_CMD = 0x09, 362 FW_IQ_CMD = 0x10, 363 FW_EQ_ETH_CMD = 0x12, 364 FW_EQ_CTRL_CMD = 0x13, 365 FW_VI_CMD = 0x14, 366 FW_VI_MAC_CMD = 0x15, 367 FW_VI_RXMODE_CMD = 0x16, 368 FW_VI_ENABLE_CMD = 0x17, 369 FW_VI_STATS_CMD = 0x1a, 370 FW_PORT_CMD = 0x1b, 371 FW_RSS_IND_TBL_CMD = 0x20, 372 FW_RSS_GLB_CONFIG_CMD = 0x22, 373 FW_RSS_VI_CONFIG_CMD = 0x23, 374 FW_CLIP_CMD = 0x28, 375 FW_DEBUG_CMD = 0x81, 376 }; 377 378 enum fw_cmd_cap { 379 FW_CMD_CAP_PORT = 0x04, 380 }; 381 382 /* 383 * Generic command header flit0 384 */ 385 struct fw_cmd_hdr { 386 __be32 hi; 387 __be32 lo; 388 }; 389 390 #define S_FW_CMD_OP 24 391 #define M_FW_CMD_OP 0xff 392 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 393 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 394 395 #define S_FW_CMD_REQUEST 23 396 #define M_FW_CMD_REQUEST 0x1 397 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 398 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 399 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 400 401 #define S_FW_CMD_READ 22 402 #define M_FW_CMD_READ 0x1 403 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 404 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 405 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 406 407 #define S_FW_CMD_WRITE 21 408 #define M_FW_CMD_WRITE 0x1 409 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 410 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 411 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 412 413 #define S_FW_CMD_EXEC 20 414 #define M_FW_CMD_EXEC 0x1 415 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 416 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 417 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 418 419 #define S_FW_CMD_RETVAL 8 420 #define M_FW_CMD_RETVAL 0xff 421 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 422 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 423 424 #define S_FW_CMD_LEN16 0 425 #define M_FW_CMD_LEN16 0xff 426 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 427 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 428 429 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 430 431 /* address spaces 432 */ 433 enum fw_ldst_addrspc { 434 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 435 }; 436 437 struct fw_ldst_cmd { 438 __be32 op_to_addrspace; 439 __be32 cycles_to_len16; 440 union fw_ldst { 441 struct fw_ldst_addrval { 442 __be32 addr; 443 __be32 val; 444 } addrval; 445 struct fw_ldst_idctxt { 446 __be32 physid; 447 __be32 msg_ctxtflush; 448 __be32 ctxt_data7; 449 __be32 ctxt_data6; 450 __be32 ctxt_data5; 451 __be32 ctxt_data4; 452 __be32 ctxt_data3; 453 __be32 ctxt_data2; 454 __be32 ctxt_data1; 455 __be32 ctxt_data0; 456 } idctxt; 457 struct fw_ldst_mdio { 458 __be16 paddr_mmd; 459 __be16 raddr; 460 __be16 vctl; 461 __be16 rval; 462 } mdio; 463 struct fw_ldst_mps { 464 __be16 fid_ctl; 465 __be16 rplcpf_pkd; 466 __be32 rplc127_96; 467 __be32 rplc95_64; 468 __be32 rplc63_32; 469 __be32 rplc31_0; 470 __be32 atrb; 471 __be16 vlan[16]; 472 } mps; 473 struct fw_ldst_func { 474 __u8 access_ctl; 475 __u8 mod_index; 476 __be16 ctl_id; 477 __be32 offset; 478 __be64 data0; 479 __be64 data1; 480 } func; 481 struct fw_ldst_pcie { 482 __u8 ctrl_to_fn; 483 __u8 bnum; 484 __u8 r; 485 __u8 ext_r; 486 __u8 select_naccess; 487 __u8 pcie_fn; 488 __be16 nset_pkd; 489 __be32 data[12]; 490 } pcie; 491 struct fw_ldst_i2c_deprecated { 492 __u8 pid_pkd; 493 __u8 base; 494 __u8 boffset; 495 __u8 data; 496 __be32 r9; 497 } i2c_deprecated; 498 struct fw_ldst_i2c { 499 __u8 pid; 500 __u8 did; 501 __u8 boffset; 502 __u8 blen; 503 __be32 r9; 504 __u8 data[48]; 505 } i2c; 506 struct fw_ldst_le { 507 __be32 index; 508 __be32 r9; 509 __u8 val[33]; 510 __u8 r11[7]; 511 } le; 512 } u; 513 }; 514 515 #define S_FW_LDST_CMD_ADDRSPACE 0 516 #define M_FW_LDST_CMD_ADDRSPACE 0xff 517 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 518 519 struct fw_reset_cmd { 520 __be32 op_to_write; 521 __be32 retval_len16; 522 __be32 val; 523 __be32 halt_pkd; 524 }; 525 526 #define S_FW_RESET_CMD_HALT 31 527 #define M_FW_RESET_CMD_HALT 0x1 528 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 529 #define G_FW_RESET_CMD_HALT(x) \ 530 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 531 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 532 533 enum { 534 FW_HELLO_CMD_STAGE_OS = 0, 535 }; 536 537 struct fw_hello_cmd { 538 __be32 op_to_write; 539 __be32 retval_len16; 540 __be32 err_to_clearinit; 541 __be32 fwrev; 542 }; 543 544 #define S_FW_HELLO_CMD_ERR 31 545 #define M_FW_HELLO_CMD_ERR 0x1 546 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 547 #define G_FW_HELLO_CMD_ERR(x) \ 548 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 549 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 550 551 #define S_FW_HELLO_CMD_INIT 30 552 #define M_FW_HELLO_CMD_INIT 0x1 553 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 554 #define G_FW_HELLO_CMD_INIT(x) \ 555 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 556 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 557 558 #define S_FW_HELLO_CMD_MASTERDIS 29 559 #define M_FW_HELLO_CMD_MASTERDIS 0x1 560 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 561 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 562 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 563 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 564 565 #define S_FW_HELLO_CMD_MASTERFORCE 28 566 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 567 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 568 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 569 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 570 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 571 572 #define S_FW_HELLO_CMD_MBMASTER 24 573 #define M_FW_HELLO_CMD_MBMASTER 0xf 574 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 575 #define G_FW_HELLO_CMD_MBMASTER(x) \ 576 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 577 578 #define S_FW_HELLO_CMD_MBASYNCNOT 20 579 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 580 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 581 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 582 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 583 584 #define S_FW_HELLO_CMD_STAGE 17 585 #define M_FW_HELLO_CMD_STAGE 0x7 586 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 587 #define G_FW_HELLO_CMD_STAGE(x) \ 588 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 589 590 #define S_FW_HELLO_CMD_CLEARINIT 16 591 #define M_FW_HELLO_CMD_CLEARINIT 0x1 592 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 593 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 594 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 595 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 596 597 struct fw_bye_cmd { 598 __be32 op_to_write; 599 __be32 retval_len16; 600 __be64 r3; 601 }; 602 603 struct fw_initialize_cmd { 604 __be32 op_to_write; 605 __be32 retval_len16; 606 __be64 r3; 607 }; 608 609 enum fw_caps_config_nic { 610 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 611 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 612 }; 613 614 enum fw_memtype_cf { 615 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 616 }; 617 618 struct fw_caps_config_cmd { 619 __be32 op_to_write; 620 __be32 cfvalid_to_len16; 621 __be32 r2; 622 __be32 hwmbitmap; 623 __be16 nbmcaps; 624 __be16 linkcaps; 625 __be16 switchcaps; 626 __be16 r3; 627 __be16 niccaps; 628 __be16 toecaps; 629 __be16 rdmacaps; 630 __be16 cryptocaps; 631 __be16 iscsicaps; 632 __be16 fcoecaps; 633 __be32 cfcsum; 634 __be32 finiver; 635 __be32 finicsum; 636 }; 637 638 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 639 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 640 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 641 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 642 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 643 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 644 645 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 646 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 647 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 648 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 649 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 650 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 651 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 652 653 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 654 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 655 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 656 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 657 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 658 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 659 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 660 661 /* 662 * params command mnemonics 663 */ 664 enum fw_params_mnem { 665 FW_PARAMS_MNEM_DEV = 1, /* device params */ 666 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 667 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 668 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 669 }; 670 671 /* 672 * device parameters 673 */ 674 675 #define S_FW_PARAMS_PARAM_FILTER_MODE 16 676 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 677 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 678 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 679 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 680 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 681 M_FW_PARAMS_PARAM_FILTER_MODE) 682 683 #define S_FW_PARAMS_PARAM_FILTER_MASK 0 684 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 685 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 686 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 687 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 688 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 689 M_FW_PARAMS_PARAM_FILTER_MASK) 690 691 enum fw_params_param_dev { 692 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 693 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 694 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 695 * allocated by the device's 696 * Lookup Engine 697 */ 698 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */ 699 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */ 700 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 701 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 702 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 703 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 704 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 705 }; 706 707 /* 708 * physical and virtual function parameters 709 */ 710 enum fw_params_param_pfvf { 711 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 712 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 713 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 714 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 715 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 716 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 717 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 718 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 719 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 720 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 721 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 722 }; 723 724 /* 725 * dma queue parameters 726 */ 727 enum fw_params_param_dmaq { 728 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 729 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 730 }; 731 732 enum fw_params_param_dev_filter { 733 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 734 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 735 }; 736 737 #define S_FW_PARAMS_MNEM 24 738 #define M_FW_PARAMS_MNEM 0xff 739 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 740 #define G_FW_PARAMS_MNEM(x) \ 741 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 742 743 #define S_FW_PARAMS_PARAM_X 16 744 #define M_FW_PARAMS_PARAM_X 0xff 745 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 746 #define G_FW_PARAMS_PARAM_X(x) \ 747 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 748 749 #define S_FW_PARAMS_PARAM_Y 8 750 #define M_FW_PARAMS_PARAM_Y 0xff 751 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 752 #define G_FW_PARAMS_PARAM_Y(x) \ 753 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 754 755 #define S_FW_PARAMS_PARAM_Z 0 756 #define M_FW_PARAMS_PARAM_Z 0xff 757 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 758 #define G_FW_PARAMS_PARAM_Z(x) \ 759 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 760 761 #define S_FW_PARAMS_PARAM_YZ 0 762 #define M_FW_PARAMS_PARAM_YZ 0xffff 763 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 764 #define G_FW_PARAMS_PARAM_YZ(x) \ 765 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 766 767 #define S_FW_PARAMS_PARAM_XYZ 0 768 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 769 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 770 771 struct fw_params_cmd { 772 __be32 op_to_vfn; 773 __be32 retval_len16; 774 struct fw_params_param { 775 __be32 mnem; 776 __be32 val; 777 } param[7]; 778 }; 779 780 #define S_FW_PARAMS_CMD_PFN 8 781 #define M_FW_PARAMS_CMD_PFN 0x7 782 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 783 #define G_FW_PARAMS_CMD_PFN(x) \ 784 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 785 786 #define S_FW_PARAMS_CMD_VFN 0 787 #define M_FW_PARAMS_CMD_VFN 0xff 788 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 789 #define G_FW_PARAMS_CMD_VFN(x) \ 790 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 791 792 struct fw_pfvf_cmd { 793 __be32 op_to_vfn; 794 __be32 retval_len16; 795 __be32 niqflint_niq; 796 __be32 type_to_neq; 797 __be32 tc_to_nexactf; 798 __be32 r_caps_to_nethctrl; 799 __be16 nricq; 800 __be16 nriqp; 801 __be32 r4; 802 }; 803 804 #define S_FW_PFVF_CMD_PFN 8 805 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 806 807 #define S_FW_PFVF_CMD_VFN 0 808 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 809 810 #define S_FW_PFVF_CMD_NIQFLINT 20 811 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 812 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 813 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 814 815 #define S_FW_PFVF_CMD_NIQ 0 816 #define M_FW_PFVF_CMD_NIQ 0xfffff 817 #define G_FW_PFVF_CMD_NIQ(x) \ 818 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 819 820 #define S_FW_PFVF_CMD_PMASK 20 821 #define M_FW_PFVF_CMD_PMASK 0xf 822 #define G_FW_PFVF_CMD_PMASK(x) \ 823 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 824 825 #define S_FW_PFVF_CMD_NEQ 0 826 #define M_FW_PFVF_CMD_NEQ 0xfffff 827 #define G_FW_PFVF_CMD_NEQ(x) \ 828 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 829 830 #define S_FW_PFVF_CMD_TC 24 831 #define M_FW_PFVF_CMD_TC 0xff 832 #define G_FW_PFVF_CMD_TC(x) \ 833 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 834 835 #define S_FW_PFVF_CMD_NVI 16 836 #define M_FW_PFVF_CMD_NVI 0xff 837 #define G_FW_PFVF_CMD_NVI(x) \ 838 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 839 840 #define S_FW_PFVF_CMD_NEXACTF 0 841 #define M_FW_PFVF_CMD_NEXACTF 0xffff 842 #define G_FW_PFVF_CMD_NEXACTF(x) \ 843 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 844 845 #define S_FW_PFVF_CMD_R_CAPS 24 846 #define M_FW_PFVF_CMD_R_CAPS 0xff 847 #define G_FW_PFVF_CMD_R_CAPS(x) \ 848 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 849 850 #define S_FW_PFVF_CMD_WX_CAPS 16 851 #define M_FW_PFVF_CMD_WX_CAPS 0xff 852 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 853 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 854 855 #define S_FW_PFVF_CMD_NETHCTRL 0 856 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 857 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 858 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 859 860 /* 861 * ingress queue type; the first 1K ingress queues can have associated 0, 862 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 863 * capabilities 864 */ 865 enum fw_iq_type { 866 FW_IQ_TYPE_FL_INT_CAP, 867 }; 868 869 enum fw_iq_iqtype { 870 FW_IQ_IQTYPE_NIC = 1, 871 FW_IQ_IQTYPE_OFLD, 872 }; 873 874 struct fw_iq_cmd { 875 __be32 op_to_vfn; 876 __be32 alloc_to_len16; 877 __be16 physiqid; 878 __be16 iqid; 879 __be16 fl0id; 880 __be16 fl1id; 881 __be32 type_to_iqandstindex; 882 __be16 iqdroprss_to_iqesize; 883 __be16 iqsize; 884 __be64 iqaddr; 885 __be32 iqns_to_fl0congen; 886 __be16 fl0dcaen_to_fl0cidxfthresh; 887 __be16 fl0size; 888 __be64 fl0addr; 889 __be32 fl1cngchmap_to_fl1congen; 890 __be16 fl1dcaen_to_fl1cidxfthresh; 891 __be16 fl1size; 892 __be64 fl1addr; 893 }; 894 895 #define S_FW_IQ_CMD_PFN 8 896 #define M_FW_IQ_CMD_PFN 0x7 897 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 898 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 899 900 #define S_FW_IQ_CMD_VFN 0 901 #define M_FW_IQ_CMD_VFN 0xff 902 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 903 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 904 905 #define S_FW_IQ_CMD_ALLOC 31 906 #define M_FW_IQ_CMD_ALLOC 0x1 907 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 908 #define G_FW_IQ_CMD_ALLOC(x) \ 909 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 910 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 911 912 #define S_FW_IQ_CMD_FREE 30 913 #define M_FW_IQ_CMD_FREE 0x1 914 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 915 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 916 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 917 918 #define S_FW_IQ_CMD_IQSTART 28 919 #define M_FW_IQ_CMD_IQSTART 0x1 920 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 921 #define G_FW_IQ_CMD_IQSTART(x) \ 922 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 923 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 924 925 #define S_FW_IQ_CMD_IQSTOP 27 926 #define M_FW_IQ_CMD_IQSTOP 0x1 927 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 928 #define G_FW_IQ_CMD_IQSTOP(x) \ 929 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 930 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 931 932 #define S_FW_IQ_CMD_TYPE 29 933 #define M_FW_IQ_CMD_TYPE 0x7 934 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 935 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 936 937 #define S_FW_IQ_CMD_IQASYNCH 28 938 #define M_FW_IQ_CMD_IQASYNCH 0x1 939 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 940 #define G_FW_IQ_CMD_IQASYNCH(x) \ 941 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 942 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 943 944 #define S_FW_IQ_CMD_VIID 16 945 #define M_FW_IQ_CMD_VIID 0xfff 946 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 947 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 948 949 #define S_FW_IQ_CMD_IQANDST 15 950 #define M_FW_IQ_CMD_IQANDST 0x1 951 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 952 #define G_FW_IQ_CMD_IQANDST(x) \ 953 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 954 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 955 956 #define S_FW_IQ_CMD_IQANUD 12 957 #define M_FW_IQ_CMD_IQANUD 0x3 958 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 959 #define G_FW_IQ_CMD_IQANUD(x) \ 960 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 961 962 #define S_FW_IQ_CMD_IQANDSTINDEX 0 963 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 964 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 965 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 966 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 967 968 #define S_FW_IQ_CMD_IQGTSMODE 14 969 #define M_FW_IQ_CMD_IQGTSMODE 0x1 970 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 971 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 972 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 973 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 974 975 #define S_FW_IQ_CMD_IQPCIECH 12 976 #define M_FW_IQ_CMD_IQPCIECH 0x3 977 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 978 #define G_FW_IQ_CMD_IQPCIECH(x) \ 979 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 980 981 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 982 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 983 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 984 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 985 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 986 987 #define S_FW_IQ_CMD_IQESIZE 0 988 #define M_FW_IQ_CMD_IQESIZE 0x3 989 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 990 #define G_FW_IQ_CMD_IQESIZE(x) \ 991 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 992 993 #define S_FW_IQ_CMD_IQRO 30 994 #define M_FW_IQ_CMD_IQRO 0x1 995 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 996 #define G_FW_IQ_CMD_IQRO(x) \ 997 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 998 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 999 1000 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 1001 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 1002 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 1003 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 1004 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 1005 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 1006 1007 #define S_FW_IQ_CMD_IQTYPE 24 1008 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 1009 1010 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 1011 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 1012 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 1013 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 1014 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 1015 1016 #define S_FW_IQ_CMD_FL0DATARO 12 1017 #define M_FW_IQ_CMD_FL0DATARO 0x1 1018 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 1019 #define G_FW_IQ_CMD_FL0DATARO(x) \ 1020 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 1021 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 1022 1023 #define S_FW_IQ_CMD_FL0CONGCIF 11 1024 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 1025 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 1026 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 1027 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 1028 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 1029 1030 #define S_FW_IQ_CMD_FL0FETCHRO 6 1031 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 1032 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 1033 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 1034 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 1035 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 1036 1037 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 1038 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 1039 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 1040 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 1041 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 1042 1043 #define S_FW_IQ_CMD_FL0PADEN 2 1044 #define M_FW_IQ_CMD_FL0PADEN 0x1 1045 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 1046 #define G_FW_IQ_CMD_FL0PADEN(x) \ 1047 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 1048 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 1049 1050 #define S_FW_IQ_CMD_FL0PACKEN 1 1051 #define M_FW_IQ_CMD_FL0PACKEN 0x1 1052 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 1053 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 1054 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 1055 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 1056 1057 #define S_FW_IQ_CMD_FL0CONGEN 0 1058 #define M_FW_IQ_CMD_FL0CONGEN 0x1 1059 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 1060 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 1061 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 1062 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 1063 1064 #define S_FW_IQ_CMD_FL0FBMIN 7 1065 #define M_FW_IQ_CMD_FL0FBMIN 0x7 1066 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 1067 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 1068 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 1069 1070 #define S_FW_IQ_CMD_FL0FBMAX 4 1071 #define M_FW_IQ_CMD_FL0FBMAX 0x7 1072 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 1073 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 1074 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 1075 1076 struct fw_eq_eth_cmd { 1077 __be32 op_to_vfn; 1078 __be32 alloc_to_len16; 1079 __be32 eqid_pkd; 1080 __be32 physeqid_pkd; 1081 __be32 fetchszm_to_iqid; 1082 __be32 dcaen_to_eqsize; 1083 __be64 eqaddr; 1084 __be32 autoequiqe_to_viid; 1085 __be32 r8_lo; 1086 __be64 r9; 1087 }; 1088 1089 #define S_FW_EQ_ETH_CMD_PFN 8 1090 #define M_FW_EQ_ETH_CMD_PFN 0x7 1091 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 1092 #define G_FW_EQ_ETH_CMD_PFN(x) \ 1093 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 1094 1095 #define S_FW_EQ_ETH_CMD_VFN 0 1096 #define M_FW_EQ_ETH_CMD_VFN 0xff 1097 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 1098 #define G_FW_EQ_ETH_CMD_VFN(x) \ 1099 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 1100 1101 #define S_FW_EQ_ETH_CMD_ALLOC 31 1102 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 1103 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 1104 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 1105 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 1106 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 1107 1108 #define S_FW_EQ_ETH_CMD_FREE 30 1109 #define M_FW_EQ_ETH_CMD_FREE 0x1 1110 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 1111 #define G_FW_EQ_ETH_CMD_FREE(x) \ 1112 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 1113 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 1114 1115 #define S_FW_EQ_ETH_CMD_EQSTART 28 1116 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 1117 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 1118 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 1119 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 1120 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 1121 1122 #define S_FW_EQ_ETH_CMD_EQID 0 1123 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 1124 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 1125 #define G_FW_EQ_ETH_CMD_EQID(x) \ 1126 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 1127 1128 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 1129 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 1130 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 1131 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 1132 1133 #define S_FW_EQ_ETH_CMD_FETCHRO 22 1134 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 1135 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 1136 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 1137 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 1138 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 1139 1140 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 1141 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 1142 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 1143 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 1144 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 1145 1146 #define S_FW_EQ_ETH_CMD_PCIECHN 16 1147 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 1148 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 1149 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 1150 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 1151 1152 #define S_FW_EQ_ETH_CMD_IQID 0 1153 #define M_FW_EQ_ETH_CMD_IQID 0xffff 1154 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 1155 #define G_FW_EQ_ETH_CMD_IQID(x) \ 1156 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 1157 1158 #define S_FW_EQ_ETH_CMD_FBMIN 23 1159 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 1160 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 1161 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 1162 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 1163 1164 #define S_FW_EQ_ETH_CMD_FBMAX 20 1165 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 1166 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 1167 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 1168 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 1169 1170 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 1171 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 1172 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 1173 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 1174 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 1175 1176 #define S_FW_EQ_ETH_CMD_EQSIZE 0 1177 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 1178 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 1179 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 1180 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 1181 1182 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 1183 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 1184 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 1185 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 1186 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 1187 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 1188 1189 #define S_FW_EQ_ETH_CMD_VIID 16 1190 #define M_FW_EQ_ETH_CMD_VIID 0xfff 1191 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 1192 #define G_FW_EQ_ETH_CMD_VIID(x) \ 1193 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 1194 1195 struct fw_eq_ctrl_cmd { 1196 __be32 op_to_vfn; 1197 __be32 alloc_to_len16; 1198 __be32 cmpliqid_eqid; 1199 __be32 physeqid_pkd; 1200 __be32 fetchszm_to_iqid; 1201 __be32 dcaen_to_eqsize; 1202 __be64 eqaddr; 1203 }; 1204 1205 #define S_FW_EQ_CTRL_CMD_PFN 8 1206 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 1207 1208 #define S_FW_EQ_CTRL_CMD_VFN 0 1209 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 1210 1211 #define S_FW_EQ_CTRL_CMD_ALLOC 31 1212 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 1213 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 1214 1215 #define S_FW_EQ_CTRL_CMD_FREE 30 1216 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 1217 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 1218 1219 #define S_FW_EQ_CTRL_CMD_EQSTART 28 1220 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 1221 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 1222 1223 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 1224 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 1225 1226 #define S_FW_EQ_CTRL_CMD_EQID 0 1227 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 1228 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 1229 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 1230 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 1231 1232 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 1233 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 1234 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 1235 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 1236 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 1237 1238 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 1239 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 1240 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 1241 1242 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 1243 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 1244 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 1245 1246 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 1247 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 1248 1249 #define S_FW_EQ_CTRL_CMD_IQID 0 1250 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 1251 1252 #define S_FW_EQ_CTRL_CMD_FBMIN 23 1253 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 1254 1255 #define S_FW_EQ_CTRL_CMD_FBMAX 20 1256 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 1257 1258 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 1259 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 1260 1261 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 1262 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 1263 1264 enum fw_vi_func { 1265 FW_VI_FUNC_ETH, 1266 }; 1267 1268 /* Macros for VIID parsing: 1269 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number 1270 */ 1271 1272 #define S_FW_VIID_VIVLD 7 1273 #define M_FW_VIID_VIVLD 0x1 1274 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 1275 1276 #define S_FW_VIID_VIN 0 1277 #define M_FW_VIID_VIN 0x7F 1278 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 1279 1280 struct fw_vi_cmd { 1281 __be32 op_to_vfn; 1282 __be32 alloc_to_len16; 1283 __be16 type_to_viid; 1284 __u8 mac[6]; 1285 __u8 portid_pkd; 1286 __u8 nmac; 1287 __u8 nmac0[6]; 1288 __be16 norss_rsssize; 1289 __u8 nmac1[6]; 1290 __be16 idsiiq_pkd; 1291 __u8 nmac2[6]; 1292 __be16 idseiq_pkd; 1293 __u8 nmac3[6]; 1294 __be64 r9; 1295 __be64 r10; 1296 }; 1297 1298 #define S_FW_VI_CMD_PFN 8 1299 #define M_FW_VI_CMD_PFN 0x7 1300 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 1301 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 1302 1303 #define S_FW_VI_CMD_VFN 0 1304 #define M_FW_VI_CMD_VFN 0xff 1305 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 1306 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 1307 1308 #define S_FW_VI_CMD_ALLOC 31 1309 #define M_FW_VI_CMD_ALLOC 0x1 1310 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 1311 #define G_FW_VI_CMD_ALLOC(x) \ 1312 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 1313 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 1314 1315 #define S_FW_VI_CMD_FREE 30 1316 #define M_FW_VI_CMD_FREE 0x1 1317 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 1318 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 1319 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 1320 1321 #define S_FW_VI_CMD_VFVLD 24 1322 #define M_FW_VI_CMD_VFVLD 0x1 1323 #define G_FW_VI_CMD_VFVLD(x) \ 1324 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 1325 1326 #define S_FW_VI_CMD_VIN 16 1327 #define M_FW_VI_CMD_VIN 0xff 1328 #define G_FW_VI_CMD_VIN(x) \ 1329 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 1330 1331 #define S_FW_VI_CMD_TYPE 15 1332 #define M_FW_VI_CMD_TYPE 0x1 1333 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 1334 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 1335 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 1336 1337 #define S_FW_VI_CMD_FUNC 12 1338 #define M_FW_VI_CMD_FUNC 0x7 1339 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 1340 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 1341 1342 #define S_FW_VI_CMD_VIID 0 1343 #define M_FW_VI_CMD_VIID 0xfff 1344 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 1345 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 1346 1347 #define S_FW_VI_CMD_PORTID 4 1348 #define M_FW_VI_CMD_PORTID 0xf 1349 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 1350 #define G_FW_VI_CMD_PORTID(x) \ 1351 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 1352 1353 #define S_FW_VI_CMD_RSSSIZE 0 1354 #define M_FW_VI_CMD_RSSSIZE 0x7ff 1355 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 1356 #define G_FW_VI_CMD_RSSSIZE(x) \ 1357 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 1358 1359 /* Special VI_MAC command index ids */ 1360 #define FW_VI_MAC_ADD_MAC 0x3FF 1361 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1362 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 1363 1364 enum fw_vi_mac_smac { 1365 FW_VI_MAC_MPS_TCAM_ENTRY = 0x0, 1366 FW_VI_MAC_SMT_AND_MPSTCAM = 0x3 1367 }; 1368 1369 enum fw_vi_mac_entry_types { 1370 FW_VI_MAC_TYPE_RAW = 0x2, 1371 }; 1372 1373 struct fw_vi_mac_cmd { 1374 __be32 op_to_viid; 1375 __be32 freemacs_to_len16; 1376 union fw_vi_mac { 1377 struct fw_vi_mac_exact { 1378 __be16 valid_to_idx; 1379 __u8 macaddr[6]; 1380 } exact[7]; 1381 struct fw_vi_mac_hash { 1382 __be64 hashvec; 1383 } hash; 1384 struct fw_vi_mac_raw { 1385 __be32 raw_idx_pkd; 1386 __be32 data0_pkd; 1387 __be32 data1[2]; 1388 __be64 data0m_pkd; 1389 __be32 data1m[2]; 1390 } raw; 1391 } u; 1392 }; 1393 1394 #define S_FW_VI_MAC_CMD_VIID 0 1395 #define M_FW_VI_MAC_CMD_VIID 0xfff 1396 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 1397 #define G_FW_VI_MAC_CMD_VIID(x) \ 1398 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 1399 1400 #define S_FW_VI_MAC_CMD_FREEMACS 31 1401 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 1402 1403 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 1404 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 1405 1406 #define S_FW_VI_MAC_CMD_VALID 15 1407 #define M_FW_VI_MAC_CMD_VALID 0x1 1408 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 1409 #define G_FW_VI_MAC_CMD_VALID(x) \ 1410 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 1411 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 1412 1413 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 1414 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 1415 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 1416 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 1417 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 1418 1419 #define S_FW_VI_MAC_CMD_IDX 0 1420 #define M_FW_VI_MAC_CMD_IDX 0x3ff 1421 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 1422 #define G_FW_VI_MAC_CMD_IDX(x) \ 1423 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 1424 1425 #define S_FW_VI_MAC_CMD_RAW_IDX 16 1426 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 1427 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 1428 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 1429 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 1430 1431 struct fw_vi_rxmode_cmd { 1432 __be32 op_to_viid; 1433 __be32 retval_len16; 1434 __be32 mtu_to_vlanexen; 1435 __be32 r4_lo; 1436 }; 1437 1438 #define S_FW_VI_RXMODE_CMD_VIID 0 1439 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 1440 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 1441 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 1442 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 1443 1444 #define S_FW_VI_RXMODE_CMD_MTU 16 1445 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 1446 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 1447 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 1448 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 1449 1450 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 1451 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 1452 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 1453 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 1454 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 1455 1456 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 1457 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 1458 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1459 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 1460 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1461 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 1462 1463 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 1464 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 1465 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1466 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 1467 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1468 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 1469 M_FW_VI_RXMODE_CMD_BROADCASTEN) 1470 1471 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 1472 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 1473 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 1474 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 1475 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 1476 1477 struct fw_vi_enable_cmd { 1478 __be32 op_to_viid; 1479 __be32 ien_to_len16; 1480 __be16 blinkdur; 1481 __be16 r3; 1482 __be32 r4; 1483 }; 1484 1485 #define S_FW_VI_ENABLE_CMD_VIID 0 1486 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 1487 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 1488 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 1489 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 1490 1491 #define S_FW_VI_ENABLE_CMD_IEN 31 1492 #define M_FW_VI_ENABLE_CMD_IEN 0x1 1493 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 1494 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 1495 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 1496 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 1497 1498 #define S_FW_VI_ENABLE_CMD_EEN 30 1499 #define M_FW_VI_ENABLE_CMD_EEN 0x1 1500 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 1501 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 1502 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 1503 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 1504 1505 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 1506 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 1507 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 1508 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 1509 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 1510 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 1511 1512 /* VI VF stats offset definitions */ 1513 #define VI_VF_NUM_STATS 16 1514 1515 /* VI PF stats offset definitions */ 1516 #define VI_PF_NUM_STATS 17 1517 enum fw_vi_stats_pf_index { 1518 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 1519 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 1520 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 1521 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 1522 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 1523 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 1524 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 1525 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 1526 FW_VI_PF_STAT_RX_BYTES_IX, 1527 FW_VI_PF_STAT_RX_FRAMES_IX, 1528 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 1529 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 1530 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 1531 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1532 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1533 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1534 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1535 }; 1536 1537 struct fw_vi_stats_cmd { 1538 __be32 op_to_viid; 1539 __be32 retval_len16; 1540 union fw_vi_stats { 1541 struct fw_vi_stats_ctl { 1542 __be16 nstats_ix; 1543 __be16 r6; 1544 __be32 r7; 1545 __be64 stat0; 1546 __be64 stat1; 1547 __be64 stat2; 1548 __be64 stat3; 1549 __be64 stat4; 1550 __be64 stat5; 1551 } ctl; 1552 struct fw_vi_stats_pf { 1553 __be64 tx_bcast_bytes; 1554 __be64 tx_bcast_frames; 1555 __be64 tx_mcast_bytes; 1556 __be64 tx_mcast_frames; 1557 __be64 tx_ucast_bytes; 1558 __be64 tx_ucast_frames; 1559 __be64 tx_offload_bytes; 1560 __be64 tx_offload_frames; 1561 __be64 rx_pf_bytes; 1562 __be64 rx_pf_frames; 1563 __be64 rx_bcast_bytes; 1564 __be64 rx_bcast_frames; 1565 __be64 rx_mcast_bytes; 1566 __be64 rx_mcast_frames; 1567 __be64 rx_ucast_bytes; 1568 __be64 rx_ucast_frames; 1569 __be64 rx_err_frames; 1570 } pf; 1571 struct fw_vi_stats_vf { 1572 __be64 tx_bcast_bytes; 1573 __be64 tx_bcast_frames; 1574 __be64 tx_mcast_bytes; 1575 __be64 tx_mcast_frames; 1576 __be64 tx_ucast_bytes; 1577 __be64 tx_ucast_frames; 1578 __be64 tx_drop_frames; 1579 __be64 tx_offload_bytes; 1580 __be64 tx_offload_frames; 1581 __be64 rx_bcast_bytes; 1582 __be64 rx_bcast_frames; 1583 __be64 rx_mcast_bytes; 1584 __be64 rx_mcast_frames; 1585 __be64 rx_ucast_bytes; 1586 __be64 rx_ucast_frames; 1587 __be64 rx_err_frames; 1588 } vf; 1589 } u; 1590 }; 1591 1592 #define S_FW_VI_STATS_CMD_VIID 0 1593 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 1594 1595 #define S_FW_VI_STATS_CMD_NSTATS 12 1596 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 1597 1598 #define S_FW_VI_STATS_CMD_IX 0 1599 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 1600 1601 /* old 16-bit port capabilities bitmap */ 1602 enum fw_port_cap { 1603 FW_PORT_CAP_SPEED_100M = 0x0001, 1604 FW_PORT_CAP_SPEED_1G = 0x0002, 1605 FW_PORT_CAP_SPEED_25G = 0x0004, 1606 FW_PORT_CAP_SPEED_10G = 0x0008, 1607 FW_PORT_CAP_SPEED_40G = 0x0010, 1608 FW_PORT_CAP_SPEED_100G = 0x0020, 1609 FW_PORT_CAP_FC_RX = 0x0040, 1610 FW_PORT_CAP_FC_TX = 0x0080, 1611 FW_PORT_CAP_ANEG = 0x0100, 1612 FW_PORT_CAP_MDIX = 0x0200, 1613 FW_PORT_CAP_MDIAUTO = 0x0400, 1614 FW_PORT_CAP_FEC_RS = 0x0800, 1615 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 1616 FW_PORT_CAP_FEC_RESERVED = 0x2000, 1617 FW_PORT_CAP_802_3_PAUSE = 0x4000, 1618 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 1619 }; 1620 1621 #define S_FW_PORT_CAP_SPEED 0 1622 #define M_FW_PORT_CAP_SPEED 0x3f 1623 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 1624 #define G_FW_PORT_CAP_SPEED(x) \ 1625 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 1626 1627 enum fw_port_mdi { 1628 FW_PORT_CAP_MDI_AUTO, 1629 }; 1630 1631 #define S_FW_PORT_CAP_MDI 9 1632 #define M_FW_PORT_CAP_MDI 3 1633 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 1634 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 1635 1636 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 1637 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 1638 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 1639 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 1640 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 1641 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 1642 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 1643 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 1644 #define FW_PORT_CAP32_FC_RX 0x00010000UL 1645 #define FW_PORT_CAP32_FC_TX 0x00020000UL 1646 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 1647 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 1648 #define FW_PORT_CAP32_ANEG 0x00100000UL 1649 #define FW_PORT_CAP32_MDIX 0x00200000UL 1650 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 1651 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 1652 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 1653 1654 #define S_FW_PORT_CAP32_SPEED 0 1655 #define M_FW_PORT_CAP32_SPEED 0xfff 1656 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 1657 #define G_FW_PORT_CAP32_SPEED(x) \ 1658 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 1659 1660 enum fw_port_mdi32 { 1661 FW_PORT_CAP32_MDI_AUTO, 1662 }; 1663 1664 #define S_FW_PORT_CAP32_MDI 21 1665 #define M_FW_PORT_CAP32_MDI 3 1666 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 1667 #define G_FW_PORT_CAP32_MDI(x) \ 1668 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 1669 1670 enum fw_port_action { 1671 FW_PORT_ACTION_L1_CFG = 0x0001, 1672 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 1673 FW_PORT_ACTION_L1_CFG32 = 0x0009, 1674 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 1675 }; 1676 1677 struct fw_port_cmd { 1678 __be32 op_to_portid; 1679 __be32 action_to_len16; 1680 union fw_port { 1681 struct fw_port_l1cfg { 1682 __be32 rcap; 1683 __be32 r; 1684 } l1cfg; 1685 struct fw_port_l2cfg { 1686 __u8 ctlbf; 1687 __u8 ovlan3_to_ivlan0; 1688 __be16 ivlantype; 1689 __be16 txipg_force_pinfo; 1690 __be16 mtu; 1691 __be16 ovlan0mask; 1692 __be16 ovlan0type; 1693 __be16 ovlan1mask; 1694 __be16 ovlan1type; 1695 __be16 ovlan2mask; 1696 __be16 ovlan2type; 1697 __be16 ovlan3mask; 1698 __be16 ovlan3type; 1699 } l2cfg; 1700 struct fw_port_info { 1701 __be32 lstatus_to_modtype; 1702 __be16 pcap; 1703 __be16 acap; 1704 __be16 mtu; 1705 __u8 cbllen; 1706 __u8 auxlinfo; 1707 __u8 dcbxdis_pkd; 1708 __u8 r8_lo; 1709 __be16 lpacap; 1710 __be64 r9; 1711 } info; 1712 struct fw_port_diags { 1713 __u8 diagop; 1714 __u8 r[3]; 1715 __be32 diagval; 1716 } diags; 1717 union fw_port_dcb { 1718 struct fw_port_dcb_pgid { 1719 __u8 type; 1720 __u8 apply_pkd; 1721 __u8 r10_lo[2]; 1722 __be32 pgid; 1723 __be64 r11; 1724 } pgid; 1725 struct fw_port_dcb_pgrate { 1726 __u8 type; 1727 __u8 apply_pkd; 1728 __u8 r10_lo[5]; 1729 __u8 num_tcs_supported; 1730 __u8 pgrate[8]; 1731 __u8 tsa[8]; 1732 } pgrate; 1733 struct fw_port_dcb_priorate { 1734 __u8 type; 1735 __u8 apply_pkd; 1736 __u8 r10_lo[6]; 1737 __u8 strict_priorate[8]; 1738 } priorate; 1739 struct fw_port_dcb_pfc { 1740 __u8 type; 1741 __u8 pfcen; 1742 __u8 r10[5]; 1743 __u8 max_pfc_tcs; 1744 __be64 r11; 1745 } pfc; 1746 struct fw_port_app_priority { 1747 __u8 type; 1748 __u8 r10[2]; 1749 __u8 idx; 1750 __u8 user_prio_map; 1751 __u8 sel_field; 1752 __be16 protocolid; 1753 __be64 r12; 1754 } app_priority; 1755 struct fw_port_dcb_control { 1756 __u8 type; 1757 __u8 all_syncd_pkd; 1758 __be16 dcb_version_to_app_state; 1759 __be32 r11; 1760 __be64 r12; 1761 } control; 1762 } dcb; 1763 struct fw_port_l1cfg32 { 1764 __be32 rcap32; 1765 __be32 r; 1766 } l1cfg32; 1767 struct fw_port_info32 { 1768 __be32 lstatus32_to_cbllen32; 1769 __be32 auxlinfo32_mtu32; 1770 __be32 linkattr32; 1771 __be32 pcaps32; 1772 __be32 acaps32; 1773 __be32 lpacaps32; 1774 } info32; 1775 } u; 1776 }; 1777 1778 #define S_FW_PORT_CMD_PORTID 0 1779 #define M_FW_PORT_CMD_PORTID 0xf 1780 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 1781 #define G_FW_PORT_CMD_PORTID(x) \ 1782 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 1783 1784 #define S_FW_PORT_CMD_ACTION 16 1785 #define M_FW_PORT_CMD_ACTION 0xffff 1786 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 1787 #define G_FW_PORT_CMD_ACTION(x) \ 1788 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 1789 1790 #define S_FW_PORT_CMD_LSTATUS 31 1791 #define M_FW_PORT_CMD_LSTATUS 0x1 1792 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 1793 #define G_FW_PORT_CMD_LSTATUS(x) \ 1794 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 1795 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 1796 1797 #define S_FW_PORT_CMD_LSPEED 24 1798 #define M_FW_PORT_CMD_LSPEED 0x3f 1799 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 1800 #define G_FW_PORT_CMD_LSPEED(x) \ 1801 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 1802 1803 #define S_FW_PORT_CMD_TXPAUSE 23 1804 #define M_FW_PORT_CMD_TXPAUSE 0x1 1805 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 1806 #define G_FW_PORT_CMD_TXPAUSE(x) \ 1807 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 1808 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 1809 1810 #define S_FW_PORT_CMD_RXPAUSE 22 1811 #define M_FW_PORT_CMD_RXPAUSE 0x1 1812 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 1813 #define G_FW_PORT_CMD_RXPAUSE(x) \ 1814 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 1815 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 1816 1817 #define S_FW_PORT_CMD_MDIOCAP 21 1818 #define M_FW_PORT_CMD_MDIOCAP 0x1 1819 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 1820 #define G_FW_PORT_CMD_MDIOCAP(x) \ 1821 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 1822 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 1823 1824 #define S_FW_PORT_CMD_MDIOADDR 16 1825 #define M_FW_PORT_CMD_MDIOADDR 0x1f 1826 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 1827 #define G_FW_PORT_CMD_MDIOADDR(x) \ 1828 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 1829 1830 #define S_FW_PORT_CMD_PTYPE 8 1831 #define M_FW_PORT_CMD_PTYPE 0x1f 1832 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 1833 #define G_FW_PORT_CMD_PTYPE(x) \ 1834 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 1835 1836 #define S_FW_PORT_CMD_LINKDNRC 5 1837 #define M_FW_PORT_CMD_LINKDNRC 0x7 1838 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 1839 #define G_FW_PORT_CMD_LINKDNRC(x) \ 1840 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 1841 1842 #define S_FW_PORT_CMD_MODTYPE 0 1843 #define M_FW_PORT_CMD_MODTYPE 0x1f 1844 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 1845 #define G_FW_PORT_CMD_MODTYPE(x) \ 1846 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 1847 1848 #define S_FW_PORT_CMD_LSTATUS32 31 1849 #define M_FW_PORT_CMD_LSTATUS32 0x1 1850 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 1851 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 1852 1853 #define S_FW_PORT_CMD_LINKDNRC32 28 1854 #define M_FW_PORT_CMD_LINKDNRC32 0x7 1855 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 1856 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 1857 1858 #define S_FW_PORT_CMD_MDIOCAP32 26 1859 #define M_FW_PORT_CMD_MDIOCAP32 0x1 1860 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 1861 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 1862 1863 #define S_FW_PORT_CMD_MDIOADDR32 21 1864 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 1865 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 1866 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 1867 1868 #define S_FW_PORT_CMD_PORTTYPE32 13 1869 #define M_FW_PORT_CMD_PORTTYPE32 0xff 1870 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 1871 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 1872 1873 #define S_FW_PORT_CMD_MODTYPE32 8 1874 #define M_FW_PORT_CMD_MODTYPE32 0x1f 1875 #define G_FW_PORT_CMD_MODTYPE32(x) \ 1876 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 1877 1878 /* 1879 * These are configured into the VPD and hence tools that generate 1880 * VPD may use this enumeration. 1881 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 1882 * 1883 * REMEMBER: 1884 * Update the Common Code t4_hw.c:t4_get_port_type_description() 1885 * with any new Firmware Port Technology Types! 1886 */ 1887 enum fw_port_type { 1888 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 1889 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 1890 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 1891 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 1892 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 1893 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 1894 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 1895 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 1896 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 1897 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 1898 FW_PORT_TYPE_BP_AP = 10, 1899 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 1900 FW_PORT_TYPE_BP4_AP = 11, 1901 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 1902 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 1903 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 1904 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 1905 FW_PORT_TYPE_BP40_BA = 15, 1906 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 1907 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 1908 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 1909 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 1910 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 1911 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 1912 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 1913 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 1914 }; 1915 1916 /* These are read from module's EEPROM and determined once the 1917 * module is inserted. 1918 */ 1919 enum fw_port_module_type { 1920 FW_PORT_MOD_TYPE_NA = 0x0, 1921 FW_PORT_MOD_TYPE_LR = 0x1, 1922 FW_PORT_MOD_TYPE_SR = 0x2, 1923 FW_PORT_MOD_TYPE_ER = 0x3, 1924 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 1925 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 1926 FW_PORT_MOD_TYPE_LRM = 0x6, 1927 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 1928 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 1929 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 1930 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 1931 }; 1932 1933 /* used by FW and tools may use this to generate VPD */ 1934 enum fw_port_mod_sub_type { 1935 FW_PORT_MOD_SUB_TYPE_NA, 1936 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 1937 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 1938 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 1939 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 1940 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 1941 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6, 1942 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7, 1943 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 1944 1945 /* 1946 * The following will never been in the VPD. They are TWINAX cable 1947 * lengths decoded from SFP+ module i2c PROMs. These should almost 1948 * certainly go somewhere else ... 1949 */ 1950 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 1951 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 1952 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 1953 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 1954 }; 1955 1956 /* link down reason codes (3b) */ 1957 enum fw_port_link_dn_rc { 1958 FW_PORT_LINK_DN_RC_NONE, 1959 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 1960 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 1961 FW_PORT_LINK_DN_RESERVED3, 1962 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 1963 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 1964 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 1965 FW_PORT_LINK_DN_RESERVED7 1966 }; 1967 1968 /* port stats */ 1969 #define FW_NUM_PORT_STATS 50 1970 #define FW_NUM_PORT_TX_STATS 23 1971 #define FW_NUM_PORT_RX_STATS 27 1972 1973 enum fw_port_stats_tx_index { 1974 FW_STAT_TX_PORT_BYTES_IX, 1975 FW_STAT_TX_PORT_FRAMES_IX, 1976 FW_STAT_TX_PORT_BCAST_IX, 1977 FW_STAT_TX_PORT_MCAST_IX, 1978 FW_STAT_TX_PORT_UCAST_IX, 1979 FW_STAT_TX_PORT_ERROR_IX, 1980 FW_STAT_TX_PORT_64B_IX, 1981 FW_STAT_TX_PORT_65B_127B_IX, 1982 FW_STAT_TX_PORT_128B_255B_IX, 1983 FW_STAT_TX_PORT_256B_511B_IX, 1984 FW_STAT_TX_PORT_512B_1023B_IX, 1985 FW_STAT_TX_PORT_1024B_1518B_IX, 1986 FW_STAT_TX_PORT_1519B_MAX_IX, 1987 FW_STAT_TX_PORT_DROP_IX, 1988 FW_STAT_TX_PORT_PAUSE_IX, 1989 FW_STAT_TX_PORT_PPP0_IX, 1990 FW_STAT_TX_PORT_PPP1_IX, 1991 FW_STAT_TX_PORT_PPP2_IX, 1992 FW_STAT_TX_PORT_PPP3_IX, 1993 FW_STAT_TX_PORT_PPP4_IX, 1994 FW_STAT_TX_PORT_PPP5_IX, 1995 FW_STAT_TX_PORT_PPP6_IX, 1996 FW_STAT_TX_PORT_PPP7_IX 1997 }; 1998 1999 enum fw_port_stat_rx_index { 2000 FW_STAT_RX_PORT_BYTES_IX, 2001 FW_STAT_RX_PORT_FRAMES_IX, 2002 FW_STAT_RX_PORT_BCAST_IX, 2003 FW_STAT_RX_PORT_MCAST_IX, 2004 FW_STAT_RX_PORT_UCAST_IX, 2005 FW_STAT_RX_PORT_MTU_ERROR_IX, 2006 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 2007 FW_STAT_RX_PORT_CRC_ERROR_IX, 2008 FW_STAT_RX_PORT_LEN_ERROR_IX, 2009 FW_STAT_RX_PORT_SYM_ERROR_IX, 2010 FW_STAT_RX_PORT_64B_IX, 2011 FW_STAT_RX_PORT_65B_127B_IX, 2012 FW_STAT_RX_PORT_128B_255B_IX, 2013 FW_STAT_RX_PORT_256B_511B_IX, 2014 FW_STAT_RX_PORT_512B_1023B_IX, 2015 FW_STAT_RX_PORT_1024B_1518B_IX, 2016 FW_STAT_RX_PORT_1519B_MAX_IX, 2017 FW_STAT_RX_PORT_PAUSE_IX, 2018 FW_STAT_RX_PORT_PPP0_IX, 2019 FW_STAT_RX_PORT_PPP1_IX, 2020 FW_STAT_RX_PORT_PPP2_IX, 2021 FW_STAT_RX_PORT_PPP3_IX, 2022 FW_STAT_RX_PORT_PPP4_IX, 2023 FW_STAT_RX_PORT_PPP5_IX, 2024 FW_STAT_RX_PORT_PPP6_IX, 2025 FW_STAT_RX_PORT_PPP7_IX, 2026 FW_STAT_RX_PORT_LESS_64B_IX 2027 }; 2028 2029 struct fw_port_stats_cmd { 2030 __be32 op_to_portid; 2031 __be32 retval_len16; 2032 union fw_port_stats { 2033 struct fw_port_stats_ctl { 2034 __u8 nstats_bg_bm; 2035 __u8 tx_ix; 2036 __be16 r6; 2037 __be32 r7; 2038 __be64 stat0; 2039 __be64 stat1; 2040 __be64 stat2; 2041 __be64 stat3; 2042 __be64 stat4; 2043 __be64 stat5; 2044 } ctl; 2045 struct fw_port_stats_all { 2046 __be64 tx_bytes; 2047 __be64 tx_frames; 2048 __be64 tx_bcast; 2049 __be64 tx_mcast; 2050 __be64 tx_ucast; 2051 __be64 tx_error; 2052 __be64 tx_64b; 2053 __be64 tx_65b_127b; 2054 __be64 tx_128b_255b; 2055 __be64 tx_256b_511b; 2056 __be64 tx_512b_1023b; 2057 __be64 tx_1024b_1518b; 2058 __be64 tx_1519b_max; 2059 __be64 tx_drop; 2060 __be64 tx_pause; 2061 __be64 tx_ppp0; 2062 __be64 tx_ppp1; 2063 __be64 tx_ppp2; 2064 __be64 tx_ppp3; 2065 __be64 tx_ppp4; 2066 __be64 tx_ppp5; 2067 __be64 tx_ppp6; 2068 __be64 tx_ppp7; 2069 __be64 rx_bytes; 2070 __be64 rx_frames; 2071 __be64 rx_bcast; 2072 __be64 rx_mcast; 2073 __be64 rx_ucast; 2074 __be64 rx_mtu_error; 2075 __be64 rx_mtu_crc_error; 2076 __be64 rx_crc_error; 2077 __be64 rx_len_error; 2078 __be64 rx_sym_error; 2079 __be64 rx_64b; 2080 __be64 rx_65b_127b; 2081 __be64 rx_128b_255b; 2082 __be64 rx_256b_511b; 2083 __be64 rx_512b_1023b; 2084 __be64 rx_1024b_1518b; 2085 __be64 rx_1519b_max; 2086 __be64 rx_pause; 2087 __be64 rx_ppp0; 2088 __be64 rx_ppp1; 2089 __be64 rx_ppp2; 2090 __be64 rx_ppp3; 2091 __be64 rx_ppp4; 2092 __be64 rx_ppp5; 2093 __be64 rx_ppp6; 2094 __be64 rx_ppp7; 2095 __be64 rx_less_64b; 2096 __be64 rx_bg_drop; 2097 __be64 rx_bg_trunc; 2098 } all; 2099 } u; 2100 }; 2101 2102 struct fw_rss_ind_tbl_cmd { 2103 __be32 op_to_viid; 2104 __be32 retval_len16; 2105 __be16 niqid; 2106 __be16 startidx; 2107 __be32 r3; 2108 __be32 iq0_to_iq2; 2109 __be32 iq3_to_iq5; 2110 __be32 iq6_to_iq8; 2111 __be32 iq9_to_iq11; 2112 __be32 iq12_to_iq14; 2113 __be32 iq15_to_iq17; 2114 __be32 iq18_to_iq20; 2115 __be32 iq21_to_iq23; 2116 __be32 iq24_to_iq26; 2117 __be32 iq27_to_iq29; 2118 __be32 iq30_iq31; 2119 __be32 r15_lo; 2120 }; 2121 2122 #define S_FW_RSS_IND_TBL_CMD_VIID 0 2123 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 2124 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 2125 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 2126 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 2127 2128 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 2129 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 2130 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 2131 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 2132 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 2133 2134 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 2135 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 2136 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 2137 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 2138 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 2139 2140 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 2141 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 2142 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 2143 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 2144 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 2145 2146 struct fw_rss_glb_config_cmd { 2147 __be32 op_to_write; 2148 __be32 retval_len16; 2149 union fw_rss_glb_config { 2150 struct fw_rss_glb_config_manual { 2151 __be32 mode_pkd; 2152 __be32 r3; 2153 __be64 r4; 2154 __be64 r5; 2155 } manual; 2156 struct fw_rss_glb_config_basicvirtual { 2157 __be32 mode_keymode; 2158 __be32 synmapen_to_hashtoeplitz; 2159 __be64 r8; 2160 __be64 r9; 2161 } basicvirtual; 2162 } u; 2163 }; 2164 2165 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 2166 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 2167 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 2168 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 2169 2170 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 2171 2172 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 2173 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 2174 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 2175 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 2176 2177 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 2178 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 2179 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 2180 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 2181 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 2182 2183 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 2184 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 2185 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 2186 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 2187 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 2188 2189 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 2190 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 2191 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 2192 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 2193 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 2194 2195 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 2196 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 2197 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 2198 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 2199 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 2200 2201 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 2202 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 2203 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 2204 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 2205 2206 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 2207 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 2208 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 2209 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 2210 2211 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 2212 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 2213 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 2214 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 2215 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 2216 2217 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 2218 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 2219 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 2220 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 2221 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 2222 2223 struct fw_rss_vi_config_cmd { 2224 __be32 op_to_viid; 2225 __be32 retval_len16; 2226 union fw_rss_vi_config { 2227 struct fw_rss_vi_config_manual { 2228 __be64 r3; 2229 __be64 r4; 2230 __be64 r5; 2231 } manual; 2232 struct fw_rss_vi_config_basicvirtual { 2233 __be32 r6; 2234 __be32 defaultq_to_udpen; 2235 __be64 r9; 2236 __be64 r10; 2237 } basicvirtual; 2238 } u; 2239 }; 2240 2241 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 2242 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 2243 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 2244 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 2245 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 2246 2247 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 2248 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 2249 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 2250 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 2251 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 2252 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 2253 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 2254 2255 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 2256 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 2257 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 2258 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 2259 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 2260 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 2261 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 2262 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 2263 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 2264 2265 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 2266 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 2267 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 2268 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 2269 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 2270 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 2271 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 2272 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 2273 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 2274 2275 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 2276 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 2277 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 2278 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 2279 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 2280 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 2281 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 2282 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 2283 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 2284 2285 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 2286 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 2287 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 2288 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 2289 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 2290 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 2291 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 2292 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 2293 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 2294 2295 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 2296 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 2297 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 2298 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 2299 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 2300 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 2301 2302 struct fw_clip_cmd { 2303 __be32 op_to_write; 2304 __be32 alloc_to_len16; 2305 __be64 ip_hi; 2306 __be64 ip_lo; 2307 __be32 r4[2]; 2308 }; 2309 2310 #define S_FW_CLIP_CMD_ALLOC 31 2311 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 2312 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 2313 2314 #define S_FW_CLIP_CMD_FREE 30 2315 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 2316 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 2317 2318 /****************************************************************************** 2319 * D E B U G C O M M A N D s 2320 ******************************************************/ 2321 2322 struct fw_debug_cmd { 2323 __be32 op_type; 2324 __be32 len16_pkd; 2325 union fw_debug { 2326 struct fw_debug_assert { 2327 __be32 fcid; 2328 __be32 line; 2329 __be32 x; 2330 __be32 y; 2331 __u8 filename_0_7[8]; 2332 __u8 filename_8_15[8]; 2333 __be64 r3; 2334 } assert; 2335 struct fw_debug_prt { 2336 __be16 dprtstridx; 2337 __be16 r3[3]; 2338 __be32 dprtstrparam0; 2339 __be32 dprtstrparam1; 2340 __be32 dprtstrparam2; 2341 __be32 dprtstrparam3; 2342 } prt; 2343 } u; 2344 }; 2345 2346 #define S_FW_DEBUG_CMD_TYPE 0 2347 #define M_FW_DEBUG_CMD_TYPE 0xff 2348 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 2349 #define G_FW_DEBUG_CMD_TYPE(x) \ 2350 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 2351 2352 /****************************************************************************** 2353 * P C I E F W R E G I S T E R 2354 **************************************/ 2355 2356 /* 2357 * Register definitions for the PCIE_FW register which the firmware uses 2358 * to retain status across RESETs. This register should be considered 2359 * as a READ-ONLY register for Host Software and only to be used to 2360 * track firmware initialization/error state, etc. 2361 */ 2362 #define S_PCIE_FW_ERR 31 2363 #define M_PCIE_FW_ERR 0x1 2364 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 2365 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 2366 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 2367 2368 #define S_PCIE_FW_INIT 30 2369 #define M_PCIE_FW_INIT 0x1 2370 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 2371 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 2372 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 2373 2374 #define S_PCIE_FW_HALT 29 2375 #define M_PCIE_FW_HALT 0x1 2376 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 2377 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 2378 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 2379 2380 #define S_PCIE_FW_EVAL 24 2381 #define M_PCIE_FW_EVAL 0x7 2382 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 2383 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 2384 2385 #define S_PCIE_FW_MASTER_VLD 15 2386 #define M_PCIE_FW_MASTER_VLD 0x1 2387 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 2388 #define G_PCIE_FW_MASTER_VLD(x) \ 2389 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 2390 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 2391 2392 #define S_PCIE_FW_MASTER 12 2393 #define M_PCIE_FW_MASTER 0x7 2394 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 2395 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 2396 2397 /****************************************************************************** 2398 * B I N A R Y H E A D E R F O R M A T 2399 **********************************************/ 2400 2401 /* 2402 * firmware binary header format 2403 */ 2404 struct fw_hdr { 2405 __u8 ver; 2406 __u8 chip; /* terminator chip family */ 2407 __be16 len512; /* bin length in units of 512-bytes */ 2408 __be32 fw_ver; /* firmware version */ 2409 __be32 tp_microcode_ver; /* tcp processor microcode version */ 2410 __u8 intfver_nic; 2411 __u8 intfver_vnic; 2412 __u8 intfver_ofld; 2413 __u8 intfver_ri; 2414 __u8 intfver_iscsipdu; 2415 __u8 intfver_iscsi; 2416 __u8 intfver_fcoepdu; 2417 __u8 intfver_fcoe; 2418 __u32 reserved2; 2419 __u32 reserved3; 2420 __u32 magic; /* runtime or bootstrap fw */ 2421 __be32 flags; 2422 __be32 reserved6[23]; 2423 }; 2424 2425 #define S_FW_HDR_FW_VER_MAJOR 24 2426 #define M_FW_HDR_FW_VER_MAJOR 0xff 2427 #define V_FW_HDR_FW_VER_MAJOR(x) \ 2428 ((x) << S_FW_HDR_FW_VER_MAJOR) 2429 #define G_FW_HDR_FW_VER_MAJOR(x) \ 2430 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 2431 2432 #define S_FW_HDR_FW_VER_MINOR 16 2433 #define M_FW_HDR_FW_VER_MINOR 0xff 2434 #define V_FW_HDR_FW_VER_MINOR(x) \ 2435 ((x) << S_FW_HDR_FW_VER_MINOR) 2436 #define G_FW_HDR_FW_VER_MINOR(x) \ 2437 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 2438 2439 #define S_FW_HDR_FW_VER_MICRO 8 2440 #define M_FW_HDR_FW_VER_MICRO 0xff 2441 #define V_FW_HDR_FW_VER_MICRO(x) \ 2442 ((x) << S_FW_HDR_FW_VER_MICRO) 2443 #define G_FW_HDR_FW_VER_MICRO(x) \ 2444 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 2445 2446 #define S_FW_HDR_FW_VER_BUILD 0 2447 #define M_FW_HDR_FW_VER_BUILD 0xff 2448 #define V_FW_HDR_FW_VER_BUILD(x) \ 2449 ((x) << S_FW_HDR_FW_VER_BUILD) 2450 #define G_FW_HDR_FW_VER_BUILD(x) \ 2451 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 2452 2453 #endif /* _T4FW_INTERFACE_H_ */ 2454