1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Chelsio Communications. 3 * All rights reserved. 4 */ 5 6 #ifndef _T4FW_INTERFACE_H_ 7 #define _T4FW_INTERFACE_H_ 8 9 /****************************************************************************** 10 * R E T U R N V A L U E S 11 ********************************/ 12 13 enum fw_retval { 14 FW_SUCCESS = 0, /* completed successfully */ 15 FW_EPERM = 1, /* operation not permitted */ 16 FW_ENOENT = 2, /* no such file or directory */ 17 FW_EIO = 5, /* input/output error; hw bad */ 18 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 19 FW_EAGAIN = 11, /* try again */ 20 FW_ENOMEM = 12, /* out of memory */ 21 FW_EFAULT = 14, /* bad address; fw bad */ 22 FW_EBUSY = 16, /* resource busy */ 23 FW_EEXIST = 17, /* file exists */ 24 FW_ENODEV = 19, /* no such device */ 25 FW_EINVAL = 22, /* invalid argument */ 26 FW_ENOSPC = 28, /* no space left on device */ 27 FW_ENOSYS = 38, /* functionality not implemented */ 28 FW_ENODATA = 61, /* no data available */ 29 FW_EPROTO = 71, /* protocol error */ 30 FW_EADDRINUSE = 98, /* address already in use */ 31 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 32 FW_ENETDOWN = 100, /* network is down */ 33 FW_ENETUNREACH = 101, /* network is unreachable */ 34 FW_ENOBUFS = 105, /* no buffer space available */ 35 FW_ETIMEDOUT = 110, /* timeout */ 36 FW_EINPROGRESS = 115, /* fw internal */ 37 }; 38 39 /****************************************************************************** 40 * M E M O R Y T Y P E s 41 ******************************/ 42 43 enum fw_memtype { 44 FW_MEMTYPE_EDC0 = 0x0, 45 FW_MEMTYPE_EDC1 = 0x1, 46 FW_MEMTYPE_EXTMEM = 0x2, 47 FW_MEMTYPE_FLASH = 0x4, 48 FW_MEMTYPE_INTERNAL = 0x5, 49 FW_MEMTYPE_EXTMEM1 = 0x6, 50 }; 51 52 /****************************************************************************** 53 * W O R K R E Q U E S T s 54 ********************************/ 55 56 enum fw_wr_opcodes { 57 FW_FILTER_WR = 0x02, 58 FW_ULPTX_WR = 0x04, 59 FW_TP_WR = 0x05, 60 FW_ETH_TX_PKT_WR = 0x08, 61 FW_ETH_TX_PKTS_WR = 0x09, 62 FW_ETH_TX_PKT_VM_WR = 0x11, 63 FW_ETH_TX_PKTS_VM_WR = 0x12, 64 FW_FILTER2_WR = 0x77, 65 FW_ETH_TX_PKTS2_WR = 0x78, 66 }; 67 68 /* 69 * Generic work request header flit0 70 */ 71 struct fw_wr_hdr { 72 __be32 hi; 73 __be32 lo; 74 }; 75 76 /* work request opcode (hi) 77 */ 78 #define S_FW_WR_OP 24 79 #define M_FW_WR_OP 0xff 80 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 81 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 82 83 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 84 */ 85 #define S_FW_WR_ATOMIC 23 86 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 87 88 /* work request immediate data length (hi) 89 */ 90 #define S_FW_WR_IMMDLEN 0 91 #define M_FW_WR_IMMDLEN 0xff 92 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 93 #define G_FW_WR_IMMDLEN(x) \ 94 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 95 96 /* egress queue status update to egress queue status entry (lo) 97 */ 98 #define S_FW_WR_EQUEQ 30 99 #define M_FW_WR_EQUEQ 0x1 100 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 101 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 102 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 103 104 /* flow context identifier (lo) 105 */ 106 #define S_FW_WR_FLOWID 8 107 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 108 109 /* length in units of 16-bytes (lo) 110 */ 111 #define S_FW_WR_LEN16 0 112 #define M_FW_WR_LEN16 0xff 113 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 114 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 115 116 struct fw_eth_tx_pkt_wr { 117 __be32 op_immdlen; 118 __be32 equiq_to_len16; 119 __be64 r3; 120 }; 121 122 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 123 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 124 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 125 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 126 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 127 128 struct fw_eth_tx_pkts_wr { 129 __be32 op_pkd; 130 __be32 equiq_to_len16; 131 __be32 r3; 132 __be16 plen; 133 __u8 npkt; 134 __u8 type; 135 }; 136 137 struct fw_eth_tx_pkt_vm_wr { 138 __be32 op_immdlen; 139 __be32 equiq_to_len16; 140 __be32 r3[2]; 141 __u8 ethmacdst[6]; 142 __u8 ethmacsrc[6]; 143 __be16 ethtype; 144 __be16 vlantci; 145 }; 146 147 struct fw_eth_tx_pkts_vm_wr { 148 __be32 op_pkd; 149 __be32 equiq_to_len16; 150 __be32 r3; 151 __be16 plen; 152 __u8 npkt; 153 __u8 r4; 154 __u8 ethmacdst[6]; 155 __u8 ethmacsrc[6]; 156 __be16 ethtype; 157 __be16 vlantci; 158 }; 159 160 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 161 enum fw_filter_wr_cookie { 162 FW_FILTER_WR_SUCCESS, 163 FW_FILTER_WR_FLT_ADDED, 164 FW_FILTER_WR_FLT_DELETED, 165 FW_FILTER_WR_SMT_TBL_FULL, 166 FW_FILTER_WR_EINVAL, 167 }; 168 169 struct fw_filter2_wr { 170 __be32 op_pkd; 171 __be32 len16_pkd; 172 __be64 r3; 173 __be32 tid_to_iq; 174 __be32 del_filter_to_l2tix; 175 __be16 ethtype; 176 __be16 ethtypem; 177 __u8 frag_to_ovlan_vldm; 178 __u8 smac_sel; 179 __be16 rx_chan_rx_rpl_iq; 180 __be32 maci_to_matchtypem; 181 __u8 ptcl; 182 __u8 ptclm; 183 __u8 ttyp; 184 __u8 ttypm; 185 __be16 ivlan; 186 __be16 ivlanm; 187 __be16 ovlan; 188 __be16 ovlanm; 189 __u8 lip[16]; 190 __u8 lipm[16]; 191 __u8 fip[16]; 192 __u8 fipm[16]; 193 __be16 lp; 194 __be16 lpm; 195 __be16 fp; 196 __be16 fpm; 197 __be16 r7; 198 __u8 sma[6]; 199 __be16 r8; 200 __u8 filter_type_swapmac; 201 __u8 natmode_to_ulp_type; 202 __be16 newlport; 203 __be16 newfport; 204 __u8 newlip[16]; 205 __u8 newfip[16]; 206 __be32 natseqcheck; 207 __be32 r9; 208 __be64 r10; 209 __be64 r11; 210 __be64 r12; 211 __be64 r13; 212 }; 213 214 #define S_FW_FILTER_WR_TID 12 215 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 216 217 #define S_FW_FILTER_WR_RQTYPE 11 218 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 219 220 #define S_FW_FILTER_WR_NOREPLY 10 221 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 222 223 #define S_FW_FILTER_WR_IQ 0 224 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 225 226 #define S_FW_FILTER_WR_DEL_FILTER 31 227 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 228 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 229 230 #define S_FW_FILTER_WR_RPTTID 25 231 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 232 233 #define S_FW_FILTER_WR_DROP 24 234 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 235 236 #define S_FW_FILTER_WR_DIRSTEER 23 237 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 238 239 #define S_FW_FILTER_WR_MASKHASH 22 240 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 241 242 #define S_FW_FILTER_WR_DIRSTEERHASH 21 243 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 244 245 #define S_FW_FILTER_WR_LPBK 20 246 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 247 248 #define S_FW_FILTER_WR_DMAC 19 249 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 250 251 #define S_FW_FILTER_WR_INSVLAN 17 252 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 253 254 #define S_FW_FILTER_WR_RMVLAN 16 255 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 256 257 #define S_FW_FILTER_WR_HITCNTS 15 258 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 259 260 #define S_FW_FILTER_WR_TXCHAN 13 261 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 262 263 #define S_FW_FILTER_WR_PRIO 12 264 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 265 266 #define S_FW_FILTER_WR_L2TIX 0 267 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 268 269 #define S_FW_FILTER_WR_FRAG 7 270 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 271 272 #define S_FW_FILTER_WR_FRAGM 6 273 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 274 275 #define S_FW_FILTER_WR_IVLAN_VLD 5 276 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 277 278 #define S_FW_FILTER_WR_OVLAN_VLD 4 279 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 280 281 #define S_FW_FILTER_WR_IVLAN_VLDM 3 282 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 283 284 #define S_FW_FILTER_WR_OVLAN_VLDM 2 285 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 286 287 #define S_FW_FILTER_WR_RX_CHAN 15 288 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 289 290 #define S_FW_FILTER_WR_RX_RPL_IQ 0 291 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 292 293 #define S_FW_FILTER_WR_MACI 23 294 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 295 296 #define S_FW_FILTER_WR_MACIM 14 297 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 298 299 #define S_FW_FILTER_WR_FCOE 13 300 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 301 302 #define S_FW_FILTER_WR_FCOEM 12 303 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 304 305 #define S_FW_FILTER_WR_PORT 9 306 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 307 308 #define S_FW_FILTER_WR_PORTM 6 309 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 310 311 #define S_FW_FILTER_WR_MATCHTYPE 3 312 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 313 314 #define S_FW_FILTER_WR_MATCHTYPEM 0 315 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 316 317 #define S_FW_FILTER2_WR_NATMODE 5 318 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 319 320 #define S_FW_FILTER2_WR_ULP_TYPE 0 321 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 322 323 /****************************************************************************** 324 * C O M M A N D s 325 *********************/ 326 327 /* 328 * The maximum length of time, in miliseconds, that we expect any firmware 329 * command to take to execute and return a reply to the host. The RESET 330 * and INITIALIZE commands can take a fair amount of time to execute but 331 * most execute in far less time than this maximum. This constant is used 332 * by host software to determine how long to wait for a firmware command 333 * reply before declaring the firmware as dead/unreachable ... 334 */ 335 #define FW_CMD_MAX_TIMEOUT 10000 336 337 /* 338 * If a host driver does a HELLO and discovers that there's already a MASTER 339 * selected, we may have to wait for that MASTER to finish issuing RESET, 340 * configuration and INITIALIZE commands. Also, there's a possibility that 341 * our own HELLO may get lost if it happens right as the MASTER is issuign a 342 * RESET command, so we need to be willing to make a few retries of our HELLO. 343 */ 344 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 345 #define FW_CMD_HELLO_RETRIES 3 346 347 enum fw_cmd_opcodes { 348 FW_LDST_CMD = 0x01, 349 FW_RESET_CMD = 0x03, 350 FW_HELLO_CMD = 0x04, 351 FW_BYE_CMD = 0x05, 352 FW_INITIALIZE_CMD = 0x06, 353 FW_CAPS_CONFIG_CMD = 0x07, 354 FW_PARAMS_CMD = 0x08, 355 FW_PFVF_CMD = 0x09, 356 FW_IQ_CMD = 0x10, 357 FW_EQ_ETH_CMD = 0x12, 358 FW_EQ_CTRL_CMD = 0x13, 359 FW_VI_CMD = 0x14, 360 FW_VI_MAC_CMD = 0x15, 361 FW_VI_RXMODE_CMD = 0x16, 362 FW_VI_ENABLE_CMD = 0x17, 363 FW_VI_STATS_CMD = 0x1a, 364 FW_PORT_CMD = 0x1b, 365 FW_RSS_IND_TBL_CMD = 0x20, 366 FW_RSS_GLB_CONFIG_CMD = 0x22, 367 FW_RSS_VI_CONFIG_CMD = 0x23, 368 FW_CLIP_CMD = 0x28, 369 FW_DEBUG_CMD = 0x81, 370 }; 371 372 enum fw_cmd_cap { 373 FW_CMD_CAP_PORT = 0x04, 374 }; 375 376 /* 377 * Generic command header flit0 378 */ 379 struct fw_cmd_hdr { 380 __be32 hi; 381 __be32 lo; 382 }; 383 384 #define S_FW_CMD_OP 24 385 #define M_FW_CMD_OP 0xff 386 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 387 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 388 389 #define S_FW_CMD_REQUEST 23 390 #define M_FW_CMD_REQUEST 0x1 391 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 392 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 393 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 394 395 #define S_FW_CMD_READ 22 396 #define M_FW_CMD_READ 0x1 397 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 398 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 399 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 400 401 #define S_FW_CMD_WRITE 21 402 #define M_FW_CMD_WRITE 0x1 403 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 404 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 405 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 406 407 #define S_FW_CMD_EXEC 20 408 #define M_FW_CMD_EXEC 0x1 409 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 410 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 411 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 412 413 #define S_FW_CMD_RETVAL 8 414 #define M_FW_CMD_RETVAL 0xff 415 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 416 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 417 418 #define S_FW_CMD_LEN16 0 419 #define M_FW_CMD_LEN16 0xff 420 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 421 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 422 423 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 424 425 /* address spaces 426 */ 427 enum fw_ldst_addrspc { 428 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 429 }; 430 431 struct fw_ldst_cmd { 432 __be32 op_to_addrspace; 433 __be32 cycles_to_len16; 434 union fw_ldst { 435 struct fw_ldst_addrval { 436 __be32 addr; 437 __be32 val; 438 } addrval; 439 struct fw_ldst_idctxt { 440 __be32 physid; 441 __be32 msg_ctxtflush; 442 __be32 ctxt_data7; 443 __be32 ctxt_data6; 444 __be32 ctxt_data5; 445 __be32 ctxt_data4; 446 __be32 ctxt_data3; 447 __be32 ctxt_data2; 448 __be32 ctxt_data1; 449 __be32 ctxt_data0; 450 } idctxt; 451 struct fw_ldst_mdio { 452 __be16 paddr_mmd; 453 __be16 raddr; 454 __be16 vctl; 455 __be16 rval; 456 } mdio; 457 struct fw_ldst_mps { 458 __be16 fid_ctl; 459 __be16 rplcpf_pkd; 460 __be32 rplc127_96; 461 __be32 rplc95_64; 462 __be32 rplc63_32; 463 __be32 rplc31_0; 464 __be32 atrb; 465 __be16 vlan[16]; 466 } mps; 467 struct fw_ldst_func { 468 __u8 access_ctl; 469 __u8 mod_index; 470 __be16 ctl_id; 471 __be32 offset; 472 __be64 data0; 473 __be64 data1; 474 } func; 475 struct fw_ldst_pcie { 476 __u8 ctrl_to_fn; 477 __u8 bnum; 478 __u8 r; 479 __u8 ext_r; 480 __u8 select_naccess; 481 __u8 pcie_fn; 482 __be16 nset_pkd; 483 __be32 data[12]; 484 } pcie; 485 struct fw_ldst_i2c_deprecated { 486 __u8 pid_pkd; 487 __u8 base; 488 __u8 boffset; 489 __u8 data; 490 __be32 r9; 491 } i2c_deprecated; 492 struct fw_ldst_i2c { 493 __u8 pid; 494 __u8 did; 495 __u8 boffset; 496 __u8 blen; 497 __be32 r9; 498 __u8 data[48]; 499 } i2c; 500 struct fw_ldst_le { 501 __be32 index; 502 __be32 r9; 503 __u8 val[33]; 504 __u8 r11[7]; 505 } le; 506 } u; 507 }; 508 509 #define S_FW_LDST_CMD_ADDRSPACE 0 510 #define M_FW_LDST_CMD_ADDRSPACE 0xff 511 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 512 513 struct fw_reset_cmd { 514 __be32 op_to_write; 515 __be32 retval_len16; 516 __be32 val; 517 __be32 halt_pkd; 518 }; 519 520 #define S_FW_RESET_CMD_HALT 31 521 #define M_FW_RESET_CMD_HALT 0x1 522 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 523 #define G_FW_RESET_CMD_HALT(x) \ 524 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 525 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 526 527 enum { 528 FW_HELLO_CMD_STAGE_OS = 0, 529 }; 530 531 struct fw_hello_cmd { 532 __be32 op_to_write; 533 __be32 retval_len16; 534 __be32 err_to_clearinit; 535 __be32 fwrev; 536 }; 537 538 #define S_FW_HELLO_CMD_ERR 31 539 #define M_FW_HELLO_CMD_ERR 0x1 540 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 541 #define G_FW_HELLO_CMD_ERR(x) \ 542 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 543 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 544 545 #define S_FW_HELLO_CMD_INIT 30 546 #define M_FW_HELLO_CMD_INIT 0x1 547 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 548 #define G_FW_HELLO_CMD_INIT(x) \ 549 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 550 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 551 552 #define S_FW_HELLO_CMD_MASTERDIS 29 553 #define M_FW_HELLO_CMD_MASTERDIS 0x1 554 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 555 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 556 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 557 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 558 559 #define S_FW_HELLO_CMD_MASTERFORCE 28 560 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 561 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 562 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 563 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 564 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 565 566 #define S_FW_HELLO_CMD_MBMASTER 24 567 #define M_FW_HELLO_CMD_MBMASTER 0xf 568 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 569 #define G_FW_HELLO_CMD_MBMASTER(x) \ 570 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 571 572 #define S_FW_HELLO_CMD_MBASYNCNOT 20 573 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 574 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 575 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 576 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 577 578 #define S_FW_HELLO_CMD_STAGE 17 579 #define M_FW_HELLO_CMD_STAGE 0x7 580 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 581 #define G_FW_HELLO_CMD_STAGE(x) \ 582 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 583 584 #define S_FW_HELLO_CMD_CLEARINIT 16 585 #define M_FW_HELLO_CMD_CLEARINIT 0x1 586 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 587 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 588 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 589 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 590 591 struct fw_bye_cmd { 592 __be32 op_to_write; 593 __be32 retval_len16; 594 __be64 r3; 595 }; 596 597 struct fw_initialize_cmd { 598 __be32 op_to_write; 599 __be32 retval_len16; 600 __be64 r3; 601 }; 602 603 enum fw_caps_config_nic { 604 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 605 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 606 }; 607 608 enum fw_memtype_cf { 609 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 610 }; 611 612 struct fw_caps_config_cmd { 613 __be32 op_to_write; 614 __be32 cfvalid_to_len16; 615 __be32 r2; 616 __be32 hwmbitmap; 617 __be16 nbmcaps; 618 __be16 linkcaps; 619 __be16 switchcaps; 620 __be16 r3; 621 __be16 niccaps; 622 __be16 toecaps; 623 __be16 rdmacaps; 624 __be16 r4; 625 __be16 iscsicaps; 626 __be16 fcoecaps; 627 __be32 cfcsum; 628 __be32 finiver; 629 __be32 finicsum; 630 }; 631 632 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 633 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 634 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 635 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 636 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 637 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 638 639 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 640 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 641 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 642 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 643 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 644 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 645 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 646 647 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 648 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 649 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 650 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 651 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 652 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 653 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 654 655 /* 656 * params command mnemonics 657 */ 658 enum fw_params_mnem { 659 FW_PARAMS_MNEM_DEV = 1, /* device params */ 660 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 661 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 662 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 663 }; 664 665 /* 666 * device parameters 667 */ 668 enum fw_params_param_dev { 669 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 670 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 671 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 672 * allocated by the device's 673 * Lookup Engine 674 */ 675 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, /* fw version */ 676 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, /* tp version */ 677 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 678 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 679 }; 680 681 /* 682 * physical and virtual function parameters 683 */ 684 enum fw_params_param_pfvf { 685 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 686 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 687 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 688 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 689 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 690 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 691 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 692 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A 693 }; 694 695 /* 696 * dma queue parameters 697 */ 698 enum fw_params_param_dmaq { 699 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 700 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 701 }; 702 703 #define S_FW_PARAMS_MNEM 24 704 #define M_FW_PARAMS_MNEM 0xff 705 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 706 #define G_FW_PARAMS_MNEM(x) \ 707 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 708 709 #define S_FW_PARAMS_PARAM_X 16 710 #define M_FW_PARAMS_PARAM_X 0xff 711 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 712 #define G_FW_PARAMS_PARAM_X(x) \ 713 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 714 715 #define S_FW_PARAMS_PARAM_Y 8 716 #define M_FW_PARAMS_PARAM_Y 0xff 717 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 718 #define G_FW_PARAMS_PARAM_Y(x) \ 719 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 720 721 #define S_FW_PARAMS_PARAM_Z 0 722 #define M_FW_PARAMS_PARAM_Z 0xff 723 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 724 #define G_FW_PARAMS_PARAM_Z(x) \ 725 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 726 727 #define S_FW_PARAMS_PARAM_YZ 0 728 #define M_FW_PARAMS_PARAM_YZ 0xffff 729 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 730 #define G_FW_PARAMS_PARAM_YZ(x) \ 731 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 732 733 #define S_FW_PARAMS_PARAM_XYZ 0 734 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 735 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 736 737 struct fw_params_cmd { 738 __be32 op_to_vfn; 739 __be32 retval_len16; 740 struct fw_params_param { 741 __be32 mnem; 742 __be32 val; 743 } param[7]; 744 }; 745 746 #define S_FW_PARAMS_CMD_PFN 8 747 #define M_FW_PARAMS_CMD_PFN 0x7 748 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 749 #define G_FW_PARAMS_CMD_PFN(x) \ 750 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 751 752 #define S_FW_PARAMS_CMD_VFN 0 753 #define M_FW_PARAMS_CMD_VFN 0xff 754 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 755 #define G_FW_PARAMS_CMD_VFN(x) \ 756 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 757 758 struct fw_pfvf_cmd { 759 __be32 op_to_vfn; 760 __be32 retval_len16; 761 __be32 niqflint_niq; 762 __be32 type_to_neq; 763 __be32 tc_to_nexactf; 764 __be32 r_caps_to_nethctrl; 765 __be16 nricq; 766 __be16 nriqp; 767 __be32 r4; 768 }; 769 770 #define S_FW_PFVF_CMD_PFN 8 771 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 772 773 #define S_FW_PFVF_CMD_VFN 0 774 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 775 776 #define S_FW_PFVF_CMD_NIQFLINT 20 777 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 778 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 779 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 780 781 #define S_FW_PFVF_CMD_NIQ 0 782 #define M_FW_PFVF_CMD_NIQ 0xfffff 783 #define G_FW_PFVF_CMD_NIQ(x) \ 784 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 785 786 #define S_FW_PFVF_CMD_PMASK 20 787 #define M_FW_PFVF_CMD_PMASK 0xf 788 #define G_FW_PFVF_CMD_PMASK(x) \ 789 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 790 791 #define S_FW_PFVF_CMD_NEQ 0 792 #define M_FW_PFVF_CMD_NEQ 0xfffff 793 #define G_FW_PFVF_CMD_NEQ(x) \ 794 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 795 796 #define S_FW_PFVF_CMD_TC 24 797 #define M_FW_PFVF_CMD_TC 0xff 798 #define G_FW_PFVF_CMD_TC(x) \ 799 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 800 801 #define S_FW_PFVF_CMD_NVI 16 802 #define M_FW_PFVF_CMD_NVI 0xff 803 #define G_FW_PFVF_CMD_NVI(x) \ 804 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 805 806 #define S_FW_PFVF_CMD_NEXACTF 0 807 #define M_FW_PFVF_CMD_NEXACTF 0xffff 808 #define G_FW_PFVF_CMD_NEXACTF(x) \ 809 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 810 811 #define S_FW_PFVF_CMD_R_CAPS 24 812 #define M_FW_PFVF_CMD_R_CAPS 0xff 813 #define G_FW_PFVF_CMD_R_CAPS(x) \ 814 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 815 816 #define S_FW_PFVF_CMD_WX_CAPS 16 817 #define M_FW_PFVF_CMD_WX_CAPS 0xff 818 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 819 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 820 821 #define S_FW_PFVF_CMD_NETHCTRL 0 822 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 823 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 824 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 825 826 /* 827 * ingress queue type; the first 1K ingress queues can have associated 0, 828 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 829 * capabilities 830 */ 831 enum fw_iq_type { 832 FW_IQ_TYPE_FL_INT_CAP, 833 }; 834 835 enum fw_iq_iqtype { 836 FW_IQ_IQTYPE_NIC = 1, 837 FW_IQ_IQTYPE_OFLD, 838 }; 839 840 struct fw_iq_cmd { 841 __be32 op_to_vfn; 842 __be32 alloc_to_len16; 843 __be16 physiqid; 844 __be16 iqid; 845 __be16 fl0id; 846 __be16 fl1id; 847 __be32 type_to_iqandstindex; 848 __be16 iqdroprss_to_iqesize; 849 __be16 iqsize; 850 __be64 iqaddr; 851 __be32 iqns_to_fl0congen; 852 __be16 fl0dcaen_to_fl0cidxfthresh; 853 __be16 fl0size; 854 __be64 fl0addr; 855 __be32 fl1cngchmap_to_fl1congen; 856 __be16 fl1dcaen_to_fl1cidxfthresh; 857 __be16 fl1size; 858 __be64 fl1addr; 859 }; 860 861 #define S_FW_IQ_CMD_PFN 8 862 #define M_FW_IQ_CMD_PFN 0x7 863 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 864 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 865 866 #define S_FW_IQ_CMD_VFN 0 867 #define M_FW_IQ_CMD_VFN 0xff 868 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 869 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 870 871 #define S_FW_IQ_CMD_ALLOC 31 872 #define M_FW_IQ_CMD_ALLOC 0x1 873 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 874 #define G_FW_IQ_CMD_ALLOC(x) \ 875 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 876 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 877 878 #define S_FW_IQ_CMD_FREE 30 879 #define M_FW_IQ_CMD_FREE 0x1 880 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 881 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 882 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 883 884 #define S_FW_IQ_CMD_IQSTART 28 885 #define M_FW_IQ_CMD_IQSTART 0x1 886 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 887 #define G_FW_IQ_CMD_IQSTART(x) \ 888 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 889 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 890 891 #define S_FW_IQ_CMD_IQSTOP 27 892 #define M_FW_IQ_CMD_IQSTOP 0x1 893 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 894 #define G_FW_IQ_CMD_IQSTOP(x) \ 895 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 896 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 897 898 #define S_FW_IQ_CMD_TYPE 29 899 #define M_FW_IQ_CMD_TYPE 0x7 900 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 901 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 902 903 #define S_FW_IQ_CMD_IQASYNCH 28 904 #define M_FW_IQ_CMD_IQASYNCH 0x1 905 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 906 #define G_FW_IQ_CMD_IQASYNCH(x) \ 907 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 908 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 909 910 #define S_FW_IQ_CMD_VIID 16 911 #define M_FW_IQ_CMD_VIID 0xfff 912 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 913 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 914 915 #define S_FW_IQ_CMD_IQANDST 15 916 #define M_FW_IQ_CMD_IQANDST 0x1 917 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 918 #define G_FW_IQ_CMD_IQANDST(x) \ 919 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 920 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 921 922 #define S_FW_IQ_CMD_IQANUD 12 923 #define M_FW_IQ_CMD_IQANUD 0x3 924 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 925 #define G_FW_IQ_CMD_IQANUD(x) \ 926 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 927 928 #define S_FW_IQ_CMD_IQANDSTINDEX 0 929 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 930 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 931 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 932 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 933 934 #define S_FW_IQ_CMD_IQGTSMODE 14 935 #define M_FW_IQ_CMD_IQGTSMODE 0x1 936 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 937 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 938 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 939 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 940 941 #define S_FW_IQ_CMD_IQPCIECH 12 942 #define M_FW_IQ_CMD_IQPCIECH 0x3 943 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 944 #define G_FW_IQ_CMD_IQPCIECH(x) \ 945 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 946 947 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 948 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 949 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 950 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 951 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 952 953 #define S_FW_IQ_CMD_IQESIZE 0 954 #define M_FW_IQ_CMD_IQESIZE 0x3 955 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 956 #define G_FW_IQ_CMD_IQESIZE(x) \ 957 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 958 959 #define S_FW_IQ_CMD_IQRO 30 960 #define M_FW_IQ_CMD_IQRO 0x1 961 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 962 #define G_FW_IQ_CMD_IQRO(x) \ 963 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 964 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 965 966 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 967 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 968 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 969 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 970 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 971 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 972 973 #define S_FW_IQ_CMD_IQTYPE 24 974 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 975 976 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 977 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 978 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 979 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 980 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 981 982 #define S_FW_IQ_CMD_FL0DATARO 12 983 #define M_FW_IQ_CMD_FL0DATARO 0x1 984 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 985 #define G_FW_IQ_CMD_FL0DATARO(x) \ 986 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 987 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 988 989 #define S_FW_IQ_CMD_FL0CONGCIF 11 990 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 991 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 992 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 993 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 994 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 995 996 #define S_FW_IQ_CMD_FL0FETCHRO 6 997 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 998 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 999 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 1000 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 1001 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 1002 1003 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 1004 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 1005 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 1006 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 1007 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 1008 1009 #define S_FW_IQ_CMD_FL0PADEN 2 1010 #define M_FW_IQ_CMD_FL0PADEN 0x1 1011 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 1012 #define G_FW_IQ_CMD_FL0PADEN(x) \ 1013 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 1014 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 1015 1016 #define S_FW_IQ_CMD_FL0PACKEN 1 1017 #define M_FW_IQ_CMD_FL0PACKEN 0x1 1018 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 1019 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 1020 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 1021 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 1022 1023 #define S_FW_IQ_CMD_FL0CONGEN 0 1024 #define M_FW_IQ_CMD_FL0CONGEN 0x1 1025 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 1026 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 1027 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 1028 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 1029 1030 #define S_FW_IQ_CMD_FL0FBMIN 7 1031 #define M_FW_IQ_CMD_FL0FBMIN 0x7 1032 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 1033 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 1034 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 1035 1036 #define S_FW_IQ_CMD_FL0FBMAX 4 1037 #define M_FW_IQ_CMD_FL0FBMAX 0x7 1038 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 1039 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 1040 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 1041 1042 struct fw_eq_eth_cmd { 1043 __be32 op_to_vfn; 1044 __be32 alloc_to_len16; 1045 __be32 eqid_pkd; 1046 __be32 physeqid_pkd; 1047 __be32 fetchszm_to_iqid; 1048 __be32 dcaen_to_eqsize; 1049 __be64 eqaddr; 1050 __be32 autoequiqe_to_viid; 1051 __be32 r8_lo; 1052 __be64 r9; 1053 }; 1054 1055 #define S_FW_EQ_ETH_CMD_PFN 8 1056 #define M_FW_EQ_ETH_CMD_PFN 0x7 1057 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 1058 #define G_FW_EQ_ETH_CMD_PFN(x) \ 1059 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 1060 1061 #define S_FW_EQ_ETH_CMD_VFN 0 1062 #define M_FW_EQ_ETH_CMD_VFN 0xff 1063 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 1064 #define G_FW_EQ_ETH_CMD_VFN(x) \ 1065 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 1066 1067 #define S_FW_EQ_ETH_CMD_ALLOC 31 1068 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 1069 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 1070 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 1071 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 1072 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 1073 1074 #define S_FW_EQ_ETH_CMD_FREE 30 1075 #define M_FW_EQ_ETH_CMD_FREE 0x1 1076 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 1077 #define G_FW_EQ_ETH_CMD_FREE(x) \ 1078 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 1079 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 1080 1081 #define S_FW_EQ_ETH_CMD_EQSTART 28 1082 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 1083 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 1084 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 1085 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 1086 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 1087 1088 #define S_FW_EQ_ETH_CMD_EQID 0 1089 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 1090 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 1091 #define G_FW_EQ_ETH_CMD_EQID(x) \ 1092 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 1093 1094 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 1095 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 1096 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 1097 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 1098 1099 #define S_FW_EQ_ETH_CMD_FETCHRO 22 1100 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 1101 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 1102 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 1103 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 1104 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 1105 1106 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 1107 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 1108 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 1109 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 1110 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 1111 1112 #define S_FW_EQ_ETH_CMD_PCIECHN 16 1113 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 1114 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 1115 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 1116 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 1117 1118 #define S_FW_EQ_ETH_CMD_IQID 0 1119 #define M_FW_EQ_ETH_CMD_IQID 0xffff 1120 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 1121 #define G_FW_EQ_ETH_CMD_IQID(x) \ 1122 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 1123 1124 #define S_FW_EQ_ETH_CMD_FBMIN 23 1125 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 1126 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 1127 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 1128 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 1129 1130 #define S_FW_EQ_ETH_CMD_FBMAX 20 1131 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 1132 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 1133 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 1134 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 1135 1136 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 1137 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 1138 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 1139 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 1140 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 1141 1142 #define S_FW_EQ_ETH_CMD_EQSIZE 0 1143 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 1144 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 1145 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 1146 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 1147 1148 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 1149 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 1150 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 1151 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 1152 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 1153 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 1154 1155 #define S_FW_EQ_ETH_CMD_VIID 16 1156 #define M_FW_EQ_ETH_CMD_VIID 0xfff 1157 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 1158 #define G_FW_EQ_ETH_CMD_VIID(x) \ 1159 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 1160 1161 struct fw_eq_ctrl_cmd { 1162 __be32 op_to_vfn; 1163 __be32 alloc_to_len16; 1164 __be32 cmpliqid_eqid; 1165 __be32 physeqid_pkd; 1166 __be32 fetchszm_to_iqid; 1167 __be32 dcaen_to_eqsize; 1168 __be64 eqaddr; 1169 }; 1170 1171 #define S_FW_EQ_CTRL_CMD_PFN 8 1172 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 1173 1174 #define S_FW_EQ_CTRL_CMD_VFN 0 1175 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 1176 1177 #define S_FW_EQ_CTRL_CMD_ALLOC 31 1178 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 1179 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 1180 1181 #define S_FW_EQ_CTRL_CMD_FREE 30 1182 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 1183 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 1184 1185 #define S_FW_EQ_CTRL_CMD_EQSTART 28 1186 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 1187 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 1188 1189 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 1190 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 1191 1192 #define S_FW_EQ_CTRL_CMD_EQID 0 1193 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 1194 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 1195 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 1196 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 1197 1198 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 1199 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 1200 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 1201 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 1202 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 1203 1204 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 1205 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 1206 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 1207 1208 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 1209 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 1210 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 1211 1212 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 1213 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 1214 1215 #define S_FW_EQ_CTRL_CMD_IQID 0 1216 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 1217 1218 #define S_FW_EQ_CTRL_CMD_FBMIN 23 1219 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 1220 1221 #define S_FW_EQ_CTRL_CMD_FBMAX 20 1222 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 1223 1224 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 1225 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 1226 1227 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 1228 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 1229 1230 enum fw_vi_func { 1231 FW_VI_FUNC_ETH, 1232 }; 1233 1234 struct fw_vi_cmd { 1235 __be32 op_to_vfn; 1236 __be32 alloc_to_len16; 1237 __be16 type_to_viid; 1238 __u8 mac[6]; 1239 __u8 portid_pkd; 1240 __u8 nmac; 1241 __u8 nmac0[6]; 1242 __be16 norss_rsssize; 1243 __u8 nmac1[6]; 1244 __be16 idsiiq_pkd; 1245 __u8 nmac2[6]; 1246 __be16 idseiq_pkd; 1247 __u8 nmac3[6]; 1248 __be64 r9; 1249 __be64 r10; 1250 }; 1251 1252 #define S_FW_VI_CMD_PFN 8 1253 #define M_FW_VI_CMD_PFN 0x7 1254 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 1255 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 1256 1257 #define S_FW_VI_CMD_VFN 0 1258 #define M_FW_VI_CMD_VFN 0xff 1259 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 1260 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 1261 1262 #define S_FW_VI_CMD_ALLOC 31 1263 #define M_FW_VI_CMD_ALLOC 0x1 1264 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 1265 #define G_FW_VI_CMD_ALLOC(x) \ 1266 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 1267 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 1268 1269 #define S_FW_VI_CMD_FREE 30 1270 #define M_FW_VI_CMD_FREE 0x1 1271 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 1272 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 1273 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 1274 1275 #define S_FW_VI_CMD_TYPE 15 1276 #define M_FW_VI_CMD_TYPE 0x1 1277 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 1278 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 1279 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 1280 1281 #define S_FW_VI_CMD_FUNC 12 1282 #define M_FW_VI_CMD_FUNC 0x7 1283 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 1284 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 1285 1286 #define S_FW_VI_CMD_VIID 0 1287 #define M_FW_VI_CMD_VIID 0xfff 1288 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 1289 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 1290 1291 #define S_FW_VI_CMD_PORTID 4 1292 #define M_FW_VI_CMD_PORTID 0xf 1293 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 1294 #define G_FW_VI_CMD_PORTID(x) \ 1295 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 1296 1297 #define S_FW_VI_CMD_RSSSIZE 0 1298 #define M_FW_VI_CMD_RSSSIZE 0x7ff 1299 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 1300 #define G_FW_VI_CMD_RSSSIZE(x) \ 1301 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 1302 1303 /* Special VI_MAC command index ids */ 1304 #define FW_VI_MAC_ADD_MAC 0x3FF 1305 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 1306 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 1307 1308 enum fw_vi_mac_smac { 1309 FW_VI_MAC_MPS_TCAM_ENTRY, 1310 FW_VI_MAC_SMT_AND_MPSTCAM 1311 }; 1312 1313 enum fw_vi_mac_entry_types { 1314 FW_VI_MAC_TYPE_RAW = 0x2, 1315 }; 1316 1317 struct fw_vi_mac_cmd { 1318 __be32 op_to_viid; 1319 __be32 freemacs_to_len16; 1320 union fw_vi_mac { 1321 struct fw_vi_mac_exact { 1322 __be16 valid_to_idx; 1323 __u8 macaddr[6]; 1324 } exact[7]; 1325 struct fw_vi_mac_hash { 1326 __be64 hashvec; 1327 } hash; 1328 struct fw_vi_mac_raw { 1329 __be32 raw_idx_pkd; 1330 __be32 data0_pkd; 1331 __be32 data1[2]; 1332 __be64 data0m_pkd; 1333 __be32 data1m[2]; 1334 } raw; 1335 } u; 1336 }; 1337 1338 #define S_FW_VI_MAC_CMD_VIID 0 1339 #define M_FW_VI_MAC_CMD_VIID 0xfff 1340 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 1341 #define G_FW_VI_MAC_CMD_VIID(x) \ 1342 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 1343 1344 #define S_FW_VI_MAC_CMD_FREEMACS 31 1345 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 1346 1347 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 1348 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 1349 1350 #define S_FW_VI_MAC_CMD_VALID 15 1351 #define M_FW_VI_MAC_CMD_VALID 0x1 1352 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 1353 #define G_FW_VI_MAC_CMD_VALID(x) \ 1354 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 1355 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 1356 1357 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 1358 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 1359 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 1360 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 1361 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 1362 1363 #define S_FW_VI_MAC_CMD_IDX 0 1364 #define M_FW_VI_MAC_CMD_IDX 0x3ff 1365 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 1366 #define G_FW_VI_MAC_CMD_IDX(x) \ 1367 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 1368 1369 #define S_FW_VI_MAC_CMD_RAW_IDX 16 1370 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 1371 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 1372 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 1373 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 1374 1375 struct fw_vi_rxmode_cmd { 1376 __be32 op_to_viid; 1377 __be32 retval_len16; 1378 __be32 mtu_to_vlanexen; 1379 __be32 r4_lo; 1380 }; 1381 1382 #define S_FW_VI_RXMODE_CMD_VIID 0 1383 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 1384 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 1385 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 1386 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 1387 1388 #define S_FW_VI_RXMODE_CMD_MTU 16 1389 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 1390 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 1391 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 1392 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 1393 1394 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 1395 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 1396 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 1397 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 1398 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 1399 1400 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 1401 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 1402 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1403 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 1404 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 1405 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 1406 1407 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 1408 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 1409 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1410 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 1411 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 1412 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & \ 1413 M_FW_VI_RXMODE_CMD_BROADCASTEN) 1414 1415 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 1416 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 1417 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 1418 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 1419 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 1420 1421 struct fw_vi_enable_cmd { 1422 __be32 op_to_viid; 1423 __be32 ien_to_len16; 1424 __be16 blinkdur; 1425 __be16 r3; 1426 __be32 r4; 1427 }; 1428 1429 #define S_FW_VI_ENABLE_CMD_VIID 0 1430 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 1431 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 1432 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 1433 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 1434 1435 #define S_FW_VI_ENABLE_CMD_IEN 31 1436 #define M_FW_VI_ENABLE_CMD_IEN 0x1 1437 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 1438 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 1439 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 1440 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 1441 1442 #define S_FW_VI_ENABLE_CMD_EEN 30 1443 #define M_FW_VI_ENABLE_CMD_EEN 0x1 1444 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 1445 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 1446 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 1447 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 1448 1449 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 1450 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 1451 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 1452 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 1453 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 1454 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 1455 1456 /* VI VF stats offset definitions */ 1457 #define VI_VF_NUM_STATS 16 1458 1459 /* VI PF stats offset definitions */ 1460 #define VI_PF_NUM_STATS 17 1461 enum fw_vi_stats_pf_index { 1462 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 1463 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 1464 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 1465 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 1466 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 1467 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 1468 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 1469 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 1470 FW_VI_PF_STAT_RX_BYTES_IX, 1471 FW_VI_PF_STAT_RX_FRAMES_IX, 1472 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 1473 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 1474 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 1475 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 1476 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 1477 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 1478 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 1479 }; 1480 1481 struct fw_vi_stats_cmd { 1482 __be32 op_to_viid; 1483 __be32 retval_len16; 1484 union fw_vi_stats { 1485 struct fw_vi_stats_ctl { 1486 __be16 nstats_ix; 1487 __be16 r6; 1488 __be32 r7; 1489 __be64 stat0; 1490 __be64 stat1; 1491 __be64 stat2; 1492 __be64 stat3; 1493 __be64 stat4; 1494 __be64 stat5; 1495 } ctl; 1496 struct fw_vi_stats_pf { 1497 __be64 tx_bcast_bytes; 1498 __be64 tx_bcast_frames; 1499 __be64 tx_mcast_bytes; 1500 __be64 tx_mcast_frames; 1501 __be64 tx_ucast_bytes; 1502 __be64 tx_ucast_frames; 1503 __be64 tx_offload_bytes; 1504 __be64 tx_offload_frames; 1505 __be64 rx_pf_bytes; 1506 __be64 rx_pf_frames; 1507 __be64 rx_bcast_bytes; 1508 __be64 rx_bcast_frames; 1509 __be64 rx_mcast_bytes; 1510 __be64 rx_mcast_frames; 1511 __be64 rx_ucast_bytes; 1512 __be64 rx_ucast_frames; 1513 __be64 rx_err_frames; 1514 } pf; 1515 struct fw_vi_stats_vf { 1516 __be64 tx_bcast_bytes; 1517 __be64 tx_bcast_frames; 1518 __be64 tx_mcast_bytes; 1519 __be64 tx_mcast_frames; 1520 __be64 tx_ucast_bytes; 1521 __be64 tx_ucast_frames; 1522 __be64 tx_drop_frames; 1523 __be64 tx_offload_bytes; 1524 __be64 tx_offload_frames; 1525 __be64 rx_bcast_bytes; 1526 __be64 rx_bcast_frames; 1527 __be64 rx_mcast_bytes; 1528 __be64 rx_mcast_frames; 1529 __be64 rx_ucast_bytes; 1530 __be64 rx_ucast_frames; 1531 __be64 rx_err_frames; 1532 } vf; 1533 } u; 1534 }; 1535 1536 #define S_FW_VI_STATS_CMD_VIID 0 1537 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 1538 1539 #define S_FW_VI_STATS_CMD_NSTATS 12 1540 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 1541 1542 #define S_FW_VI_STATS_CMD_IX 0 1543 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 1544 1545 /* old 16-bit port capabilities bitmap */ 1546 enum fw_port_cap { 1547 FW_PORT_CAP_SPEED_100M = 0x0001, 1548 FW_PORT_CAP_SPEED_1G = 0x0002, 1549 FW_PORT_CAP_SPEED_25G = 0x0004, 1550 FW_PORT_CAP_SPEED_10G = 0x0008, 1551 FW_PORT_CAP_SPEED_40G = 0x0010, 1552 FW_PORT_CAP_SPEED_100G = 0x0020, 1553 FW_PORT_CAP_FC_RX = 0x0040, 1554 FW_PORT_CAP_FC_TX = 0x0080, 1555 FW_PORT_CAP_ANEG = 0x0100, 1556 FW_PORT_CAP_MDIX = 0x0200, 1557 FW_PORT_CAP_MDIAUTO = 0x0400, 1558 FW_PORT_CAP_FEC_RS = 0x0800, 1559 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 1560 FW_PORT_CAP_FEC_RESERVED = 0x2000, 1561 FW_PORT_CAP_802_3_PAUSE = 0x4000, 1562 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 1563 }; 1564 1565 #define S_FW_PORT_CAP_SPEED 0 1566 #define M_FW_PORT_CAP_SPEED 0x3f 1567 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 1568 #define G_FW_PORT_CAP_SPEED(x) \ 1569 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 1570 1571 enum fw_port_mdi { 1572 FW_PORT_CAP_MDI_AUTO, 1573 }; 1574 1575 #define S_FW_PORT_CAP_MDI 9 1576 #define M_FW_PORT_CAP_MDI 3 1577 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 1578 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 1579 1580 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 1581 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 1582 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 1583 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 1584 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 1585 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 1586 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 1587 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 1588 #define FW_PORT_CAP32_FC_RX 0x00010000UL 1589 #define FW_PORT_CAP32_FC_TX 0x00020000UL 1590 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 1591 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 1592 #define FW_PORT_CAP32_ANEG 0x00100000UL 1593 #define FW_PORT_CAP32_MDIX 0x00200000UL 1594 #define FW_PORT_CAP32_MDIAUTO 0x00400000UL 1595 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 1596 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 1597 1598 #define S_FW_PORT_CAP32_SPEED 0 1599 #define M_FW_PORT_CAP32_SPEED 0xfff 1600 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 1601 #define G_FW_PORT_CAP32_SPEED(x) \ 1602 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 1603 1604 enum fw_port_mdi32 { 1605 FW_PORT_CAP32_MDI_AUTO, 1606 }; 1607 1608 #define S_FW_PORT_CAP32_MDI 21 1609 #define M_FW_PORT_CAP32_MDI 3 1610 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 1611 #define G_FW_PORT_CAP32_MDI(x) \ 1612 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 1613 1614 enum fw_port_action { 1615 FW_PORT_ACTION_L1_CFG = 0x0001, 1616 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 1617 FW_PORT_ACTION_L1_CFG32 = 0x0009, 1618 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 1619 }; 1620 1621 struct fw_port_cmd { 1622 __be32 op_to_portid; 1623 __be32 action_to_len16; 1624 union fw_port { 1625 struct fw_port_l1cfg { 1626 __be32 rcap; 1627 __be32 r; 1628 } l1cfg; 1629 struct fw_port_l2cfg { 1630 __u8 ctlbf; 1631 __u8 ovlan3_to_ivlan0; 1632 __be16 ivlantype; 1633 __be16 txipg_force_pinfo; 1634 __be16 mtu; 1635 __be16 ovlan0mask; 1636 __be16 ovlan0type; 1637 __be16 ovlan1mask; 1638 __be16 ovlan1type; 1639 __be16 ovlan2mask; 1640 __be16 ovlan2type; 1641 __be16 ovlan3mask; 1642 __be16 ovlan3type; 1643 } l2cfg; 1644 struct fw_port_info { 1645 __be32 lstatus_to_modtype; 1646 __be16 pcap; 1647 __be16 acap; 1648 __be16 mtu; 1649 __u8 cbllen; 1650 __u8 auxlinfo; 1651 __u8 dcbxdis_pkd; 1652 __u8 r8_lo; 1653 __be16 lpacap; 1654 __be64 r9; 1655 } info; 1656 struct fw_port_diags { 1657 __u8 diagop; 1658 __u8 r[3]; 1659 __be32 diagval; 1660 } diags; 1661 union fw_port_dcb { 1662 struct fw_port_dcb_pgid { 1663 __u8 type; 1664 __u8 apply_pkd; 1665 __u8 r10_lo[2]; 1666 __be32 pgid; 1667 __be64 r11; 1668 } pgid; 1669 struct fw_port_dcb_pgrate { 1670 __u8 type; 1671 __u8 apply_pkd; 1672 __u8 r10_lo[5]; 1673 __u8 num_tcs_supported; 1674 __u8 pgrate[8]; 1675 __u8 tsa[8]; 1676 } pgrate; 1677 struct fw_port_dcb_priorate { 1678 __u8 type; 1679 __u8 apply_pkd; 1680 __u8 r10_lo[6]; 1681 __u8 strict_priorate[8]; 1682 } priorate; 1683 struct fw_port_dcb_pfc { 1684 __u8 type; 1685 __u8 pfcen; 1686 __u8 r10[5]; 1687 __u8 max_pfc_tcs; 1688 __be64 r11; 1689 } pfc; 1690 struct fw_port_app_priority { 1691 __u8 type; 1692 __u8 r10[2]; 1693 __u8 idx; 1694 __u8 user_prio_map; 1695 __u8 sel_field; 1696 __be16 protocolid; 1697 __be64 r12; 1698 } app_priority; 1699 struct fw_port_dcb_control { 1700 __u8 type; 1701 __u8 all_syncd_pkd; 1702 __be16 dcb_version_to_app_state; 1703 __be32 r11; 1704 __be64 r12; 1705 } control; 1706 } dcb; 1707 struct fw_port_l1cfg32 { 1708 __be32 rcap32; 1709 __be32 r; 1710 } l1cfg32; 1711 struct fw_port_info32 { 1712 __be32 lstatus32_to_cbllen32; 1713 __be32 auxlinfo32_mtu32; 1714 __be32 linkattr32; 1715 __be32 pcaps32; 1716 __be32 acaps32; 1717 __be32 lpacaps32; 1718 } info32; 1719 } u; 1720 }; 1721 1722 #define S_FW_PORT_CMD_PORTID 0 1723 #define M_FW_PORT_CMD_PORTID 0xf 1724 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 1725 #define G_FW_PORT_CMD_PORTID(x) \ 1726 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 1727 1728 #define S_FW_PORT_CMD_ACTION 16 1729 #define M_FW_PORT_CMD_ACTION 0xffff 1730 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 1731 #define G_FW_PORT_CMD_ACTION(x) \ 1732 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 1733 1734 #define S_FW_PORT_CMD_LSTATUS 31 1735 #define M_FW_PORT_CMD_LSTATUS 0x1 1736 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 1737 #define G_FW_PORT_CMD_LSTATUS(x) \ 1738 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 1739 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 1740 1741 #define S_FW_PORT_CMD_LSPEED 24 1742 #define M_FW_PORT_CMD_LSPEED 0x3f 1743 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 1744 #define G_FW_PORT_CMD_LSPEED(x) \ 1745 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 1746 1747 #define S_FW_PORT_CMD_TXPAUSE 23 1748 #define M_FW_PORT_CMD_TXPAUSE 0x1 1749 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 1750 #define G_FW_PORT_CMD_TXPAUSE(x) \ 1751 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 1752 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 1753 1754 #define S_FW_PORT_CMD_RXPAUSE 22 1755 #define M_FW_PORT_CMD_RXPAUSE 0x1 1756 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 1757 #define G_FW_PORT_CMD_RXPAUSE(x) \ 1758 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 1759 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 1760 1761 #define S_FW_PORT_CMD_MDIOCAP 21 1762 #define M_FW_PORT_CMD_MDIOCAP 0x1 1763 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 1764 #define G_FW_PORT_CMD_MDIOCAP(x) \ 1765 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 1766 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 1767 1768 #define S_FW_PORT_CMD_MDIOADDR 16 1769 #define M_FW_PORT_CMD_MDIOADDR 0x1f 1770 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 1771 #define G_FW_PORT_CMD_MDIOADDR(x) \ 1772 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 1773 1774 #define S_FW_PORT_CMD_PTYPE 8 1775 #define M_FW_PORT_CMD_PTYPE 0x1f 1776 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 1777 #define G_FW_PORT_CMD_PTYPE(x) \ 1778 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 1779 1780 #define S_FW_PORT_CMD_LINKDNRC 5 1781 #define M_FW_PORT_CMD_LINKDNRC 0x7 1782 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 1783 #define G_FW_PORT_CMD_LINKDNRC(x) \ 1784 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 1785 1786 #define S_FW_PORT_CMD_MODTYPE 0 1787 #define M_FW_PORT_CMD_MODTYPE 0x1f 1788 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 1789 #define G_FW_PORT_CMD_MODTYPE(x) \ 1790 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 1791 1792 #define S_FW_PORT_CMD_LSTATUS32 31 1793 #define M_FW_PORT_CMD_LSTATUS32 0x1 1794 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 1795 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 1796 1797 #define S_FW_PORT_CMD_LINKDNRC32 28 1798 #define M_FW_PORT_CMD_LINKDNRC32 0x7 1799 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 1800 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 1801 1802 #define S_FW_PORT_CMD_MDIOCAP32 26 1803 #define M_FW_PORT_CMD_MDIOCAP32 0x1 1804 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 1805 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 1806 1807 #define S_FW_PORT_CMD_MDIOADDR32 21 1808 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 1809 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 1810 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 1811 1812 #define S_FW_PORT_CMD_PORTTYPE32 13 1813 #define M_FW_PORT_CMD_PORTTYPE32 0xff 1814 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 1815 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 1816 1817 #define S_FW_PORT_CMD_MODTYPE32 8 1818 #define M_FW_PORT_CMD_MODTYPE32 0x1f 1819 #define G_FW_PORT_CMD_MODTYPE32(x) \ 1820 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 1821 1822 /* 1823 * These are configured into the VPD and hence tools that generate 1824 * VPD may use this enumeration. 1825 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 1826 * 1827 * REMEMBER: 1828 * Update the Common Code t4_hw.c:t4_get_port_type_description() 1829 * with any new Firmware Port Technology Types! 1830 */ 1831 enum fw_port_type { 1832 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 1833 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 1834 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 1835 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 1836 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 1837 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 1838 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 1839 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 1840 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 1841 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 1842 FW_PORT_TYPE_BP_AP = 10, 1843 /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 1844 FW_PORT_TYPE_BP4_AP = 11, 1845 /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 1846 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 1847 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 1848 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 1849 FW_PORT_TYPE_BP40_BA = 15, 1850 /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 1851 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/25G, Backplane */ 1852 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 1853 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G Spider cable */ 1854 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 1855 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 1856 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 1857 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 1858 }; 1859 1860 /* These are read from module's EEPROM and determined once the 1861 * module is inserted. 1862 */ 1863 enum fw_port_module_type { 1864 FW_PORT_MOD_TYPE_NA = 0x0, 1865 FW_PORT_MOD_TYPE_LR = 0x1, 1866 FW_PORT_MOD_TYPE_SR = 0x2, 1867 FW_PORT_MOD_TYPE_ER = 0x3, 1868 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 1869 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 1870 FW_PORT_MOD_TYPE_LRM = 0x6, 1871 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 1872 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 1873 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 1874 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 1875 }; 1876 1877 /* used by FW and tools may use this to generate VPD */ 1878 enum fw_port_mod_sub_type { 1879 FW_PORT_MOD_SUB_TYPE_NA, 1880 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1, 1881 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2, 1882 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3, 1883 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4, 1884 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5, 1885 FW_PORT_MOD_SUB_TYPE_BCM5482 = 0x6, 1886 FW_PORT_MOD_SUB_TYPE_BCM84856 = 0x7, 1887 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8, 1888 1889 /* 1890 * The following will never been in the VPD. They are TWINAX cable 1891 * lengths decoded from SFP+ module i2c PROMs. These should almost 1892 * certainly go somewhere else ... 1893 */ 1894 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9, 1895 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA, 1896 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB, 1897 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC, 1898 }; 1899 1900 /* link down reason codes (3b) */ 1901 enum fw_port_link_dn_rc { 1902 FW_PORT_LINK_DN_RC_NONE, 1903 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 1904 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 1905 FW_PORT_LINK_DN_RESERVED3, 1906 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 1907 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 1908 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 1909 FW_PORT_LINK_DN_RESERVED7 1910 }; 1911 1912 /* port stats */ 1913 #define FW_NUM_PORT_STATS 50 1914 #define FW_NUM_PORT_TX_STATS 23 1915 #define FW_NUM_PORT_RX_STATS 27 1916 1917 enum fw_port_stats_tx_index { 1918 FW_STAT_TX_PORT_BYTES_IX, 1919 FW_STAT_TX_PORT_FRAMES_IX, 1920 FW_STAT_TX_PORT_BCAST_IX, 1921 FW_STAT_TX_PORT_MCAST_IX, 1922 FW_STAT_TX_PORT_UCAST_IX, 1923 FW_STAT_TX_PORT_ERROR_IX, 1924 FW_STAT_TX_PORT_64B_IX, 1925 FW_STAT_TX_PORT_65B_127B_IX, 1926 FW_STAT_TX_PORT_128B_255B_IX, 1927 FW_STAT_TX_PORT_256B_511B_IX, 1928 FW_STAT_TX_PORT_512B_1023B_IX, 1929 FW_STAT_TX_PORT_1024B_1518B_IX, 1930 FW_STAT_TX_PORT_1519B_MAX_IX, 1931 FW_STAT_TX_PORT_DROP_IX, 1932 FW_STAT_TX_PORT_PAUSE_IX, 1933 FW_STAT_TX_PORT_PPP0_IX, 1934 FW_STAT_TX_PORT_PPP1_IX, 1935 FW_STAT_TX_PORT_PPP2_IX, 1936 FW_STAT_TX_PORT_PPP3_IX, 1937 FW_STAT_TX_PORT_PPP4_IX, 1938 FW_STAT_TX_PORT_PPP5_IX, 1939 FW_STAT_TX_PORT_PPP6_IX, 1940 FW_STAT_TX_PORT_PPP7_IX 1941 }; 1942 1943 enum fw_port_stat_rx_index { 1944 FW_STAT_RX_PORT_BYTES_IX, 1945 FW_STAT_RX_PORT_FRAMES_IX, 1946 FW_STAT_RX_PORT_BCAST_IX, 1947 FW_STAT_RX_PORT_MCAST_IX, 1948 FW_STAT_RX_PORT_UCAST_IX, 1949 FW_STAT_RX_PORT_MTU_ERROR_IX, 1950 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 1951 FW_STAT_RX_PORT_CRC_ERROR_IX, 1952 FW_STAT_RX_PORT_LEN_ERROR_IX, 1953 FW_STAT_RX_PORT_SYM_ERROR_IX, 1954 FW_STAT_RX_PORT_64B_IX, 1955 FW_STAT_RX_PORT_65B_127B_IX, 1956 FW_STAT_RX_PORT_128B_255B_IX, 1957 FW_STAT_RX_PORT_256B_511B_IX, 1958 FW_STAT_RX_PORT_512B_1023B_IX, 1959 FW_STAT_RX_PORT_1024B_1518B_IX, 1960 FW_STAT_RX_PORT_1519B_MAX_IX, 1961 FW_STAT_RX_PORT_PAUSE_IX, 1962 FW_STAT_RX_PORT_PPP0_IX, 1963 FW_STAT_RX_PORT_PPP1_IX, 1964 FW_STAT_RX_PORT_PPP2_IX, 1965 FW_STAT_RX_PORT_PPP3_IX, 1966 FW_STAT_RX_PORT_PPP4_IX, 1967 FW_STAT_RX_PORT_PPP5_IX, 1968 FW_STAT_RX_PORT_PPP6_IX, 1969 FW_STAT_RX_PORT_PPP7_IX, 1970 FW_STAT_RX_PORT_LESS_64B_IX 1971 }; 1972 1973 struct fw_port_stats_cmd { 1974 __be32 op_to_portid; 1975 __be32 retval_len16; 1976 union fw_port_stats { 1977 struct fw_port_stats_ctl { 1978 __u8 nstats_bg_bm; 1979 __u8 tx_ix; 1980 __be16 r6; 1981 __be32 r7; 1982 __be64 stat0; 1983 __be64 stat1; 1984 __be64 stat2; 1985 __be64 stat3; 1986 __be64 stat4; 1987 __be64 stat5; 1988 } ctl; 1989 struct fw_port_stats_all { 1990 __be64 tx_bytes; 1991 __be64 tx_frames; 1992 __be64 tx_bcast; 1993 __be64 tx_mcast; 1994 __be64 tx_ucast; 1995 __be64 tx_error; 1996 __be64 tx_64b; 1997 __be64 tx_65b_127b; 1998 __be64 tx_128b_255b; 1999 __be64 tx_256b_511b; 2000 __be64 tx_512b_1023b; 2001 __be64 tx_1024b_1518b; 2002 __be64 tx_1519b_max; 2003 __be64 tx_drop; 2004 __be64 tx_pause; 2005 __be64 tx_ppp0; 2006 __be64 tx_ppp1; 2007 __be64 tx_ppp2; 2008 __be64 tx_ppp3; 2009 __be64 tx_ppp4; 2010 __be64 tx_ppp5; 2011 __be64 tx_ppp6; 2012 __be64 tx_ppp7; 2013 __be64 rx_bytes; 2014 __be64 rx_frames; 2015 __be64 rx_bcast; 2016 __be64 rx_mcast; 2017 __be64 rx_ucast; 2018 __be64 rx_mtu_error; 2019 __be64 rx_mtu_crc_error; 2020 __be64 rx_crc_error; 2021 __be64 rx_len_error; 2022 __be64 rx_sym_error; 2023 __be64 rx_64b; 2024 __be64 rx_65b_127b; 2025 __be64 rx_128b_255b; 2026 __be64 rx_256b_511b; 2027 __be64 rx_512b_1023b; 2028 __be64 rx_1024b_1518b; 2029 __be64 rx_1519b_max; 2030 __be64 rx_pause; 2031 __be64 rx_ppp0; 2032 __be64 rx_ppp1; 2033 __be64 rx_ppp2; 2034 __be64 rx_ppp3; 2035 __be64 rx_ppp4; 2036 __be64 rx_ppp5; 2037 __be64 rx_ppp6; 2038 __be64 rx_ppp7; 2039 __be64 rx_less_64b; 2040 __be64 rx_bg_drop; 2041 __be64 rx_bg_trunc; 2042 } all; 2043 } u; 2044 }; 2045 2046 struct fw_rss_ind_tbl_cmd { 2047 __be32 op_to_viid; 2048 __be32 retval_len16; 2049 __be16 niqid; 2050 __be16 startidx; 2051 __be32 r3; 2052 __be32 iq0_to_iq2; 2053 __be32 iq3_to_iq5; 2054 __be32 iq6_to_iq8; 2055 __be32 iq9_to_iq11; 2056 __be32 iq12_to_iq14; 2057 __be32 iq15_to_iq17; 2058 __be32 iq18_to_iq20; 2059 __be32 iq21_to_iq23; 2060 __be32 iq24_to_iq26; 2061 __be32 iq27_to_iq29; 2062 __be32 iq30_iq31; 2063 __be32 r15_lo; 2064 }; 2065 2066 #define S_FW_RSS_IND_TBL_CMD_VIID 0 2067 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 2068 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 2069 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 2070 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 2071 2072 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 2073 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 2074 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 2075 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 2076 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 2077 2078 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 2079 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 2080 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 2081 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 2082 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 2083 2084 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 2085 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 2086 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 2087 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 2088 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 2089 2090 struct fw_rss_glb_config_cmd { 2091 __be32 op_to_write; 2092 __be32 retval_len16; 2093 union fw_rss_glb_config { 2094 struct fw_rss_glb_config_manual { 2095 __be32 mode_pkd; 2096 __be32 r3; 2097 __be64 r4; 2098 __be64 r5; 2099 } manual; 2100 struct fw_rss_glb_config_basicvirtual { 2101 __be32 mode_keymode; 2102 __be32 synmapen_to_hashtoeplitz; 2103 __be64 r8; 2104 __be64 r9; 2105 } basicvirtual; 2106 } u; 2107 }; 2108 2109 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 2110 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 2111 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 2112 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 2113 2114 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 2115 2116 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 2117 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 2118 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 2119 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 2120 2121 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 2122 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 2123 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 2124 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 2125 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 2126 2127 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 2128 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 2129 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 2130 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 2131 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 2132 2133 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 2134 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 2135 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 2136 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 2137 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 2138 2139 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 2140 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 2141 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 2142 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 2143 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 2144 2145 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 2146 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 2147 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 2148 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 2149 2150 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 2151 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 2152 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 2153 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 2154 2155 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 2156 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 2157 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 2158 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 2159 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 2160 2161 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 2162 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 2163 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 2164 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 2165 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 2166 2167 struct fw_rss_vi_config_cmd { 2168 __be32 op_to_viid; 2169 __be32 retval_len16; 2170 union fw_rss_vi_config { 2171 struct fw_rss_vi_config_manual { 2172 __be64 r3; 2173 __be64 r4; 2174 __be64 r5; 2175 } manual; 2176 struct fw_rss_vi_config_basicvirtual { 2177 __be32 r6; 2178 __be32 defaultq_to_udpen; 2179 __be64 r9; 2180 __be64 r10; 2181 } basicvirtual; 2182 } u; 2183 }; 2184 2185 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 2186 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 2187 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 2188 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 2189 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 2190 2191 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 2192 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 2193 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 2194 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 2195 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 2196 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 2197 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 2198 2199 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 2200 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 2201 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 2202 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 2203 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 2204 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 2205 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 2206 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 2207 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 2208 2209 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 2210 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 2211 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 2212 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 2213 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 2214 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 2215 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 2216 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 2217 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 2218 2219 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 2220 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 2221 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 2222 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 2223 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 2224 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 2225 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 2226 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 2227 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 2228 2229 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 2230 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 2231 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 2232 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 2233 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 2234 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 2235 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 2236 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 2237 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 2238 2239 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 2240 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 2241 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 2242 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 2243 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 2244 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 2245 2246 struct fw_clip_cmd { 2247 __be32 op_to_write; 2248 __be32 alloc_to_len16; 2249 __be64 ip_hi; 2250 __be64 ip_lo; 2251 __be32 r4[2]; 2252 }; 2253 2254 #define S_FW_CLIP_CMD_ALLOC 31 2255 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 2256 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 2257 2258 #define S_FW_CLIP_CMD_FREE 30 2259 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 2260 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 2261 2262 /****************************************************************************** 2263 * D E B U G C O M M A N D s 2264 ******************************************************/ 2265 2266 struct fw_debug_cmd { 2267 __be32 op_type; 2268 __be32 len16_pkd; 2269 union fw_debug { 2270 struct fw_debug_assert { 2271 __be32 fcid; 2272 __be32 line; 2273 __be32 x; 2274 __be32 y; 2275 __u8 filename_0_7[8]; 2276 __u8 filename_8_15[8]; 2277 __be64 r3; 2278 } assert; 2279 struct fw_debug_prt { 2280 __be16 dprtstridx; 2281 __be16 r3[3]; 2282 __be32 dprtstrparam0; 2283 __be32 dprtstrparam1; 2284 __be32 dprtstrparam2; 2285 __be32 dprtstrparam3; 2286 } prt; 2287 } u; 2288 }; 2289 2290 #define S_FW_DEBUG_CMD_TYPE 0 2291 #define M_FW_DEBUG_CMD_TYPE 0xff 2292 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 2293 #define G_FW_DEBUG_CMD_TYPE(x) \ 2294 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 2295 2296 /****************************************************************************** 2297 * P C I E F W R E G I S T E R 2298 **************************************/ 2299 2300 /* 2301 * Register definitions for the PCIE_FW register which the firmware uses 2302 * to retain status across RESETs. This register should be considered 2303 * as a READ-ONLY register for Host Software and only to be used to 2304 * track firmware initialization/error state, etc. 2305 */ 2306 #define S_PCIE_FW_ERR 31 2307 #define M_PCIE_FW_ERR 0x1 2308 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 2309 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 2310 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 2311 2312 #define S_PCIE_FW_INIT 30 2313 #define M_PCIE_FW_INIT 0x1 2314 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 2315 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 2316 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 2317 2318 #define S_PCIE_FW_HALT 29 2319 #define M_PCIE_FW_HALT 0x1 2320 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 2321 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 2322 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 2323 2324 #define S_PCIE_FW_EVAL 24 2325 #define M_PCIE_FW_EVAL 0x7 2326 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 2327 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 2328 2329 #define S_PCIE_FW_MASTER_VLD 15 2330 #define M_PCIE_FW_MASTER_VLD 0x1 2331 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 2332 #define G_PCIE_FW_MASTER_VLD(x) \ 2333 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 2334 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 2335 2336 #define S_PCIE_FW_MASTER 12 2337 #define M_PCIE_FW_MASTER 0x7 2338 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 2339 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 2340 2341 /****************************************************************************** 2342 * B I N A R Y H E A D E R F O R M A T 2343 **********************************************/ 2344 2345 /* 2346 * firmware binary header format 2347 */ 2348 struct fw_hdr { 2349 __u8 ver; 2350 __u8 chip; /* terminator chip family */ 2351 __be16 len512; /* bin length in units of 512-bytes */ 2352 __be32 fw_ver; /* firmware version */ 2353 __be32 tp_microcode_ver; /* tcp processor microcode version */ 2354 __u8 intfver_nic; 2355 __u8 intfver_vnic; 2356 __u8 intfver_ofld; 2357 __u8 intfver_ri; 2358 __u8 intfver_iscsipdu; 2359 __u8 intfver_iscsi; 2360 __u8 intfver_fcoepdu; 2361 __u8 intfver_fcoe; 2362 __u32 reserved2; 2363 __u32 reserved3; 2364 __u32 magic; /* runtime or bootstrap fw */ 2365 __be32 flags; 2366 __be32 reserved6[23]; 2367 }; 2368 2369 #define S_FW_HDR_FW_VER_MAJOR 24 2370 #define M_FW_HDR_FW_VER_MAJOR 0xff 2371 #define V_FW_HDR_FW_VER_MAJOR(x) \ 2372 ((x) << S_FW_HDR_FW_VER_MAJOR) 2373 #define G_FW_HDR_FW_VER_MAJOR(x) \ 2374 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 2375 2376 #define S_FW_HDR_FW_VER_MINOR 16 2377 #define M_FW_HDR_FW_VER_MINOR 0xff 2378 #define V_FW_HDR_FW_VER_MINOR(x) \ 2379 ((x) << S_FW_HDR_FW_VER_MINOR) 2380 #define G_FW_HDR_FW_VER_MINOR(x) \ 2381 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 2382 2383 #define S_FW_HDR_FW_VER_MICRO 8 2384 #define M_FW_HDR_FW_VER_MICRO 0xff 2385 #define V_FW_HDR_FW_VER_MICRO(x) \ 2386 ((x) << S_FW_HDR_FW_VER_MICRO) 2387 #define G_FW_HDR_FW_VER_MICRO(x) \ 2388 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 2389 2390 #define S_FW_HDR_FW_VER_BUILD 0 2391 #define M_FW_HDR_FW_VER_BUILD 0xff 2392 #define V_FW_HDR_FW_VER_BUILD(x) \ 2393 ((x) << S_FW_HDR_FW_VER_BUILD) 2394 #define G_FW_HDR_FW_VER_BUILD(x) \ 2395 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 2396 2397 #endif /* _T4FW_INTERFACE_H_ */ 2398