1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2019-2023 Broadcom All rights reserved. */ 3 4 #include <inttypes.h> 5 #include <stdbool.h> 6 7 #include <rte_bitmap.h> 8 #include <rte_byteorder.h> 9 #include <rte_malloc.h> 10 #include <rte_memory.h> 11 #include <rte_vect.h> 12 13 #include "bnxt.h" 14 #include "bnxt_cpr.h" 15 #include "bnxt_ring.h" 16 17 #include "bnxt_txq.h" 18 #include "bnxt_txr.h" 19 #include "bnxt_rxtx_vec_common.h" 20 21 /* 22 * RX Ring handling 23 */ 24 25 #define GET_OL_FLAGS(rss_flags, ol_index, errors, pi, ol_flags) \ 26 { \ 27 uint32_t tmp, of; \ 28 \ 29 of = _mm_extract_epi32((rss_flags), (pi)) | \ 30 rxr->ol_flags_table[_mm_extract_epi32((ol_index), (pi))]; \ 31 \ 32 tmp = _mm_extract_epi32((errors), (pi)); \ 33 if (tmp) \ 34 of |= rxr->ol_flags_err_table[tmp]; \ 35 (ol_flags) = of; \ 36 } 37 38 #define GET_DESC_FIELDS(rxcmp, rxcmp1, shuf_msk, ptype_idx, pi, ret) \ 39 { \ 40 uint32_t ptype; \ 41 __m128i r; \ 42 \ 43 /* Set mbuf pkt_len, data_len, and rss_hash fields. */ \ 44 r = _mm_shuffle_epi8((rxcmp), (shuf_msk)); \ 45 \ 46 /* Set packet type. */ \ 47 ptype = bnxt_ptype_table[_mm_extract_epi32((ptype_idx), (pi))]; \ 48 r = _mm_blend_epi16(r, _mm_set_epi32(0, 0, 0, ptype), 0x3); \ 49 \ 50 /* Set vlan_tci. */ \ 51 r = _mm_blend_epi16(r, _mm_slli_si128((rxcmp1), 6), 0x20); \ 52 (ret) = r; \ 53 } 54 55 static inline void 56 descs_to_mbufs(__m128i mm_rxcmp[4], __m128i mm_rxcmp1[4], 57 __m128i mbuf_init, const __m128i shuf_msk, 58 struct rte_mbuf **mbuf, struct bnxt_rx_ring_info *rxr) 59 { 60 const __m128i flags_type_mask = 61 _mm_set1_epi32(RX_PKT_CMPL_FLAGS_ITYPE_MASK); 62 const __m128i flags2_mask1 = 63 _mm_set1_epi32(CMPL_FLAGS2_VLAN_TUN_MSK); 64 const __m128i flags2_mask2 = 65 _mm_set1_epi32(RX_PKT_CMPL_FLAGS2_IP_TYPE); 66 const __m128i rss_mask = 67 _mm_set1_epi32(RX_PKT_CMPL_FLAGS_RSS_VALID); 68 __m128i t0, t1, flags_type, flags2, index, errors, rss_flags; 69 __m128i ptype_idx, is_tunnel; 70 uint32_t ol_flags; 71 72 /* Validate ptype table indexing at build time. */ 73 bnxt_check_ptype_constants(); 74 75 /* Compute packet type table indexes for four packets */ 76 t0 = _mm_unpacklo_epi32(mm_rxcmp[0], mm_rxcmp[1]); 77 t1 = _mm_unpacklo_epi32(mm_rxcmp[2], mm_rxcmp[3]); 78 flags_type = _mm_unpacklo_epi64(t0, t1); 79 ptype_idx = _mm_srli_epi32(_mm_and_si128(flags_type, flags_type_mask), 80 RX_PKT_CMPL_FLAGS_ITYPE_SFT - BNXT_PTYPE_TBL_TYPE_SFT); 81 82 t0 = _mm_unpacklo_epi32(mm_rxcmp1[0], mm_rxcmp1[1]); 83 t1 = _mm_unpacklo_epi32(mm_rxcmp1[2], mm_rxcmp1[3]); 84 flags2 = _mm_unpacklo_epi64(t0, t1); 85 86 ptype_idx = _mm_or_si128(ptype_idx, 87 _mm_srli_epi32(_mm_and_si128(flags2, flags2_mask1), 88 RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT - 89 BNXT_PTYPE_TBL_VLAN_SFT)); 90 ptype_idx = _mm_or_si128(ptype_idx, 91 _mm_srli_epi32(_mm_and_si128(flags2, flags2_mask2), 92 RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT - 93 BNXT_PTYPE_TBL_IP_VER_SFT)); 94 95 /* Extract RSS valid flags for four packets. */ 96 rss_flags = _mm_srli_epi32(_mm_and_si128(flags_type, rss_mask), 9); 97 98 /* Extract errors_v2 fields for four packets. */ 99 t0 = _mm_unpackhi_epi32(mm_rxcmp1[0], mm_rxcmp1[1]); 100 t1 = _mm_unpackhi_epi32(mm_rxcmp1[2], mm_rxcmp1[3]); 101 102 /* Compute ol_flags and checksum error indexes for four packets. */ 103 is_tunnel = _mm_and_si128(flags2, _mm_set1_epi32(4)); 104 is_tunnel = _mm_slli_epi32(is_tunnel, 3); 105 flags2 = _mm_and_si128(flags2, _mm_set1_epi32(0x1F)); 106 107 errors = _mm_srli_epi32(_mm_unpacklo_epi64(t0, t1), 4); 108 errors = _mm_and_si128(errors, _mm_set1_epi32(0xF)); 109 errors = _mm_and_si128(errors, flags2); 110 111 index = _mm_andnot_si128(errors, flags2); 112 errors = _mm_or_si128(errors, _mm_srli_epi32(is_tunnel, 1)); 113 index = _mm_or_si128(index, is_tunnel); 114 115 /* Update mbuf rearm_data for four packets. */ 116 GET_OL_FLAGS(rss_flags, index, errors, 0, ol_flags); 117 _mm_store_si128((void *)&mbuf[0]->rearm_data, 118 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 119 120 GET_OL_FLAGS(rss_flags, index, errors, 1, ol_flags); 121 _mm_store_si128((void *)&mbuf[1]->rearm_data, 122 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 123 124 GET_OL_FLAGS(rss_flags, index, errors, 2, ol_flags); 125 _mm_store_si128((void *)&mbuf[2]->rearm_data, 126 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 127 128 GET_OL_FLAGS(rss_flags, index, errors, 3, ol_flags); 129 _mm_store_si128((void *)&mbuf[3]->rearm_data, 130 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 131 132 /* Update mbuf rx_descriptor_fields1 for four packets. */ 133 GET_DESC_FIELDS(mm_rxcmp[0], mm_rxcmp1[0], shuf_msk, ptype_idx, 0, t0); 134 _mm_store_si128((void *)&mbuf[0]->rx_descriptor_fields1, t0); 135 136 GET_DESC_FIELDS(mm_rxcmp[1], mm_rxcmp1[1], shuf_msk, ptype_idx, 1, t0); 137 _mm_store_si128((void *)&mbuf[1]->rx_descriptor_fields1, t0); 138 139 GET_DESC_FIELDS(mm_rxcmp[2], mm_rxcmp1[2], shuf_msk, ptype_idx, 2, t0); 140 _mm_store_si128((void *)&mbuf[2]->rx_descriptor_fields1, t0); 141 142 GET_DESC_FIELDS(mm_rxcmp[3], mm_rxcmp1[3], shuf_msk, ptype_idx, 3, t0); 143 _mm_store_si128((void *)&mbuf[3]->rx_descriptor_fields1, t0); 144 } 145 146 static inline void 147 crx_descs_to_mbufs(__m128i mm_rxcmp[4], __m128i mm_rxcmp1[4], 148 __m128i mbuf_init, const __m128i shuf_msk, 149 struct rte_mbuf **mbuf, struct bnxt_rx_ring_info *rxr) 150 { 151 const __m128i flags_type_mask = 152 _mm_set1_epi32(RX_PKT_COMPRESS_CMPL_FLAGS_ITYPE_MASK); 153 const __m128i flags2_mask1 = 154 _mm_set1_epi32(CMPL_FLAGS2_VLAN_TUN_MSK_CRX); 155 const __m128i flags2_mask2 = 156 _mm_set1_epi32(RX_PKT_COMPRESS_CMPL_FLAGS_IP_TYPE); 157 const __m128i rss_mask = 158 _mm_set1_epi32(RX_PKT_COMPRESS_CMPL_FLAGS_RSS_VALID); 159 const __m128i cs_err_mask = 160 _mm_set1_epi32(RX_PKT_COMPRESS_CMPL_CS_ERROR_CALC_MASK | 161 BNXT_RXC_METADATA1_VLAN_VALID); 162 const __m128i crx_flags_mask = 163 _mm_set1_epi32(BNXT_CRX_CQE_CSUM_CALC_MASK); 164 const __m128i crx_tun_cs = 165 _mm_set1_epi32(BNXT_CRX_TUN_CS_CALC); 166 __m128i t0, t1, flags_type, flags, index, errors, rss_flags; 167 __m128i ptype_idx, is_tunnel; 168 uint32_t ol_flags; 169 __m128i cs_err; 170 __m128i t3, t4; 171 172 /* Validate ptype table indexing at build time. */ 173 bnxt_check_ptype_constants(); 174 175 /* Compute packet type table indexes for four packets */ 176 t0 = _mm_unpacklo_epi32(mm_rxcmp[0], mm_rxcmp[1]); 177 t3 = _mm_unpackhi_epi32(mm_rxcmp[0], mm_rxcmp[1]); 178 t1 = _mm_unpacklo_epi32(mm_rxcmp[2], mm_rxcmp[3]); 179 t4 = _mm_unpackhi_epi32(mm_rxcmp[2], mm_rxcmp[3]); 180 flags_type = _mm_unpacklo_epi64(t0, t1); 181 ptype_idx = _mm_srli_epi32(_mm_and_si128(flags_type, flags_type_mask), 182 RX_PKT_CMPL_FLAGS_ITYPE_SFT - BNXT_PTYPE_TBL_TYPE_SFT); 183 184 flags = _mm_unpacklo_epi64(t0, t1); 185 186 ptype_idx = _mm_or_si128(ptype_idx, 187 _mm_srli_epi32(_mm_and_si128(flags, flags2_mask1), 188 RX_PKT_CMPL_FLAGS2_META_FORMAT_SFT - 189 BNXT_PTYPE_TBL_VLAN_SFT)); 190 ptype_idx = _mm_or_si128(ptype_idx, 191 _mm_srli_epi32(_mm_and_si128(flags, flags2_mask2), 192 RX_PKT_CMPL_FLAGS2_IP_TYPE_SFT - 193 BNXT_PTYPE_TBL_IP_VER_SFT)); 194 195 /* Extract RSS valid flags for four packets. */ 196 rss_flags = _mm_srli_epi32(_mm_and_si128(flags, rss_mask), 9); 197 198 /* Extract cs_err fields for four packets. */ 199 cs_err = _mm_unpacklo_epi64(t3, t4); 200 cs_err = _mm_and_si128(cs_err, cs_err_mask); 201 flags = _mm_and_si128(cs_err, crx_flags_mask); 202 203 /* Compute ol_flags and checksum error indexes for four packets. */ 204 is_tunnel = _mm_and_si128(flags, crx_tun_cs); 205 is_tunnel = _mm_slli_epi32(is_tunnel, 0x20); 206 flags = _mm_or_si128(flags, is_tunnel); 207 208 flags = _mm_srli_si128(flags, 1); 209 210 errors = _mm_and_si128(cs_err, _mm_set1_epi32(0xF0)); 211 errors = _mm_and_si128(_mm_srli_epi32(errors, 4), flags); 212 213 index = _mm_andnot_si128(errors, flags); 214 /* reuse is_tunnel - just shift right one bit to index correctly. */ 215 errors = _mm_or_si128(errors, _mm_srli_epi32(is_tunnel, 1)); 216 index = _mm_or_si128(index, is_tunnel); 217 218 /* Update mbuf rearm_data for four packets. */ 219 GET_OL_FLAGS(rss_flags, index, errors, 0, ol_flags); 220 _mm_store_si128((void *)&mbuf[0]->rearm_data, 221 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 222 223 GET_OL_FLAGS(rss_flags, index, errors, 1, ol_flags); 224 _mm_store_si128((void *)&mbuf[1]->rearm_data, 225 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 226 227 GET_OL_FLAGS(rss_flags, index, errors, 2, ol_flags); 228 _mm_store_si128((void *)&mbuf[2]->rearm_data, 229 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 230 231 GET_OL_FLAGS(rss_flags, index, errors, 3, ol_flags); 232 _mm_store_si128((void *)&mbuf[3]->rearm_data, 233 _mm_or_si128(mbuf_init, _mm_set_epi64x(ol_flags, 0))); 234 235 /* Update mbuf rx_descriptor_fields1 for four packes. */ 236 GET_DESC_FIELDS(mm_rxcmp[0], mm_rxcmp1[0], shuf_msk, ptype_idx, 0, t0); 237 _mm_store_si128((void *)&mbuf[0]->rx_descriptor_fields1, t0); 238 239 GET_DESC_FIELDS(mm_rxcmp[1], mm_rxcmp1[1], shuf_msk, ptype_idx, 1, t0); 240 _mm_store_si128((void *)&mbuf[1]->rx_descriptor_fields1, t0); 241 242 GET_DESC_FIELDS(mm_rxcmp[2], mm_rxcmp1[2], shuf_msk, ptype_idx, 2, t0); 243 _mm_store_si128((void *)&mbuf[2]->rx_descriptor_fields1, t0); 244 245 GET_DESC_FIELDS(mm_rxcmp[3], mm_rxcmp1[3], shuf_msk, ptype_idx, 3, t0); 246 _mm_store_si128((void *)&mbuf[3]->rx_descriptor_fields1, t0); 247 } 248 249 static uint16_t 250 recv_burst_vec_sse(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 251 { 252 struct bnxt_rx_queue *rxq = rx_queue; 253 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer); 254 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 255 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 256 uint16_t cp_ring_size = cpr->cp_ring_struct->ring_size; 257 uint16_t rx_ring_size = rxr->rx_ring_struct->ring_size; 258 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring; 259 uint64_t valid, desc_valid_mask = ~0ULL; 260 const __m128i info3_v_mask = _mm_set1_epi32(CMPL_BASE_V); 261 uint32_t raw_cons = cpr->cp_raw_cons; 262 uint32_t cons, mbcons; 263 int nb_rx_pkts = 0; 264 const __m128i valid_target = 265 _mm_set1_epi32(!!(raw_cons & cp_ring_size)); 266 const __m128i shuf_msk = 267 _mm_set_epi8(15, 14, 13, 12, /* rss */ 268 0xFF, 0xFF, /* vlan_tci (zeroes) */ 269 3, 2, /* data_len */ 270 0xFF, 0xFF, 3, 2, /* pkt_len */ 271 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */ 272 int i; 273 274 /* If Rx Q was stopped return */ 275 if (unlikely(!rxq->rx_started)) 276 return 0; 277 278 if (rxq->rxrearm_nb >= rxq->rx_free_thresh) 279 bnxt_rxq_rearm(rxq, rxr); 280 281 cons = raw_cons & (cp_ring_size - 1); 282 mbcons = (raw_cons / 2) & (rx_ring_size - 1); 283 284 /* Prefetch first four descriptor pairs. */ 285 rte_prefetch0(&cp_desc_ring[cons]); 286 rte_prefetch0(&cp_desc_ring[cons + 4]); 287 288 /* Ensure that we do not go past the ends of the rings. */ 289 nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons, 290 (cp_ring_size - cons) / 2)); 291 /* 292 * If we are at the end of the ring, ensure that descriptors after the 293 * last valid entry are not treated as valid. Otherwise, force the 294 * maximum number of packets to receive to be a multiple of the per- 295 * loop count. 296 */ 297 if (nb_pkts < BNXT_RX_DESCS_PER_LOOP_VEC128) { 298 desc_valid_mask >>= 299 16 * (BNXT_RX_DESCS_PER_LOOP_VEC128 - nb_pkts); 300 } else { 301 nb_pkts = 302 RTE_ALIGN_FLOOR(nb_pkts, BNXT_RX_DESCS_PER_LOOP_VEC128); 303 } 304 305 /* Handle RX burst request */ 306 for (i = 0; i < nb_pkts; i += BNXT_RX_DESCS_PER_LOOP_VEC128, 307 cons += BNXT_RX_DESCS_PER_LOOP_VEC128 * 2, 308 mbcons += BNXT_RX_DESCS_PER_LOOP_VEC128) { 309 __m128i rxcmp1[BNXT_RX_DESCS_PER_LOOP_VEC128]; 310 __m128i rxcmp[BNXT_RX_DESCS_PER_LOOP_VEC128]; 311 __m128i tmp0, tmp1, info3_v; 312 uint32_t num_valid; 313 314 /* Copy four mbuf pointers to output array. */ 315 tmp0 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons]); 316 #ifdef RTE_ARCH_X86_64 317 tmp1 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons + 2]); 318 #endif 319 _mm_storeu_si128((void *)&rx_pkts[i], tmp0); 320 #ifdef RTE_ARCH_X86_64 321 _mm_storeu_si128((void *)&rx_pkts[i + 2], tmp1); 322 #endif 323 324 /* Prefetch four descriptor pairs for next iteration. */ 325 if (i + BNXT_RX_DESCS_PER_LOOP_VEC128 < nb_pkts) { 326 rte_prefetch0(&cp_desc_ring[cons + 8]); 327 rte_prefetch0(&cp_desc_ring[cons + 12]); 328 } 329 330 /* 331 * Load the four current descriptors into SSE registers in 332 * reverse order to ensure consistent state. 333 */ 334 rxcmp1[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 7]); 335 rte_compiler_barrier(); 336 rxcmp[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 6]); 337 338 rxcmp1[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 5]); 339 rte_compiler_barrier(); 340 rxcmp[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 4]); 341 342 tmp1 = _mm_unpackhi_epi32(rxcmp1[2], rxcmp1[3]); 343 344 rxcmp1[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 3]); 345 rte_compiler_barrier(); 346 rxcmp[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 2]); 347 348 rxcmp1[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 1]); 349 rte_compiler_barrier(); 350 rxcmp[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 0]); 351 352 tmp0 = _mm_unpackhi_epi32(rxcmp1[0], rxcmp1[1]); 353 354 /* Isolate descriptor valid flags. */ 355 info3_v = _mm_and_si128(_mm_unpacklo_epi64(tmp0, tmp1), 356 info3_v_mask); 357 info3_v = _mm_xor_si128(info3_v, valid_target); 358 359 /* 360 * Pack the 128-bit array of valid descriptor flags into 64 361 * bits and count the number of set bits in order to determine 362 * the number of valid descriptors. 363 */ 364 valid = _mm_cvtsi128_si64(_mm_packs_epi32(info3_v, info3_v)); 365 num_valid = rte_popcount64(valid & desc_valid_mask); 366 367 if (num_valid == 0) 368 break; 369 370 descs_to_mbufs(rxcmp, rxcmp1, mbuf_init, shuf_msk, &rx_pkts[nb_rx_pkts], 371 rxr); 372 nb_rx_pkts += num_valid; 373 374 if (num_valid < BNXT_RX_DESCS_PER_LOOP_VEC128) 375 break; 376 } 377 378 if (nb_rx_pkts) { 379 rxr->rx_raw_prod = RING_ADV(rxr->rx_raw_prod, nb_rx_pkts); 380 381 rxq->rxrearm_nb += nb_rx_pkts; 382 cpr->cp_raw_cons += 2 * nb_rx_pkts; 383 bnxt_db_cq(cpr); 384 } 385 386 return nb_rx_pkts; 387 } 388 389 static uint16_t 390 crx_burst_vec_sse(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 391 { 392 struct bnxt_rx_queue *rxq = rx_queue; 393 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer); 394 struct bnxt_cp_ring_info *cpr = rxq->cp_ring; 395 struct bnxt_rx_ring_info *rxr = rxq->rx_ring; 396 uint16_t cp_ring_size = cpr->cp_ring_struct->ring_size; 397 uint16_t rx_ring_size = rxr->rx_ring_struct->ring_size; 398 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring; 399 uint64_t valid, desc_valid_mask = ~0ULL; 400 const __m128i info3_v_mask = _mm_set1_epi32(CMPL_BASE_V); 401 uint32_t raw_cons = cpr->cp_raw_cons; 402 uint32_t cons, mbcons; 403 int nb_rx_pkts = 0; 404 const __m128i valid_target = 405 _mm_set1_epi32(!!(raw_cons & cp_ring_size)); 406 const __m128i shuf_msk = 407 _mm_set_epi8(7, 6, 5, 4, /* rss */ 408 0xFF, 0xFF, /* vlan_tci (zeroes) */ 409 3, 2, /* data_len */ 410 0xFF, 0xFF, 3, 2, /* pkt_len */ 411 0xFF, 0xFF, 0xFF, 0xFF); /* pkt_type (zeroes) */ 412 int i; 413 414 /* If Rx Q was stopped return */ 415 if (unlikely(!rxq->rx_started)) 416 return 0; 417 418 if (rxq->rxrearm_nb >= rxq->rx_free_thresh) 419 bnxt_rxq_rearm(rxq, rxr); 420 421 cons = raw_cons & (cp_ring_size - 1); 422 mbcons = raw_cons & (rx_ring_size - 1); 423 424 /* Prefetch first four descriptor pairs. */ 425 rte_prefetch0(&cp_desc_ring[cons]); 426 427 /* Ensure that we do not go past the ends of the rings. */ 428 nb_pkts = RTE_MIN(nb_pkts, RTE_MIN(rx_ring_size - mbcons, 429 cp_ring_size - cons)); 430 /* 431 * If we are at the end of the ring, ensure that descriptors after the 432 * last valid entry are not treated as valid. Otherwise, force the 433 * maximum number of packets to receive to be a multiple of the per- 434 * loop count. 435 */ 436 if (nb_pkts < BNXT_RX_DESCS_PER_LOOP_VEC128) { 437 desc_valid_mask >>= 438 16 * (BNXT_RX_DESCS_PER_LOOP_VEC128 - nb_pkts); 439 } else { 440 nb_pkts = 441 RTE_ALIGN_FLOOR(nb_pkts, BNXT_RX_DESCS_PER_LOOP_VEC128); 442 } 443 444 /* Handle RX burst request */ 445 for (i = 0; i < nb_pkts; i += BNXT_RX_DESCS_PER_LOOP_VEC128, 446 cons += BNXT_RX_DESCS_PER_LOOP_VEC128, 447 mbcons += BNXT_RX_DESCS_PER_LOOP_VEC128) { 448 __m128i rxcmp1[BNXT_RX_DESCS_PER_LOOP_VEC128]; 449 __m128i rxcmp[BNXT_RX_DESCS_PER_LOOP_VEC128]; 450 __m128i tmp0, tmp1, info3_v; 451 uint32_t num_valid; 452 453 /* Copy four mbuf pointers to output array. */ 454 tmp0 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons]); 455 #ifdef RTE_ARCH_X86_64 456 tmp1 = _mm_loadu_si128((void *)&rxr->rx_buf_ring[mbcons + 2]); 457 #endif 458 _mm_storeu_si128((void *)&rx_pkts[i], tmp0); 459 #ifdef RTE_ARCH_X86_64 460 _mm_storeu_si128((void *)&rx_pkts[i + 2], tmp1); 461 #endif 462 463 /* Prefetch four descriptor pairs for next iteration. */ 464 if (i + BNXT_RX_DESCS_PER_LOOP_VEC128 < nb_pkts) 465 rte_prefetch0(&cp_desc_ring[cons + 4]); 466 467 /* 468 * Load the four current descriptors into SSE registers in 469 * reverse order to ensure consistent state. 470 */ 471 rxcmp[3] = _mm_load_si128((void *)&cp_desc_ring[cons + 3]); 472 rte_compiler_barrier(); 473 rxcmp[2] = _mm_load_si128((void *)&cp_desc_ring[cons + 2]); 474 rte_compiler_barrier(); 475 rxcmp[1] = _mm_load_si128((void *)&cp_desc_ring[cons + 1]); 476 rte_compiler_barrier(); 477 rxcmp[0] = _mm_load_si128((void *)&cp_desc_ring[cons + 0]); 478 479 tmp1 = _mm_unpackhi_epi32(rxcmp[2], rxcmp[3]); 480 tmp0 = _mm_unpackhi_epi32(rxcmp[0], rxcmp[1]); 481 482 /* Isolate descriptor valid flags. */ 483 info3_v = _mm_and_si128(_mm_unpacklo_epi64(tmp0, tmp1), 484 info3_v_mask); 485 info3_v = _mm_xor_si128(info3_v, valid_target); 486 487 /* 488 * Pack the 128-bit array of valid descriptor flags into 64 489 * bits and count the number of set bits in order to determine 490 * the number of valid descriptors. 491 */ 492 valid = _mm_cvtsi128_si64(_mm_packs_epi32(info3_v, info3_v)); 493 num_valid = rte_popcount64(valid & desc_valid_mask); 494 495 if (num_valid == 0) 496 break; 497 498 crx_descs_to_mbufs(rxcmp, rxcmp1, mbuf_init, shuf_msk, 499 &rx_pkts[nb_rx_pkts], rxr); 500 nb_rx_pkts += num_valid; 501 502 if (num_valid < BNXT_RX_DESCS_PER_LOOP_VEC128) 503 break; 504 } 505 506 if (nb_rx_pkts) { 507 rxr->rx_raw_prod = RING_ADV(rxr->rx_raw_prod, nb_rx_pkts); 508 509 rxq->rxrearm_nb += nb_rx_pkts; 510 cpr->cp_raw_cons += nb_rx_pkts; 511 bnxt_db_cq(cpr); 512 } 513 514 return nb_rx_pkts; 515 } 516 517 uint16_t 518 bnxt_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 519 { 520 uint16_t cnt = 0; 521 522 while (nb_pkts > RTE_BNXT_MAX_RX_BURST) { 523 uint16_t burst; 524 525 burst = recv_burst_vec_sse(rx_queue, rx_pkts + cnt, 526 RTE_BNXT_MAX_RX_BURST); 527 528 cnt += burst; 529 nb_pkts -= burst; 530 531 if (burst < RTE_BNXT_MAX_RX_BURST) 532 return cnt; 533 } 534 535 return cnt + recv_burst_vec_sse(rx_queue, rx_pkts + cnt, nb_pkts); 536 } 537 538 uint16_t 539 bnxt_crx_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 540 { 541 uint16_t cnt = 0; 542 543 while (nb_pkts > RTE_BNXT_MAX_RX_BURST) { 544 uint16_t burst; 545 546 burst = crx_burst_vec_sse(rx_queue, rx_pkts + cnt, 547 RTE_BNXT_MAX_RX_BURST); 548 549 cnt += burst; 550 nb_pkts -= burst; 551 552 if (burst < RTE_BNXT_MAX_RX_BURST) 553 return cnt; 554 } 555 556 return cnt + crx_burst_vec_sse(rx_queue, rx_pkts + cnt, nb_pkts); 557 } 558 559 static void 560 bnxt_handle_tx_cp_vec(struct bnxt_tx_queue *txq) 561 { 562 struct bnxt_cp_ring_info *cpr = txq->cp_ring; 563 uint32_t raw_cons = cpr->cp_raw_cons; 564 uint32_t cons; 565 uint32_t nb_tx_pkts = 0; 566 struct tx_cmpl *txcmp; 567 struct cmpl_base *cp_desc_ring = cpr->cp_desc_ring; 568 struct bnxt_ring *cp_ring_struct = cpr->cp_ring_struct; 569 uint32_t ring_mask = cp_ring_struct->ring_mask; 570 571 do { 572 cons = RING_CMPL(ring_mask, raw_cons); 573 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons]; 574 575 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) 576 break; 577 578 if (likely(CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2)) 579 nb_tx_pkts += txcmp->opaque; 580 else 581 RTE_LOG_DP(ERR, BNXT, 582 "Unhandled CMP type %02x\n", 583 CMP_TYPE(txcmp)); 584 raw_cons = NEXT_RAW_CMP(raw_cons); 585 } while (nb_tx_pkts < ring_mask); 586 587 if (nb_tx_pkts) { 588 if (txq->offloads & RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) 589 bnxt_tx_cmp_vec_fast(txq, nb_tx_pkts); 590 else 591 bnxt_tx_cmp_vec(txq, nb_tx_pkts); 592 cpr->cp_raw_cons = raw_cons; 593 bnxt_db_cq(cpr); 594 } 595 } 596 597 static inline void 598 bnxt_xmit_one(struct rte_mbuf *mbuf, struct tx_bd_long *txbd, 599 struct rte_mbuf **tx_buf) 600 { 601 __m128i desc; 602 603 *tx_buf = mbuf; 604 605 desc = _mm_set_epi64x(mbuf->buf_iova + mbuf->data_off, 606 bnxt_xmit_flags_len(mbuf->data_len, 607 TX_BD_FLAGS_NOCMPL)); 608 desc = _mm_blend_epi16(desc, _mm_set_epi16(0, 0, 0, 0, 0, 0, 609 mbuf->data_len, 0), 0x02); 610 _mm_store_si128((void *)txbd, desc); 611 } 612 613 static uint16_t 614 bnxt_xmit_fixed_burst_vec(struct bnxt_tx_queue *txq, struct rte_mbuf **tx_pkts, 615 uint16_t nb_pkts) 616 { 617 struct bnxt_tx_ring_info *txr = txq->tx_ring; 618 uint16_t tx_prod, tx_raw_prod = txr->tx_raw_prod; 619 struct tx_bd_long *txbd; 620 struct rte_mbuf **tx_buf; 621 uint16_t to_send; 622 623 tx_prod = RING_IDX(txr->tx_ring_struct, tx_raw_prod); 624 txbd = &txr->tx_desc_ring[tx_prod]; 625 tx_buf = &txr->tx_buf_ring[tx_prod]; 626 627 /* Prefetch next transmit buffer descriptors. */ 628 rte_prefetch0(txbd); 629 rte_prefetch0(txbd + 3); 630 631 nb_pkts = RTE_MIN(nb_pkts, bnxt_tx_avail(txq)); 632 633 if (unlikely(nb_pkts == 0)) 634 return 0; 635 636 /* Handle TX burst request */ 637 to_send = nb_pkts; 638 while (to_send >= BNXT_TX_DESCS_PER_LOOP) { 639 /* Prefetch next transmit buffer descriptors. */ 640 rte_prefetch0(txbd + 4); 641 rte_prefetch0(txbd + 7); 642 643 bnxt_xmit_one(tx_pkts[0], txbd++, tx_buf++); 644 bnxt_xmit_one(tx_pkts[1], txbd++, tx_buf++); 645 bnxt_xmit_one(tx_pkts[2], txbd++, tx_buf++); 646 bnxt_xmit_one(tx_pkts[3], txbd++, tx_buf++); 647 648 to_send -= BNXT_TX_DESCS_PER_LOOP; 649 tx_pkts += BNXT_TX_DESCS_PER_LOOP; 650 } 651 652 while (to_send) { 653 bnxt_xmit_one(tx_pkts[0], txbd++, tx_buf++); 654 to_send--; 655 tx_pkts++; 656 } 657 658 /* Request a completion for the final packet of burst. */ 659 rte_compiler_barrier(); 660 txbd[-1].opaque = nb_pkts; 661 txbd[-1].flags_type &= ~TX_BD_LONG_FLAGS_NO_CMPL; 662 663 tx_raw_prod += nb_pkts; 664 bnxt_db_write(&txr->tx_db, tx_raw_prod); 665 666 txr->tx_raw_prod = tx_raw_prod; 667 668 return nb_pkts; 669 } 670 671 uint16_t 672 bnxt_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts, 673 uint16_t nb_pkts) 674 { 675 int nb_sent = 0; 676 struct bnxt_tx_queue *txq = tx_queue; 677 struct bnxt_tx_ring_info *txr = txq->tx_ring; 678 uint16_t ring_size = txr->tx_ring_struct->ring_size; 679 680 /* Tx queue was stopped; wait for it to be restarted */ 681 if (unlikely(!txq->tx_started)) { 682 PMD_DRV_LOG(DEBUG, "Tx q stopped;return\n"); 683 return 0; 684 } 685 686 /* Handle TX completions */ 687 if (bnxt_tx_bds_in_hw(txq) >= txq->tx_free_thresh) 688 bnxt_handle_tx_cp_vec(txq); 689 690 while (nb_pkts) { 691 uint16_t ret, num; 692 693 /* 694 * Ensure that no more than RTE_BNXT_MAX_TX_BURST packets 695 * are transmitted before the next completion. 696 */ 697 num = RTE_MIN(nb_pkts, RTE_BNXT_MAX_TX_BURST); 698 699 /* 700 * Ensure that a ring wrap does not occur within a call to 701 * bnxt_xmit_fixed_burst_vec(). 702 */ 703 num = RTE_MIN(num, ring_size - 704 (txr->tx_raw_prod & (ring_size - 1))); 705 ret = bnxt_xmit_fixed_burst_vec(txq, &tx_pkts[nb_sent], num); 706 nb_sent += ret; 707 nb_pkts -= ret; 708 if (ret < num) 709 break; 710 } 711 712 return nb_sent; 713 } 714 715 int __rte_cold 716 bnxt_rxq_vec_setup(struct bnxt_rx_queue *rxq) 717 { 718 return bnxt_rxq_vec_setup_common(rxq); 719 } 720