1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 15 #include "bnxt.h" 16 #include "bnxt_cpr.h" 17 #include "bnxt_filter.h" 18 #include "bnxt_hwrm.h" 19 #include "bnxt_irq.h" 20 #include "bnxt_ring.h" 21 #include "bnxt_rxq.h" 22 #include "bnxt_rxr.h" 23 #include "bnxt_stats.h" 24 #include "bnxt_txq.h" 25 #include "bnxt_txr.h" 26 #include "bnxt_vnic.h" 27 #include "hsi_struct_def_dpdk.h" 28 #include "bnxt_nvm_defs.h" 29 #include "bnxt_util.h" 30 31 #define DRV_MODULE_NAME "bnxt" 32 static const char bnxt_version[] = 33 "Broadcom NetXtreme driver " DRV_MODULE_NAME "\n"; 34 int bnxt_logtype_driver; 35 36 #define PCI_VENDOR_ID_BROADCOM 0x14E4 37 38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 41 #define BROADCOM_DEV_ID_57414_VF 0x16c1 42 #define BROADCOM_DEV_ID_57301 0x16c8 43 #define BROADCOM_DEV_ID_57302 0x16c9 44 #define BROADCOM_DEV_ID_57304_PF 0x16ca 45 #define BROADCOM_DEV_ID_57304_VF 0x16cb 46 #define BROADCOM_DEV_ID_57417_MF 0x16cc 47 #define BROADCOM_DEV_ID_NS2 0x16cd 48 #define BROADCOM_DEV_ID_57311 0x16ce 49 #define BROADCOM_DEV_ID_57312 0x16cf 50 #define BROADCOM_DEV_ID_57402 0x16d0 51 #define BROADCOM_DEV_ID_57404 0x16d1 52 #define BROADCOM_DEV_ID_57406_PF 0x16d2 53 #define BROADCOM_DEV_ID_57406_VF 0x16d3 54 #define BROADCOM_DEV_ID_57402_MF 0x16d4 55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 56 #define BROADCOM_DEV_ID_57412 0x16d6 57 #define BROADCOM_DEV_ID_57414 0x16d7 58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 61 #define BROADCOM_DEV_ID_57412_MF 0x16de 62 #define BROADCOM_DEV_ID_57314 0x16df 63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 68 #define BROADCOM_DEV_ID_57404_MF 0x16e7 69 #define BROADCOM_DEV_ID_57406_MF 0x16e8 70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 71 #define BROADCOM_DEV_ID_57407_MF 0x16ea 72 #define BROADCOM_DEV_ID_57414_MF 0x16ec 73 #define BROADCOM_DEV_ID_57416_MF 0x16ee 74 #define BROADCOM_DEV_ID_58802 0xd802 75 #define BROADCOM_DEV_ID_58804 0xd804 76 #define BROADCOM_DEV_ID_58808 0x16f0 77 #define BROADCOM_DEV_ID_58802_VF 0xd800 78 79 static const struct rte_pci_id bnxt_pci_id_map[] = { 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 122 { .vendor_id = 0, /* sentinel */ }, 123 }; 124 125 #define BNXT_ETH_RSS_SUPPORT ( \ 126 ETH_RSS_IPV4 | \ 127 ETH_RSS_NONFRAG_IPV4_TCP | \ 128 ETH_RSS_NONFRAG_IPV4_UDP | \ 129 ETH_RSS_IPV6 | \ 130 ETH_RSS_NONFRAG_IPV6_TCP | \ 131 ETH_RSS_NONFRAG_IPV6_UDP) 132 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 134 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 135 DEV_TX_OFFLOAD_TCP_CKSUM | \ 136 DEV_TX_OFFLOAD_UDP_CKSUM | \ 137 DEV_TX_OFFLOAD_TCP_TSO | \ 138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 143 DEV_TX_OFFLOAD_MULTI_SEGS) 144 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 146 DEV_RX_OFFLOAD_VLAN_STRIP | \ 147 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 148 DEV_RX_OFFLOAD_UDP_CKSUM | \ 149 DEV_RX_OFFLOAD_TCP_CKSUM | \ 150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 151 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 152 DEV_RX_OFFLOAD_CRC_STRIP | \ 153 DEV_RX_OFFLOAD_KEEP_CRC | \ 154 DEV_RX_OFFLOAD_TCP_LRO) 155 156 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 157 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 158 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 159 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 160 161 /***********************/ 162 163 /* 164 * High level utility functions 165 */ 166 167 static void bnxt_free_mem(struct bnxt *bp) 168 { 169 bnxt_free_filter_mem(bp); 170 bnxt_free_vnic_attributes(bp); 171 bnxt_free_vnic_mem(bp); 172 173 bnxt_free_stats(bp); 174 bnxt_free_tx_rings(bp); 175 bnxt_free_rx_rings(bp); 176 } 177 178 static int bnxt_alloc_mem(struct bnxt *bp) 179 { 180 int rc; 181 182 rc = bnxt_alloc_vnic_mem(bp); 183 if (rc) 184 goto alloc_mem_err; 185 186 rc = bnxt_alloc_vnic_attributes(bp); 187 if (rc) 188 goto alloc_mem_err; 189 190 rc = bnxt_alloc_filter_mem(bp); 191 if (rc) 192 goto alloc_mem_err; 193 194 return 0; 195 196 alloc_mem_err: 197 bnxt_free_mem(bp); 198 return rc; 199 } 200 201 static int bnxt_init_chip(struct bnxt *bp) 202 { 203 struct bnxt_rx_queue *rxq; 204 struct rte_eth_link new; 205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 207 uint32_t intr_vector = 0; 208 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 209 uint32_t vec = BNXT_MISC_VEC_ID; 210 unsigned int i, j; 211 int rc; 212 213 /* disable uio/vfio intr/eventfd mapping */ 214 rte_intr_disable(intr_handle); 215 216 if (bp->eth_dev->data->mtu > ETHER_MTU) { 217 bp->eth_dev->data->dev_conf.rxmode.offloads |= 218 DEV_RX_OFFLOAD_JUMBO_FRAME; 219 bp->flags |= BNXT_FLAG_JUMBO; 220 } else { 221 bp->eth_dev->data->dev_conf.rxmode.offloads &= 222 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 223 bp->flags &= ~BNXT_FLAG_JUMBO; 224 } 225 226 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 227 if (rc) { 228 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 229 goto err_out; 230 } 231 232 rc = bnxt_alloc_hwrm_rings(bp); 233 if (rc) { 234 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 235 goto err_out; 236 } 237 238 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 239 if (rc) { 240 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 241 goto err_out; 242 } 243 244 rc = bnxt_mq_rx_configure(bp); 245 if (rc) { 246 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 247 goto err_out; 248 } 249 250 /* VNIC configuration */ 251 for (i = 0; i < bp->nr_vnics; i++) { 252 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 253 254 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 255 if (rc) { 256 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 257 i, rc); 258 goto err_out; 259 } 260 261 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic); 262 if (rc) { 263 PMD_DRV_LOG(ERR, 264 "HWRM vnic %d ctx alloc failure rc: %x\n", 265 i, rc); 266 goto err_out; 267 } 268 269 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 270 if (rc) { 271 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 272 i, rc); 273 goto err_out; 274 } 275 276 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 277 if (rc) { 278 PMD_DRV_LOG(ERR, 279 "HWRM vnic %d filter failure rc: %x\n", 280 i, rc); 281 goto err_out; 282 } 283 284 for (j = 0; j < bp->rx_nr_rings; j++) { 285 rxq = bp->eth_dev->data->rx_queues[j]; 286 287 if (rxq->rx_deferred_start) 288 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 289 } 290 291 rc = bnxt_vnic_rss_configure(bp, vnic); 292 if (rc) { 293 PMD_DRV_LOG(ERR, 294 "HWRM vnic set RSS failure rc: %x\n", rc); 295 goto err_out; 296 } 297 298 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 299 300 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 301 DEV_RX_OFFLOAD_TCP_LRO) 302 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 303 else 304 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 305 } 306 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 307 if (rc) { 308 PMD_DRV_LOG(ERR, 309 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 310 goto err_out; 311 } 312 313 /* check and configure queue intr-vector mapping */ 314 if ((rte_intr_cap_multiple(intr_handle) || 315 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 316 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 317 intr_vector = bp->eth_dev->data->nb_rx_queues; 318 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 319 if (intr_vector > bp->rx_cp_nr_rings) { 320 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 321 bp->rx_cp_nr_rings); 322 return -ENOTSUP; 323 } 324 if (rte_intr_efd_enable(intr_handle, intr_vector)) 325 return -1; 326 } 327 328 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 329 intr_handle->intr_vec = 330 rte_zmalloc("intr_vec", 331 bp->eth_dev->data->nb_rx_queues * 332 sizeof(int), 0); 333 if (intr_handle->intr_vec == NULL) { 334 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 335 " intr_vec", bp->eth_dev->data->nb_rx_queues); 336 return -ENOMEM; 337 } 338 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 339 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 340 intr_handle->intr_vec, intr_handle->nb_efd, 341 intr_handle->max_intr); 342 } 343 344 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 345 queue_id++) { 346 intr_handle->intr_vec[queue_id] = vec; 347 if (vec < base + intr_handle->nb_efd - 1) 348 vec++; 349 } 350 351 /* enable uio/vfio intr/eventfd mapping */ 352 rte_intr_enable(intr_handle); 353 354 rc = bnxt_get_hwrm_link_config(bp, &new); 355 if (rc) { 356 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 357 goto err_out; 358 } 359 360 if (!bp->link_info.link_up) { 361 rc = bnxt_set_hwrm_link_config(bp, true); 362 if (rc) { 363 PMD_DRV_LOG(ERR, 364 "HWRM link config failure rc: %x\n", rc); 365 goto err_out; 366 } 367 } 368 bnxt_print_link_info(bp->eth_dev); 369 370 return 0; 371 372 err_out: 373 bnxt_free_all_hwrm_resources(bp); 374 375 /* Some of the error status returned by FW may not be from errno.h */ 376 if (rc > 0) 377 rc = -EIO; 378 379 return rc; 380 } 381 382 static int bnxt_shutdown_nic(struct bnxt *bp) 383 { 384 bnxt_free_all_hwrm_resources(bp); 385 bnxt_free_all_filters(bp); 386 bnxt_free_all_vnics(bp); 387 return 0; 388 } 389 390 static int bnxt_init_nic(struct bnxt *bp) 391 { 392 int rc; 393 394 rc = bnxt_init_ring_grps(bp); 395 if (rc) 396 return rc; 397 398 bnxt_init_vnics(bp); 399 bnxt_init_filters(bp); 400 401 return 0; 402 } 403 404 /* 405 * Device configuration and status function 406 */ 407 408 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 409 struct rte_eth_dev_info *dev_info) 410 { 411 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 412 uint16_t max_vnics, i, j, vpool, vrxq; 413 unsigned int max_rx_rings; 414 415 /* MAC Specifics */ 416 dev_info->max_mac_addrs = bp->max_l2_ctx; 417 dev_info->max_hash_mac_addrs = 0; 418 419 /* PF/VF specifics */ 420 if (BNXT_PF(bp)) 421 dev_info->max_vfs = bp->pdev->max_vfs; 422 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx); 423 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 424 dev_info->max_rx_queues = max_rx_rings; 425 dev_info->max_tx_queues = max_rx_rings; 426 dev_info->reta_size = bp->max_rsscos_ctx; 427 dev_info->hash_key_size = 40; 428 max_vnics = bp->max_vnics; 429 430 /* Fast path specifics */ 431 dev_info->min_rx_bufsize = 1; 432 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN 433 + VLAN_TAG_SIZE; 434 435 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 436 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 437 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 438 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 439 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 440 441 /* *INDENT-OFF* */ 442 dev_info->default_rxconf = (struct rte_eth_rxconf) { 443 .rx_thresh = { 444 .pthresh = 8, 445 .hthresh = 8, 446 .wthresh = 0, 447 }, 448 .rx_free_thresh = 32, 449 /* If no descriptors available, pkts are dropped by default */ 450 .rx_drop_en = 1, 451 }; 452 453 dev_info->default_txconf = (struct rte_eth_txconf) { 454 .tx_thresh = { 455 .pthresh = 32, 456 .hthresh = 0, 457 .wthresh = 0, 458 }, 459 .tx_free_thresh = 32, 460 .tx_rs_thresh = 32, 461 }; 462 eth_dev->data->dev_conf.intr_conf.lsc = 1; 463 464 eth_dev->data->dev_conf.intr_conf.rxq = 1; 465 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 466 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 467 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 468 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 469 470 /* *INDENT-ON* */ 471 472 /* 473 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 474 * need further investigation. 475 */ 476 477 /* VMDq resources */ 478 vpool = 64; /* ETH_64_POOLS */ 479 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 480 for (i = 0; i < 4; vpool >>= 1, i++) { 481 if (max_vnics > vpool) { 482 for (j = 0; j < 5; vrxq >>= 1, j++) { 483 if (dev_info->max_rx_queues > vrxq) { 484 if (vpool > vrxq) 485 vpool = vrxq; 486 goto found; 487 } 488 } 489 /* Not enough resources to support VMDq */ 490 break; 491 } 492 } 493 /* Not enough resources to support VMDq */ 494 vpool = 0; 495 vrxq = 0; 496 found: 497 dev_info->max_vmdq_pools = vpool; 498 dev_info->vmdq_queue_num = vrxq; 499 500 dev_info->vmdq_pool_base = 0; 501 dev_info->vmdq_queue_base = 0; 502 } 503 504 /* Configure the device based on the configuration provided */ 505 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 506 { 507 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 508 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 509 510 bp->rx_queues = (void *)eth_dev->data->rx_queues; 511 bp->tx_queues = (void *)eth_dev->data->tx_queues; 512 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 513 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 514 515 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 516 int rc; 517 518 rc = bnxt_hwrm_func_reserve_vf_resc(bp); 519 if (rc) { 520 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 521 return -ENOSPC; 522 } 523 524 /* legacy driver needs to get updated values */ 525 rc = bnxt_hwrm_func_qcaps(bp); 526 if (rc) { 527 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 528 return -ENOSPC; 529 } 530 } 531 532 /* Inherit new configurations */ 533 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 534 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 535 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 536 bp->max_cp_rings || 537 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 538 bp->max_stat_ctx || 539 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) { 540 PMD_DRV_LOG(ERR, 541 "Insufficient resources to support requested config\n"); 542 PMD_DRV_LOG(ERR, 543 "Num Queues Requested: Tx %d, Rx %d\n", 544 eth_dev->data->nb_tx_queues, 545 eth_dev->data->nb_rx_queues); 546 PMD_DRV_LOG(ERR, 547 "Res available: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d\n", 548 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 549 bp->max_stat_ctx, bp->max_ring_grps); 550 return -ENOSPC; 551 } 552 553 bp->rx_cp_nr_rings = bp->rx_nr_rings; 554 bp->tx_cp_nr_rings = bp->tx_nr_rings; 555 556 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 557 eth_dev->data->mtu = 558 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 559 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 560 BNXT_NUM_VLANS; 561 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 562 } 563 return 0; 564 } 565 566 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 567 { 568 struct rte_eth_link *link = ð_dev->data->dev_link; 569 570 if (link->link_status) 571 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 572 eth_dev->data->port_id, 573 (uint32_t)link->link_speed, 574 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 575 ("full-duplex") : ("half-duplex\n")); 576 else 577 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 578 eth_dev->data->port_id); 579 } 580 581 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev) 582 { 583 bnxt_print_link_info(eth_dev); 584 return 0; 585 } 586 587 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 588 { 589 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 590 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 591 int vlan_mask = 0; 592 int rc; 593 594 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 595 PMD_DRV_LOG(ERR, 596 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 597 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 598 } 599 bp->dev_stopped = 0; 600 601 rc = bnxt_init_chip(bp); 602 if (rc) 603 goto error; 604 605 bnxt_link_update_op(eth_dev, 1); 606 607 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 608 vlan_mask |= ETH_VLAN_FILTER_MASK; 609 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 610 vlan_mask |= ETH_VLAN_STRIP_MASK; 611 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 612 if (rc) 613 goto error; 614 615 bp->flags |= BNXT_FLAG_INIT_DONE; 616 return 0; 617 618 error: 619 bnxt_shutdown_nic(bp); 620 bnxt_free_tx_mbufs(bp); 621 bnxt_free_rx_mbufs(bp); 622 return rc; 623 } 624 625 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 626 { 627 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 628 int rc = 0; 629 630 if (!bp->link_info.link_up) 631 rc = bnxt_set_hwrm_link_config(bp, true); 632 if (!rc) 633 eth_dev->data->dev_link.link_status = 1; 634 635 bnxt_print_link_info(eth_dev); 636 return 0; 637 } 638 639 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 640 { 641 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 642 643 eth_dev->data->dev_link.link_status = 0; 644 bnxt_set_hwrm_link_config(bp, false); 645 bp->link_info.link_up = 0; 646 647 return 0; 648 } 649 650 /* Unload the driver, release resources */ 651 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 652 { 653 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 654 655 bp->flags &= ~BNXT_FLAG_INIT_DONE; 656 if (bp->eth_dev->data->dev_started) { 657 /* TBD: STOP HW queues DMA */ 658 eth_dev->data->dev_link.link_status = 0; 659 } 660 bnxt_set_hwrm_link_config(bp, false); 661 bnxt_hwrm_port_clr_stats(bp); 662 bnxt_free_tx_mbufs(bp); 663 bnxt_free_rx_mbufs(bp); 664 bnxt_shutdown_nic(bp); 665 bp->dev_stopped = 1; 666 } 667 668 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 669 { 670 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 671 672 if (bp->dev_stopped == 0) 673 bnxt_dev_stop_op(eth_dev); 674 675 bnxt_free_mem(bp); 676 if (eth_dev->data->mac_addrs != NULL) { 677 rte_free(eth_dev->data->mac_addrs); 678 eth_dev->data->mac_addrs = NULL; 679 } 680 if (bp->grp_info != NULL) { 681 rte_free(bp->grp_info); 682 bp->grp_info = NULL; 683 } 684 685 bnxt_dev_uninit(eth_dev); 686 } 687 688 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 689 uint32_t index) 690 { 691 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 692 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 693 struct bnxt_vnic_info *vnic; 694 struct bnxt_filter_info *filter, *temp_filter; 695 uint32_t pool = RTE_MIN(MAX_FF_POOLS, ETH_64_POOLS); 696 uint32_t i; 697 698 /* 699 * Loop through all VNICs from the specified filter flow pools to 700 * remove the corresponding MAC addr filter 701 */ 702 for (i = 0; i < pool; i++) { 703 if (!(pool_mask & (1ULL << i))) 704 continue; 705 706 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 707 filter = STAILQ_FIRST(&vnic->filter); 708 while (filter) { 709 temp_filter = STAILQ_NEXT(filter, next); 710 if (filter->mac_index == index) { 711 STAILQ_REMOVE(&vnic->filter, filter, 712 bnxt_filter_info, next); 713 bnxt_hwrm_clear_l2_filter(bp, filter); 714 filter->mac_index = INVALID_MAC_INDEX; 715 memset(&filter->l2_addr, 0, 716 ETHER_ADDR_LEN); 717 STAILQ_INSERT_TAIL( 718 &bp->free_filter_list, 719 filter, next); 720 } 721 filter = temp_filter; 722 } 723 } 724 } 725 } 726 727 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 728 struct ether_addr *mac_addr, 729 uint32_t index, uint32_t pool) 730 { 731 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 732 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]); 733 struct bnxt_filter_info *filter; 734 735 if (BNXT_VF(bp)) { 736 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 737 return -ENOTSUP; 738 } 739 740 if (!vnic) { 741 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 742 return -EINVAL; 743 } 744 /* Attach requested MAC address to the new l2_filter */ 745 STAILQ_FOREACH(filter, &vnic->filter, next) { 746 if (filter->mac_index == index) { 747 PMD_DRV_LOG(ERR, 748 "MAC addr already existed for pool %d\n", pool); 749 return 0; 750 } 751 } 752 filter = bnxt_alloc_filter(bp); 753 if (!filter) { 754 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 755 return -ENODEV; 756 } 757 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 758 filter->mac_index = index; 759 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN); 760 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 761 } 762 763 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 764 { 765 int rc = 0; 766 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 767 struct rte_eth_link new; 768 unsigned int cnt = BNXT_LINK_WAIT_CNT; 769 770 memset(&new, 0, sizeof(new)); 771 do { 772 /* Retrieve link info from hardware */ 773 rc = bnxt_get_hwrm_link_config(bp, &new); 774 if (rc) { 775 new.link_speed = ETH_LINK_SPEED_100M; 776 new.link_duplex = ETH_LINK_FULL_DUPLEX; 777 PMD_DRV_LOG(ERR, 778 "Failed to retrieve link rc = 0x%x!\n", rc); 779 goto out; 780 } 781 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 782 783 if (!wait_to_complete) 784 break; 785 } while (!new.link_status && cnt--); 786 787 out: 788 /* Timed out or success */ 789 if (new.link_status != eth_dev->data->dev_link.link_status || 790 new.link_speed != eth_dev->data->dev_link.link_speed) { 791 memcpy(ð_dev->data->dev_link, &new, 792 sizeof(struct rte_eth_link)); 793 794 _rte_eth_dev_callback_process(eth_dev, 795 RTE_ETH_EVENT_INTR_LSC, 796 NULL); 797 798 bnxt_print_link_info(eth_dev); 799 } 800 801 return rc; 802 } 803 804 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 805 { 806 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 807 struct bnxt_vnic_info *vnic; 808 809 if (bp->vnic_info == NULL) 810 return; 811 812 vnic = &bp->vnic_info[0]; 813 814 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 815 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 816 } 817 818 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 819 { 820 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 821 struct bnxt_vnic_info *vnic; 822 823 if (bp->vnic_info == NULL) 824 return; 825 826 vnic = &bp->vnic_info[0]; 827 828 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 829 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 830 } 831 832 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 833 { 834 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 835 struct bnxt_vnic_info *vnic; 836 837 if (bp->vnic_info == NULL) 838 return; 839 840 vnic = &bp->vnic_info[0]; 841 842 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 843 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 844 } 845 846 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 847 { 848 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 849 struct bnxt_vnic_info *vnic; 850 851 if (bp->vnic_info == NULL) 852 return; 853 854 vnic = &bp->vnic_info[0]; 855 856 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 857 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 858 } 859 860 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 861 struct rte_eth_rss_reta_entry64 *reta_conf, 862 uint16_t reta_size) 863 { 864 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 865 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 866 struct bnxt_vnic_info *vnic; 867 int i; 868 869 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 870 return -EINVAL; 871 872 if (reta_size != HW_HASH_INDEX_SIZE) { 873 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 874 "(%d) must equal the size supported by the hardware " 875 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 876 return -EINVAL; 877 } 878 /* Update the RSS VNIC(s) */ 879 for (i = 0; i < MAX_FF_POOLS; i++) { 880 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 881 memcpy(vnic->rss_table, reta_conf, reta_size); 882 883 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 884 } 885 } 886 return 0; 887 } 888 889 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 890 struct rte_eth_rss_reta_entry64 *reta_conf, 891 uint16_t reta_size) 892 { 893 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 894 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 895 struct rte_intr_handle *intr_handle 896 = &bp->pdev->intr_handle; 897 898 /* Retrieve from the default VNIC */ 899 if (!vnic) 900 return -EINVAL; 901 if (!vnic->rss_table) 902 return -EINVAL; 903 904 if (reta_size != HW_HASH_INDEX_SIZE) { 905 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 906 "(%d) must equal the size supported by the hardware " 907 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 908 return -EINVAL; 909 } 910 /* EW - need to revisit here copying from uint64_t to uint16_t */ 911 memcpy(reta_conf, vnic->rss_table, reta_size); 912 913 if (rte_intr_allow_others(intr_handle)) { 914 if (eth_dev->data->dev_conf.intr_conf.lsc != 0) 915 bnxt_dev_lsc_intr_setup(eth_dev); 916 } 917 918 return 0; 919 } 920 921 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 922 struct rte_eth_rss_conf *rss_conf) 923 { 924 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 925 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 926 struct bnxt_vnic_info *vnic; 927 uint16_t hash_type = 0; 928 int i; 929 930 /* 931 * If RSS enablement were different than dev_configure, 932 * then return -EINVAL 933 */ 934 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 935 if (!rss_conf->rss_hf) 936 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 937 } else { 938 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 939 return -EINVAL; 940 } 941 942 bp->flags |= BNXT_FLAG_UPDATE_HASH; 943 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 944 945 if (rss_conf->rss_hf & ETH_RSS_IPV4) 946 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 947 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 948 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 949 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 950 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 951 if (rss_conf->rss_hf & ETH_RSS_IPV6) 952 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 953 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 954 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 955 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 956 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 957 958 /* Update the RSS VNIC(s) */ 959 for (i = 0; i < MAX_FF_POOLS; i++) { 960 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 961 vnic->hash_type = hash_type; 962 963 /* 964 * Use the supplied key if the key length is 965 * acceptable and the rss_key is not NULL 966 */ 967 if (rss_conf->rss_key && 968 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 969 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 970 rss_conf->rss_key_len); 971 972 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 973 } 974 } 975 return 0; 976 } 977 978 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 979 struct rte_eth_rss_conf *rss_conf) 980 { 981 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 982 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 983 int len; 984 uint32_t hash_types; 985 986 /* RSS configuration is the same for all VNICs */ 987 if (vnic && vnic->rss_hash_key) { 988 if (rss_conf->rss_key) { 989 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 990 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 991 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 992 } 993 994 hash_types = vnic->hash_type; 995 rss_conf->rss_hf = 0; 996 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 997 rss_conf->rss_hf |= ETH_RSS_IPV4; 998 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 999 } 1000 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1001 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1002 hash_types &= 1003 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1004 } 1005 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1006 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1007 hash_types &= 1008 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1009 } 1010 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1011 rss_conf->rss_hf |= ETH_RSS_IPV6; 1012 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1013 } 1014 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1015 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1016 hash_types &= 1017 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1018 } 1019 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1020 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1021 hash_types &= 1022 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1023 } 1024 if (hash_types) { 1025 PMD_DRV_LOG(ERR, 1026 "Unknwon RSS config from firmware (%08x), RSS disabled", 1027 vnic->hash_type); 1028 return -ENOTSUP; 1029 } 1030 } else { 1031 rss_conf->rss_hf = 0; 1032 } 1033 return 0; 1034 } 1035 1036 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1037 struct rte_eth_fc_conf *fc_conf) 1038 { 1039 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1040 struct rte_eth_link link_info; 1041 int rc; 1042 1043 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1044 if (rc) 1045 return rc; 1046 1047 memset(fc_conf, 0, sizeof(*fc_conf)); 1048 if (bp->link_info.auto_pause) 1049 fc_conf->autoneg = 1; 1050 switch (bp->link_info.pause) { 1051 case 0: 1052 fc_conf->mode = RTE_FC_NONE; 1053 break; 1054 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1055 fc_conf->mode = RTE_FC_TX_PAUSE; 1056 break; 1057 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1058 fc_conf->mode = RTE_FC_RX_PAUSE; 1059 break; 1060 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1061 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1062 fc_conf->mode = RTE_FC_FULL; 1063 break; 1064 } 1065 return 0; 1066 } 1067 1068 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1069 struct rte_eth_fc_conf *fc_conf) 1070 { 1071 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1072 1073 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1074 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1075 return -ENOTSUP; 1076 } 1077 1078 switch (fc_conf->mode) { 1079 case RTE_FC_NONE: 1080 bp->link_info.auto_pause = 0; 1081 bp->link_info.force_pause = 0; 1082 break; 1083 case RTE_FC_RX_PAUSE: 1084 if (fc_conf->autoneg) { 1085 bp->link_info.auto_pause = 1086 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1087 bp->link_info.force_pause = 0; 1088 } else { 1089 bp->link_info.auto_pause = 0; 1090 bp->link_info.force_pause = 1091 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1092 } 1093 break; 1094 case RTE_FC_TX_PAUSE: 1095 if (fc_conf->autoneg) { 1096 bp->link_info.auto_pause = 1097 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1098 bp->link_info.force_pause = 0; 1099 } else { 1100 bp->link_info.auto_pause = 0; 1101 bp->link_info.force_pause = 1102 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1103 } 1104 break; 1105 case RTE_FC_FULL: 1106 if (fc_conf->autoneg) { 1107 bp->link_info.auto_pause = 1108 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1109 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1110 bp->link_info.force_pause = 0; 1111 } else { 1112 bp->link_info.auto_pause = 0; 1113 bp->link_info.force_pause = 1114 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1115 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1116 } 1117 break; 1118 } 1119 return bnxt_set_hwrm_link_config(bp, true); 1120 } 1121 1122 /* Add UDP tunneling port */ 1123 static int 1124 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1125 struct rte_eth_udp_tunnel *udp_tunnel) 1126 { 1127 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1128 uint16_t tunnel_type = 0; 1129 int rc = 0; 1130 1131 switch (udp_tunnel->prot_type) { 1132 case RTE_TUNNEL_TYPE_VXLAN: 1133 if (bp->vxlan_port_cnt) { 1134 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1135 udp_tunnel->udp_port); 1136 if (bp->vxlan_port != udp_tunnel->udp_port) { 1137 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1138 return -ENOSPC; 1139 } 1140 bp->vxlan_port_cnt++; 1141 return 0; 1142 } 1143 tunnel_type = 1144 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1145 bp->vxlan_port_cnt++; 1146 break; 1147 case RTE_TUNNEL_TYPE_GENEVE: 1148 if (bp->geneve_port_cnt) { 1149 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1150 udp_tunnel->udp_port); 1151 if (bp->geneve_port != udp_tunnel->udp_port) { 1152 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1153 return -ENOSPC; 1154 } 1155 bp->geneve_port_cnt++; 1156 return 0; 1157 } 1158 tunnel_type = 1159 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1160 bp->geneve_port_cnt++; 1161 break; 1162 default: 1163 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1164 return -ENOTSUP; 1165 } 1166 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1167 tunnel_type); 1168 return rc; 1169 } 1170 1171 static int 1172 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1173 struct rte_eth_udp_tunnel *udp_tunnel) 1174 { 1175 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1176 uint16_t tunnel_type = 0; 1177 uint16_t port = 0; 1178 int rc = 0; 1179 1180 switch (udp_tunnel->prot_type) { 1181 case RTE_TUNNEL_TYPE_VXLAN: 1182 if (!bp->vxlan_port_cnt) { 1183 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1184 return -EINVAL; 1185 } 1186 if (bp->vxlan_port != udp_tunnel->udp_port) { 1187 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1188 udp_tunnel->udp_port, bp->vxlan_port); 1189 return -EINVAL; 1190 } 1191 if (--bp->vxlan_port_cnt) 1192 return 0; 1193 1194 tunnel_type = 1195 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1196 port = bp->vxlan_fw_dst_port_id; 1197 break; 1198 case RTE_TUNNEL_TYPE_GENEVE: 1199 if (!bp->geneve_port_cnt) { 1200 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1201 return -EINVAL; 1202 } 1203 if (bp->geneve_port != udp_tunnel->udp_port) { 1204 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1205 udp_tunnel->udp_port, bp->geneve_port); 1206 return -EINVAL; 1207 } 1208 if (--bp->geneve_port_cnt) 1209 return 0; 1210 1211 tunnel_type = 1212 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1213 port = bp->geneve_fw_dst_port_id; 1214 break; 1215 default: 1216 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1217 return -ENOTSUP; 1218 } 1219 1220 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1221 if (!rc) { 1222 if (tunnel_type == 1223 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1224 bp->vxlan_port = 0; 1225 if (tunnel_type == 1226 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1227 bp->geneve_port = 0; 1228 } 1229 return rc; 1230 } 1231 1232 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1233 { 1234 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1235 struct bnxt_vnic_info *vnic; 1236 unsigned int i; 1237 int rc = 0; 1238 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN; 1239 1240 /* Cycle through all VNICs */ 1241 for (i = 0; i < bp->nr_vnics; i++) { 1242 /* 1243 * For each VNIC and each associated filter(s) 1244 * if VLAN exists && VLAN matches vlan_id 1245 * remove the MAC+VLAN filter 1246 * add a new MAC only filter 1247 * else 1248 * VLAN filter doesn't exist, just skip and continue 1249 */ 1250 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 1251 filter = STAILQ_FIRST(&vnic->filter); 1252 while (filter) { 1253 temp_filter = STAILQ_NEXT(filter, next); 1254 1255 if (filter->enables & chk && 1256 filter->l2_ovlan == vlan_id) { 1257 /* Must delete the filter */ 1258 STAILQ_REMOVE(&vnic->filter, filter, 1259 bnxt_filter_info, next); 1260 bnxt_hwrm_clear_l2_filter(bp, filter); 1261 STAILQ_INSERT_TAIL( 1262 &bp->free_filter_list, 1263 filter, next); 1264 1265 /* 1266 * Need to examine to see if the MAC 1267 * filter already existed or not before 1268 * allocating a new one 1269 */ 1270 1271 new_filter = bnxt_alloc_filter(bp); 1272 if (!new_filter) { 1273 PMD_DRV_LOG(ERR, 1274 "MAC/VLAN filter alloc failed\n"); 1275 rc = -ENOMEM; 1276 goto exit; 1277 } 1278 STAILQ_INSERT_TAIL(&vnic->filter, 1279 new_filter, next); 1280 /* Inherit MAC from previous filter */ 1281 new_filter->mac_index = 1282 filter->mac_index; 1283 memcpy(new_filter->l2_addr, 1284 filter->l2_addr, ETHER_ADDR_LEN); 1285 /* MAC only filter */ 1286 rc = bnxt_hwrm_set_l2_filter(bp, 1287 vnic->fw_vnic_id, 1288 new_filter); 1289 if (rc) 1290 goto exit; 1291 PMD_DRV_LOG(INFO, 1292 "Del Vlan filter for %d\n", 1293 vlan_id); 1294 } 1295 filter = temp_filter; 1296 } 1297 } 1298 } 1299 exit: 1300 return rc; 1301 } 1302 1303 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1304 { 1305 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1306 struct bnxt_vnic_info *vnic; 1307 unsigned int i; 1308 int rc = 0; 1309 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN | 1310 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK; 1311 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN; 1312 1313 /* Cycle through all VNICs */ 1314 for (i = 0; i < bp->nr_vnics; i++) { 1315 /* 1316 * For each VNIC and each associated filter(s) 1317 * if VLAN exists: 1318 * if VLAN matches vlan_id 1319 * VLAN filter already exists, just skip and continue 1320 * else 1321 * add a new MAC+VLAN filter 1322 * else 1323 * Remove the old MAC only filter 1324 * Add a new MAC+VLAN filter 1325 */ 1326 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 1327 filter = STAILQ_FIRST(&vnic->filter); 1328 while (filter) { 1329 temp_filter = STAILQ_NEXT(filter, next); 1330 1331 if (filter->enables & chk) { 1332 if (filter->l2_ovlan == vlan_id) 1333 goto cont; 1334 } else { 1335 /* Must delete the MAC filter */ 1336 STAILQ_REMOVE(&vnic->filter, filter, 1337 bnxt_filter_info, next); 1338 bnxt_hwrm_clear_l2_filter(bp, filter); 1339 filter->l2_ovlan = 0; 1340 STAILQ_INSERT_TAIL( 1341 &bp->free_filter_list, 1342 filter, next); 1343 } 1344 new_filter = bnxt_alloc_filter(bp); 1345 if (!new_filter) { 1346 PMD_DRV_LOG(ERR, 1347 "MAC/VLAN filter alloc failed\n"); 1348 rc = -ENOMEM; 1349 goto exit; 1350 } 1351 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, 1352 next); 1353 /* Inherit MAC from the previous filter */ 1354 new_filter->mac_index = filter->mac_index; 1355 memcpy(new_filter->l2_addr, filter->l2_addr, 1356 ETHER_ADDR_LEN); 1357 /* MAC + VLAN ID filter */ 1358 new_filter->l2_ovlan = vlan_id; 1359 new_filter->l2_ovlan_mask = 0xF000; 1360 new_filter->enables |= en; 1361 rc = bnxt_hwrm_set_l2_filter(bp, 1362 vnic->fw_vnic_id, 1363 new_filter); 1364 if (rc) 1365 goto exit; 1366 PMD_DRV_LOG(INFO, 1367 "Added Vlan filter for %d\n", vlan_id); 1368 cont: 1369 filter = temp_filter; 1370 } 1371 } 1372 } 1373 exit: 1374 return rc; 1375 } 1376 1377 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1378 uint16_t vlan_id, int on) 1379 { 1380 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1381 1382 /* These operations apply to ALL existing MAC/VLAN filters */ 1383 if (on) 1384 return bnxt_add_vlan_filter(bp, vlan_id); 1385 else 1386 return bnxt_del_vlan_filter(bp, vlan_id); 1387 } 1388 1389 static int 1390 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1391 { 1392 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1393 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1394 unsigned int i; 1395 1396 if (mask & ETH_VLAN_FILTER_MASK) { 1397 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1398 /* Remove any VLAN filters programmed */ 1399 for (i = 0; i < 4095; i++) 1400 bnxt_del_vlan_filter(bp, i); 1401 } 1402 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1403 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1404 } 1405 1406 if (mask & ETH_VLAN_STRIP_MASK) { 1407 /* Enable or disable VLAN stripping */ 1408 for (i = 0; i < bp->nr_vnics; i++) { 1409 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1410 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1411 vnic->vlan_strip = true; 1412 else 1413 vnic->vlan_strip = false; 1414 bnxt_hwrm_vnic_cfg(bp, vnic); 1415 } 1416 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1417 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1418 } 1419 1420 if (mask & ETH_VLAN_EXTEND_MASK) 1421 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n"); 1422 1423 return 0; 1424 } 1425 1426 static int 1427 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr) 1428 { 1429 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1430 /* Default Filter is tied to VNIC 0 */ 1431 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1432 struct bnxt_filter_info *filter; 1433 int rc; 1434 1435 if (BNXT_VF(bp)) 1436 return -EPERM; 1437 1438 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr)); 1439 1440 STAILQ_FOREACH(filter, &vnic->filter, next) { 1441 /* Default Filter is at Index 0 */ 1442 if (filter->mac_index != 0) 1443 continue; 1444 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1445 if (rc) 1446 return rc; 1447 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN); 1448 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN); 1449 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX; 1450 filter->enables |= 1451 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 1452 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 1453 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1454 if (rc) 1455 return rc; 1456 filter->mac_index = 0; 1457 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int 1464 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 1465 struct ether_addr *mc_addr_set, 1466 uint32_t nb_mc_addr) 1467 { 1468 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1469 char *mc_addr_list = (char *)mc_addr_set; 1470 struct bnxt_vnic_info *vnic; 1471 uint32_t off = 0, i = 0; 1472 1473 vnic = &bp->vnic_info[0]; 1474 1475 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 1476 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1477 goto allmulti; 1478 } 1479 1480 /* TODO Check for Duplicate mcast addresses */ 1481 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1482 for (i = 0; i < nb_mc_addr; i++) { 1483 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN); 1484 off += ETHER_ADDR_LEN; 1485 } 1486 1487 vnic->mc_addr_cnt = i; 1488 1489 allmulti: 1490 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1491 } 1492 1493 static int 1494 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 1495 { 1496 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1497 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 1498 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 1499 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 1500 int ret; 1501 1502 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 1503 fw_major, fw_minor, fw_updt); 1504 1505 ret += 1; /* add the size of '\0' */ 1506 if (fw_size < (uint32_t)ret) 1507 return ret; 1508 else 1509 return 0; 1510 } 1511 1512 static void 1513 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1514 struct rte_eth_rxq_info *qinfo) 1515 { 1516 struct bnxt_rx_queue *rxq; 1517 1518 rxq = dev->data->rx_queues[queue_id]; 1519 1520 qinfo->mp = rxq->mb_pool; 1521 qinfo->scattered_rx = dev->data->scattered_rx; 1522 qinfo->nb_desc = rxq->nb_rx_desc; 1523 1524 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 1525 qinfo->conf.rx_drop_en = 0; 1526 qinfo->conf.rx_deferred_start = 0; 1527 } 1528 1529 static void 1530 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1531 struct rte_eth_txq_info *qinfo) 1532 { 1533 struct bnxt_tx_queue *txq; 1534 1535 txq = dev->data->tx_queues[queue_id]; 1536 1537 qinfo->nb_desc = txq->nb_tx_desc; 1538 1539 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 1540 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 1541 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 1542 1543 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 1544 qinfo->conf.tx_rs_thresh = 0; 1545 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1546 } 1547 1548 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 1549 { 1550 struct bnxt *bp = eth_dev->data->dev_private; 1551 struct rte_eth_dev_info dev_info; 1552 uint32_t max_dev_mtu; 1553 uint32_t rc = 0; 1554 uint32_t i; 1555 1556 bnxt_dev_info_get_op(eth_dev, &dev_info); 1557 max_dev_mtu = dev_info.max_rx_pktlen - 1558 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2; 1559 1560 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) { 1561 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n", 1562 ETHER_MIN_MTU, max_dev_mtu); 1563 return -EINVAL; 1564 } 1565 1566 1567 if (new_mtu > ETHER_MTU) { 1568 bp->flags |= BNXT_FLAG_JUMBO; 1569 bp->eth_dev->data->dev_conf.rxmode.offloads |= 1570 DEV_RX_OFFLOAD_JUMBO_FRAME; 1571 } else { 1572 bp->eth_dev->data->dev_conf.rxmode.offloads &= 1573 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1574 bp->flags &= ~BNXT_FLAG_JUMBO; 1575 } 1576 1577 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = 1578 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1579 1580 eth_dev->data->mtu = new_mtu; 1581 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu); 1582 1583 for (i = 0; i < bp->nr_vnics; i++) { 1584 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1585 uint16_t size = 0; 1586 1587 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN + 1588 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1589 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 1590 if (rc) 1591 break; 1592 1593 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 1594 size -= RTE_PKTMBUF_HEADROOM; 1595 1596 if (size < new_mtu) { 1597 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 1598 if (rc) 1599 return rc; 1600 } 1601 } 1602 1603 return rc; 1604 } 1605 1606 static int 1607 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 1608 { 1609 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1610 uint16_t vlan = bp->vlan; 1611 int rc; 1612 1613 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1614 PMD_DRV_LOG(ERR, 1615 "PVID cannot be modified for this function\n"); 1616 return -ENOTSUP; 1617 } 1618 bp->vlan = on ? pvid : 0; 1619 1620 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 1621 if (rc) 1622 bp->vlan = vlan; 1623 return rc; 1624 } 1625 1626 static int 1627 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 1628 { 1629 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1630 1631 return bnxt_hwrm_port_led_cfg(bp, true); 1632 } 1633 1634 static int 1635 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 1636 { 1637 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1638 1639 return bnxt_hwrm_port_led_cfg(bp, false); 1640 } 1641 1642 static uint32_t 1643 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1644 { 1645 uint32_t desc = 0, raw_cons = 0, cons; 1646 struct bnxt_cp_ring_info *cpr; 1647 struct bnxt_rx_queue *rxq; 1648 struct rx_pkt_cmpl *rxcmp; 1649 uint16_t cmp_type; 1650 uint8_t cmp = 1; 1651 bool valid; 1652 1653 rxq = dev->data->rx_queues[rx_queue_id]; 1654 cpr = rxq->cp_ring; 1655 valid = cpr->valid; 1656 1657 while (raw_cons < rxq->nb_rx_desc) { 1658 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 1659 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1660 1661 if (!CMPL_VALID(rxcmp, valid)) 1662 goto nothing_to_do; 1663 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid); 1664 cmp_type = CMP_TYPE(rxcmp); 1665 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { 1666 cmp = (rte_le_to_cpu_32( 1667 ((struct rx_tpa_end_cmpl *) 1668 (rxcmp))->agg_bufs_v1) & 1669 RX_TPA_END_CMPL_AGG_BUFS_MASK) >> 1670 RX_TPA_END_CMPL_AGG_BUFS_SFT; 1671 desc++; 1672 } else if (cmp_type == 0x11) { 1673 desc++; 1674 cmp = (rxcmp->agg_bufs_v1 & 1675 RX_PKT_CMPL_AGG_BUFS_MASK) >> 1676 RX_PKT_CMPL_AGG_BUFS_SFT; 1677 } else { 1678 cmp = 1; 1679 } 1680 nothing_to_do: 1681 raw_cons += cmp ? cmp : 2; 1682 } 1683 1684 return desc; 1685 } 1686 1687 static int 1688 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 1689 { 1690 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 1691 struct bnxt_rx_ring_info *rxr; 1692 struct bnxt_cp_ring_info *cpr; 1693 struct bnxt_sw_rx_bd *rx_buf; 1694 struct rx_pkt_cmpl *rxcmp; 1695 uint32_t cons, cp_cons; 1696 1697 if (!rxq) 1698 return -EINVAL; 1699 1700 cpr = rxq->cp_ring; 1701 rxr = rxq->rx_ring; 1702 1703 if (offset >= rxq->nb_rx_desc) 1704 return -EINVAL; 1705 1706 cons = RING_CMP(cpr->cp_ring_struct, offset); 1707 cp_cons = cpr->cp_raw_cons; 1708 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1709 1710 if (cons > cp_cons) { 1711 if (CMPL_VALID(rxcmp, cpr->valid)) 1712 return RTE_ETH_RX_DESC_DONE; 1713 } else { 1714 if (CMPL_VALID(rxcmp, !cpr->valid)) 1715 return RTE_ETH_RX_DESC_DONE; 1716 } 1717 rx_buf = &rxr->rx_buf_ring[cons]; 1718 if (rx_buf->mbuf == NULL) 1719 return RTE_ETH_RX_DESC_UNAVAIL; 1720 1721 1722 return RTE_ETH_RX_DESC_AVAIL; 1723 } 1724 1725 static int 1726 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 1727 { 1728 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 1729 struct bnxt_tx_ring_info *txr; 1730 struct bnxt_cp_ring_info *cpr; 1731 struct bnxt_sw_tx_bd *tx_buf; 1732 struct tx_pkt_cmpl *txcmp; 1733 uint32_t cons, cp_cons; 1734 1735 if (!txq) 1736 return -EINVAL; 1737 1738 cpr = txq->cp_ring; 1739 txr = txq->tx_ring; 1740 1741 if (offset >= txq->nb_tx_desc) 1742 return -EINVAL; 1743 1744 cons = RING_CMP(cpr->cp_ring_struct, offset); 1745 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1746 cp_cons = cpr->cp_raw_cons; 1747 1748 if (cons > cp_cons) { 1749 if (CMPL_VALID(txcmp, cpr->valid)) 1750 return RTE_ETH_TX_DESC_UNAVAIL; 1751 } else { 1752 if (CMPL_VALID(txcmp, !cpr->valid)) 1753 return RTE_ETH_TX_DESC_UNAVAIL; 1754 } 1755 tx_buf = &txr->tx_buf_ring[cons]; 1756 if (tx_buf->mbuf == NULL) 1757 return RTE_ETH_TX_DESC_DONE; 1758 1759 return RTE_ETH_TX_DESC_FULL; 1760 } 1761 1762 static struct bnxt_filter_info * 1763 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 1764 struct rte_eth_ethertype_filter *efilter, 1765 struct bnxt_vnic_info *vnic0, 1766 struct bnxt_vnic_info *vnic, 1767 int *ret) 1768 { 1769 struct bnxt_filter_info *mfilter = NULL; 1770 int match = 0; 1771 *ret = 0; 1772 1773 if (efilter->ether_type == ETHER_TYPE_IPv4 || 1774 efilter->ether_type == ETHER_TYPE_IPv6) { 1775 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 1776 " ethertype filter.", efilter->ether_type); 1777 *ret = -EINVAL; 1778 goto exit; 1779 } 1780 if (efilter->queue >= bp->rx_nr_rings) { 1781 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 1782 *ret = -EINVAL; 1783 goto exit; 1784 } 1785 1786 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1787 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); 1788 if (vnic == NULL) { 1789 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 1790 *ret = -EINVAL; 1791 goto exit; 1792 } 1793 1794 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1795 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 1796 if ((!memcmp(efilter->mac_addr.addr_bytes, 1797 mfilter->l2_addr, ETHER_ADDR_LEN) && 1798 mfilter->flags == 1799 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 1800 mfilter->ethertype == efilter->ether_type)) { 1801 match = 1; 1802 break; 1803 } 1804 } 1805 } else { 1806 STAILQ_FOREACH(mfilter, &vnic->filter, next) 1807 if ((!memcmp(efilter->mac_addr.addr_bytes, 1808 mfilter->l2_addr, ETHER_ADDR_LEN) && 1809 mfilter->ethertype == efilter->ether_type && 1810 mfilter->flags == 1811 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 1812 match = 1; 1813 break; 1814 } 1815 } 1816 1817 if (match) 1818 *ret = -EEXIST; 1819 1820 exit: 1821 return mfilter; 1822 } 1823 1824 static int 1825 bnxt_ethertype_filter(struct rte_eth_dev *dev, 1826 enum rte_filter_op filter_op, 1827 void *arg) 1828 { 1829 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1830 struct rte_eth_ethertype_filter *efilter = 1831 (struct rte_eth_ethertype_filter *)arg; 1832 struct bnxt_filter_info *bfilter, *filter1; 1833 struct bnxt_vnic_info *vnic, *vnic0; 1834 int ret; 1835 1836 if (filter_op == RTE_ETH_FILTER_NOP) 1837 return 0; 1838 1839 if (arg == NULL) { 1840 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 1841 filter_op); 1842 return -EINVAL; 1843 } 1844 1845 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1846 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); 1847 1848 switch (filter_op) { 1849 case RTE_ETH_FILTER_ADD: 1850 bnxt_match_and_validate_ether_filter(bp, efilter, 1851 vnic0, vnic, &ret); 1852 if (ret < 0) 1853 return ret; 1854 1855 bfilter = bnxt_get_unused_filter(bp); 1856 if (bfilter == NULL) { 1857 PMD_DRV_LOG(ERR, 1858 "Not enough resources for a new filter.\n"); 1859 return -ENOMEM; 1860 } 1861 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 1862 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 1863 ETHER_ADDR_LEN); 1864 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 1865 ETHER_ADDR_LEN); 1866 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 1867 bfilter->ethertype = efilter->ether_type; 1868 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 1869 1870 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 1871 if (filter1 == NULL) { 1872 ret = -1; 1873 goto cleanup; 1874 } 1875 bfilter->enables |= 1876 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 1877 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 1878 1879 bfilter->dst_id = vnic->fw_vnic_id; 1880 1881 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1882 bfilter->flags = 1883 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 1884 } 1885 1886 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 1887 if (ret) 1888 goto cleanup; 1889 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 1890 break; 1891 case RTE_ETH_FILTER_DELETE: 1892 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 1893 vnic0, vnic, &ret); 1894 if (ret == -EEXIST) { 1895 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 1896 1897 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 1898 next); 1899 bnxt_free_filter(bp, filter1); 1900 } else if (ret == 0) { 1901 PMD_DRV_LOG(ERR, "No matching filter found\n"); 1902 } 1903 break; 1904 default: 1905 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 1906 ret = -EINVAL; 1907 goto error; 1908 } 1909 return ret; 1910 cleanup: 1911 bnxt_free_filter(bp, bfilter); 1912 error: 1913 return ret; 1914 } 1915 1916 static inline int 1917 parse_ntuple_filter(struct bnxt *bp, 1918 struct rte_eth_ntuple_filter *nfilter, 1919 struct bnxt_filter_info *bfilter) 1920 { 1921 uint32_t en = 0; 1922 1923 if (nfilter->queue >= bp->rx_nr_rings) { 1924 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 1925 return -EINVAL; 1926 } 1927 1928 switch (nfilter->dst_port_mask) { 1929 case UINT16_MAX: 1930 bfilter->dst_port_mask = -1; 1931 bfilter->dst_port = nfilter->dst_port; 1932 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 1933 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 1934 break; 1935 default: 1936 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 1937 return -EINVAL; 1938 } 1939 1940 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 1941 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1942 1943 switch (nfilter->proto_mask) { 1944 case UINT8_MAX: 1945 if (nfilter->proto == 17) /* IPPROTO_UDP */ 1946 bfilter->ip_protocol = 17; 1947 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 1948 bfilter->ip_protocol = 6; 1949 else 1950 return -EINVAL; 1951 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1952 break; 1953 default: 1954 PMD_DRV_LOG(ERR, "invalid protocol mask."); 1955 return -EINVAL; 1956 } 1957 1958 switch (nfilter->dst_ip_mask) { 1959 case UINT32_MAX: 1960 bfilter->dst_ipaddr_mask[0] = -1; 1961 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 1962 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 1963 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 1964 break; 1965 default: 1966 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 1967 return -EINVAL; 1968 } 1969 1970 switch (nfilter->src_ip_mask) { 1971 case UINT32_MAX: 1972 bfilter->src_ipaddr_mask[0] = -1; 1973 bfilter->src_ipaddr[0] = nfilter->src_ip; 1974 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 1975 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 1976 break; 1977 default: 1978 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 1979 return -EINVAL; 1980 } 1981 1982 switch (nfilter->src_port_mask) { 1983 case UINT16_MAX: 1984 bfilter->src_port_mask = -1; 1985 bfilter->src_port = nfilter->src_port; 1986 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 1987 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 1988 break; 1989 default: 1990 PMD_DRV_LOG(ERR, "invalid src_port mask."); 1991 return -EINVAL; 1992 } 1993 1994 //TODO Priority 1995 //nfilter->priority = (uint8_t)filter->priority; 1996 1997 bfilter->enables = en; 1998 return 0; 1999 } 2000 2001 static struct bnxt_filter_info* 2002 bnxt_match_ntuple_filter(struct bnxt *bp, 2003 struct bnxt_filter_info *bfilter, 2004 struct bnxt_vnic_info **mvnic) 2005 { 2006 struct bnxt_filter_info *mfilter = NULL; 2007 int i; 2008 2009 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2010 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2011 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2012 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2013 bfilter->src_ipaddr_mask[0] == 2014 mfilter->src_ipaddr_mask[0] && 2015 bfilter->src_port == mfilter->src_port && 2016 bfilter->src_port_mask == mfilter->src_port_mask && 2017 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2018 bfilter->dst_ipaddr_mask[0] == 2019 mfilter->dst_ipaddr_mask[0] && 2020 bfilter->dst_port == mfilter->dst_port && 2021 bfilter->dst_port_mask == mfilter->dst_port_mask && 2022 bfilter->flags == mfilter->flags && 2023 bfilter->enables == mfilter->enables) { 2024 if (mvnic) 2025 *mvnic = vnic; 2026 return mfilter; 2027 } 2028 } 2029 } 2030 return NULL; 2031 } 2032 2033 static int 2034 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2035 struct rte_eth_ntuple_filter *nfilter, 2036 enum rte_filter_op filter_op) 2037 { 2038 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2039 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2040 int ret; 2041 2042 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2043 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2044 return -EINVAL; 2045 } 2046 2047 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2048 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2049 return -EINVAL; 2050 } 2051 2052 bfilter = bnxt_get_unused_filter(bp); 2053 if (bfilter == NULL) { 2054 PMD_DRV_LOG(ERR, 2055 "Not enough resources for a new filter.\n"); 2056 return -ENOMEM; 2057 } 2058 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2059 if (ret < 0) 2060 goto free_filter; 2061 2062 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]); 2063 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 2064 filter1 = STAILQ_FIRST(&vnic0->filter); 2065 if (filter1 == NULL) { 2066 ret = -1; 2067 goto free_filter; 2068 } 2069 2070 bfilter->dst_id = vnic->fw_vnic_id; 2071 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2072 bfilter->enables |= 2073 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2074 bfilter->ethertype = 0x800; 2075 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2076 2077 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2078 2079 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2080 bfilter->dst_id == mfilter->dst_id) { 2081 PMD_DRV_LOG(ERR, "filter exists.\n"); 2082 ret = -EEXIST; 2083 goto free_filter; 2084 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2085 bfilter->dst_id != mfilter->dst_id) { 2086 mfilter->dst_id = vnic->fw_vnic_id; 2087 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2088 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2089 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2090 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2091 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2092 goto free_filter; 2093 } 2094 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2095 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2096 ret = -ENOENT; 2097 goto free_filter; 2098 } 2099 2100 if (filter_op == RTE_ETH_FILTER_ADD) { 2101 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2102 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2103 if (ret) 2104 goto free_filter; 2105 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2106 } else { 2107 if (mfilter == NULL) { 2108 /* This should not happen. But for Coverity! */ 2109 ret = -ENOENT; 2110 goto free_filter; 2111 } 2112 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2113 2114 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2115 bnxt_free_filter(bp, mfilter); 2116 mfilter->fw_l2_filter_id = -1; 2117 bnxt_free_filter(bp, bfilter); 2118 bfilter->fw_l2_filter_id = -1; 2119 } 2120 2121 return 0; 2122 free_filter: 2123 bfilter->fw_l2_filter_id = -1; 2124 bnxt_free_filter(bp, bfilter); 2125 return ret; 2126 } 2127 2128 static int 2129 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2130 enum rte_filter_op filter_op, 2131 void *arg) 2132 { 2133 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2134 int ret; 2135 2136 if (filter_op == RTE_ETH_FILTER_NOP) 2137 return 0; 2138 2139 if (arg == NULL) { 2140 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2141 filter_op); 2142 return -EINVAL; 2143 } 2144 2145 switch (filter_op) { 2146 case RTE_ETH_FILTER_ADD: 2147 ret = bnxt_cfg_ntuple_filter(bp, 2148 (struct rte_eth_ntuple_filter *)arg, 2149 filter_op); 2150 break; 2151 case RTE_ETH_FILTER_DELETE: 2152 ret = bnxt_cfg_ntuple_filter(bp, 2153 (struct rte_eth_ntuple_filter *)arg, 2154 filter_op); 2155 break; 2156 default: 2157 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2158 ret = -EINVAL; 2159 break; 2160 } 2161 return ret; 2162 } 2163 2164 static int 2165 bnxt_parse_fdir_filter(struct bnxt *bp, 2166 struct rte_eth_fdir_filter *fdir, 2167 struct bnxt_filter_info *filter) 2168 { 2169 enum rte_fdir_mode fdir_mode = 2170 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2171 struct bnxt_vnic_info *vnic0, *vnic; 2172 struct bnxt_filter_info *filter1; 2173 uint32_t en = 0; 2174 int i; 2175 2176 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2177 return -EINVAL; 2178 2179 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2180 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2181 2182 switch (fdir->input.flow_type) { 2183 case RTE_ETH_FLOW_IPV4: 2184 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2185 /* FALLTHROUGH */ 2186 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2188 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2190 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2191 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2192 filter->ip_addr_type = 2193 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2194 filter->src_ipaddr_mask[0] = 0xffffffff; 2195 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2196 filter->dst_ipaddr_mask[0] = 0xffffffff; 2197 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2198 filter->ethertype = 0x800; 2199 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2200 break; 2201 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2202 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2203 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2204 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2205 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2206 filter->dst_port_mask = 0xffff; 2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2208 filter->src_port_mask = 0xffff; 2209 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2210 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2211 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2212 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2214 filter->ip_protocol = 6; 2215 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2216 filter->ip_addr_type = 2217 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2218 filter->src_ipaddr_mask[0] = 0xffffffff; 2219 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2220 filter->dst_ipaddr_mask[0] = 0xffffffff; 2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2222 filter->ethertype = 0x800; 2223 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2224 break; 2225 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2226 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2227 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2228 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2229 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2230 filter->dst_port_mask = 0xffff; 2231 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2232 filter->src_port_mask = 0xffff; 2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2234 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2235 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2236 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2237 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2238 filter->ip_protocol = 17; 2239 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2240 filter->ip_addr_type = 2241 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2242 filter->src_ipaddr_mask[0] = 0xffffffff; 2243 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2244 filter->dst_ipaddr_mask[0] = 0xffffffff; 2245 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2246 filter->ethertype = 0x800; 2247 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2248 break; 2249 case RTE_ETH_FLOW_IPV6: 2250 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2251 /* FALLTHROUGH */ 2252 filter->ip_addr_type = 2253 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2254 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2255 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2256 rte_memcpy(filter->src_ipaddr, 2257 fdir->input.flow.ipv6_flow.src_ip, 16); 2258 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2259 rte_memcpy(filter->dst_ipaddr, 2260 fdir->input.flow.ipv6_flow.dst_ip, 16); 2261 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2262 memset(filter->dst_ipaddr_mask, 0xff, 16); 2263 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2264 memset(filter->src_ipaddr_mask, 0xff, 16); 2265 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2266 filter->ethertype = 0x86dd; 2267 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2268 break; 2269 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2270 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2272 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2273 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2274 filter->dst_port_mask = 0xffff; 2275 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2276 filter->src_port_mask = 0xffff; 2277 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2278 filter->ip_addr_type = 2279 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2280 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2281 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2282 rte_memcpy(filter->src_ipaddr, 2283 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2285 rte_memcpy(filter->dst_ipaddr, 2286 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2287 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2288 memset(filter->dst_ipaddr_mask, 0xff, 16); 2289 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2290 memset(filter->src_ipaddr_mask, 0xff, 16); 2291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2292 filter->ethertype = 0x86dd; 2293 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2294 break; 2295 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2296 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2298 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2299 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2300 filter->dst_port_mask = 0xffff; 2301 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2302 filter->src_port_mask = 0xffff; 2303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2304 filter->ip_addr_type = 2305 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2306 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2307 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2308 rte_memcpy(filter->src_ipaddr, 2309 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2311 rte_memcpy(filter->dst_ipaddr, 2312 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2313 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2314 memset(filter->dst_ipaddr_mask, 0xff, 16); 2315 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2316 memset(filter->src_ipaddr_mask, 0xff, 16); 2317 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2318 filter->ethertype = 0x86dd; 2319 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2320 break; 2321 case RTE_ETH_FLOW_L2_PAYLOAD: 2322 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2323 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2324 break; 2325 case RTE_ETH_FLOW_VXLAN: 2326 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2327 return -EINVAL; 2328 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2329 filter->tunnel_type = 2330 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2331 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2332 break; 2333 case RTE_ETH_FLOW_NVGRE: 2334 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2335 return -EINVAL; 2336 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2337 filter->tunnel_type = 2338 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2339 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2340 break; 2341 case RTE_ETH_FLOW_UNKNOWN: 2342 case RTE_ETH_FLOW_RAW: 2343 case RTE_ETH_FLOW_FRAG_IPV4: 2344 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2345 case RTE_ETH_FLOW_FRAG_IPV6: 2346 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2347 case RTE_ETH_FLOW_IPV6_EX: 2348 case RTE_ETH_FLOW_IPV6_TCP_EX: 2349 case RTE_ETH_FLOW_IPV6_UDP_EX: 2350 case RTE_ETH_FLOW_GENEVE: 2351 /* FALLTHROUGH */ 2352 default: 2353 return -EINVAL; 2354 } 2355 2356 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 2357 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); 2358 if (vnic == NULL) { 2359 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2360 return -EINVAL; 2361 } 2362 2363 2364 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2365 rte_memcpy(filter->dst_macaddr, 2366 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2367 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2368 } 2369 2370 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2371 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2372 filter1 = STAILQ_FIRST(&vnic0->filter); 2373 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2374 } else { 2375 filter->dst_id = vnic->fw_vnic_id; 2376 for (i = 0; i < ETHER_ADDR_LEN; i++) 2377 if (filter->dst_macaddr[i] == 0x00) 2378 filter1 = STAILQ_FIRST(&vnic0->filter); 2379 else 2380 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2381 } 2382 2383 if (filter1 == NULL) 2384 return -EINVAL; 2385 2386 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2387 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2388 2389 filter->enables = en; 2390 2391 return 0; 2392 } 2393 2394 static struct bnxt_filter_info * 2395 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 2396 struct bnxt_vnic_info **mvnic) 2397 { 2398 struct bnxt_filter_info *mf = NULL; 2399 int i; 2400 2401 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2402 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2403 2404 STAILQ_FOREACH(mf, &vnic->filter, next) { 2405 if (mf->filter_type == nf->filter_type && 2406 mf->flags == nf->flags && 2407 mf->src_port == nf->src_port && 2408 mf->src_port_mask == nf->src_port_mask && 2409 mf->dst_port == nf->dst_port && 2410 mf->dst_port_mask == nf->dst_port_mask && 2411 mf->ip_protocol == nf->ip_protocol && 2412 mf->ip_addr_type == nf->ip_addr_type && 2413 mf->ethertype == nf->ethertype && 2414 mf->vni == nf->vni && 2415 mf->tunnel_type == nf->tunnel_type && 2416 mf->l2_ovlan == nf->l2_ovlan && 2417 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 2418 mf->l2_ivlan == nf->l2_ivlan && 2419 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 2420 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) && 2421 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 2422 ETHER_ADDR_LEN) && 2423 !memcmp(mf->src_macaddr, nf->src_macaddr, 2424 ETHER_ADDR_LEN) && 2425 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 2426 ETHER_ADDR_LEN) && 2427 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 2428 sizeof(nf->src_ipaddr)) && 2429 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 2430 sizeof(nf->src_ipaddr_mask)) && 2431 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 2432 sizeof(nf->dst_ipaddr)) && 2433 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 2434 sizeof(nf->dst_ipaddr_mask))) { 2435 if (mvnic) 2436 *mvnic = vnic; 2437 return mf; 2438 } 2439 } 2440 } 2441 return NULL; 2442 } 2443 2444 static int 2445 bnxt_fdir_filter(struct rte_eth_dev *dev, 2446 enum rte_filter_op filter_op, 2447 void *arg) 2448 { 2449 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2450 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 2451 struct bnxt_filter_info *filter, *match; 2452 struct bnxt_vnic_info *vnic, *mvnic; 2453 int ret = 0, i; 2454 2455 if (filter_op == RTE_ETH_FILTER_NOP) 2456 return 0; 2457 2458 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 2459 return -EINVAL; 2460 2461 switch (filter_op) { 2462 case RTE_ETH_FILTER_ADD: 2463 case RTE_ETH_FILTER_DELETE: 2464 /* FALLTHROUGH */ 2465 filter = bnxt_get_unused_filter(bp); 2466 if (filter == NULL) { 2467 PMD_DRV_LOG(ERR, 2468 "Not enough resources for a new flow.\n"); 2469 return -ENOMEM; 2470 } 2471 2472 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 2473 if (ret != 0) 2474 goto free_filter; 2475 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2476 2477 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2478 vnic = STAILQ_FIRST(&bp->ff_pool[0]); 2479 else 2480 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); 2481 2482 match = bnxt_match_fdir(bp, filter, &mvnic); 2483 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2484 if (match->dst_id == vnic->fw_vnic_id) { 2485 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 2486 ret = -EEXIST; 2487 goto free_filter; 2488 } else { 2489 match->dst_id = vnic->fw_vnic_id; 2490 ret = bnxt_hwrm_set_ntuple_filter(bp, 2491 match->dst_id, 2492 match); 2493 STAILQ_REMOVE(&mvnic->filter, match, 2494 bnxt_filter_info, next); 2495 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 2496 PMD_DRV_LOG(ERR, 2497 "Filter with matching pattern exist\n"); 2498 PMD_DRV_LOG(ERR, 2499 "Updated it to new destination q\n"); 2500 goto free_filter; 2501 } 2502 } 2503 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2504 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 2505 ret = -ENOENT; 2506 goto free_filter; 2507 } 2508 2509 if (filter_op == RTE_ETH_FILTER_ADD) { 2510 ret = bnxt_hwrm_set_ntuple_filter(bp, 2511 filter->dst_id, 2512 filter); 2513 if (ret) 2514 goto free_filter; 2515 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2516 } else { 2517 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 2518 STAILQ_REMOVE(&vnic->filter, match, 2519 bnxt_filter_info, next); 2520 bnxt_free_filter(bp, match); 2521 filter->fw_l2_filter_id = -1; 2522 bnxt_free_filter(bp, filter); 2523 } 2524 break; 2525 case RTE_ETH_FILTER_FLUSH: 2526 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2527 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2528 2529 STAILQ_FOREACH(filter, &vnic->filter, next) { 2530 if (filter->filter_type == 2531 HWRM_CFA_NTUPLE_FILTER) { 2532 ret = 2533 bnxt_hwrm_clear_ntuple_filter(bp, 2534 filter); 2535 STAILQ_REMOVE(&vnic->filter, filter, 2536 bnxt_filter_info, next); 2537 } 2538 } 2539 } 2540 return ret; 2541 case RTE_ETH_FILTER_UPDATE: 2542 case RTE_ETH_FILTER_STATS: 2543 case RTE_ETH_FILTER_INFO: 2544 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 2545 break; 2546 default: 2547 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 2548 ret = -EINVAL; 2549 break; 2550 } 2551 return ret; 2552 2553 free_filter: 2554 filter->fw_l2_filter_id = -1; 2555 bnxt_free_filter(bp, filter); 2556 return ret; 2557 } 2558 2559 static int 2560 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 2561 enum rte_filter_type filter_type, 2562 enum rte_filter_op filter_op, void *arg) 2563 { 2564 int ret = 0; 2565 2566 switch (filter_type) { 2567 case RTE_ETH_FILTER_TUNNEL: 2568 PMD_DRV_LOG(ERR, 2569 "filter type: %d: To be implemented\n", filter_type); 2570 break; 2571 case RTE_ETH_FILTER_FDIR: 2572 ret = bnxt_fdir_filter(dev, filter_op, arg); 2573 break; 2574 case RTE_ETH_FILTER_NTUPLE: 2575 ret = bnxt_ntuple_filter(dev, filter_op, arg); 2576 break; 2577 case RTE_ETH_FILTER_ETHERTYPE: 2578 ret = bnxt_ethertype_filter(dev, filter_op, arg); 2579 break; 2580 case RTE_ETH_FILTER_GENERIC: 2581 if (filter_op != RTE_ETH_FILTER_GET) 2582 return -EINVAL; 2583 *(const void **)arg = &bnxt_flow_ops; 2584 break; 2585 default: 2586 PMD_DRV_LOG(ERR, 2587 "Filter type (%d) not supported", filter_type); 2588 ret = -EINVAL; 2589 break; 2590 } 2591 return ret; 2592 } 2593 2594 static const uint32_t * 2595 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 2596 { 2597 static const uint32_t ptypes[] = { 2598 RTE_PTYPE_L2_ETHER_VLAN, 2599 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2600 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2601 RTE_PTYPE_L4_ICMP, 2602 RTE_PTYPE_L4_TCP, 2603 RTE_PTYPE_L4_UDP, 2604 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2605 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2606 RTE_PTYPE_INNER_L4_ICMP, 2607 RTE_PTYPE_INNER_L4_TCP, 2608 RTE_PTYPE_INNER_L4_UDP, 2609 RTE_PTYPE_UNKNOWN 2610 }; 2611 2612 if (dev->rx_pkt_burst == bnxt_recv_pkts) 2613 return ptypes; 2614 return NULL; 2615 } 2616 2617 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 2618 int reg_win) 2619 { 2620 uint32_t reg_base = *reg_arr & 0xfffff000; 2621 uint32_t win_off; 2622 int i; 2623 2624 for (i = 0; i < count; i++) { 2625 if ((reg_arr[i] & 0xfffff000) != reg_base) 2626 return -ERANGE; 2627 } 2628 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 2629 rte_cpu_to_le_32(rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off)); 2630 return 0; 2631 } 2632 2633 static int bnxt_map_ptp_regs(struct bnxt *bp) 2634 { 2635 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2636 uint32_t *reg_arr; 2637 int rc, i; 2638 2639 reg_arr = ptp->rx_regs; 2640 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 2641 if (rc) 2642 return rc; 2643 2644 reg_arr = ptp->tx_regs; 2645 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 2646 if (rc) 2647 return rc; 2648 2649 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 2650 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 2651 2652 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 2653 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 2654 2655 return 0; 2656 } 2657 2658 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 2659 { 2660 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 + 2661 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16)); 2662 rte_cpu_to_le_32(rte_write32(0, (uint8_t *)bp->bar0 + 2663 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20)); 2664 } 2665 2666 static uint64_t bnxt_cc_read(struct bnxt *bp) 2667 { 2668 uint64_t ns; 2669 2670 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2671 BNXT_GRCPF_REG_SYNC_TIME)); 2672 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2673 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 2674 return ns; 2675 } 2676 2677 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 2678 { 2679 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2680 uint32_t fifo; 2681 2682 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2683 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2684 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 2685 return -EAGAIN; 2686 2687 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2688 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2689 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2690 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 2691 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2692 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 2693 2694 return 0; 2695 } 2696 2697 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 2698 { 2699 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2700 struct bnxt_pf_info *pf = &bp->pf; 2701 uint16_t port_id; 2702 uint32_t fifo; 2703 2704 if (!ptp) 2705 return -ENODEV; 2706 2707 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2708 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2709 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 2710 return -EAGAIN; 2711 2712 port_id = pf->port_id; 2713 rte_cpu_to_le_32(rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 2714 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV])); 2715 2716 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2717 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2718 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 2719 /* bnxt_clr_rx_ts(bp); TBD */ 2720 return -EBUSY; 2721 } 2722 2723 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2724 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 2725 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2726 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 2727 2728 return 0; 2729 } 2730 2731 static int 2732 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 2733 { 2734 uint64_t ns; 2735 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2736 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2737 2738 if (!ptp) 2739 return 0; 2740 2741 ns = rte_timespec_to_ns(ts); 2742 /* Set the timecounters to a new value. */ 2743 ptp->tc.nsec = ns; 2744 2745 return 0; 2746 } 2747 2748 static int 2749 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 2750 { 2751 uint64_t ns, systime_cycles; 2752 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2753 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2754 2755 if (!ptp) 2756 return 0; 2757 2758 systime_cycles = bnxt_cc_read(bp); 2759 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 2760 *ts = rte_ns_to_timespec(ns); 2761 2762 return 0; 2763 } 2764 static int 2765 bnxt_timesync_enable(struct rte_eth_dev *dev) 2766 { 2767 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2768 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2769 uint32_t shift = 0; 2770 2771 if (!ptp) 2772 return 0; 2773 2774 ptp->rx_filter = 1; 2775 ptp->tx_tstamp_en = 1; 2776 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 2777 2778 if (!bnxt_hwrm_ptp_cfg(bp)) 2779 bnxt_map_ptp_regs(bp); 2780 2781 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 2782 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 2783 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 2784 2785 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2786 ptp->tc.cc_shift = shift; 2787 ptp->tc.nsec_mask = (1ULL << shift) - 1; 2788 2789 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2790 ptp->rx_tstamp_tc.cc_shift = shift; 2791 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 2792 2793 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2794 ptp->tx_tstamp_tc.cc_shift = shift; 2795 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 2796 2797 return 0; 2798 } 2799 2800 static int 2801 bnxt_timesync_disable(struct rte_eth_dev *dev) 2802 { 2803 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2804 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2805 2806 if (!ptp) 2807 return 0; 2808 2809 ptp->rx_filter = 0; 2810 ptp->tx_tstamp_en = 0; 2811 ptp->rxctl = 0; 2812 2813 bnxt_hwrm_ptp_cfg(bp); 2814 2815 bnxt_unmap_ptp_regs(bp); 2816 2817 return 0; 2818 } 2819 2820 static int 2821 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 2822 struct timespec *timestamp, 2823 uint32_t flags __rte_unused) 2824 { 2825 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2826 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2827 uint64_t rx_tstamp_cycles = 0; 2828 uint64_t ns; 2829 2830 if (!ptp) 2831 return 0; 2832 2833 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 2834 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 2835 *timestamp = rte_ns_to_timespec(ns); 2836 return 0; 2837 } 2838 2839 static int 2840 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 2841 struct timespec *timestamp) 2842 { 2843 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2844 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2845 uint64_t tx_tstamp_cycles = 0; 2846 uint64_t ns; 2847 2848 if (!ptp) 2849 return 0; 2850 2851 bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 2852 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 2853 *timestamp = rte_ns_to_timespec(ns); 2854 2855 return 0; 2856 } 2857 2858 static int 2859 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 2860 { 2861 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2862 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2863 2864 if (!ptp) 2865 return 0; 2866 2867 ptp->tc.nsec += delta; 2868 2869 return 0; 2870 } 2871 2872 static int 2873 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 2874 { 2875 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2876 int rc; 2877 uint32_t dir_entries; 2878 uint32_t entry_length; 2879 2880 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 2881 bp->pdev->addr.domain, bp->pdev->addr.bus, 2882 bp->pdev->addr.devid, bp->pdev->addr.function); 2883 2884 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 2885 if (rc != 0) 2886 return rc; 2887 2888 return dir_entries * entry_length; 2889 } 2890 2891 static int 2892 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 2893 struct rte_dev_eeprom_info *in_eeprom) 2894 { 2895 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2896 uint32_t index; 2897 uint32_t offset; 2898 2899 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 2900 "len = %d\n", bp->pdev->addr.domain, 2901 bp->pdev->addr.bus, bp->pdev->addr.devid, 2902 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2903 2904 if (in_eeprom->offset == 0) /* special offset value to get directory */ 2905 return bnxt_get_nvram_directory(bp, in_eeprom->length, 2906 in_eeprom->data); 2907 2908 index = in_eeprom->offset >> 24; 2909 offset = in_eeprom->offset & 0xffffff; 2910 2911 if (index != 0) 2912 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 2913 in_eeprom->length, in_eeprom->data); 2914 2915 return 0; 2916 } 2917 2918 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 2919 { 2920 switch (dir_type) { 2921 case BNX_DIR_TYPE_CHIMP_PATCH: 2922 case BNX_DIR_TYPE_BOOTCODE: 2923 case BNX_DIR_TYPE_BOOTCODE_2: 2924 case BNX_DIR_TYPE_APE_FW: 2925 case BNX_DIR_TYPE_APE_PATCH: 2926 case BNX_DIR_TYPE_KONG_FW: 2927 case BNX_DIR_TYPE_KONG_PATCH: 2928 case BNX_DIR_TYPE_BONO_FW: 2929 case BNX_DIR_TYPE_BONO_PATCH: 2930 /* FALLTHROUGH */ 2931 return true; 2932 } 2933 2934 return false; 2935 } 2936 2937 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 2938 { 2939 switch (dir_type) { 2940 case BNX_DIR_TYPE_AVS: 2941 case BNX_DIR_TYPE_EXP_ROM_MBA: 2942 case BNX_DIR_TYPE_PCIE: 2943 case BNX_DIR_TYPE_TSCF_UCODE: 2944 case BNX_DIR_TYPE_EXT_PHY: 2945 case BNX_DIR_TYPE_CCM: 2946 case BNX_DIR_TYPE_ISCSI_BOOT: 2947 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2948 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2949 /* FALLTHROUGH */ 2950 return true; 2951 } 2952 2953 return false; 2954 } 2955 2956 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 2957 { 2958 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2959 bnxt_dir_type_is_other_exec_format(dir_type); 2960 } 2961 2962 static int 2963 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 2964 struct rte_dev_eeprom_info *in_eeprom) 2965 { 2966 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2967 uint8_t index, dir_op; 2968 uint16_t type, ext, ordinal, attr; 2969 2970 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 2971 "len = %d\n", bp->pdev->addr.domain, 2972 bp->pdev->addr.bus, bp->pdev->addr.devid, 2973 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2974 2975 if (!BNXT_PF(bp)) { 2976 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 2977 return -EINVAL; 2978 } 2979 2980 type = in_eeprom->magic >> 16; 2981 2982 if (type == 0xffff) { /* special value for directory operations */ 2983 index = in_eeprom->magic & 0xff; 2984 dir_op = in_eeprom->magic >> 8; 2985 if (index == 0) 2986 return -EINVAL; 2987 switch (dir_op) { 2988 case 0x0e: /* erase */ 2989 if (in_eeprom->offset != ~in_eeprom->magic) 2990 return -EINVAL; 2991 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 2992 default: 2993 return -EINVAL; 2994 } 2995 } 2996 2997 /* Create or re-write an NVM item: */ 2998 if (bnxt_dir_type_is_executable(type) == true) 2999 return -EOPNOTSUPP; 3000 ext = in_eeprom->magic & 0xffff; 3001 ordinal = in_eeprom->offset >> 16; 3002 attr = in_eeprom->offset & 0xffff; 3003 3004 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3005 in_eeprom->data, in_eeprom->length); 3006 return 0; 3007 } 3008 3009 /* 3010 * Initialization 3011 */ 3012 3013 static const struct eth_dev_ops bnxt_dev_ops = { 3014 .dev_infos_get = bnxt_dev_info_get_op, 3015 .dev_close = bnxt_dev_close_op, 3016 .dev_configure = bnxt_dev_configure_op, 3017 .dev_start = bnxt_dev_start_op, 3018 .dev_stop = bnxt_dev_stop_op, 3019 .dev_set_link_up = bnxt_dev_set_link_up_op, 3020 .dev_set_link_down = bnxt_dev_set_link_down_op, 3021 .stats_get = bnxt_stats_get_op, 3022 .stats_reset = bnxt_stats_reset_op, 3023 .rx_queue_setup = bnxt_rx_queue_setup_op, 3024 .rx_queue_release = bnxt_rx_queue_release_op, 3025 .tx_queue_setup = bnxt_tx_queue_setup_op, 3026 .tx_queue_release = bnxt_tx_queue_release_op, 3027 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3028 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3029 .reta_update = bnxt_reta_update_op, 3030 .reta_query = bnxt_reta_query_op, 3031 .rss_hash_update = bnxt_rss_hash_update_op, 3032 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3033 .link_update = bnxt_link_update_op, 3034 .promiscuous_enable = bnxt_promiscuous_enable_op, 3035 .promiscuous_disable = bnxt_promiscuous_disable_op, 3036 .allmulticast_enable = bnxt_allmulticast_enable_op, 3037 .allmulticast_disable = bnxt_allmulticast_disable_op, 3038 .mac_addr_add = bnxt_mac_addr_add_op, 3039 .mac_addr_remove = bnxt_mac_addr_remove_op, 3040 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3041 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3042 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3043 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3044 .vlan_filter_set = bnxt_vlan_filter_set_op, 3045 .vlan_offload_set = bnxt_vlan_offload_set_op, 3046 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3047 .mtu_set = bnxt_mtu_set_op, 3048 .mac_addr_set = bnxt_set_default_mac_addr_op, 3049 .xstats_get = bnxt_dev_xstats_get_op, 3050 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3051 .xstats_reset = bnxt_dev_xstats_reset_op, 3052 .fw_version_get = bnxt_fw_version_get, 3053 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3054 .rxq_info_get = bnxt_rxq_info_get_op, 3055 .txq_info_get = bnxt_txq_info_get_op, 3056 .dev_led_on = bnxt_dev_led_on_op, 3057 .dev_led_off = bnxt_dev_led_off_op, 3058 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3059 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3060 .rx_queue_count = bnxt_rx_queue_count_op, 3061 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3062 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3063 .rx_queue_start = bnxt_rx_queue_start, 3064 .rx_queue_stop = bnxt_rx_queue_stop, 3065 .tx_queue_start = bnxt_tx_queue_start, 3066 .tx_queue_stop = bnxt_tx_queue_stop, 3067 .filter_ctrl = bnxt_filter_ctrl_op, 3068 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3069 .get_eeprom_length = bnxt_get_eeprom_length_op, 3070 .get_eeprom = bnxt_get_eeprom_op, 3071 .set_eeprom = bnxt_set_eeprom_op, 3072 .timesync_enable = bnxt_timesync_enable, 3073 .timesync_disable = bnxt_timesync_disable, 3074 .timesync_read_time = bnxt_timesync_read_time, 3075 .timesync_write_time = bnxt_timesync_write_time, 3076 .timesync_adjust_time = bnxt_timesync_adjust_time, 3077 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3078 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3079 }; 3080 3081 static bool bnxt_vf_pciid(uint16_t id) 3082 { 3083 if (id == BROADCOM_DEV_ID_57304_VF || 3084 id == BROADCOM_DEV_ID_57406_VF || 3085 id == BROADCOM_DEV_ID_5731X_VF || 3086 id == BROADCOM_DEV_ID_5741X_VF || 3087 id == BROADCOM_DEV_ID_57414_VF || 3088 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3089 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 || 3090 id == BROADCOM_DEV_ID_58802_VF) 3091 return true; 3092 return false; 3093 } 3094 3095 bool bnxt_stratus_device(struct bnxt *bp) 3096 { 3097 uint16_t id = bp->pdev->id.device_id; 3098 3099 if (id == BROADCOM_DEV_ID_STRATUS_NIC || 3100 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3101 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2) 3102 return true; 3103 return false; 3104 } 3105 3106 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 3107 { 3108 struct bnxt *bp = eth_dev->data->dev_private; 3109 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3110 int rc; 3111 3112 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 3113 if (!pci_dev->mem_resource[0].addr) { 3114 PMD_DRV_LOG(ERR, 3115 "Cannot find PCI device base address, aborting\n"); 3116 rc = -ENODEV; 3117 goto init_err_disable; 3118 } 3119 3120 bp->eth_dev = eth_dev; 3121 bp->pdev = pci_dev; 3122 3123 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 3124 if (!bp->bar0) { 3125 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n"); 3126 rc = -ENOMEM; 3127 goto init_err_release; 3128 } 3129 3130 if (!pci_dev->mem_resource[2].addr) { 3131 PMD_DRV_LOG(ERR, 3132 "Cannot find PCI device BAR 2 address, aborting\n"); 3133 rc = -ENODEV; 3134 goto init_err_release; 3135 } else { 3136 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 3137 } 3138 3139 return 0; 3140 3141 init_err_release: 3142 if (bp->bar0) 3143 bp->bar0 = NULL; 3144 if (bp->doorbell_base) 3145 bp->doorbell_base = NULL; 3146 3147 init_err_disable: 3148 3149 return rc; 3150 } 3151 3152 3153 #define ALLOW_FUNC(x) \ 3154 { \ 3155 typeof(x) arg = (x); \ 3156 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 3157 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 3158 } 3159 static int 3160 bnxt_dev_init(struct rte_eth_dev *eth_dev) 3161 { 3162 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3163 char mz_name[RTE_MEMZONE_NAMESIZE]; 3164 const struct rte_memzone *mz = NULL; 3165 static int version_printed; 3166 uint32_t total_alloc_len; 3167 rte_iova_t mz_phys_addr; 3168 struct bnxt *bp; 3169 int rc; 3170 3171 if (version_printed++ == 0) 3172 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 3173 3174 rte_eth_copy_pci_info(eth_dev, pci_dev); 3175 3176 bp = eth_dev->data->dev_private; 3177 3178 bp->dev_stopped = 1; 3179 3180 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3181 goto skip_init; 3182 3183 if (bnxt_vf_pciid(pci_dev->id.device_id)) 3184 bp->flags |= BNXT_FLAG_VF; 3185 3186 rc = bnxt_init_board(eth_dev); 3187 if (rc) { 3188 PMD_DRV_LOG(ERR, 3189 "Board initialization failed rc: %x\n", rc); 3190 goto error; 3191 } 3192 skip_init: 3193 eth_dev->dev_ops = &bnxt_dev_ops; 3194 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 3195 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 3196 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3197 return 0; 3198 3199 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) { 3200 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3201 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 3202 pci_dev->addr.bus, pci_dev->addr.devid, 3203 pci_dev->addr.function, "rx_port_stats"); 3204 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3205 mz = rte_memzone_lookup(mz_name); 3206 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 3207 sizeof(struct rx_port_stats) + 512); 3208 if (!mz) { 3209 mz = rte_memzone_reserve(mz_name, total_alloc_len, 3210 SOCKET_ID_ANY, 3211 RTE_MEMZONE_2MB | 3212 RTE_MEMZONE_SIZE_HINT_ONLY | 3213 RTE_MEMZONE_IOVA_CONTIG); 3214 if (mz == NULL) 3215 return -ENOMEM; 3216 } 3217 memset(mz->addr, 0, mz->len); 3218 mz_phys_addr = mz->iova; 3219 if ((unsigned long)mz->addr == mz_phys_addr) { 3220 PMD_DRV_LOG(WARNING, 3221 "Memzone physical address same as virtual.\n"); 3222 PMD_DRV_LOG(WARNING, 3223 "Using rte_mem_virt2iova()\n"); 3224 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3225 if (mz_phys_addr == 0) { 3226 PMD_DRV_LOG(ERR, 3227 "unable to map address to physical memory\n"); 3228 return -ENOMEM; 3229 } 3230 } 3231 3232 bp->rx_mem_zone = (const void *)mz; 3233 bp->hw_rx_port_stats = mz->addr; 3234 bp->hw_rx_port_stats_map = mz_phys_addr; 3235 3236 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3237 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 3238 pci_dev->addr.bus, pci_dev->addr.devid, 3239 pci_dev->addr.function, "tx_port_stats"); 3240 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3241 mz = rte_memzone_lookup(mz_name); 3242 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 3243 sizeof(struct tx_port_stats) + 512); 3244 if (!mz) { 3245 mz = rte_memzone_reserve(mz_name, 3246 total_alloc_len, 3247 SOCKET_ID_ANY, 3248 RTE_MEMZONE_2MB | 3249 RTE_MEMZONE_SIZE_HINT_ONLY | 3250 RTE_MEMZONE_IOVA_CONTIG); 3251 if (mz == NULL) 3252 return -ENOMEM; 3253 } 3254 memset(mz->addr, 0, mz->len); 3255 mz_phys_addr = mz->iova; 3256 if ((unsigned long)mz->addr == mz_phys_addr) { 3257 PMD_DRV_LOG(WARNING, 3258 "Memzone physical address same as virtual.\n"); 3259 PMD_DRV_LOG(WARNING, 3260 "Using rte_mem_virt2iova()\n"); 3261 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3262 if (mz_phys_addr == 0) { 3263 PMD_DRV_LOG(ERR, 3264 "unable to map address to physical memory\n"); 3265 return -ENOMEM; 3266 } 3267 } 3268 3269 bp->tx_mem_zone = (const void *)mz; 3270 bp->hw_tx_port_stats = mz->addr; 3271 bp->hw_tx_port_stats_map = mz_phys_addr; 3272 3273 bp->flags |= BNXT_FLAG_PORT_STATS; 3274 } 3275 3276 rc = bnxt_alloc_hwrm_resources(bp); 3277 if (rc) { 3278 PMD_DRV_LOG(ERR, 3279 "hwrm resource allocation failure rc: %x\n", rc); 3280 goto error_free; 3281 } 3282 rc = bnxt_hwrm_ver_get(bp); 3283 if (rc) 3284 goto error_free; 3285 rc = bnxt_hwrm_queue_qportcfg(bp); 3286 if (rc) { 3287 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n"); 3288 goto error_free; 3289 } 3290 3291 rc = bnxt_hwrm_func_qcfg(bp); 3292 if (rc) { 3293 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n"); 3294 goto error_free; 3295 } 3296 3297 /* Get the MAX capabilities for this function */ 3298 rc = bnxt_hwrm_func_qcaps(bp); 3299 if (rc) { 3300 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc); 3301 goto error_free; 3302 } 3303 if (bp->max_tx_rings == 0) { 3304 PMD_DRV_LOG(ERR, "No TX rings available!\n"); 3305 rc = -EBUSY; 3306 goto error_free; 3307 } 3308 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 3309 ETHER_ADDR_LEN * bp->max_l2_ctx, 0); 3310 if (eth_dev->data->mac_addrs == NULL) { 3311 PMD_DRV_LOG(ERR, 3312 "Failed to alloc %u bytes needed to store MAC addr tbl", 3313 ETHER_ADDR_LEN * bp->max_l2_ctx); 3314 rc = -ENOMEM; 3315 goto error_free; 3316 } 3317 3318 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, ETHER_ADDR_LEN)) { 3319 PMD_DRV_LOG(ERR, 3320 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n", 3321 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1], 3322 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3], 3323 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]); 3324 rc = -EINVAL; 3325 goto error_free; 3326 } 3327 /* Copy the permanent MAC from the qcap response address now. */ 3328 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr)); 3329 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN); 3330 3331 if (bp->max_ring_grps < bp->rx_cp_nr_rings) { 3332 /* 1 ring is for default completion ring */ 3333 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n"); 3334 rc = -ENOSPC; 3335 goto error_free; 3336 } 3337 3338 bp->grp_info = rte_zmalloc("bnxt_grp_info", 3339 sizeof(*bp->grp_info) * bp->max_ring_grps, 0); 3340 if (!bp->grp_info) { 3341 PMD_DRV_LOG(ERR, 3342 "Failed to alloc %zu bytes to store group info table\n", 3343 sizeof(*bp->grp_info) * bp->max_ring_grps); 3344 rc = -ENOMEM; 3345 goto error_free; 3346 } 3347 3348 /* Forward all requests if firmware is new enough */ 3349 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 3350 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 3351 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 3352 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 3353 } else { 3354 PMD_DRV_LOG(WARNING, 3355 "Firmware too old for VF mailbox functionality\n"); 3356 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 3357 } 3358 3359 /* 3360 * The following are used for driver cleanup. If we disallow these, 3361 * VF drivers can't clean up cleanly. 3362 */ 3363 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 3364 ALLOW_FUNC(HWRM_VNIC_FREE); 3365 ALLOW_FUNC(HWRM_RING_FREE); 3366 ALLOW_FUNC(HWRM_RING_GRP_FREE); 3367 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 3368 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 3369 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 3370 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 3371 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 3372 rc = bnxt_hwrm_func_driver_register(bp); 3373 if (rc) { 3374 PMD_DRV_LOG(ERR, 3375 "Failed to register driver"); 3376 rc = -EBUSY; 3377 goto error_free; 3378 } 3379 3380 PMD_DRV_LOG(INFO, 3381 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n", 3382 pci_dev->mem_resource[0].phys_addr, 3383 pci_dev->mem_resource[0].addr); 3384 3385 rc = bnxt_hwrm_func_reset(bp); 3386 if (rc) { 3387 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc); 3388 rc = -EIO; 3389 goto error_free; 3390 } 3391 3392 if (BNXT_PF(bp)) { 3393 //if (bp->pf.active_vfs) { 3394 // TODO: Deallocate VF resources? 3395 //} 3396 if (bp->pdev->max_vfs) { 3397 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 3398 if (rc) { 3399 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 3400 goto error_free; 3401 } 3402 } else { 3403 rc = bnxt_hwrm_allocate_pf_only(bp); 3404 if (rc) { 3405 PMD_DRV_LOG(ERR, 3406 "Failed to allocate PF resources\n"); 3407 goto error_free; 3408 } 3409 } 3410 } 3411 3412 bnxt_hwrm_port_led_qcaps(bp); 3413 3414 rc = bnxt_setup_int(bp); 3415 if (rc) 3416 goto error_free; 3417 3418 rc = bnxt_alloc_mem(bp); 3419 if (rc) 3420 goto error_free_int; 3421 3422 rc = bnxt_request_int(bp); 3423 if (rc) 3424 goto error_free_int; 3425 3426 bnxt_enable_int(bp); 3427 bnxt_init_nic(bp); 3428 3429 return 0; 3430 3431 error_free_int: 3432 bnxt_disable_int(bp); 3433 bnxt_hwrm_func_buf_unrgtr(bp); 3434 bnxt_free_int(bp); 3435 bnxt_free_mem(bp); 3436 error_free: 3437 bnxt_dev_uninit(eth_dev); 3438 error: 3439 return rc; 3440 } 3441 3442 static int 3443 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 3444 { 3445 struct bnxt *bp = eth_dev->data->dev_private; 3446 int rc; 3447 3448 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3449 return -EPERM; 3450 3451 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 3452 bnxt_disable_int(bp); 3453 bnxt_free_int(bp); 3454 bnxt_free_mem(bp); 3455 if (eth_dev->data->mac_addrs != NULL) { 3456 rte_free(eth_dev->data->mac_addrs); 3457 eth_dev->data->mac_addrs = NULL; 3458 } 3459 if (bp->grp_info != NULL) { 3460 rte_free(bp->grp_info); 3461 bp->grp_info = NULL; 3462 } 3463 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 3464 bnxt_free_hwrm_resources(bp); 3465 3466 if (bp->tx_mem_zone) { 3467 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 3468 bp->tx_mem_zone = NULL; 3469 } 3470 3471 if (bp->rx_mem_zone) { 3472 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 3473 bp->rx_mem_zone = NULL; 3474 } 3475 3476 if (bp->dev_stopped == 0) 3477 bnxt_dev_close_op(eth_dev); 3478 if (bp->pf.vf_info) 3479 rte_free(bp->pf.vf_info); 3480 eth_dev->dev_ops = NULL; 3481 eth_dev->rx_pkt_burst = NULL; 3482 eth_dev->tx_pkt_burst = NULL; 3483 3484 return rc; 3485 } 3486 3487 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3488 struct rte_pci_device *pci_dev) 3489 { 3490 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 3491 bnxt_dev_init); 3492 } 3493 3494 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 3495 { 3496 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit); 3497 } 3498 3499 static struct rte_pci_driver bnxt_rte_pmd = { 3500 .id_table = bnxt_pci_id_map, 3501 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 3502 RTE_PCI_DRV_INTR_LSC, 3503 .probe = bnxt_pci_probe, 3504 .remove = bnxt_pci_remove, 3505 }; 3506 3507 static bool 3508 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 3509 { 3510 if (strcmp(dev->device->driver->name, drv->driver.name)) 3511 return false; 3512 3513 return true; 3514 } 3515 3516 bool is_bnxt_supported(struct rte_eth_dev *dev) 3517 { 3518 return is_device_supported(dev, &bnxt_rte_pmd); 3519 } 3520 3521 RTE_INIT(bnxt_init_log); 3522 static void 3523 bnxt_init_log(void) 3524 { 3525 bnxt_logtype_driver = rte_log_register("pmd.bnxt.driver"); 3526 if (bnxt_logtype_driver >= 0) 3527 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_INFO); 3528 } 3529 3530 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 3531 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 3532 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 3533