1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_ACCUM_STATS "accum-stats" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 #define BNXT_DEVARG_APP_ID "app-id" 101 102 static const char *const bnxt_dev_args[] = { 103 BNXT_DEVARG_REPRESENTOR, 104 BNXT_DEVARG_ACCUM_STATS, 105 BNXT_DEVARG_FLOW_XSTAT, 106 BNXT_DEVARG_MAX_NUM_KFLOWS, 107 BNXT_DEVARG_REP_BASED_PF, 108 BNXT_DEVARG_REP_IS_PF, 109 BNXT_DEVARG_REP_Q_R2F, 110 BNXT_DEVARG_REP_Q_F2R, 111 BNXT_DEVARG_REP_FC_R2F, 112 BNXT_DEVARG_REP_FC_F2R, 113 BNXT_DEVARG_APP_ID, 114 NULL 115 }; 116 117 /* 118 * accum-stats == false to disable flow counter accumulation 119 * accum-stats == true to enable flow counter accumulation 120 */ 121 #define BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats) ((accum_stats) > 1) 122 123 /* 124 * app-id = an non-negative 8-bit number 125 */ 126 #define BNXT_DEVARG_APP_ID_INVALID(val) ((val) > 255) 127 128 /* 129 * flow_xstat == false to disable the feature 130 * flow_xstat == true to enable the feature 131 */ 132 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 133 134 /* 135 * rep_is_pf == false to indicate VF representor 136 * rep_is_pf == true to indicate PF representor 137 */ 138 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 139 140 /* 141 * rep_based_pf == Physical index of the PF 142 */ 143 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 144 /* 145 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 146 */ 147 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 148 149 /* 150 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 151 */ 152 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 153 154 /* 155 * rep_fc_r2f == Flow control for the representor to endpoint direction 156 */ 157 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 158 159 /* 160 * rep_fc_f2r == Flow control for the endpoint to representor direction 161 */ 162 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 163 164 int bnxt_cfa_code_dynfield_offset = -1; 165 166 /* 167 * max_num_kflows must be >= 32 168 * and must be a power-of-2 supported value 169 * return: 1 -> invalid 170 * 0 -> valid 171 */ 172 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 173 { 174 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 175 return 1; 176 return 0; 177 } 178 179 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 180 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 181 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 182 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 183 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 184 static int bnxt_restore_vlan_filters(struct bnxt *bp); 185 static void bnxt_dev_recover(void *arg); 186 static void bnxt_free_error_recovery_info(struct bnxt *bp); 187 static void bnxt_free_rep_info(struct bnxt *bp); 188 189 int is_bnxt_in_error(struct bnxt *bp) 190 { 191 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 192 return -EIO; 193 if (bp->flags & BNXT_FLAG_FW_RESET) 194 return -EBUSY; 195 196 return 0; 197 } 198 199 /***********************/ 200 201 /* 202 * High level utility functions 203 */ 204 205 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 206 { 207 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 208 BNXT_RSS_TBL_SIZE_P5); 209 210 if (!BNXT_CHIP_P5(bp)) 211 return 1; 212 213 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 214 BNXT_RSS_ENTRIES_PER_CTX_P5) / 215 BNXT_RSS_ENTRIES_PER_CTX_P5; 216 } 217 218 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 219 { 220 if (!BNXT_CHIP_P5(bp)) 221 return HW_HASH_INDEX_SIZE; 222 223 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 224 } 225 226 static void bnxt_free_parent_info(struct bnxt *bp) 227 { 228 rte_free(bp->parent); 229 bp->parent = NULL; 230 } 231 232 static void bnxt_free_pf_info(struct bnxt *bp) 233 { 234 rte_free(bp->pf); 235 bp->pf = NULL; 236 } 237 238 static void bnxt_free_link_info(struct bnxt *bp) 239 { 240 rte_free(bp->link_info); 241 bp->link_info = NULL; 242 } 243 244 static void bnxt_free_leds_info(struct bnxt *bp) 245 { 246 if (BNXT_VF(bp)) 247 return; 248 249 rte_free(bp->leds); 250 bp->leds = NULL; 251 } 252 253 static void bnxt_free_flow_stats_info(struct bnxt *bp) 254 { 255 rte_free(bp->flow_stat); 256 bp->flow_stat = NULL; 257 } 258 259 static void bnxt_free_cos_queues(struct bnxt *bp) 260 { 261 rte_free(bp->rx_cos_queue); 262 bp->rx_cos_queue = NULL; 263 rte_free(bp->tx_cos_queue); 264 bp->tx_cos_queue = NULL; 265 } 266 267 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 268 { 269 bnxt_free_filter_mem(bp); 270 bnxt_free_vnic_attributes(bp); 271 bnxt_free_vnic_mem(bp); 272 273 /* tx/rx rings are configured as part of *_queue_setup callbacks. 274 * If the number of rings change across fw update, 275 * we don't have much choice except to warn the user. 276 */ 277 if (!reconfig) { 278 bnxt_free_stats(bp); 279 bnxt_free_tx_rings(bp); 280 bnxt_free_rx_rings(bp); 281 } 282 bnxt_free_async_cp_ring(bp); 283 bnxt_free_rxtx_nq_ring(bp); 284 285 rte_free(bp->grp_info); 286 bp->grp_info = NULL; 287 } 288 289 static int bnxt_alloc_parent_info(struct bnxt *bp) 290 { 291 bp->parent = rte_zmalloc("bnxt_parent_info", 292 sizeof(struct bnxt_parent_info), 0); 293 if (bp->parent == NULL) 294 return -ENOMEM; 295 296 return 0; 297 } 298 299 static int bnxt_alloc_pf_info(struct bnxt *bp) 300 { 301 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 302 if (bp->pf == NULL) 303 return -ENOMEM; 304 305 return 0; 306 } 307 308 static int bnxt_alloc_link_info(struct bnxt *bp) 309 { 310 bp->link_info = 311 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 312 if (bp->link_info == NULL) 313 return -ENOMEM; 314 315 return 0; 316 } 317 318 static int bnxt_alloc_leds_info(struct bnxt *bp) 319 { 320 if (BNXT_VF(bp)) 321 return 0; 322 323 bp->leds = rte_zmalloc("bnxt_leds", 324 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 325 0); 326 if (bp->leds == NULL) 327 return -ENOMEM; 328 329 return 0; 330 } 331 332 static int bnxt_alloc_cos_queues(struct bnxt *bp) 333 { 334 bp->rx_cos_queue = 335 rte_zmalloc("bnxt_rx_cosq", 336 BNXT_COS_QUEUE_COUNT * 337 sizeof(struct bnxt_cos_queue_info), 338 0); 339 if (bp->rx_cos_queue == NULL) 340 return -ENOMEM; 341 342 bp->tx_cos_queue = 343 rte_zmalloc("bnxt_tx_cosq", 344 BNXT_COS_QUEUE_COUNT * 345 sizeof(struct bnxt_cos_queue_info), 346 0); 347 if (bp->tx_cos_queue == NULL) 348 return -ENOMEM; 349 350 return 0; 351 } 352 353 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 354 { 355 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 356 sizeof(struct bnxt_flow_stat_info), 0); 357 if (bp->flow_stat == NULL) 358 return -ENOMEM; 359 360 return 0; 361 } 362 363 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 364 { 365 int rc; 366 367 rc = bnxt_alloc_ring_grps(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_async_ring_struct(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_vnic_mem(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_vnic_attributes(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 rc = bnxt_alloc_filter_mem(bp); 384 if (rc) 385 goto alloc_mem_err; 386 387 rc = bnxt_alloc_async_cp_ring(bp); 388 if (rc) 389 goto alloc_mem_err; 390 391 rc = bnxt_alloc_rxtx_nq_ring(bp); 392 if (rc) 393 goto alloc_mem_err; 394 395 if (BNXT_FLOW_XSTATS_EN(bp)) { 396 rc = bnxt_alloc_flow_stats_info(bp); 397 if (rc) 398 goto alloc_mem_err; 399 } 400 401 return 0; 402 403 alloc_mem_err: 404 bnxt_free_mem(bp, reconfig); 405 return rc; 406 } 407 408 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 409 { 410 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 411 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 412 uint64_t rx_offloads = dev_conf->rxmode.offloads; 413 struct bnxt_rx_queue *rxq; 414 unsigned int j; 415 int rc; 416 417 rc = bnxt_vnic_grp_alloc(bp, vnic); 418 if (rc) 419 goto err_out; 420 421 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 422 vnic_id, vnic, vnic->fw_grp_ids); 423 424 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 425 if (rc) 426 goto err_out; 427 428 /* Alloc RSS context only if RSS mode is enabled */ 429 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) { 430 int j, nr_ctxs = bnxt_rss_ctxts(bp); 431 432 /* RSS table size in Thor is 512. 433 * Cap max Rx rings to same value 434 */ 435 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 436 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 437 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 438 goto err_out; 439 } 440 441 rc = 0; 442 for (j = 0; j < nr_ctxs; j++) { 443 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 444 if (rc) 445 break; 446 } 447 if (rc) { 448 PMD_DRV_LOG(ERR, 449 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 450 vnic_id, j, rc); 451 goto err_out; 452 } 453 vnic->num_lb_ctxts = nr_ctxs; 454 } 455 456 /* 457 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 458 * setting is not available at this time, it will not be 459 * configured correctly in the CFA. 460 */ 461 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 462 vnic->vlan_strip = true; 463 else 464 vnic->vlan_strip = false; 465 466 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 467 if (rc) 468 goto err_out; 469 470 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 471 if (rc) 472 goto err_out; 473 474 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 475 rxq = bp->eth_dev->data->rx_queues[j]; 476 477 PMD_DRV_LOG(DEBUG, 478 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 479 j, rxq->vnic, rxq->vnic->fw_grp_ids); 480 481 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 482 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 483 else 484 vnic->rx_queue_cnt++; 485 } 486 487 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 488 489 rc = bnxt_vnic_rss_configure(bp, vnic); 490 if (rc) 491 goto err_out; 492 493 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 494 495 rc = bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 496 (rx_offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) ? 497 true : false); 498 if (rc) 499 goto err_out; 500 501 return 0; 502 err_out: 503 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 504 vnic_id, rc); 505 return rc; 506 } 507 508 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 509 { 510 int rc = 0; 511 512 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 513 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 514 if (rc) 515 return rc; 516 517 PMD_DRV_LOG(DEBUG, 518 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 519 " rx_fc_in_tbl.ctx_id = %d\n", 520 bp->flow_stat->rx_fc_in_tbl.va, 521 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 522 bp->flow_stat->rx_fc_in_tbl.ctx_id); 523 524 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 525 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 526 if (rc) 527 return rc; 528 529 PMD_DRV_LOG(DEBUG, 530 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 531 " rx_fc_out_tbl.ctx_id = %d\n", 532 bp->flow_stat->rx_fc_out_tbl.va, 533 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 534 bp->flow_stat->rx_fc_out_tbl.ctx_id); 535 536 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 537 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 538 if (rc) 539 return rc; 540 541 PMD_DRV_LOG(DEBUG, 542 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 543 " tx_fc_in_tbl.ctx_id = %d\n", 544 bp->flow_stat->tx_fc_in_tbl.va, 545 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 546 bp->flow_stat->tx_fc_in_tbl.ctx_id); 547 548 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 549 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 550 if (rc) 551 return rc; 552 553 PMD_DRV_LOG(DEBUG, 554 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 555 " tx_fc_out_tbl.ctx_id = %d\n", 556 bp->flow_stat->tx_fc_out_tbl.va, 557 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 558 bp->flow_stat->tx_fc_out_tbl.ctx_id); 559 560 memset(bp->flow_stat->rx_fc_out_tbl.va, 561 0, 562 bp->flow_stat->rx_fc_out_tbl.size); 563 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 564 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 565 bp->flow_stat->rx_fc_out_tbl.ctx_id, 566 bp->flow_stat->max_fc, 567 true); 568 if (rc) 569 return rc; 570 571 memset(bp->flow_stat->tx_fc_out_tbl.va, 572 0, 573 bp->flow_stat->tx_fc_out_tbl.size); 574 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 575 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 576 bp->flow_stat->tx_fc_out_tbl.ctx_id, 577 bp->flow_stat->max_fc, 578 true); 579 580 return rc; 581 } 582 583 static int bnxt_alloc_ctx_mem_buf(struct bnxt *bp, char *type, size_t size, 584 struct bnxt_ctx_mem_buf_info *ctx) 585 { 586 if (!ctx) 587 return -EINVAL; 588 589 ctx->va = rte_zmalloc_socket(type, size, 0, 590 bp->eth_dev->device->numa_node); 591 if (ctx->va == NULL) 592 return -ENOMEM; 593 rte_mem_lock_page(ctx->va); 594 ctx->size = size; 595 ctx->dma = rte_mem_virt2iova(ctx->va); 596 if (ctx->dma == RTE_BAD_IOVA) 597 return -ENOMEM; 598 599 return 0; 600 } 601 602 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 603 { 604 struct rte_pci_device *pdev = bp->pdev; 605 char type[RTE_MEMZONE_NAMESIZE]; 606 uint16_t max_fc; 607 int rc = 0; 608 609 max_fc = bp->flow_stat->max_fc; 610 611 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 612 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 613 /* 4 bytes for each counter-id */ 614 rc = bnxt_alloc_ctx_mem_buf(bp, type, 615 max_fc * 4, 616 &bp->flow_stat->rx_fc_in_tbl); 617 if (rc) 618 return rc; 619 620 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 621 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 622 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 623 rc = bnxt_alloc_ctx_mem_buf(bp, type, 624 max_fc * 16, 625 &bp->flow_stat->rx_fc_out_tbl); 626 if (rc) 627 return rc; 628 629 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 630 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 631 /* 4 bytes for each counter-id */ 632 rc = bnxt_alloc_ctx_mem_buf(bp, type, 633 max_fc * 4, 634 &bp->flow_stat->tx_fc_in_tbl); 635 if (rc) 636 return rc; 637 638 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 639 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 640 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 641 rc = bnxt_alloc_ctx_mem_buf(bp, type, 642 max_fc * 16, 643 &bp->flow_stat->tx_fc_out_tbl); 644 if (rc) 645 return rc; 646 647 rc = bnxt_register_fc_ctx_mem(bp); 648 649 return rc; 650 } 651 652 static int bnxt_init_ctx_mem(struct bnxt *bp) 653 { 654 int rc = 0; 655 656 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 657 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 658 !BNXT_FLOW_XSTATS_EN(bp)) 659 return 0; 660 661 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 662 if (rc) 663 return rc; 664 665 rc = bnxt_init_fc_ctx_mem(bp); 666 667 return rc; 668 } 669 670 static int bnxt_update_phy_setting(struct bnxt *bp) 671 { 672 struct rte_eth_link new; 673 int rc; 674 675 rc = bnxt_get_hwrm_link_config(bp, &new); 676 if (rc) { 677 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 678 return rc; 679 } 680 681 /* 682 * On BCM957508-N2100 adapters, FW will not allow any user other 683 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 684 * always returns link up. Force phy update always in that case. 685 */ 686 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 687 rc = bnxt_set_hwrm_link_config(bp, true); 688 if (rc) { 689 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 690 return rc; 691 } 692 } 693 694 return rc; 695 } 696 697 static void bnxt_free_prev_ring_stats(struct bnxt *bp) 698 { 699 rte_free(bp->prev_rx_ring_stats); 700 rte_free(bp->prev_tx_ring_stats); 701 702 bp->prev_rx_ring_stats = NULL; 703 bp->prev_tx_ring_stats = NULL; 704 } 705 706 static int bnxt_alloc_prev_ring_stats(struct bnxt *bp) 707 { 708 bp->prev_rx_ring_stats = rte_zmalloc("bnxt_prev_rx_ring_stats", 709 sizeof(struct bnxt_ring_stats) * 710 bp->rx_cp_nr_rings, 711 0); 712 if (bp->prev_rx_ring_stats == NULL) 713 return -ENOMEM; 714 715 bp->prev_tx_ring_stats = rte_zmalloc("bnxt_prev_tx_ring_stats", 716 sizeof(struct bnxt_ring_stats) * 717 bp->tx_cp_nr_rings, 718 0); 719 if (bp->prev_tx_ring_stats == NULL) 720 goto error; 721 722 return 0; 723 724 error: 725 bnxt_free_prev_ring_stats(bp); 726 return -ENOMEM; 727 } 728 729 static int bnxt_start_nic(struct bnxt *bp) 730 { 731 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 732 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 733 uint32_t intr_vector = 0; 734 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 735 uint32_t vec = BNXT_MISC_VEC_ID; 736 unsigned int i, j; 737 int rc; 738 739 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) 740 bp->flags |= BNXT_FLAG_JUMBO; 741 else 742 bp->flags &= ~BNXT_FLAG_JUMBO; 743 744 /* THOR does not support ring groups. 745 * But we will use the array to save RSS context IDs. 746 */ 747 if (BNXT_CHIP_P5(bp)) 748 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 749 750 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 751 if (rc) { 752 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 753 goto err_out; 754 } 755 756 rc = bnxt_alloc_hwrm_rings(bp); 757 if (rc) { 758 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 759 goto err_out; 760 } 761 762 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 763 if (rc) { 764 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 765 goto err_out; 766 } 767 768 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 769 goto skip_cosq_cfg; 770 771 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 772 if (bp->rx_cos_queue[i].id != 0xff) { 773 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 774 775 if (!vnic) { 776 PMD_DRV_LOG(ERR, 777 "Num pools more than FW profile\n"); 778 rc = -EINVAL; 779 goto err_out; 780 } 781 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 782 bp->rx_cosq_cnt++; 783 } 784 } 785 786 skip_cosq_cfg: 787 rc = bnxt_mq_rx_configure(bp); 788 if (rc) { 789 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 790 goto err_out; 791 } 792 793 /* default vnic 0 */ 794 rc = bnxt_setup_one_vnic(bp, 0); 795 if (rc) 796 goto err_out; 797 /* VNIC configuration */ 798 if (BNXT_RFS_NEEDS_VNIC(bp)) { 799 for (i = 1; i < bp->nr_vnics; i++) { 800 rc = bnxt_setup_one_vnic(bp, i); 801 if (rc) 802 goto err_out; 803 } 804 } 805 806 for (j = 0; j < bp->tx_nr_rings; j++) { 807 struct bnxt_tx_queue *txq = bp->tx_queues[j]; 808 809 if (!txq->tx_deferred_start) { 810 bp->eth_dev->data->tx_queue_state[j] = 811 RTE_ETH_QUEUE_STATE_STARTED; 812 txq->tx_started = true; 813 } 814 } 815 816 for (j = 0; j < bp->rx_nr_rings; j++) { 817 struct bnxt_rx_queue *rxq = bp->rx_queues[j]; 818 819 if (!rxq->rx_deferred_start) { 820 bp->eth_dev->data->rx_queue_state[j] = 821 RTE_ETH_QUEUE_STATE_STARTED; 822 rxq->rx_started = true; 823 } 824 } 825 826 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 827 if (rc) { 828 PMD_DRV_LOG(ERR, 829 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 830 goto err_out; 831 } 832 833 /* check and configure queue intr-vector mapping */ 834 if ((rte_intr_cap_multiple(intr_handle) || 835 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 836 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 837 intr_vector = bp->eth_dev->data->nb_rx_queues; 838 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 839 if (intr_vector > bp->rx_cp_nr_rings) { 840 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 841 bp->rx_cp_nr_rings); 842 return -ENOTSUP; 843 } 844 rc = rte_intr_efd_enable(intr_handle, intr_vector); 845 if (rc) 846 return rc; 847 } 848 849 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 850 intr_handle->intr_vec = 851 rte_zmalloc("intr_vec", 852 bp->eth_dev->data->nb_rx_queues * 853 sizeof(int), 0); 854 if (intr_handle->intr_vec == NULL) { 855 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 856 " intr_vec", bp->eth_dev->data->nb_rx_queues); 857 rc = -ENOMEM; 858 goto err_out; 859 } 860 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 861 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 862 intr_handle->intr_vec, intr_handle->nb_efd, 863 intr_handle->max_intr); 864 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 865 queue_id++) { 866 intr_handle->intr_vec[queue_id] = 867 vec + BNXT_RX_VEC_START; 868 if (vec < base + intr_handle->nb_efd - 1) 869 vec++; 870 } 871 } 872 873 /* enable uio/vfio intr/eventfd mapping */ 874 rc = rte_intr_enable(intr_handle); 875 #ifndef RTE_EXEC_ENV_FREEBSD 876 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 877 if (rc) 878 goto err_out; 879 #endif 880 881 rc = bnxt_update_phy_setting(bp); 882 if (rc) 883 goto err_out; 884 885 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 886 if (!bp->mark_table) 887 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 888 889 return 0; 890 891 err_out: 892 /* Some of the error status returned by FW may not be from errno.h */ 893 if (rc > 0) 894 rc = -EIO; 895 896 return rc; 897 } 898 899 static int bnxt_shutdown_nic(struct bnxt *bp) 900 { 901 bnxt_free_all_hwrm_resources(bp); 902 bnxt_free_all_filters(bp); 903 bnxt_free_all_vnics(bp); 904 return 0; 905 } 906 907 /* 908 * Device configuration and status function 909 */ 910 911 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 912 { 913 uint32_t link_speed = 0; 914 uint32_t speed_capa = 0; 915 916 if (bp->link_info == NULL) 917 return 0; 918 919 link_speed = bp->link_info->support_speeds; 920 921 /* If PAM4 is configured, use PAM4 supported speed */ 922 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 923 link_speed = bp->link_info->support_pam4_speeds; 924 925 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 926 speed_capa |= RTE_ETH_LINK_SPEED_100M; 927 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 928 speed_capa |= RTE_ETH_LINK_SPEED_100M_HD; 929 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 930 speed_capa |= RTE_ETH_LINK_SPEED_1G; 931 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 932 speed_capa |= RTE_ETH_LINK_SPEED_2_5G; 933 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 934 speed_capa |= RTE_ETH_LINK_SPEED_10G; 935 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 936 speed_capa |= RTE_ETH_LINK_SPEED_20G; 937 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 938 speed_capa |= RTE_ETH_LINK_SPEED_25G; 939 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 940 speed_capa |= RTE_ETH_LINK_SPEED_40G; 941 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 942 speed_capa |= RTE_ETH_LINK_SPEED_50G; 943 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 944 speed_capa |= RTE_ETH_LINK_SPEED_100G; 945 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 946 speed_capa |= RTE_ETH_LINK_SPEED_50G; 947 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 948 speed_capa |= RTE_ETH_LINK_SPEED_100G; 949 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 950 speed_capa |= RTE_ETH_LINK_SPEED_200G; 951 952 if (bp->link_info->auto_mode == 953 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 954 speed_capa |= RTE_ETH_LINK_SPEED_FIXED; 955 956 return speed_capa; 957 } 958 959 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 960 struct rte_eth_dev_info *dev_info) 961 { 962 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 963 struct bnxt *bp = eth_dev->data->dev_private; 964 uint16_t max_vnics, i, j, vpool, vrxq; 965 unsigned int max_rx_rings; 966 int rc; 967 968 rc = is_bnxt_in_error(bp); 969 if (rc) 970 return rc; 971 972 /* MAC Specifics */ 973 dev_info->max_mac_addrs = bp->max_l2_ctx; 974 dev_info->max_hash_mac_addrs = 0; 975 976 /* PF/VF specifics */ 977 if (BNXT_PF(bp)) 978 dev_info->max_vfs = pdev->max_vfs; 979 980 max_rx_rings = bnxt_max_rings(bp); 981 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 982 dev_info->max_rx_queues = max_rx_rings; 983 dev_info->max_tx_queues = max_rx_rings; 984 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 985 dev_info->hash_key_size = HW_HASH_KEY_SIZE; 986 max_vnics = bp->max_vnics; 987 988 /* MTU specifics */ 989 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 990 dev_info->max_mtu = BNXT_MAX_MTU; 991 992 /* Fast path specifics */ 993 dev_info->min_rx_bufsize = 1; 994 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 995 996 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 997 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 998 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_TIMESTAMP; 999 if (bp->vnic_cap_flags & BNXT_VNIC_CAP_VLAN_RX_STRIP) 1000 dev_info->rx_offload_capa |= RTE_ETH_RX_OFFLOAD_VLAN_STRIP; 1001 dev_info->tx_queue_offload_capa = RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 1002 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 1003 dev_info->tx_queue_offload_capa; 1004 if (bp->fw_cap & BNXT_FW_CAP_VLAN_TX_INSERT) 1005 dev_info->tx_offload_capa |= RTE_ETH_TX_OFFLOAD_VLAN_INSERT; 1006 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 1007 1008 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 1009 dev_info->dev_capa = RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP | 1010 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP; 1011 1012 dev_info->default_rxconf = (struct rte_eth_rxconf) { 1013 .rx_thresh = { 1014 .pthresh = 8, 1015 .hthresh = 8, 1016 .wthresh = 0, 1017 }, 1018 .rx_free_thresh = 32, 1019 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 1020 }; 1021 1022 dev_info->default_txconf = (struct rte_eth_txconf) { 1023 .tx_thresh = { 1024 .pthresh = 32, 1025 .hthresh = 0, 1026 .wthresh = 0, 1027 }, 1028 .tx_free_thresh = 32, 1029 .tx_rs_thresh = 32, 1030 }; 1031 eth_dev->data->dev_conf.intr_conf.lsc = 1; 1032 1033 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1034 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 1035 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 1036 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 1037 1038 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 1039 dev_info->switch_info.name = eth_dev->device->name; 1040 dev_info->switch_info.domain_id = bp->switch_domain_id; 1041 dev_info->switch_info.port_id = 1042 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 1043 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 1044 } 1045 1046 /* 1047 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 1048 * need further investigation. 1049 */ 1050 1051 /* VMDq resources */ 1052 vpool = 64; /* RTE_ETH_64_POOLS */ 1053 vrxq = 128; /* RTE_ETH_VMDQ_DCB_NUM_QUEUES */ 1054 for (i = 0; i < 4; vpool >>= 1, i++) { 1055 if (max_vnics > vpool) { 1056 for (j = 0; j < 5; vrxq >>= 1, j++) { 1057 if (dev_info->max_rx_queues > vrxq) { 1058 if (vpool > vrxq) 1059 vpool = vrxq; 1060 goto found; 1061 } 1062 } 1063 /* Not enough resources to support VMDq */ 1064 break; 1065 } 1066 } 1067 /* Not enough resources to support VMDq */ 1068 vpool = 0; 1069 vrxq = 0; 1070 found: 1071 dev_info->max_vmdq_pools = vpool; 1072 dev_info->vmdq_queue_num = vrxq; 1073 1074 dev_info->vmdq_pool_base = 0; 1075 dev_info->vmdq_queue_base = 0; 1076 1077 return 0; 1078 } 1079 1080 /* Configure the device based on the configuration provided */ 1081 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1082 { 1083 struct bnxt *bp = eth_dev->data->dev_private; 1084 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1085 int rc; 1086 1087 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1088 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1089 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1090 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1091 1092 rc = is_bnxt_in_error(bp); 1093 if (rc) 1094 return rc; 1095 1096 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1097 rc = bnxt_hwrm_check_vf_rings(bp); 1098 if (rc) { 1099 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1100 return -ENOSPC; 1101 } 1102 1103 /* If a resource has already been allocated - in this case 1104 * it is the async completion ring, free it. Reallocate it after 1105 * resource reservation. This will ensure the resource counts 1106 * are calculated correctly. 1107 */ 1108 1109 pthread_mutex_lock(&bp->def_cp_lock); 1110 1111 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1112 bnxt_disable_int(bp); 1113 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1114 } 1115 1116 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1117 if (rc) { 1118 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1119 pthread_mutex_unlock(&bp->def_cp_lock); 1120 return -ENOSPC; 1121 } 1122 1123 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1124 rc = bnxt_alloc_async_cp_ring(bp); 1125 if (rc) { 1126 pthread_mutex_unlock(&bp->def_cp_lock); 1127 return rc; 1128 } 1129 bnxt_enable_int(bp); 1130 } 1131 1132 pthread_mutex_unlock(&bp->def_cp_lock); 1133 } 1134 1135 /* Inherit new configurations */ 1136 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1137 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1138 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1139 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1140 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1141 bp->max_stat_ctx) 1142 goto resource_error; 1143 1144 if (BNXT_HAS_RING_GRPS(bp) && 1145 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1146 goto resource_error; 1147 1148 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS) && 1149 bp->max_vnics < eth_dev->data->nb_rx_queues) 1150 goto resource_error; 1151 1152 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1153 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1154 1155 if (eth_dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) 1156 rx_offloads |= RTE_ETH_RX_OFFLOAD_RSS_HASH; 1157 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1158 1159 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1160 1161 return 0; 1162 1163 resource_error: 1164 PMD_DRV_LOG(ERR, 1165 "Insufficient resources to support requested config\n"); 1166 PMD_DRV_LOG(ERR, 1167 "Num Queues Requested: Tx %d, Rx %d\n", 1168 eth_dev->data->nb_tx_queues, 1169 eth_dev->data->nb_rx_queues); 1170 PMD_DRV_LOG(ERR, 1171 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1172 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1173 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1174 return -ENOSPC; 1175 } 1176 1177 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1178 { 1179 struct rte_eth_link *link = ð_dev->data->dev_link; 1180 1181 if (link->link_status) 1182 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1183 eth_dev->data->port_id, 1184 (uint32_t)link->link_speed, 1185 (link->link_duplex == RTE_ETH_LINK_FULL_DUPLEX) ? 1186 ("full-duplex") : ("half-duplex\n")); 1187 else 1188 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1189 eth_dev->data->port_id); 1190 } 1191 1192 /* 1193 * Determine whether the current configuration requires support for scattered 1194 * receive; return 1 if scattered receive is required and 0 if not. 1195 */ 1196 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1197 { 1198 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU; 1199 uint16_t buf_size; 1200 int i; 1201 1202 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_SCATTER) 1203 return 1; 1204 1205 if (eth_dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_TCP_LRO) 1206 return 1; 1207 1208 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1209 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1210 1211 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1212 RTE_PKTMBUF_HEADROOM); 1213 if (eth_dev->data->mtu + overhead > buf_size) 1214 return 1; 1215 } 1216 return 0; 1217 } 1218 1219 static eth_rx_burst_t 1220 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1221 { 1222 struct bnxt *bp = eth_dev->data->dev_private; 1223 1224 /* Disable vector mode RX for Stingray2 for now */ 1225 if (BNXT_CHIP_SR2(bp)) { 1226 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1227 return bnxt_recv_pkts; 1228 } 1229 1230 #if (defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64)) && \ 1231 !defined(RTE_LIBRTE_IEEE1588) 1232 1233 /* Vector mode receive cannot be enabled if scattered rx is in use. */ 1234 if (eth_dev->data->scattered_rx) 1235 goto use_scalar_rx; 1236 1237 /* 1238 * Vector mode receive cannot be enabled if Truflow is enabled or if 1239 * asynchronous completions and receive completions can be placed in 1240 * the same completion ring. 1241 */ 1242 if (BNXT_TRUFLOW_EN(bp) || !BNXT_NUM_ASYNC_CPR(bp)) 1243 goto use_scalar_rx; 1244 1245 /* 1246 * Vector mode receive cannot be enabled if any receive offloads outside 1247 * a limited subset have been enabled. 1248 */ 1249 if (eth_dev->data->dev_conf.rxmode.offloads & 1250 ~(RTE_ETH_RX_OFFLOAD_VLAN_STRIP | 1251 RTE_ETH_RX_OFFLOAD_KEEP_CRC | 1252 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 1253 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 1254 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 1255 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1256 RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM | 1257 RTE_ETH_RX_OFFLOAD_RSS_HASH | 1258 RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) 1259 goto use_scalar_rx; 1260 1261 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1262 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1263 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1264 PMD_DRV_LOG(INFO, 1265 "Using AVX2 vector mode receive for port %d\n", 1266 eth_dev->data->port_id); 1267 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1268 return bnxt_recv_pkts_vec_avx2; 1269 } 1270 #endif 1271 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1272 PMD_DRV_LOG(INFO, 1273 "Using SSE vector mode receive for port %d\n", 1274 eth_dev->data->port_id); 1275 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1276 return bnxt_recv_pkts_vec; 1277 } 1278 1279 use_scalar_rx: 1280 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1281 eth_dev->data->port_id); 1282 PMD_DRV_LOG(INFO, 1283 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1284 eth_dev->data->port_id, 1285 eth_dev->data->scattered_rx, 1286 eth_dev->data->dev_conf.rxmode.offloads); 1287 #endif 1288 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1289 return bnxt_recv_pkts; 1290 } 1291 1292 static eth_tx_burst_t 1293 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1294 { 1295 struct bnxt *bp = eth_dev->data->dev_private; 1296 1297 /* Disable vector mode TX for Stingray2 for now */ 1298 if (BNXT_CHIP_SR2(bp)) 1299 return bnxt_xmit_pkts; 1300 1301 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) && \ 1302 !defined(RTE_LIBRTE_IEEE1588) 1303 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1304 1305 /* 1306 * Vector mode transmit can be enabled only if not using scatter rx 1307 * or tx offloads. 1308 */ 1309 if (eth_dev->data->scattered_rx || 1310 (offloads & ~RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE) || 1311 BNXT_TRUFLOW_EN(bp)) 1312 goto use_scalar_tx; 1313 1314 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 1315 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_256 && 1316 rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1) { 1317 PMD_DRV_LOG(INFO, 1318 "Using AVX2 vector mode transmit for port %d\n", 1319 eth_dev->data->port_id); 1320 return bnxt_xmit_pkts_vec_avx2; 1321 } 1322 #endif 1323 if (rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1324 PMD_DRV_LOG(INFO, 1325 "Using SSE vector mode transmit for port %d\n", 1326 eth_dev->data->port_id); 1327 return bnxt_xmit_pkts_vec; 1328 } 1329 1330 use_scalar_tx: 1331 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1332 eth_dev->data->port_id); 1333 PMD_DRV_LOG(INFO, 1334 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1335 eth_dev->data->port_id, 1336 eth_dev->data->scattered_rx, 1337 offloads); 1338 #endif 1339 return bnxt_xmit_pkts; 1340 } 1341 1342 static int bnxt_handle_if_change_status(struct bnxt *bp) 1343 { 1344 int rc; 1345 1346 /* Since fw has undergone a reset and lost all contexts, 1347 * set fatal flag to not issue hwrm during cleanup 1348 */ 1349 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1350 bnxt_uninit_resources(bp, true); 1351 1352 /* clear fatal flag so that re-init happens */ 1353 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1354 rc = bnxt_init_resources(bp, true); 1355 1356 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1357 1358 return rc; 1359 } 1360 1361 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1362 { 1363 struct bnxt *bp = eth_dev->data->dev_private; 1364 int rc = 0; 1365 1366 if (!BNXT_SINGLE_PF(bp)) 1367 return -ENOTSUP; 1368 1369 if (!bp->link_info->link_up) 1370 rc = bnxt_set_hwrm_link_config(bp, true); 1371 if (!rc) 1372 eth_dev->data->dev_link.link_status = 1; 1373 1374 bnxt_print_link_info(eth_dev); 1375 return rc; 1376 } 1377 1378 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1379 { 1380 struct bnxt *bp = eth_dev->data->dev_private; 1381 1382 if (!BNXT_SINGLE_PF(bp)) 1383 return -ENOTSUP; 1384 1385 eth_dev->data->dev_link.link_status = 0; 1386 bnxt_set_hwrm_link_config(bp, false); 1387 bp->link_info->link_up = 0; 1388 1389 return 0; 1390 } 1391 1392 static void bnxt_free_switch_domain(struct bnxt *bp) 1393 { 1394 int rc = 0; 1395 1396 if (!(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp))) 1397 return; 1398 1399 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1400 if (rc) 1401 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1402 bp->switch_domain_id, rc); 1403 } 1404 1405 static void bnxt_ptp_get_current_time(void *arg) 1406 { 1407 struct bnxt *bp = arg; 1408 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1409 int rc; 1410 1411 rc = is_bnxt_in_error(bp); 1412 if (rc) 1413 return; 1414 1415 if (!ptp) 1416 return; 1417 1418 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1419 &ptp->current_time); 1420 1421 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1422 if (rc != 0) { 1423 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1424 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1425 } 1426 } 1427 1428 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1429 { 1430 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1431 int rc; 1432 1433 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1434 return 0; 1435 1436 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1437 &ptp->current_time); 1438 1439 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1440 return rc; 1441 } 1442 1443 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1444 { 1445 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1446 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1447 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1448 } 1449 } 1450 1451 static void bnxt_ptp_stop(struct bnxt *bp) 1452 { 1453 bnxt_cancel_ptp_alarm(bp); 1454 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1455 } 1456 1457 static int bnxt_ptp_start(struct bnxt *bp) 1458 { 1459 int rc; 1460 1461 rc = bnxt_schedule_ptp_alarm(bp); 1462 if (rc != 0) { 1463 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1464 } else { 1465 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1466 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1467 } 1468 1469 return rc; 1470 } 1471 1472 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1473 { 1474 struct bnxt *bp = eth_dev->data->dev_private; 1475 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1476 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1477 struct rte_eth_link link; 1478 int ret; 1479 1480 eth_dev->data->dev_started = 0; 1481 eth_dev->data->scattered_rx = 0; 1482 1483 /* Prevent crashes when queues are still in use */ 1484 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1485 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1486 1487 bnxt_disable_int(bp); 1488 1489 /* disable uio/vfio intr/eventfd mapping */ 1490 rte_intr_disable(intr_handle); 1491 1492 /* Stop the child representors for this device */ 1493 ret = bnxt_rep_stop_all(bp); 1494 if (ret != 0) 1495 return ret; 1496 1497 /* delete the bnxt ULP port details */ 1498 bnxt_ulp_port_deinit(bp); 1499 1500 bnxt_cancel_fw_health_check(bp); 1501 1502 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1503 bnxt_cancel_ptp_alarm(bp); 1504 1505 /* Do not bring link down during reset recovery */ 1506 if (!is_bnxt_in_error(bp)) { 1507 bnxt_dev_set_link_down_op(eth_dev); 1508 /* Wait for link to be reset */ 1509 if (BNXT_SINGLE_PF(bp)) 1510 rte_delay_ms(500); 1511 /* clear the recorded link status */ 1512 memset(&link, 0, sizeof(link)); 1513 rte_eth_linkstatus_set(eth_dev, &link); 1514 } 1515 1516 /* Clean queue intr-vector mapping */ 1517 rte_intr_efd_disable(intr_handle); 1518 if (intr_handle->intr_vec != NULL) { 1519 rte_free(intr_handle->intr_vec); 1520 intr_handle->intr_vec = NULL; 1521 } 1522 1523 bnxt_hwrm_port_clr_stats(bp); 1524 bnxt_free_tx_mbufs(bp); 1525 bnxt_free_rx_mbufs(bp); 1526 /* Process any remaining notifications in default completion queue */ 1527 bnxt_int_handler(eth_dev); 1528 bnxt_shutdown_nic(bp); 1529 bnxt_hwrm_if_change(bp, false); 1530 1531 bnxt_free_prev_ring_stats(bp); 1532 rte_free(bp->mark_table); 1533 bp->mark_table = NULL; 1534 1535 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1536 bp->rx_cosq_cnt = 0; 1537 /* All filters are deleted on a port stop. */ 1538 if (BNXT_FLOW_XSTATS_EN(bp)) 1539 bp->flow_stat->flow_count = 0; 1540 1541 return 0; 1542 } 1543 1544 /* Unload the driver, release resources */ 1545 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1546 { 1547 struct bnxt *bp = eth_dev->data->dev_private; 1548 1549 pthread_mutex_lock(&bp->err_recovery_lock); 1550 if (bp->flags & BNXT_FLAG_FW_RESET) { 1551 PMD_DRV_LOG(ERR, 1552 "Adapter recovering from error..Please retry\n"); 1553 pthread_mutex_unlock(&bp->err_recovery_lock); 1554 return -EAGAIN; 1555 } 1556 pthread_mutex_unlock(&bp->err_recovery_lock); 1557 1558 return bnxt_dev_stop(eth_dev); 1559 } 1560 1561 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1562 { 1563 struct bnxt *bp = eth_dev->data->dev_private; 1564 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1565 int vlan_mask = 0; 1566 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1567 1568 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1569 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1570 return -EINVAL; 1571 } 1572 1573 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1574 PMD_DRV_LOG(ERR, 1575 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1576 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1577 1578 do { 1579 rc = bnxt_hwrm_if_change(bp, true); 1580 if (rc == 0 || rc != -EAGAIN) 1581 break; 1582 1583 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1584 } while (retry_cnt--); 1585 1586 if (rc) 1587 return rc; 1588 1589 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1590 rc = bnxt_handle_if_change_status(bp); 1591 if (rc) 1592 return rc; 1593 } 1594 1595 bnxt_enable_int(bp); 1596 1597 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1598 1599 rc = bnxt_start_nic(bp); 1600 if (rc) 1601 goto error; 1602 1603 rc = bnxt_alloc_prev_ring_stats(bp); 1604 if (rc) 1605 goto error; 1606 1607 eth_dev->data->dev_started = 1; 1608 1609 bnxt_link_update_op(eth_dev, 1); 1610 1611 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) 1612 vlan_mask |= RTE_ETH_VLAN_FILTER_MASK; 1613 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 1614 vlan_mask |= RTE_ETH_VLAN_STRIP_MASK; 1615 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1616 if (rc) 1617 goto error; 1618 1619 /* Initialize bnxt ULP port details */ 1620 rc = bnxt_ulp_port_init(bp); 1621 if (rc) 1622 goto error; 1623 1624 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1625 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1626 1627 bnxt_schedule_fw_health_check(bp); 1628 1629 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1630 bnxt_schedule_ptp_alarm(bp); 1631 1632 return 0; 1633 1634 error: 1635 bnxt_dev_stop(eth_dev); 1636 return rc; 1637 } 1638 1639 static void 1640 bnxt_uninit_locks(struct bnxt *bp) 1641 { 1642 pthread_mutex_destroy(&bp->flow_lock); 1643 pthread_mutex_destroy(&bp->def_cp_lock); 1644 pthread_mutex_destroy(&bp->health_check_lock); 1645 pthread_mutex_destroy(&bp->err_recovery_lock); 1646 if (bp->rep_info) { 1647 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1648 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1649 } 1650 } 1651 1652 static void bnxt_drv_uninit(struct bnxt *bp) 1653 { 1654 bnxt_free_leds_info(bp); 1655 bnxt_free_cos_queues(bp); 1656 bnxt_free_link_info(bp); 1657 bnxt_free_parent_info(bp); 1658 bnxt_uninit_locks(bp); 1659 1660 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1661 bp->tx_mem_zone = NULL; 1662 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1663 bp->rx_mem_zone = NULL; 1664 1665 bnxt_free_vf_info(bp); 1666 bnxt_free_pf_info(bp); 1667 1668 rte_free(bp->grp_info); 1669 bp->grp_info = NULL; 1670 } 1671 1672 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1673 { 1674 struct bnxt *bp = eth_dev->data->dev_private; 1675 int ret = 0; 1676 1677 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1678 return 0; 1679 1680 pthread_mutex_lock(&bp->err_recovery_lock); 1681 if (bp->flags & BNXT_FLAG_FW_RESET) { 1682 PMD_DRV_LOG(ERR, 1683 "Adapter recovering from error...Please retry\n"); 1684 pthread_mutex_unlock(&bp->err_recovery_lock); 1685 return -EAGAIN; 1686 } 1687 pthread_mutex_unlock(&bp->err_recovery_lock); 1688 1689 /* cancel the recovery handler before remove dev */ 1690 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1691 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1692 bnxt_cancel_fc_thread(bp); 1693 1694 if (eth_dev->data->dev_started) 1695 ret = bnxt_dev_stop(eth_dev); 1696 1697 bnxt_uninit_resources(bp, false); 1698 1699 bnxt_drv_uninit(bp); 1700 1701 return ret; 1702 } 1703 1704 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1705 uint32_t index) 1706 { 1707 struct bnxt *bp = eth_dev->data->dev_private; 1708 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1709 struct bnxt_vnic_info *vnic; 1710 struct bnxt_filter_info *filter, *temp_filter; 1711 uint32_t i; 1712 1713 if (is_bnxt_in_error(bp)) 1714 return; 1715 1716 /* 1717 * Loop through all VNICs from the specified filter flow pools to 1718 * remove the corresponding MAC addr filter 1719 */ 1720 for (i = 0; i < bp->nr_vnics; i++) { 1721 if (!(pool_mask & (1ULL << i))) 1722 continue; 1723 1724 vnic = &bp->vnic_info[i]; 1725 filter = STAILQ_FIRST(&vnic->filter); 1726 while (filter) { 1727 temp_filter = STAILQ_NEXT(filter, next); 1728 if (filter->mac_index == index) { 1729 STAILQ_REMOVE(&vnic->filter, filter, 1730 bnxt_filter_info, next); 1731 bnxt_hwrm_clear_l2_filter(bp, filter); 1732 bnxt_free_filter(bp, filter); 1733 } 1734 filter = temp_filter; 1735 } 1736 } 1737 } 1738 1739 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1740 struct rte_ether_addr *mac_addr, uint32_t index, 1741 uint32_t pool) 1742 { 1743 struct bnxt_filter_info *filter; 1744 int rc = 0; 1745 1746 /* Attach requested MAC address to the new l2_filter */ 1747 STAILQ_FOREACH(filter, &vnic->filter, next) { 1748 if (filter->mac_index == index) { 1749 PMD_DRV_LOG(DEBUG, 1750 "MAC addr already existed for pool %d\n", 1751 pool); 1752 return 0; 1753 } 1754 } 1755 1756 filter = bnxt_alloc_filter(bp); 1757 if (!filter) { 1758 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1759 return -ENODEV; 1760 } 1761 1762 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1763 * if the MAC that's been programmed now is a different one, then, 1764 * copy that addr to filter->l2_addr 1765 */ 1766 if (mac_addr) 1767 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1768 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1769 1770 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1771 if (!rc) { 1772 filter->mac_index = index; 1773 if (filter->mac_index == 0) 1774 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1775 else 1776 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1777 } else { 1778 bnxt_free_filter(bp, filter); 1779 } 1780 1781 return rc; 1782 } 1783 1784 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1785 struct rte_ether_addr *mac_addr, 1786 uint32_t index, uint32_t pool) 1787 { 1788 struct bnxt *bp = eth_dev->data->dev_private; 1789 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1790 int rc = 0; 1791 1792 rc = is_bnxt_in_error(bp); 1793 if (rc) 1794 return rc; 1795 1796 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1797 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1798 return -ENOTSUP; 1799 } 1800 1801 if (!vnic) { 1802 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1803 return -EINVAL; 1804 } 1805 1806 /* Filter settings will get applied when port is started */ 1807 if (!eth_dev->data->dev_started) 1808 return 0; 1809 1810 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1811 1812 return rc; 1813 } 1814 1815 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1816 { 1817 int rc = 0; 1818 struct bnxt *bp = eth_dev->data->dev_private; 1819 struct rte_eth_link new; 1820 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1821 BNXT_MIN_LINK_WAIT_CNT; 1822 1823 rc = is_bnxt_in_error(bp); 1824 if (rc) 1825 return rc; 1826 1827 memset(&new, 0, sizeof(new)); 1828 1829 if (bp->link_info == NULL) 1830 goto out; 1831 1832 do { 1833 /* Retrieve link info from hardware */ 1834 rc = bnxt_get_hwrm_link_config(bp, &new); 1835 if (rc) { 1836 new.link_speed = RTE_ETH_LINK_SPEED_100M; 1837 new.link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 1838 PMD_DRV_LOG(ERR, 1839 "Failed to retrieve link rc = 0x%x!\n", rc); 1840 goto out; 1841 } 1842 1843 if (!wait_to_complete || new.link_status) 1844 break; 1845 1846 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1847 } while (cnt--); 1848 1849 /* Only single function PF can bring phy down. 1850 * When port is stopped, report link down for VF/MH/NPAR functions. 1851 */ 1852 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1853 memset(&new, 0, sizeof(new)); 1854 1855 out: 1856 /* Timed out or success */ 1857 if (new.link_status != eth_dev->data->dev_link.link_status || 1858 new.link_speed != eth_dev->data->dev_link.link_speed) { 1859 rte_eth_linkstatus_set(eth_dev, &new); 1860 bnxt_print_link_info(eth_dev); 1861 } 1862 1863 return rc; 1864 } 1865 1866 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1867 { 1868 struct bnxt *bp = eth_dev->data->dev_private; 1869 struct bnxt_vnic_info *vnic; 1870 uint32_t old_flags; 1871 int rc; 1872 1873 rc = is_bnxt_in_error(bp); 1874 if (rc) 1875 return rc; 1876 1877 /* Filter settings will get applied when port is started */ 1878 if (!eth_dev->data->dev_started) 1879 return 0; 1880 1881 if (bp->vnic_info == NULL) 1882 return 0; 1883 1884 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1885 1886 old_flags = vnic->flags; 1887 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1888 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1889 if (rc != 0) 1890 vnic->flags = old_flags; 1891 1892 return rc; 1893 } 1894 1895 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1896 { 1897 struct bnxt *bp = eth_dev->data->dev_private; 1898 struct bnxt_vnic_info *vnic; 1899 uint32_t old_flags; 1900 int rc; 1901 1902 rc = is_bnxt_in_error(bp); 1903 if (rc) 1904 return rc; 1905 1906 /* Filter settings will get applied when port is started */ 1907 if (!eth_dev->data->dev_started) 1908 return 0; 1909 1910 if (bp->vnic_info == NULL) 1911 return 0; 1912 1913 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1914 1915 old_flags = vnic->flags; 1916 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1917 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1918 if (rc != 0) 1919 vnic->flags = old_flags; 1920 1921 return rc; 1922 } 1923 1924 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1925 { 1926 struct bnxt *bp = eth_dev->data->dev_private; 1927 struct bnxt_vnic_info *vnic; 1928 uint32_t old_flags; 1929 int rc; 1930 1931 rc = is_bnxt_in_error(bp); 1932 if (rc) 1933 return rc; 1934 1935 /* Filter settings will get applied when port is started */ 1936 if (!eth_dev->data->dev_started) 1937 return 0; 1938 1939 if (bp->vnic_info == NULL) 1940 return 0; 1941 1942 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1943 1944 old_flags = vnic->flags; 1945 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1946 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1947 if (rc != 0) 1948 vnic->flags = old_flags; 1949 1950 return rc; 1951 } 1952 1953 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1954 { 1955 struct bnxt *bp = eth_dev->data->dev_private; 1956 struct bnxt_vnic_info *vnic; 1957 uint32_t old_flags; 1958 int rc; 1959 1960 rc = is_bnxt_in_error(bp); 1961 if (rc) 1962 return rc; 1963 1964 /* Filter settings will get applied when port is started */ 1965 if (!eth_dev->data->dev_started) 1966 return 0; 1967 1968 if (bp->vnic_info == NULL) 1969 return 0; 1970 1971 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1972 1973 old_flags = vnic->flags; 1974 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1975 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1976 if (rc != 0) 1977 vnic->flags = old_flags; 1978 1979 return rc; 1980 } 1981 1982 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1983 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1984 { 1985 if (qid >= bp->rx_nr_rings) 1986 return NULL; 1987 1988 return bp->eth_dev->data->rx_queues[qid]; 1989 } 1990 1991 /* Return rxq corresponding to a given rss table ring/group ID. */ 1992 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1993 { 1994 struct bnxt_rx_queue *rxq; 1995 unsigned int i; 1996 1997 if (!BNXT_HAS_RING_GRPS(bp)) { 1998 for (i = 0; i < bp->rx_nr_rings; i++) { 1999 rxq = bp->eth_dev->data->rx_queues[i]; 2000 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 2001 return rxq->index; 2002 } 2003 } else { 2004 for (i = 0; i < bp->rx_nr_rings; i++) { 2005 if (bp->grp_info[i].fw_grp_id == fwr) 2006 return i; 2007 } 2008 } 2009 2010 return INVALID_HW_RING_ID; 2011 } 2012 2013 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 2014 struct rte_eth_rss_reta_entry64 *reta_conf, 2015 uint16_t reta_size) 2016 { 2017 struct bnxt *bp = eth_dev->data->dev_private; 2018 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2019 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2020 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2021 uint16_t idx, sft; 2022 int i, rc; 2023 2024 rc = is_bnxt_in_error(bp); 2025 if (rc) 2026 return rc; 2027 2028 if (!vnic->rss_table) 2029 return -EINVAL; 2030 2031 if (!(dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 2032 return -EINVAL; 2033 2034 if (reta_size != tbl_size) { 2035 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2036 "(%d) must equal the size supported by the hardware " 2037 "(%d)\n", reta_size, tbl_size); 2038 return -EINVAL; 2039 } 2040 2041 for (i = 0; i < reta_size; i++) { 2042 struct bnxt_rx_queue *rxq; 2043 2044 idx = i / RTE_ETH_RETA_GROUP_SIZE; 2045 sft = i % RTE_ETH_RETA_GROUP_SIZE; 2046 2047 if (!(reta_conf[idx].mask & (1ULL << sft))) 2048 continue; 2049 2050 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 2051 if (!rxq) { 2052 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 2053 return -EINVAL; 2054 } 2055 2056 if (BNXT_CHIP_P5(bp)) { 2057 vnic->rss_table[i * 2] = 2058 rxq->rx_ring->rx_ring_struct->fw_ring_id; 2059 vnic->rss_table[i * 2 + 1] = 2060 rxq->cp_ring->cp_ring_struct->fw_ring_id; 2061 } else { 2062 vnic->rss_table[i] = 2063 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 2064 } 2065 } 2066 2067 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2068 return rc; 2069 } 2070 2071 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 2072 struct rte_eth_rss_reta_entry64 *reta_conf, 2073 uint16_t reta_size) 2074 { 2075 struct bnxt *bp = eth_dev->data->dev_private; 2076 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2077 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 2078 uint16_t idx, sft, i; 2079 int rc; 2080 2081 rc = is_bnxt_in_error(bp); 2082 if (rc) 2083 return rc; 2084 2085 if (!vnic) 2086 return -EINVAL; 2087 if (!vnic->rss_table) 2088 return -EINVAL; 2089 2090 if (reta_size != tbl_size) { 2091 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 2092 "(%d) must equal the size supported by the hardware " 2093 "(%d)\n", reta_size, tbl_size); 2094 return -EINVAL; 2095 } 2096 2097 for (idx = 0, i = 0; i < reta_size; i++) { 2098 idx = i / RTE_ETH_RETA_GROUP_SIZE; 2099 sft = i % RTE_ETH_RETA_GROUP_SIZE; 2100 2101 if (reta_conf[idx].mask & (1ULL << sft)) { 2102 uint16_t qid; 2103 2104 if (BNXT_CHIP_P5(bp)) 2105 qid = bnxt_rss_to_qid(bp, 2106 vnic->rss_table[i * 2]); 2107 else 2108 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2109 2110 if (qid == INVALID_HW_RING_ID) { 2111 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2112 return -EINVAL; 2113 } 2114 reta_conf[idx].reta[sft] = qid; 2115 } 2116 } 2117 2118 return 0; 2119 } 2120 2121 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2122 struct rte_eth_rss_conf *rss_conf) 2123 { 2124 struct bnxt *bp = eth_dev->data->dev_private; 2125 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2126 struct bnxt_vnic_info *vnic; 2127 int rc; 2128 2129 rc = is_bnxt_in_error(bp); 2130 if (rc) 2131 return rc; 2132 2133 /* 2134 * If RSS enablement were different than dev_configure, 2135 * then return -EINVAL 2136 */ 2137 if (dev_conf->rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG) { 2138 if (!rss_conf->rss_hf) 2139 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2140 } else { 2141 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2142 return -EINVAL; 2143 } 2144 2145 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2146 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2147 rss_conf, 2148 sizeof(*rss_conf)); 2149 2150 /* Update the default RSS VNIC(s) */ 2151 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2152 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2153 vnic->hash_mode = 2154 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2155 RTE_ETH_RSS_LEVEL(rss_conf->rss_hf)); 2156 2157 /* 2158 * If hashkey is not specified, use the previously configured 2159 * hashkey 2160 */ 2161 if (!rss_conf->rss_key) 2162 goto rss_config; 2163 2164 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2165 PMD_DRV_LOG(ERR, 2166 "Invalid hashkey length, should be %d bytes\n", 2167 HW_HASH_KEY_SIZE); 2168 return -EINVAL; 2169 } 2170 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2171 2172 rss_config: 2173 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2174 return rc; 2175 } 2176 2177 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2178 struct rte_eth_rss_conf *rss_conf) 2179 { 2180 struct bnxt *bp = eth_dev->data->dev_private; 2181 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2182 int len, rc; 2183 uint32_t hash_types; 2184 2185 rc = is_bnxt_in_error(bp); 2186 if (rc) 2187 return rc; 2188 2189 /* RSS configuration is the same for all VNICs */ 2190 if (vnic && vnic->rss_hash_key) { 2191 if (rss_conf->rss_key) { 2192 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2193 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2194 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2195 } 2196 2197 hash_types = vnic->hash_type; 2198 rss_conf->rss_hf = 0; 2199 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2200 rss_conf->rss_hf |= RTE_ETH_RSS_IPV4; 2201 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2202 } 2203 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2204 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_TCP; 2205 hash_types &= 2206 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2207 } 2208 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2209 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV4_UDP; 2210 hash_types &= 2211 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2212 } 2213 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2214 rss_conf->rss_hf |= RTE_ETH_RSS_IPV6; 2215 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2216 } 2217 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2218 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_TCP; 2219 hash_types &= 2220 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2221 } 2222 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2223 rss_conf->rss_hf |= RTE_ETH_RSS_NONFRAG_IPV6_UDP; 2224 hash_types &= 2225 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2226 } 2227 2228 rss_conf->rss_hf |= 2229 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2230 2231 if (hash_types) { 2232 PMD_DRV_LOG(ERR, 2233 "Unknown RSS config from firmware (%08x), RSS disabled", 2234 vnic->hash_type); 2235 return -ENOTSUP; 2236 } 2237 } else { 2238 rss_conf->rss_hf = 0; 2239 } 2240 return 0; 2241 } 2242 2243 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2244 struct rte_eth_fc_conf *fc_conf) 2245 { 2246 struct bnxt *bp = dev->data->dev_private; 2247 struct rte_eth_link link_info; 2248 int rc; 2249 2250 rc = is_bnxt_in_error(bp); 2251 if (rc) 2252 return rc; 2253 2254 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2255 if (rc) 2256 return rc; 2257 2258 memset(fc_conf, 0, sizeof(*fc_conf)); 2259 if (bp->link_info->auto_pause) 2260 fc_conf->autoneg = 1; 2261 switch (bp->link_info->pause) { 2262 case 0: 2263 fc_conf->mode = RTE_ETH_FC_NONE; 2264 break; 2265 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2266 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 2267 break; 2268 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2269 fc_conf->mode = RTE_ETH_FC_RX_PAUSE; 2270 break; 2271 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2272 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2273 fc_conf->mode = RTE_ETH_FC_FULL; 2274 break; 2275 } 2276 return 0; 2277 } 2278 2279 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2280 struct rte_eth_fc_conf *fc_conf) 2281 { 2282 struct bnxt *bp = dev->data->dev_private; 2283 int rc; 2284 2285 rc = is_bnxt_in_error(bp); 2286 if (rc) 2287 return rc; 2288 2289 if (!BNXT_SINGLE_PF(bp)) { 2290 PMD_DRV_LOG(ERR, 2291 "Flow Control Settings cannot be modified on VF or on shared PF\n"); 2292 return -ENOTSUP; 2293 } 2294 2295 switch (fc_conf->mode) { 2296 case RTE_ETH_FC_NONE: 2297 bp->link_info->auto_pause = 0; 2298 bp->link_info->force_pause = 0; 2299 break; 2300 case RTE_ETH_FC_RX_PAUSE: 2301 if (fc_conf->autoneg) { 2302 bp->link_info->auto_pause = 2303 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2304 bp->link_info->force_pause = 0; 2305 } else { 2306 bp->link_info->auto_pause = 0; 2307 bp->link_info->force_pause = 2308 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2309 } 2310 break; 2311 case RTE_ETH_FC_TX_PAUSE: 2312 if (fc_conf->autoneg) { 2313 bp->link_info->auto_pause = 2314 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2315 bp->link_info->force_pause = 0; 2316 } else { 2317 bp->link_info->auto_pause = 0; 2318 bp->link_info->force_pause = 2319 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2320 } 2321 break; 2322 case RTE_ETH_FC_FULL: 2323 if (fc_conf->autoneg) { 2324 bp->link_info->auto_pause = 2325 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2326 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2327 bp->link_info->force_pause = 0; 2328 } else { 2329 bp->link_info->auto_pause = 0; 2330 bp->link_info->force_pause = 2331 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2332 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2333 } 2334 break; 2335 } 2336 return bnxt_set_hwrm_link_config(bp, true); 2337 } 2338 2339 /* Add UDP tunneling port */ 2340 static int 2341 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2342 struct rte_eth_udp_tunnel *udp_tunnel) 2343 { 2344 struct bnxt *bp = eth_dev->data->dev_private; 2345 uint16_t tunnel_type = 0; 2346 int rc = 0; 2347 2348 rc = is_bnxt_in_error(bp); 2349 if (rc) 2350 return rc; 2351 2352 switch (udp_tunnel->prot_type) { 2353 case RTE_ETH_TUNNEL_TYPE_VXLAN: 2354 if (bp->vxlan_port_cnt) { 2355 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2356 udp_tunnel->udp_port); 2357 if (bp->vxlan_port != udp_tunnel->udp_port) { 2358 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2359 return -ENOSPC; 2360 } 2361 bp->vxlan_port_cnt++; 2362 return 0; 2363 } 2364 tunnel_type = 2365 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2366 break; 2367 case RTE_ETH_TUNNEL_TYPE_GENEVE: 2368 if (bp->geneve_port_cnt) { 2369 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2370 udp_tunnel->udp_port); 2371 if (bp->geneve_port != udp_tunnel->udp_port) { 2372 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2373 return -ENOSPC; 2374 } 2375 bp->geneve_port_cnt++; 2376 return 0; 2377 } 2378 tunnel_type = 2379 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2380 break; 2381 default: 2382 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2383 return -ENOTSUP; 2384 } 2385 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2386 tunnel_type); 2387 2388 if (rc != 0) 2389 return rc; 2390 2391 if (tunnel_type == 2392 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN) 2393 bp->vxlan_port_cnt++; 2394 2395 if (tunnel_type == 2396 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE) 2397 bp->geneve_port_cnt++; 2398 2399 return rc; 2400 } 2401 2402 static int 2403 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2404 struct rte_eth_udp_tunnel *udp_tunnel) 2405 { 2406 struct bnxt *bp = eth_dev->data->dev_private; 2407 uint16_t tunnel_type = 0; 2408 uint16_t port = 0; 2409 int rc = 0; 2410 2411 rc = is_bnxt_in_error(bp); 2412 if (rc) 2413 return rc; 2414 2415 switch (udp_tunnel->prot_type) { 2416 case RTE_ETH_TUNNEL_TYPE_VXLAN: 2417 if (!bp->vxlan_port_cnt) { 2418 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2419 return -EINVAL; 2420 } 2421 if (bp->vxlan_port != udp_tunnel->udp_port) { 2422 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2423 udp_tunnel->udp_port, bp->vxlan_port); 2424 return -EINVAL; 2425 } 2426 if (--bp->vxlan_port_cnt) 2427 return 0; 2428 2429 tunnel_type = 2430 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2431 port = bp->vxlan_fw_dst_port_id; 2432 break; 2433 case RTE_ETH_TUNNEL_TYPE_GENEVE: 2434 if (!bp->geneve_port_cnt) { 2435 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2436 return -EINVAL; 2437 } 2438 if (bp->geneve_port != udp_tunnel->udp_port) { 2439 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2440 udp_tunnel->udp_port, bp->geneve_port); 2441 return -EINVAL; 2442 } 2443 if (--bp->geneve_port_cnt) 2444 return 0; 2445 2446 tunnel_type = 2447 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2448 port = bp->geneve_fw_dst_port_id; 2449 break; 2450 default: 2451 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2452 return -ENOTSUP; 2453 } 2454 2455 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2456 return rc; 2457 } 2458 2459 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2460 { 2461 struct bnxt_filter_info *filter; 2462 struct bnxt_vnic_info *vnic; 2463 int rc = 0; 2464 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2465 2466 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2467 filter = STAILQ_FIRST(&vnic->filter); 2468 while (filter) { 2469 /* Search for this matching MAC+VLAN filter */ 2470 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2471 /* Delete the filter */ 2472 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2473 if (rc) 2474 return rc; 2475 STAILQ_REMOVE(&vnic->filter, filter, 2476 bnxt_filter_info, next); 2477 bnxt_free_filter(bp, filter); 2478 PMD_DRV_LOG(INFO, 2479 "Deleted vlan filter for %d\n", 2480 vlan_id); 2481 return 0; 2482 } 2483 filter = STAILQ_NEXT(filter, next); 2484 } 2485 return -ENOENT; 2486 } 2487 2488 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2489 { 2490 struct bnxt_filter_info *filter; 2491 struct bnxt_vnic_info *vnic; 2492 int rc = 0; 2493 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2494 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2495 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2496 2497 /* Implementation notes on the use of VNIC in this command: 2498 * 2499 * By default, these filters belong to default vnic for the function. 2500 * Once these filters are set up, only destination VNIC can be modified. 2501 * If the destination VNIC is not specified in this command, 2502 * then the HWRM shall only create an l2 context id. 2503 */ 2504 2505 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2506 filter = STAILQ_FIRST(&vnic->filter); 2507 /* Check if the VLAN has already been added */ 2508 while (filter) { 2509 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2510 return -EEXIST; 2511 2512 filter = STAILQ_NEXT(filter, next); 2513 } 2514 2515 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2516 * command to create MAC+VLAN filter with the right flags, enables set. 2517 */ 2518 filter = bnxt_alloc_filter(bp); 2519 if (!filter) { 2520 PMD_DRV_LOG(ERR, 2521 "MAC/VLAN filter alloc failed\n"); 2522 return -ENOMEM; 2523 } 2524 /* MAC + VLAN ID filter */ 2525 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2526 * untagged packets are received 2527 * 2528 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2529 * packets and only the programmed vlan's packets are received 2530 */ 2531 filter->l2_ivlan = vlan_id; 2532 filter->l2_ivlan_mask = 0x0FFF; 2533 filter->enables |= en; 2534 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2535 2536 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2537 if (rc) { 2538 /* Free the newly allocated filter as we were 2539 * not able to create the filter in hardware. 2540 */ 2541 bnxt_free_filter(bp, filter); 2542 return rc; 2543 } 2544 2545 filter->mac_index = 0; 2546 /* Add this new filter to the list */ 2547 if (vlan_id == 0) 2548 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2549 else 2550 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2551 2552 PMD_DRV_LOG(INFO, 2553 "Added Vlan filter for %d\n", vlan_id); 2554 return rc; 2555 } 2556 2557 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2558 uint16_t vlan_id, int on) 2559 { 2560 struct bnxt *bp = eth_dev->data->dev_private; 2561 int rc; 2562 2563 rc = is_bnxt_in_error(bp); 2564 if (rc) 2565 return rc; 2566 2567 if (!eth_dev->data->dev_started) { 2568 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2569 return -EINVAL; 2570 } 2571 2572 /* These operations apply to ALL existing MAC/VLAN filters */ 2573 if (on) 2574 return bnxt_add_vlan_filter(bp, vlan_id); 2575 else 2576 return bnxt_del_vlan_filter(bp, vlan_id); 2577 } 2578 2579 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2580 struct bnxt_vnic_info *vnic) 2581 { 2582 struct bnxt_filter_info *filter; 2583 int rc; 2584 2585 filter = STAILQ_FIRST(&vnic->filter); 2586 while (filter) { 2587 if (filter->mac_index == 0 && 2588 !memcmp(filter->l2_addr, bp->mac_addr, 2589 RTE_ETHER_ADDR_LEN)) { 2590 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2591 if (!rc) { 2592 STAILQ_REMOVE(&vnic->filter, filter, 2593 bnxt_filter_info, next); 2594 bnxt_free_filter(bp, filter); 2595 } 2596 return rc; 2597 } 2598 filter = STAILQ_NEXT(filter, next); 2599 } 2600 return 0; 2601 } 2602 2603 static int 2604 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2605 { 2606 struct bnxt_vnic_info *vnic; 2607 unsigned int i; 2608 int rc; 2609 2610 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2611 if (!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)) { 2612 /* Remove any VLAN filters programmed */ 2613 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2614 bnxt_del_vlan_filter(bp, i); 2615 2616 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2617 if (rc) 2618 return rc; 2619 } else { 2620 /* Default filter will allow packets that match the 2621 * dest mac. So, it has to be deleted, otherwise, we 2622 * will endup receiving vlan packets for which the 2623 * filter is not programmed, when hw-vlan-filter 2624 * configuration is ON 2625 */ 2626 bnxt_del_dflt_mac_filter(bp, vnic); 2627 /* This filter will allow only untagged packets */ 2628 bnxt_add_vlan_filter(bp, 0); 2629 } 2630 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2631 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER)); 2632 2633 return 0; 2634 } 2635 2636 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2637 { 2638 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2639 unsigned int i; 2640 int rc; 2641 2642 /* Destroy vnic filters and vnic */ 2643 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2644 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 2645 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2646 bnxt_del_vlan_filter(bp, i); 2647 } 2648 bnxt_del_dflt_mac_filter(bp, vnic); 2649 2650 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2651 if (rc) 2652 return rc; 2653 2654 rc = bnxt_hwrm_vnic_free(bp, vnic); 2655 if (rc) 2656 return rc; 2657 2658 rte_free(vnic->fw_grp_ids); 2659 vnic->fw_grp_ids = NULL; 2660 2661 vnic->rx_queue_cnt = 0; 2662 2663 return 0; 2664 } 2665 2666 static int 2667 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2668 { 2669 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2670 int rc; 2671 2672 /* Destroy, recreate and reconfigure the default vnic */ 2673 rc = bnxt_free_one_vnic(bp, 0); 2674 if (rc) 2675 return rc; 2676 2677 /* default vnic 0 */ 2678 rc = bnxt_setup_one_vnic(bp, 0); 2679 if (rc) 2680 return rc; 2681 2682 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2683 RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 2684 rc = bnxt_add_vlan_filter(bp, 0); 2685 if (rc) 2686 return rc; 2687 rc = bnxt_restore_vlan_filters(bp); 2688 if (rc) 2689 return rc; 2690 } else { 2691 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2692 if (rc) 2693 return rc; 2694 } 2695 2696 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2697 if (rc) 2698 return rc; 2699 2700 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2701 !!(rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP)); 2702 2703 return rc; 2704 } 2705 2706 static int 2707 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2708 { 2709 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2710 struct bnxt *bp = dev->data->dev_private; 2711 int rc; 2712 2713 rc = is_bnxt_in_error(bp); 2714 if (rc) 2715 return rc; 2716 2717 /* Filter settings will get applied when port is started */ 2718 if (!dev->data->dev_started) 2719 return 0; 2720 2721 if (mask & RTE_ETH_VLAN_FILTER_MASK) { 2722 /* Enable or disable VLAN filtering */ 2723 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2724 if (rc) 2725 return rc; 2726 } 2727 2728 if (mask & RTE_ETH_VLAN_STRIP_MASK) { 2729 /* Enable or disable VLAN stripping */ 2730 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2731 if (rc) 2732 return rc; 2733 } 2734 2735 if (mask & RTE_ETH_VLAN_EXTEND_MASK) { 2736 if (rx_offloads & RTE_ETH_RX_OFFLOAD_VLAN_EXTEND) 2737 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2738 else 2739 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2740 } 2741 2742 return 0; 2743 } 2744 2745 static int 2746 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2747 uint16_t tpid) 2748 { 2749 struct bnxt *bp = dev->data->dev_private; 2750 int qinq = dev->data->dev_conf.rxmode.offloads & 2751 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND; 2752 2753 if (vlan_type != RTE_ETH_VLAN_TYPE_INNER && 2754 vlan_type != RTE_ETH_VLAN_TYPE_OUTER) { 2755 PMD_DRV_LOG(ERR, 2756 "Unsupported vlan type."); 2757 return -EINVAL; 2758 } 2759 if (!qinq) { 2760 PMD_DRV_LOG(ERR, 2761 "QinQ not enabled. Needs to be ON as we can " 2762 "accelerate only outer vlan\n"); 2763 return -EINVAL; 2764 } 2765 2766 if (vlan_type == RTE_ETH_VLAN_TYPE_OUTER) { 2767 switch (tpid) { 2768 case RTE_ETHER_TYPE_QINQ: 2769 bp->outer_tpid_bd = 2770 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2771 break; 2772 case RTE_ETHER_TYPE_VLAN: 2773 bp->outer_tpid_bd = 2774 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2775 break; 2776 case RTE_ETHER_TYPE_QINQ1: 2777 bp->outer_tpid_bd = 2778 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2779 break; 2780 case RTE_ETHER_TYPE_QINQ2: 2781 bp->outer_tpid_bd = 2782 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2783 break; 2784 case RTE_ETHER_TYPE_QINQ3: 2785 bp->outer_tpid_bd = 2786 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2787 break; 2788 default: 2789 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2790 return -EINVAL; 2791 } 2792 bp->outer_tpid_bd |= tpid; 2793 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2794 } else if (vlan_type == RTE_ETH_VLAN_TYPE_INNER) { 2795 PMD_DRV_LOG(ERR, 2796 "Can accelerate only outer vlan in QinQ\n"); 2797 return -EINVAL; 2798 } 2799 2800 return 0; 2801 } 2802 2803 static int 2804 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2805 struct rte_ether_addr *addr) 2806 { 2807 struct bnxt *bp = dev->data->dev_private; 2808 /* Default Filter is tied to VNIC 0 */ 2809 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2810 int rc; 2811 2812 rc = is_bnxt_in_error(bp); 2813 if (rc) 2814 return rc; 2815 2816 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2817 return -EPERM; 2818 2819 if (rte_is_zero_ether_addr(addr)) 2820 return -EINVAL; 2821 2822 /* Filter settings will get applied when port is started */ 2823 if (!dev->data->dev_started) 2824 return 0; 2825 2826 /* Check if the requested MAC is already added */ 2827 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2828 return 0; 2829 2830 /* Destroy filter and re-create it */ 2831 bnxt_del_dflt_mac_filter(bp, vnic); 2832 2833 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2834 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_VLAN_FILTER) { 2835 /* This filter will allow only untagged packets */ 2836 rc = bnxt_add_vlan_filter(bp, 0); 2837 } else { 2838 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2839 } 2840 2841 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2842 return rc; 2843 } 2844 2845 static int 2846 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2847 struct rte_ether_addr *mc_addr_set, 2848 uint32_t nb_mc_addr) 2849 { 2850 struct bnxt *bp = eth_dev->data->dev_private; 2851 char *mc_addr_list = (char *)mc_addr_set; 2852 struct bnxt_vnic_info *vnic; 2853 uint32_t off = 0, i = 0; 2854 int rc; 2855 2856 rc = is_bnxt_in_error(bp); 2857 if (rc) 2858 return rc; 2859 2860 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2861 2862 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2863 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2864 goto allmulti; 2865 } 2866 2867 /* TODO Check for Duplicate mcast addresses */ 2868 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2869 for (i = 0; i < nb_mc_addr; i++) { 2870 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2871 RTE_ETHER_ADDR_LEN); 2872 off += RTE_ETHER_ADDR_LEN; 2873 } 2874 2875 vnic->mc_addr_cnt = i; 2876 if (vnic->mc_addr_cnt) 2877 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2878 else 2879 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2880 2881 allmulti: 2882 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2883 } 2884 2885 static int 2886 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2887 { 2888 struct bnxt *bp = dev->data->dev_private; 2889 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2890 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2891 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2892 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2893 int ret; 2894 2895 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2896 fw_major, fw_minor, fw_updt, fw_rsvd); 2897 if (ret < 0) 2898 return -EINVAL; 2899 2900 ret += 1; /* add the size of '\0' */ 2901 if (fw_size < (size_t)ret) 2902 return ret; 2903 else 2904 return 0; 2905 } 2906 2907 static void 2908 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2909 struct rte_eth_rxq_info *qinfo) 2910 { 2911 struct bnxt *bp = dev->data->dev_private; 2912 struct bnxt_rx_queue *rxq; 2913 2914 if (is_bnxt_in_error(bp)) 2915 return; 2916 2917 rxq = dev->data->rx_queues[queue_id]; 2918 2919 qinfo->mp = rxq->mb_pool; 2920 qinfo->scattered_rx = dev->data->scattered_rx; 2921 qinfo->nb_desc = rxq->nb_rx_desc; 2922 2923 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2924 qinfo->conf.rx_drop_en = rxq->drop_en; 2925 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2926 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2927 } 2928 2929 static void 2930 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2931 struct rte_eth_txq_info *qinfo) 2932 { 2933 struct bnxt *bp = dev->data->dev_private; 2934 struct bnxt_tx_queue *txq; 2935 2936 if (is_bnxt_in_error(bp)) 2937 return; 2938 2939 txq = dev->data->tx_queues[queue_id]; 2940 2941 qinfo->nb_desc = txq->nb_tx_desc; 2942 2943 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2944 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2945 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2946 2947 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2948 qinfo->conf.tx_rs_thresh = 0; 2949 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2950 qinfo->conf.offloads = txq->offloads; 2951 } 2952 2953 static const struct { 2954 eth_rx_burst_t pkt_burst; 2955 const char *info; 2956 } bnxt_rx_burst_info[] = { 2957 {bnxt_recv_pkts, "Scalar"}, 2958 #if defined(RTE_ARCH_X86) 2959 {bnxt_recv_pkts_vec, "Vector SSE"}, 2960 #endif 2961 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2962 {bnxt_recv_pkts_vec_avx2, "Vector AVX2"}, 2963 #endif 2964 #if defined(RTE_ARCH_ARM64) 2965 {bnxt_recv_pkts_vec, "Vector Neon"}, 2966 #endif 2967 }; 2968 2969 static int 2970 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2971 struct rte_eth_burst_mode *mode) 2972 { 2973 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2974 size_t i; 2975 2976 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2977 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2978 snprintf(mode->info, sizeof(mode->info), "%s", 2979 bnxt_rx_burst_info[i].info); 2980 return 0; 2981 } 2982 } 2983 2984 return -EINVAL; 2985 } 2986 2987 static const struct { 2988 eth_tx_burst_t pkt_burst; 2989 const char *info; 2990 } bnxt_tx_burst_info[] = { 2991 {bnxt_xmit_pkts, "Scalar"}, 2992 #if defined(RTE_ARCH_X86) 2993 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2994 #endif 2995 #if defined(RTE_ARCH_X86) && defined(CC_AVX2_SUPPORT) 2996 {bnxt_xmit_pkts_vec_avx2, "Vector AVX2"}, 2997 #endif 2998 #if defined(RTE_ARCH_ARM64) 2999 {bnxt_xmit_pkts_vec, "Vector Neon"}, 3000 #endif 3001 }; 3002 3003 static int 3004 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 3005 struct rte_eth_burst_mode *mode) 3006 { 3007 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 3008 size_t i; 3009 3010 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 3011 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 3012 snprintf(mode->info, sizeof(mode->info), "%s", 3013 bnxt_tx_burst_info[i].info); 3014 return 0; 3015 } 3016 } 3017 3018 return -EINVAL; 3019 } 3020 3021 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 3022 { 3023 uint32_t overhead = BNXT_MAX_PKT_LEN - BNXT_MAX_MTU; 3024 struct bnxt *bp = eth_dev->data->dev_private; 3025 uint32_t new_pkt_size; 3026 uint32_t rc; 3027 uint32_t i; 3028 3029 rc = is_bnxt_in_error(bp); 3030 if (rc) 3031 return rc; 3032 3033 /* Exit if receive queues are not configured yet */ 3034 if (!eth_dev->data->nb_rx_queues) 3035 return rc; 3036 3037 new_pkt_size = new_mtu + overhead; 3038 3039 /* 3040 * Disallow any MTU change that would require scattered receive support 3041 * if it is not already enabled. 3042 */ 3043 if (eth_dev->data->dev_started && 3044 !eth_dev->data->scattered_rx && 3045 (new_pkt_size > 3046 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 3047 PMD_DRV_LOG(ERR, 3048 "MTU change would require scattered rx support. "); 3049 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 3050 return -EINVAL; 3051 } 3052 3053 if (new_mtu > RTE_ETHER_MTU) 3054 bp->flags |= BNXT_FLAG_JUMBO; 3055 else 3056 bp->flags &= ~BNXT_FLAG_JUMBO; 3057 3058 /* Is there a change in mtu setting? */ 3059 if (eth_dev->data->mtu == new_mtu) 3060 return rc; 3061 3062 for (i = 0; i < bp->nr_vnics; i++) { 3063 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 3064 uint16_t size = 0; 3065 3066 vnic->mru = BNXT_VNIC_MRU(new_mtu); 3067 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 3068 if (rc) 3069 break; 3070 3071 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 3072 size -= RTE_PKTMBUF_HEADROOM; 3073 3074 if (size < new_mtu) { 3075 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 3076 if (rc) 3077 return rc; 3078 } 3079 } 3080 3081 if (bnxt_hwrm_config_host_mtu(bp)) 3082 PMD_DRV_LOG(WARNING, "Failed to configure host MTU\n"); 3083 3084 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 3085 3086 return rc; 3087 } 3088 3089 static int 3090 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 3091 { 3092 struct bnxt *bp = dev->data->dev_private; 3093 uint16_t vlan = bp->vlan; 3094 int rc; 3095 3096 rc = is_bnxt_in_error(bp); 3097 if (rc) 3098 return rc; 3099 3100 if (!BNXT_SINGLE_PF(bp)) { 3101 PMD_DRV_LOG(ERR, "PVID cannot be modified on VF or on shared PF\n"); 3102 return -ENOTSUP; 3103 } 3104 bp->vlan = on ? pvid : 0; 3105 3106 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 3107 if (rc) 3108 bp->vlan = vlan; 3109 return rc; 3110 } 3111 3112 static int 3113 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3114 { 3115 struct bnxt *bp = dev->data->dev_private; 3116 int rc; 3117 3118 rc = is_bnxt_in_error(bp); 3119 if (rc) 3120 return rc; 3121 3122 return bnxt_hwrm_port_led_cfg(bp, true); 3123 } 3124 3125 static int 3126 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3127 { 3128 struct bnxt *bp = dev->data->dev_private; 3129 int rc; 3130 3131 rc = is_bnxt_in_error(bp); 3132 if (rc) 3133 return rc; 3134 3135 return bnxt_hwrm_port_led_cfg(bp, false); 3136 } 3137 3138 static uint32_t 3139 bnxt_rx_queue_count_op(void *rx_queue) 3140 { 3141 struct bnxt *bp; 3142 struct bnxt_cp_ring_info *cpr; 3143 uint32_t desc = 0, raw_cons, cp_ring_size; 3144 struct bnxt_rx_queue *rxq; 3145 struct rx_pkt_cmpl *rxcmp; 3146 int rc; 3147 3148 rxq = rx_queue; 3149 bp = rxq->bp; 3150 3151 rc = is_bnxt_in_error(bp); 3152 if (rc) 3153 return rc; 3154 3155 cpr = rxq->cp_ring; 3156 raw_cons = cpr->cp_raw_cons; 3157 cp_ring_size = cpr->cp_ring_struct->ring_size; 3158 3159 while (1) { 3160 uint32_t agg_cnt, cons, cmpl_type; 3161 3162 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3163 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3164 3165 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3166 break; 3167 3168 cmpl_type = CMP_TYPE(rxcmp); 3169 3170 switch (cmpl_type) { 3171 case CMPL_BASE_TYPE_RX_L2: 3172 case CMPL_BASE_TYPE_RX_L2_V2: 3173 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3174 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3175 desc++; 3176 break; 3177 3178 case CMPL_BASE_TYPE_RX_TPA_END: 3179 if (BNXT_CHIP_P5(rxq->bp)) { 3180 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3181 3182 p5_tpa_end = (void *)rxcmp; 3183 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3184 } else { 3185 struct rx_tpa_end_cmpl *tpa_end; 3186 3187 tpa_end = (void *)rxcmp; 3188 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3189 } 3190 3191 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3192 desc++; 3193 break; 3194 3195 default: 3196 raw_cons += CMP_LEN(cmpl_type); 3197 } 3198 } 3199 3200 return desc; 3201 } 3202 3203 static int 3204 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3205 { 3206 struct bnxt_rx_queue *rxq = rx_queue; 3207 struct bnxt_cp_ring_info *cpr; 3208 struct bnxt_rx_ring_info *rxr; 3209 uint32_t desc, raw_cons, cp_ring_size; 3210 struct bnxt *bp = rxq->bp; 3211 struct rx_pkt_cmpl *rxcmp; 3212 int rc; 3213 3214 rc = is_bnxt_in_error(bp); 3215 if (rc) 3216 return rc; 3217 3218 if (offset >= rxq->nb_rx_desc) 3219 return -EINVAL; 3220 3221 rxr = rxq->rx_ring; 3222 cpr = rxq->cp_ring; 3223 cp_ring_size = cpr->cp_ring_struct->ring_size; 3224 3225 /* 3226 * For the vector receive case, the completion at the requested 3227 * offset can be indexed directly. 3228 */ 3229 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3230 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3231 struct rx_pkt_cmpl *rxcmp; 3232 uint32_t cons; 3233 3234 /* Check status of completion descriptor. */ 3235 raw_cons = cpr->cp_raw_cons + 3236 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3237 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3238 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3239 3240 if (bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3241 return RTE_ETH_RX_DESC_DONE; 3242 3243 /* Check whether rx desc has an mbuf attached. */ 3244 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3245 if (cons >= rxq->rxrearm_start && 3246 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3247 return RTE_ETH_RX_DESC_UNAVAIL; 3248 } 3249 3250 return RTE_ETH_RX_DESC_AVAIL; 3251 } 3252 #endif 3253 3254 /* 3255 * For the non-vector receive case, scan the completion ring to 3256 * locate the completion descriptor for the requested offset. 3257 */ 3258 raw_cons = cpr->cp_raw_cons; 3259 desc = 0; 3260 while (1) { 3261 uint32_t agg_cnt, cons, cmpl_type; 3262 3263 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3264 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3265 3266 if (!bnxt_cpr_cmp_valid(rxcmp, raw_cons, cp_ring_size)) 3267 break; 3268 3269 cmpl_type = CMP_TYPE(rxcmp); 3270 3271 switch (cmpl_type) { 3272 case CMPL_BASE_TYPE_RX_L2: 3273 case CMPL_BASE_TYPE_RX_L2_V2: 3274 if (desc == offset) { 3275 cons = rxcmp->opaque; 3276 if (rxr->rx_buf_ring[cons]) 3277 return RTE_ETH_RX_DESC_DONE; 3278 else 3279 return RTE_ETH_RX_DESC_UNAVAIL; 3280 } 3281 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3282 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3283 desc++; 3284 break; 3285 3286 case CMPL_BASE_TYPE_RX_TPA_END: 3287 if (desc == offset) 3288 return RTE_ETH_RX_DESC_DONE; 3289 3290 if (BNXT_CHIP_P5(rxq->bp)) { 3291 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3292 3293 p5_tpa_end = (void *)rxcmp; 3294 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3295 } else { 3296 struct rx_tpa_end_cmpl *tpa_end; 3297 3298 tpa_end = (void *)rxcmp; 3299 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3300 } 3301 3302 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3303 desc++; 3304 break; 3305 3306 default: 3307 raw_cons += CMP_LEN(cmpl_type); 3308 } 3309 } 3310 3311 return RTE_ETH_RX_DESC_AVAIL; 3312 } 3313 3314 static int 3315 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3316 { 3317 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3318 struct bnxt_cp_ring_info *cpr = txq->cp_ring; 3319 uint32_t ring_mask, raw_cons, nb_tx_pkts = 0; 3320 struct cmpl_base *cp_desc_ring; 3321 int rc; 3322 3323 rc = is_bnxt_in_error(txq->bp); 3324 if (rc) 3325 return rc; 3326 3327 if (offset >= txq->nb_tx_desc) 3328 return -EINVAL; 3329 3330 /* Return "desc done" if descriptor is available for use. */ 3331 if (bnxt_tx_bds_in_hw(txq) <= offset) 3332 return RTE_ETH_TX_DESC_DONE; 3333 3334 raw_cons = cpr->cp_raw_cons; 3335 cp_desc_ring = cpr->cp_desc_ring; 3336 ring_mask = cpr->cp_ring_struct->ring_mask; 3337 3338 /* Check to see if hw has posted a completion for the descriptor. */ 3339 while (1) { 3340 struct tx_cmpl *txcmp; 3341 uint32_t cons; 3342 3343 cons = RING_CMPL(ring_mask, raw_cons); 3344 txcmp = (struct tx_cmpl *)&cp_desc_ring[cons]; 3345 3346 if (!bnxt_cpr_cmp_valid(txcmp, raw_cons, ring_mask + 1)) 3347 break; 3348 3349 if (CMP_TYPE(txcmp) == TX_CMPL_TYPE_TX_L2) 3350 nb_tx_pkts += rte_le_to_cpu_32(txcmp->opaque); 3351 3352 if (nb_tx_pkts > offset) 3353 return RTE_ETH_TX_DESC_DONE; 3354 3355 raw_cons = NEXT_RAW_CMP(raw_cons); 3356 } 3357 3358 /* Descriptor is pending transmit, not yet completed by hardware. */ 3359 return RTE_ETH_TX_DESC_FULL; 3360 } 3361 3362 int 3363 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3364 const struct rte_flow_ops **ops) 3365 { 3366 struct bnxt *bp = dev->data->dev_private; 3367 int ret = 0; 3368 3369 if (!bp) 3370 return -EIO; 3371 3372 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3373 struct bnxt_representor *vfr = dev->data->dev_private; 3374 bp = vfr->parent_dev->data->dev_private; 3375 /* parent is deleted while children are still valid */ 3376 if (!bp) { 3377 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3378 dev->data->port_id); 3379 return -EIO; 3380 } 3381 } 3382 3383 ret = is_bnxt_in_error(bp); 3384 if (ret) 3385 return ret; 3386 3387 /* PMD supports thread-safe flow operations. rte_flow API 3388 * functions can avoid mutex for multi-thread safety. 3389 */ 3390 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3391 3392 if (BNXT_TRUFLOW_EN(bp)) 3393 *ops = &bnxt_ulp_rte_flow_ops; 3394 else 3395 *ops = &bnxt_flow_ops; 3396 3397 return ret; 3398 } 3399 3400 static const uint32_t * 3401 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3402 { 3403 static const uint32_t ptypes[] = { 3404 RTE_PTYPE_L2_ETHER_VLAN, 3405 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3406 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3407 RTE_PTYPE_L4_ICMP, 3408 RTE_PTYPE_L4_TCP, 3409 RTE_PTYPE_L4_UDP, 3410 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3411 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3412 RTE_PTYPE_INNER_L4_ICMP, 3413 RTE_PTYPE_INNER_L4_TCP, 3414 RTE_PTYPE_INNER_L4_UDP, 3415 RTE_PTYPE_UNKNOWN 3416 }; 3417 3418 if (!dev->rx_pkt_burst) 3419 return NULL; 3420 3421 return ptypes; 3422 } 3423 3424 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3425 int reg_win) 3426 { 3427 uint32_t reg_base = *reg_arr & 0xfffff000; 3428 uint32_t win_off; 3429 int i; 3430 3431 for (i = 0; i < count; i++) { 3432 if ((reg_arr[i] & 0xfffff000) != reg_base) 3433 return -ERANGE; 3434 } 3435 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3436 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3437 return 0; 3438 } 3439 3440 static int bnxt_map_ptp_regs(struct bnxt *bp) 3441 { 3442 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3443 uint32_t *reg_arr; 3444 int rc, i; 3445 3446 reg_arr = ptp->rx_regs; 3447 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3448 if (rc) 3449 return rc; 3450 3451 reg_arr = ptp->tx_regs; 3452 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3453 if (rc) 3454 return rc; 3455 3456 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3457 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3458 3459 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3460 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3461 3462 return 0; 3463 } 3464 3465 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3466 { 3467 rte_write32(0, (uint8_t *)bp->bar0 + 3468 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3469 rte_write32(0, (uint8_t *)bp->bar0 + 3470 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3471 } 3472 3473 static uint64_t bnxt_cc_read(struct bnxt *bp) 3474 { 3475 uint64_t ns; 3476 3477 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3478 BNXT_GRCPF_REG_SYNC_TIME)); 3479 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3480 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3481 return ns; 3482 } 3483 3484 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3485 { 3486 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3487 uint32_t fifo; 3488 3489 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3490 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3491 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3492 return -EAGAIN; 3493 3494 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3495 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3496 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3497 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3498 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3499 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3500 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3501 3502 return 0; 3503 } 3504 3505 static int bnxt_clr_rx_ts(struct bnxt *bp, uint64_t *last_ts) 3506 { 3507 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3508 struct bnxt_pf_info *pf = bp->pf; 3509 uint16_t port_id; 3510 int i = 0; 3511 uint32_t fifo; 3512 3513 if (!ptp || (bp->flags & BNXT_FLAG_CHIP_P5)) 3514 return -EINVAL; 3515 3516 port_id = pf->port_id; 3517 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3518 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3519 while ((fifo & BNXT_PTP_RX_FIFO_PENDING) && (i < BNXT_PTP_RX_PND_CNT)) { 3520 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3521 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3522 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3523 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3524 *last_ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3525 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3526 *last_ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3527 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3528 i++; 3529 } 3530 3531 if (i >= BNXT_PTP_RX_PND_CNT) 3532 return -EBUSY; 3533 3534 return 0; 3535 } 3536 3537 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3538 { 3539 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3540 struct bnxt_pf_info *pf = bp->pf; 3541 uint16_t port_id; 3542 uint32_t fifo; 3543 3544 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3545 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3546 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3547 return -EAGAIN; 3548 3549 port_id = pf->port_id; 3550 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3551 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3552 3553 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3554 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3555 if (fifo & BNXT_PTP_RX_FIFO_PENDING) 3556 return bnxt_clr_rx_ts(bp, ts); 3557 3558 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3559 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3560 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3561 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3562 3563 return 0; 3564 } 3565 3566 static int 3567 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3568 { 3569 uint64_t ns; 3570 struct bnxt *bp = dev->data->dev_private; 3571 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3572 3573 if (!ptp) 3574 return -ENOTSUP; 3575 3576 ns = rte_timespec_to_ns(ts); 3577 /* Set the timecounters to a new value. */ 3578 ptp->tc.nsec = ns; 3579 ptp->tx_tstamp_tc.nsec = ns; 3580 ptp->rx_tstamp_tc.nsec = ns; 3581 3582 return 0; 3583 } 3584 3585 static int 3586 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3587 { 3588 struct bnxt *bp = dev->data->dev_private; 3589 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3590 uint64_t ns, systime_cycles = 0; 3591 int rc = 0; 3592 3593 if (!ptp) 3594 return -ENOTSUP; 3595 3596 if (BNXT_CHIP_P5(bp)) 3597 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3598 &systime_cycles); 3599 else 3600 systime_cycles = bnxt_cc_read(bp); 3601 3602 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3603 *ts = rte_ns_to_timespec(ns); 3604 3605 return rc; 3606 } 3607 static int 3608 bnxt_timesync_enable(struct rte_eth_dev *dev) 3609 { 3610 struct bnxt *bp = dev->data->dev_private; 3611 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3612 uint32_t shift = 0; 3613 int rc; 3614 3615 if (!ptp) 3616 return -ENOTSUP; 3617 3618 ptp->rx_filter = 1; 3619 ptp->tx_tstamp_en = 1; 3620 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3621 3622 rc = bnxt_hwrm_ptp_cfg(bp); 3623 if (rc) 3624 return rc; 3625 3626 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3627 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3628 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3629 3630 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3631 ptp->tc.cc_shift = shift; 3632 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3633 3634 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3635 ptp->rx_tstamp_tc.cc_shift = shift; 3636 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3637 3638 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3639 ptp->tx_tstamp_tc.cc_shift = shift; 3640 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3641 3642 if (!BNXT_CHIP_P5(bp)) 3643 bnxt_map_ptp_regs(bp); 3644 else 3645 rc = bnxt_ptp_start(bp); 3646 3647 return rc; 3648 } 3649 3650 static int 3651 bnxt_timesync_disable(struct rte_eth_dev *dev) 3652 { 3653 struct bnxt *bp = dev->data->dev_private; 3654 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3655 3656 if (!ptp) 3657 return -ENOTSUP; 3658 3659 ptp->rx_filter = 0; 3660 ptp->tx_tstamp_en = 0; 3661 ptp->rxctl = 0; 3662 3663 bnxt_hwrm_ptp_cfg(bp); 3664 3665 if (!BNXT_CHIP_P5(bp)) 3666 bnxt_unmap_ptp_regs(bp); 3667 else 3668 bnxt_ptp_stop(bp); 3669 3670 return 0; 3671 } 3672 3673 static int 3674 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3675 struct timespec *timestamp, 3676 uint32_t flags __rte_unused) 3677 { 3678 struct bnxt *bp = dev->data->dev_private; 3679 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3680 uint64_t rx_tstamp_cycles = 0; 3681 uint64_t ns; 3682 3683 if (!ptp) 3684 return -ENOTSUP; 3685 3686 if (BNXT_CHIP_P5(bp)) 3687 rx_tstamp_cycles = ptp->rx_timestamp; 3688 else 3689 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3690 3691 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3692 *timestamp = rte_ns_to_timespec(ns); 3693 return 0; 3694 } 3695 3696 static int 3697 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3698 struct timespec *timestamp) 3699 { 3700 struct bnxt *bp = dev->data->dev_private; 3701 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3702 uint64_t tx_tstamp_cycles = 0; 3703 uint64_t ns; 3704 int rc = 0; 3705 3706 if (!ptp) 3707 return -ENOTSUP; 3708 3709 if (BNXT_CHIP_P5(bp)) 3710 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3711 &tx_tstamp_cycles); 3712 else 3713 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3714 3715 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3716 *timestamp = rte_ns_to_timespec(ns); 3717 3718 return rc; 3719 } 3720 3721 static int 3722 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3723 { 3724 struct bnxt *bp = dev->data->dev_private; 3725 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3726 3727 if (!ptp) 3728 return -ENOTSUP; 3729 3730 ptp->tc.nsec += delta; 3731 ptp->tx_tstamp_tc.nsec += delta; 3732 ptp->rx_tstamp_tc.nsec += delta; 3733 3734 return 0; 3735 } 3736 3737 static int 3738 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3739 { 3740 struct bnxt *bp = dev->data->dev_private; 3741 int rc; 3742 uint32_t dir_entries; 3743 uint32_t entry_length; 3744 3745 rc = is_bnxt_in_error(bp); 3746 if (rc) 3747 return rc; 3748 3749 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3750 bp->pdev->addr.domain, bp->pdev->addr.bus, 3751 bp->pdev->addr.devid, bp->pdev->addr.function); 3752 3753 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3754 if (rc != 0) 3755 return rc; 3756 3757 return dir_entries * entry_length; 3758 } 3759 3760 static int 3761 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3762 struct rte_dev_eeprom_info *in_eeprom) 3763 { 3764 struct bnxt *bp = dev->data->dev_private; 3765 uint32_t index; 3766 uint32_t offset; 3767 int rc; 3768 3769 rc = is_bnxt_in_error(bp); 3770 if (rc) 3771 return rc; 3772 3773 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3774 bp->pdev->addr.domain, bp->pdev->addr.bus, 3775 bp->pdev->addr.devid, bp->pdev->addr.function, 3776 in_eeprom->offset, in_eeprom->length); 3777 3778 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3779 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3780 in_eeprom->data); 3781 3782 index = in_eeprom->offset >> 24; 3783 offset = in_eeprom->offset & 0xffffff; 3784 3785 if (index != 0) 3786 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3787 in_eeprom->length, in_eeprom->data); 3788 3789 return 0; 3790 } 3791 3792 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3793 { 3794 switch (dir_type) { 3795 case BNX_DIR_TYPE_CHIMP_PATCH: 3796 case BNX_DIR_TYPE_BOOTCODE: 3797 case BNX_DIR_TYPE_BOOTCODE_2: 3798 case BNX_DIR_TYPE_APE_FW: 3799 case BNX_DIR_TYPE_APE_PATCH: 3800 case BNX_DIR_TYPE_KONG_FW: 3801 case BNX_DIR_TYPE_KONG_PATCH: 3802 case BNX_DIR_TYPE_BONO_FW: 3803 case BNX_DIR_TYPE_BONO_PATCH: 3804 /* FALLTHROUGH */ 3805 return true; 3806 } 3807 3808 return false; 3809 } 3810 3811 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3812 { 3813 switch (dir_type) { 3814 case BNX_DIR_TYPE_AVS: 3815 case BNX_DIR_TYPE_EXP_ROM_MBA: 3816 case BNX_DIR_TYPE_PCIE: 3817 case BNX_DIR_TYPE_TSCF_UCODE: 3818 case BNX_DIR_TYPE_EXT_PHY: 3819 case BNX_DIR_TYPE_CCM: 3820 case BNX_DIR_TYPE_ISCSI_BOOT: 3821 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3822 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3823 /* FALLTHROUGH */ 3824 return true; 3825 } 3826 3827 return false; 3828 } 3829 3830 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3831 { 3832 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3833 bnxt_dir_type_is_other_exec_format(dir_type); 3834 } 3835 3836 static int 3837 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3838 struct rte_dev_eeprom_info *in_eeprom) 3839 { 3840 struct bnxt *bp = dev->data->dev_private; 3841 uint8_t index, dir_op; 3842 uint16_t type, ext, ordinal, attr; 3843 int rc; 3844 3845 rc = is_bnxt_in_error(bp); 3846 if (rc) 3847 return rc; 3848 3849 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3850 bp->pdev->addr.domain, bp->pdev->addr.bus, 3851 bp->pdev->addr.devid, bp->pdev->addr.function, 3852 in_eeprom->offset, in_eeprom->length); 3853 3854 if (!BNXT_PF(bp)) { 3855 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3856 return -EINVAL; 3857 } 3858 3859 type = in_eeprom->magic >> 16; 3860 3861 if (type == 0xffff) { /* special value for directory operations */ 3862 index = in_eeprom->magic & 0xff; 3863 dir_op = in_eeprom->magic >> 8; 3864 if (index == 0) 3865 return -EINVAL; 3866 switch (dir_op) { 3867 case 0x0e: /* erase */ 3868 if (in_eeprom->offset != ~in_eeprom->magic) 3869 return -EINVAL; 3870 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3871 default: 3872 return -EINVAL; 3873 } 3874 } 3875 3876 /* Create or re-write an NVM item: */ 3877 if (bnxt_dir_type_is_executable(type) == true) 3878 return -EOPNOTSUPP; 3879 ext = in_eeprom->magic & 0xffff; 3880 ordinal = in_eeprom->offset >> 16; 3881 attr = in_eeprom->offset & 0xffff; 3882 3883 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3884 in_eeprom->data, in_eeprom->length); 3885 } 3886 3887 static int bnxt_get_module_info(struct rte_eth_dev *dev, 3888 struct rte_eth_dev_module_info *modinfo) 3889 { 3890 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3891 struct bnxt *bp = dev->data->dev_private; 3892 int rc; 3893 3894 /* No point in going further if phy status indicates 3895 * module is not inserted or if it is powered down or 3896 * if it is of type 10GBase-T 3897 */ 3898 if (bp->link_info->module_status > 3899 HWRM_PORT_PHY_QCFG_OUTPUT_MODULE_STATUS_WARNINGMSG) { 3900 PMD_DRV_LOG(NOTICE, "Port %u : Module is not inserted or is powered down\n", 3901 dev->data->port_id); 3902 return -ENOTSUP; 3903 } 3904 3905 /* This feature is not supported in older firmware versions */ 3906 if (bp->hwrm_spec_code < 0x10202) { 3907 PMD_DRV_LOG(NOTICE, "Port %u : Feature is not supported in older firmware\n", 3908 dev->data->port_id); 3909 return -ENOTSUP; 3910 } 3911 3912 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3913 SFF_DIAG_SUPPORT_OFFSET + 1, 3914 module_info); 3915 3916 if (rc) 3917 return rc; 3918 3919 switch (module_info[0]) { 3920 case SFF_MODULE_ID_SFP: 3921 modinfo->type = RTE_ETH_MODULE_SFF_8472; 3922 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN; 3923 if (module_info[SFF_DIAG_SUPPORT_OFFSET] == 0) 3924 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3925 break; 3926 case SFF_MODULE_ID_QSFP: 3927 case SFF_MODULE_ID_QSFP_PLUS: 3928 modinfo->type = RTE_ETH_MODULE_SFF_8436; 3929 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8436_LEN; 3930 break; 3931 case SFF_MODULE_ID_QSFP28: 3932 modinfo->type = RTE_ETH_MODULE_SFF_8636; 3933 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_MAX_LEN; 3934 if (module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) 3935 modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8636_LEN; 3936 break; 3937 default: 3938 PMD_DRV_LOG(NOTICE, "Port %u : Unsupported module\n", dev->data->port_id); 3939 return -ENOTSUP; 3940 } 3941 3942 PMD_DRV_LOG(INFO, "Port %u : modinfo->type = %d modinfo->eeprom_len = %d\n", 3943 dev->data->port_id, modinfo->type, modinfo->eeprom_len); 3944 3945 return 0; 3946 } 3947 3948 static int bnxt_get_module_eeprom(struct rte_eth_dev *dev, 3949 struct rte_dev_eeprom_info *info) 3950 { 3951 uint8_t pg_addr[5] = { I2C_DEV_ADDR_A0, I2C_DEV_ADDR_A0 }; 3952 uint32_t offset = info->offset, length = info->length; 3953 uint8_t module_info[SFF_DIAG_SUPPORT_OFFSET + 1]; 3954 struct bnxt *bp = dev->data->dev_private; 3955 uint8_t *data = info->data; 3956 uint8_t page = offset >> 7; 3957 uint8_t max_pages = 2; 3958 uint8_t opt_pages; 3959 int rc; 3960 3961 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 0, 3962 SFF_DIAG_SUPPORT_OFFSET + 1, 3963 module_info); 3964 if (rc) 3965 return rc; 3966 3967 switch (module_info[0]) { 3968 case SFF_MODULE_ID_SFP: 3969 module_info[SFF_DIAG_SUPPORT_OFFSET] = 0; 3970 if (module_info[SFF_DIAG_SUPPORT_OFFSET]) { 3971 pg_addr[2] = I2C_DEV_ADDR_A2; 3972 pg_addr[3] = I2C_DEV_ADDR_A2; 3973 max_pages = 4; 3974 } 3975 break; 3976 case SFF_MODULE_ID_QSFP28: 3977 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, I2C_DEV_ADDR_A0, 0, 3978 SFF8636_OPT_PAGES_OFFSET, 3979 1, &opt_pages); 3980 if (rc) 3981 return rc; 3982 3983 if (opt_pages & SFF8636_PAGE1_MASK) { 3984 pg_addr[2] = I2C_DEV_ADDR_A0; 3985 max_pages = 3; 3986 } 3987 if (opt_pages & SFF8636_PAGE2_MASK) { 3988 pg_addr[3] = I2C_DEV_ADDR_A0; 3989 max_pages = 4; 3990 } 3991 if (~module_info[SFF8636_FLATMEM_OFFSET] & SFF8636_FLATMEM_MASK) { 3992 pg_addr[4] = I2C_DEV_ADDR_A0; 3993 max_pages = 5; 3994 } 3995 break; 3996 default: 3997 break; 3998 } 3999 4000 memset(data, 0, length); 4001 4002 offset &= 0xff; 4003 while (length && page < max_pages) { 4004 uint8_t raw_page = page ? page - 1 : 0; 4005 uint16_t chunk; 4006 4007 if (pg_addr[page] == I2C_DEV_ADDR_A2) 4008 raw_page = 0; 4009 else if (page) 4010 offset |= 0x80; 4011 chunk = RTE_MIN(length, 256 - offset); 4012 4013 if (pg_addr[page]) { 4014 rc = bnxt_hwrm_read_sfp_module_eeprom_info(bp, pg_addr[page], 4015 raw_page, offset, 4016 chunk, data); 4017 if (rc) 4018 return rc; 4019 } 4020 4021 data += chunk; 4022 length -= chunk; 4023 offset = 0; 4024 page += 1 + (chunk > 128); 4025 } 4026 4027 return length ? -EINVAL : 0; 4028 } 4029 4030 /* 4031 * Initialization 4032 */ 4033 4034 static const struct eth_dev_ops bnxt_dev_ops = { 4035 .dev_infos_get = bnxt_dev_info_get_op, 4036 .dev_close = bnxt_dev_close_op, 4037 .dev_configure = bnxt_dev_configure_op, 4038 .dev_start = bnxt_dev_start_op, 4039 .dev_stop = bnxt_dev_stop_op, 4040 .dev_set_link_up = bnxt_dev_set_link_up_op, 4041 .dev_set_link_down = bnxt_dev_set_link_down_op, 4042 .stats_get = bnxt_stats_get_op, 4043 .stats_reset = bnxt_stats_reset_op, 4044 .rx_queue_setup = bnxt_rx_queue_setup_op, 4045 .rx_queue_release = bnxt_rx_queue_release_op, 4046 .tx_queue_setup = bnxt_tx_queue_setup_op, 4047 .tx_queue_release = bnxt_tx_queue_release_op, 4048 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 4049 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 4050 .reta_update = bnxt_reta_update_op, 4051 .reta_query = bnxt_reta_query_op, 4052 .rss_hash_update = bnxt_rss_hash_update_op, 4053 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 4054 .link_update = bnxt_link_update_op, 4055 .promiscuous_enable = bnxt_promiscuous_enable_op, 4056 .promiscuous_disable = bnxt_promiscuous_disable_op, 4057 .allmulticast_enable = bnxt_allmulticast_enable_op, 4058 .allmulticast_disable = bnxt_allmulticast_disable_op, 4059 .mac_addr_add = bnxt_mac_addr_add_op, 4060 .mac_addr_remove = bnxt_mac_addr_remove_op, 4061 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 4062 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 4063 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 4064 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 4065 .vlan_filter_set = bnxt_vlan_filter_set_op, 4066 .vlan_offload_set = bnxt_vlan_offload_set_op, 4067 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 4068 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 4069 .mtu_set = bnxt_mtu_set_op, 4070 .mac_addr_set = bnxt_set_default_mac_addr_op, 4071 .xstats_get = bnxt_dev_xstats_get_op, 4072 .xstats_get_names = bnxt_dev_xstats_get_names_op, 4073 .xstats_reset = bnxt_dev_xstats_reset_op, 4074 .fw_version_get = bnxt_fw_version_get, 4075 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 4076 .rxq_info_get = bnxt_rxq_info_get_op, 4077 .txq_info_get = bnxt_txq_info_get_op, 4078 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 4079 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 4080 .dev_led_on = bnxt_dev_led_on_op, 4081 .dev_led_off = bnxt_dev_led_off_op, 4082 .rx_queue_start = bnxt_rx_queue_start, 4083 .rx_queue_stop = bnxt_rx_queue_stop, 4084 .tx_queue_start = bnxt_tx_queue_start, 4085 .tx_queue_stop = bnxt_tx_queue_stop, 4086 .flow_ops_get = bnxt_flow_ops_get_op, 4087 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 4088 .get_eeprom_length = bnxt_get_eeprom_length_op, 4089 .get_eeprom = bnxt_get_eeprom_op, 4090 .set_eeprom = bnxt_set_eeprom_op, 4091 .get_module_info = bnxt_get_module_info, 4092 .get_module_eeprom = bnxt_get_module_eeprom, 4093 .timesync_enable = bnxt_timesync_enable, 4094 .timesync_disable = bnxt_timesync_disable, 4095 .timesync_read_time = bnxt_timesync_read_time, 4096 .timesync_write_time = bnxt_timesync_write_time, 4097 .timesync_adjust_time = bnxt_timesync_adjust_time, 4098 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 4099 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 4100 }; 4101 4102 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 4103 { 4104 uint32_t offset; 4105 4106 /* Only pre-map the reset GRC registers using window 3 */ 4107 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 4108 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 4109 4110 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 4111 4112 return offset; 4113 } 4114 4115 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 4116 { 4117 struct bnxt_error_recovery_info *info = bp->recovery_info; 4118 uint32_t reg_base = 0xffffffff; 4119 int i; 4120 4121 /* Only pre-map the monitoring GRC registers using window 2 */ 4122 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 4123 uint32_t reg = info->status_regs[i]; 4124 4125 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 4126 continue; 4127 4128 if (reg_base == 0xffffffff) 4129 reg_base = reg & 0xfffff000; 4130 if ((reg & 0xfffff000) != reg_base) 4131 return -ERANGE; 4132 4133 /* Use mask 0xffc as the Lower 2 bits indicates 4134 * address space location 4135 */ 4136 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 4137 (reg & 0xffc); 4138 } 4139 4140 if (reg_base == 0xffffffff) 4141 return 0; 4142 4143 rte_write32(reg_base, (uint8_t *)bp->bar0 + 4144 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4145 4146 return 0; 4147 } 4148 4149 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 4150 { 4151 struct bnxt_error_recovery_info *info = bp->recovery_info; 4152 uint32_t delay = info->delay_after_reset[index]; 4153 uint32_t val = info->reset_reg_val[index]; 4154 uint32_t reg = info->reset_reg[index]; 4155 uint32_t type, offset; 4156 int ret; 4157 4158 type = BNXT_FW_STATUS_REG_TYPE(reg); 4159 offset = BNXT_FW_STATUS_REG_OFF(reg); 4160 4161 switch (type) { 4162 case BNXT_FW_STATUS_REG_TYPE_CFG: 4163 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 4164 if (ret < 0) { 4165 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 4166 val, offset); 4167 return; 4168 } 4169 break; 4170 case BNXT_FW_STATUS_REG_TYPE_GRC: 4171 offset = bnxt_map_reset_regs(bp, offset); 4172 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4173 break; 4174 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4175 rte_write32(val, (uint8_t *)bp->bar0 + offset); 4176 break; 4177 } 4178 /* wait on a specific interval of time until core reset is complete */ 4179 if (delay) 4180 rte_delay_ms(delay); 4181 } 4182 4183 static void bnxt_dev_cleanup(struct bnxt *bp) 4184 { 4185 bp->eth_dev->data->dev_link.link_status = 0; 4186 bp->link_info->link_up = 0; 4187 if (bp->eth_dev->data->dev_started) 4188 bnxt_dev_stop(bp->eth_dev); 4189 4190 bnxt_uninit_resources(bp, true); 4191 } 4192 4193 static int 4194 bnxt_check_fw_reset_done(struct bnxt *bp) 4195 { 4196 int timeout = bp->fw_reset_max_msecs; 4197 uint16_t val = 0; 4198 int rc; 4199 4200 do { 4201 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4202 if (rc < 0) { 4203 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4204 return rc; 4205 } 4206 if (val != 0xffff) 4207 break; 4208 rte_delay_ms(1); 4209 } while (timeout--); 4210 4211 if (val == 0xffff) { 4212 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 4213 return -1; 4214 } 4215 4216 return 0; 4217 } 4218 4219 static int bnxt_restore_vlan_filters(struct bnxt *bp) 4220 { 4221 struct rte_eth_dev *dev = bp->eth_dev; 4222 struct rte_vlan_filter_conf *vfc; 4223 int vidx, vbit, rc; 4224 uint16_t vlan_id; 4225 4226 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 4227 vfc = &dev->data->vlan_filter_conf; 4228 vidx = vlan_id / 64; 4229 vbit = vlan_id % 64; 4230 4231 /* Each bit corresponds to a VLAN id */ 4232 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 4233 rc = bnxt_add_vlan_filter(bp, vlan_id); 4234 if (rc) 4235 return rc; 4236 } 4237 } 4238 4239 return 0; 4240 } 4241 4242 static int bnxt_restore_mac_filters(struct bnxt *bp) 4243 { 4244 struct rte_eth_dev *dev = bp->eth_dev; 4245 struct rte_eth_dev_info dev_info; 4246 struct rte_ether_addr *addr; 4247 uint64_t pool_mask; 4248 uint32_t pool = 0; 4249 uint32_t i; 4250 int rc; 4251 4252 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 4253 return 0; 4254 4255 rc = bnxt_dev_info_get_op(dev, &dev_info); 4256 if (rc) 4257 return rc; 4258 4259 /* replay MAC address configuration */ 4260 for (i = 1; i < dev_info.max_mac_addrs; i++) { 4261 addr = &dev->data->mac_addrs[i]; 4262 4263 /* skip zero address */ 4264 if (rte_is_zero_ether_addr(addr)) 4265 continue; 4266 4267 pool = 0; 4268 pool_mask = dev->data->mac_pool_sel[i]; 4269 4270 do { 4271 if (pool_mask & 1ULL) { 4272 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 4273 if (rc) 4274 return rc; 4275 } 4276 pool_mask >>= 1; 4277 pool++; 4278 } while (pool_mask); 4279 } 4280 4281 return 0; 4282 } 4283 4284 static int bnxt_restore_filters(struct bnxt *bp) 4285 { 4286 struct rte_eth_dev *dev = bp->eth_dev; 4287 int ret = 0; 4288 4289 if (dev->data->all_multicast) { 4290 ret = bnxt_allmulticast_enable_op(dev); 4291 if (ret) 4292 return ret; 4293 } 4294 if (dev->data->promiscuous) { 4295 ret = bnxt_promiscuous_enable_op(dev); 4296 if (ret) 4297 return ret; 4298 } 4299 4300 ret = bnxt_restore_mac_filters(bp); 4301 if (ret) 4302 return ret; 4303 4304 ret = bnxt_restore_vlan_filters(bp); 4305 /* TODO restore other filters as well */ 4306 return ret; 4307 } 4308 4309 static int bnxt_check_fw_ready(struct bnxt *bp) 4310 { 4311 int timeout = bp->fw_reset_max_msecs; 4312 int rc = 0; 4313 4314 do { 4315 rc = bnxt_hwrm_poll_ver_get(bp); 4316 if (rc == 0) 4317 break; 4318 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4319 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4320 } while (rc && timeout > 0); 4321 4322 if (rc) 4323 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4324 4325 return rc; 4326 } 4327 4328 static void bnxt_dev_recover(void *arg) 4329 { 4330 struct bnxt *bp = arg; 4331 int rc = 0; 4332 4333 pthread_mutex_lock(&bp->err_recovery_lock); 4334 4335 if (!bp->fw_reset_min_msecs) { 4336 rc = bnxt_check_fw_reset_done(bp); 4337 if (rc) 4338 goto err; 4339 } 4340 4341 /* Clear Error flag so that device re-init should happen */ 4342 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4343 4344 rc = bnxt_check_fw_ready(bp); 4345 if (rc) 4346 goto err; 4347 4348 rc = bnxt_init_resources(bp, true); 4349 if (rc) { 4350 PMD_DRV_LOG(ERR, 4351 "Failed to initialize resources after reset\n"); 4352 goto err; 4353 } 4354 /* clear reset flag as the device is initialized now */ 4355 bp->flags &= ~BNXT_FLAG_FW_RESET; 4356 4357 rc = bnxt_dev_start_op(bp->eth_dev); 4358 if (rc) { 4359 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4360 goto err_start; 4361 } 4362 4363 rc = bnxt_restore_filters(bp); 4364 if (rc) 4365 goto err_start; 4366 4367 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4368 pthread_mutex_unlock(&bp->err_recovery_lock); 4369 4370 return; 4371 err_start: 4372 bnxt_dev_stop(bp->eth_dev); 4373 err: 4374 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4375 bnxt_uninit_resources(bp, false); 4376 if (bp->eth_dev->data->dev_conf.intr_conf.rmv) 4377 rte_eth_dev_callback_process(bp->eth_dev, 4378 RTE_ETH_EVENT_INTR_RMV, 4379 NULL); 4380 pthread_mutex_unlock(&bp->err_recovery_lock); 4381 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4382 } 4383 4384 void bnxt_dev_reset_and_resume(void *arg) 4385 { 4386 struct bnxt *bp = arg; 4387 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4388 uint16_t val = 0; 4389 int rc; 4390 4391 bnxt_dev_cleanup(bp); 4392 4393 bnxt_wait_for_device_shutdown(bp); 4394 4395 /* During some fatal firmware error conditions, the PCI config space 4396 * register 0x2e which normally contains the subsystem ID will become 4397 * 0xffff. This register will revert back to the normal value after 4398 * the chip has completed core reset. If we detect this condition, 4399 * we can poll this config register immediately for the value to revert. 4400 */ 4401 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4402 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4403 if (rc < 0) { 4404 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4405 return; 4406 } 4407 if (val == 0xffff) { 4408 bp->fw_reset_min_msecs = 0; 4409 us = 1; 4410 } 4411 } 4412 4413 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4414 if (rc) 4415 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4416 } 4417 4418 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4419 { 4420 struct bnxt_error_recovery_info *info = bp->recovery_info; 4421 uint32_t reg = info->status_regs[index]; 4422 uint32_t type, offset, val = 0; 4423 int ret = 0; 4424 4425 type = BNXT_FW_STATUS_REG_TYPE(reg); 4426 offset = BNXT_FW_STATUS_REG_OFF(reg); 4427 4428 switch (type) { 4429 case BNXT_FW_STATUS_REG_TYPE_CFG: 4430 ret = rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4431 if (ret < 0) 4432 PMD_DRV_LOG(ERR, "Failed to read PCI offset %#x", 4433 offset); 4434 break; 4435 case BNXT_FW_STATUS_REG_TYPE_GRC: 4436 offset = info->mapped_status_regs[index]; 4437 /* FALLTHROUGH */ 4438 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4439 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4440 offset)); 4441 break; 4442 } 4443 4444 return val; 4445 } 4446 4447 static int bnxt_fw_reset_all(struct bnxt *bp) 4448 { 4449 struct bnxt_error_recovery_info *info = bp->recovery_info; 4450 uint32_t i; 4451 int rc = 0; 4452 4453 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4454 /* Reset through primary function driver */ 4455 for (i = 0; i < info->reg_array_cnt; i++) 4456 bnxt_write_fw_reset_reg(bp, i); 4457 /* Wait for time specified by FW after triggering reset */ 4458 rte_delay_ms(info->primary_func_wait_period_after_reset); 4459 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4460 /* Reset with the help of Kong processor */ 4461 rc = bnxt_hwrm_fw_reset(bp); 4462 if (rc) 4463 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4464 } 4465 4466 return rc; 4467 } 4468 4469 static void bnxt_fw_reset_cb(void *arg) 4470 { 4471 struct bnxt *bp = arg; 4472 struct bnxt_error_recovery_info *info = bp->recovery_info; 4473 int rc = 0; 4474 4475 /* Only Primary function can do FW reset */ 4476 if (bnxt_is_primary_func(bp) && 4477 bnxt_is_recovery_enabled(bp)) { 4478 rc = bnxt_fw_reset_all(bp); 4479 if (rc) { 4480 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4481 return; 4482 } 4483 } 4484 4485 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4486 * EXCEPTION_FATAL_ASYNC event to all the functions 4487 * (including MASTER FUNC). After receiving this Async, all the active 4488 * drivers should treat this case as FW initiated recovery 4489 */ 4490 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4491 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4492 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4493 4494 /* To recover from error */ 4495 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4496 (void *)bp); 4497 } 4498 } 4499 4500 /* Driver should poll FW heartbeat, reset_counter with the frequency 4501 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4502 * When the driver detects heartbeat stop or change in reset_counter, 4503 * it has to trigger a reset to recover from the error condition. 4504 * A “primary function” is the function who will have the privilege to 4505 * initiate the chimp reset. The primary function will be elected by the 4506 * firmware and will be notified through async message. 4507 */ 4508 static void bnxt_check_fw_health(void *arg) 4509 { 4510 struct bnxt *bp = arg; 4511 struct bnxt_error_recovery_info *info = bp->recovery_info; 4512 uint32_t val = 0, wait_msec; 4513 4514 if (!info || !bnxt_is_recovery_enabled(bp) || 4515 is_bnxt_in_error(bp)) 4516 return; 4517 4518 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4519 if (val == info->last_heart_beat) 4520 goto reset; 4521 4522 info->last_heart_beat = val; 4523 4524 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4525 if (val != info->last_reset_counter) 4526 goto reset; 4527 4528 info->last_reset_counter = val; 4529 4530 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4531 bnxt_check_fw_health, (void *)bp); 4532 4533 return; 4534 reset: 4535 /* Stop DMA to/from device */ 4536 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4537 bp->flags |= BNXT_FLAG_FW_RESET; 4538 4539 bnxt_stop_rxtx(bp); 4540 4541 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4542 4543 if (bnxt_is_primary_func(bp)) 4544 wait_msec = info->primary_func_wait_period; 4545 else 4546 wait_msec = info->normal_func_wait_period; 4547 4548 rte_eal_alarm_set(US_PER_MS * wait_msec, 4549 bnxt_fw_reset_cb, (void *)bp); 4550 } 4551 4552 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4553 { 4554 uint32_t polling_freq; 4555 4556 pthread_mutex_lock(&bp->health_check_lock); 4557 4558 if (!bnxt_is_recovery_enabled(bp)) 4559 goto done; 4560 4561 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4562 goto done; 4563 4564 polling_freq = bp->recovery_info->driver_polling_freq; 4565 4566 rte_eal_alarm_set(US_PER_MS * polling_freq, 4567 bnxt_check_fw_health, (void *)bp); 4568 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4569 4570 done: 4571 pthread_mutex_unlock(&bp->health_check_lock); 4572 } 4573 4574 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4575 { 4576 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4577 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4578 } 4579 4580 static bool bnxt_vf_pciid(uint16_t device_id) 4581 { 4582 switch (device_id) { 4583 case BROADCOM_DEV_ID_57304_VF: 4584 case BROADCOM_DEV_ID_57406_VF: 4585 case BROADCOM_DEV_ID_5731X_VF: 4586 case BROADCOM_DEV_ID_5741X_VF: 4587 case BROADCOM_DEV_ID_57414_VF: 4588 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4589 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4590 case BROADCOM_DEV_ID_58802_VF: 4591 case BROADCOM_DEV_ID_57500_VF1: 4592 case BROADCOM_DEV_ID_57500_VF2: 4593 case BROADCOM_DEV_ID_58818_VF: 4594 /* FALLTHROUGH */ 4595 return true; 4596 default: 4597 return false; 4598 } 4599 } 4600 4601 /* Phase 5 device */ 4602 static bool bnxt_p5_device(uint16_t device_id) 4603 { 4604 switch (device_id) { 4605 case BROADCOM_DEV_ID_57508: 4606 case BROADCOM_DEV_ID_57504: 4607 case BROADCOM_DEV_ID_57502: 4608 case BROADCOM_DEV_ID_57508_MF1: 4609 case BROADCOM_DEV_ID_57504_MF1: 4610 case BROADCOM_DEV_ID_57502_MF1: 4611 case BROADCOM_DEV_ID_57508_MF2: 4612 case BROADCOM_DEV_ID_57504_MF2: 4613 case BROADCOM_DEV_ID_57502_MF2: 4614 case BROADCOM_DEV_ID_57500_VF1: 4615 case BROADCOM_DEV_ID_57500_VF2: 4616 case BROADCOM_DEV_ID_58812: 4617 case BROADCOM_DEV_ID_58814: 4618 case BROADCOM_DEV_ID_58818: 4619 case BROADCOM_DEV_ID_58818_VF: 4620 /* FALLTHROUGH */ 4621 return true; 4622 default: 4623 return false; 4624 } 4625 } 4626 4627 bool bnxt_stratus_device(struct bnxt *bp) 4628 { 4629 uint16_t device_id = bp->pdev->id.device_id; 4630 4631 switch (device_id) { 4632 case BROADCOM_DEV_ID_STRATUS_NIC: 4633 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4634 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4635 /* FALLTHROUGH */ 4636 return true; 4637 default: 4638 return false; 4639 } 4640 } 4641 4642 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4643 { 4644 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4645 struct bnxt *bp = eth_dev->data->dev_private; 4646 4647 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4648 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4649 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4650 if (!bp->bar0 || !bp->doorbell_base) { 4651 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4652 return -ENODEV; 4653 } 4654 4655 bp->eth_dev = eth_dev; 4656 bp->pdev = pci_dev; 4657 4658 return 0; 4659 } 4660 4661 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4662 struct bnxt_ctx_pg_info *ctx_pg, 4663 uint32_t mem_size, 4664 const char *suffix, 4665 uint16_t idx) 4666 { 4667 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4668 const struct rte_memzone *mz = NULL; 4669 char mz_name[RTE_MEMZONE_NAMESIZE]; 4670 rte_iova_t mz_phys_addr; 4671 uint64_t valid_bits = 0; 4672 uint32_t sz; 4673 int i; 4674 4675 if (!mem_size) 4676 return 0; 4677 4678 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4679 BNXT_PAGE_SIZE; 4680 rmem->page_size = BNXT_PAGE_SIZE; 4681 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4682 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4683 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4684 4685 valid_bits = PTU_PTE_VALID; 4686 4687 if (rmem->nr_pages > 1) { 4688 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4689 "bnxt_ctx_pg_tbl%s_%x_%d", 4690 suffix, idx, bp->eth_dev->data->port_id); 4691 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4692 mz = rte_memzone_lookup(mz_name); 4693 if (!mz) { 4694 mz = rte_memzone_reserve_aligned(mz_name, 4695 rmem->nr_pages * 8, 4696 bp->eth_dev->device->numa_node, 4697 RTE_MEMZONE_2MB | 4698 RTE_MEMZONE_SIZE_HINT_ONLY | 4699 RTE_MEMZONE_IOVA_CONTIG, 4700 BNXT_PAGE_SIZE); 4701 if (mz == NULL) 4702 return -ENOMEM; 4703 } 4704 4705 memset(mz->addr, 0, mz->len); 4706 mz_phys_addr = mz->iova; 4707 4708 rmem->pg_tbl = mz->addr; 4709 rmem->pg_tbl_map = mz_phys_addr; 4710 rmem->pg_tbl_mz = mz; 4711 } 4712 4713 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4714 suffix, idx, bp->eth_dev->data->port_id); 4715 mz = rte_memzone_lookup(mz_name); 4716 if (!mz) { 4717 mz = rte_memzone_reserve_aligned(mz_name, 4718 mem_size, 4719 bp->eth_dev->device->numa_node, 4720 RTE_MEMZONE_1GB | 4721 RTE_MEMZONE_SIZE_HINT_ONLY | 4722 RTE_MEMZONE_IOVA_CONTIG, 4723 BNXT_PAGE_SIZE); 4724 if (mz == NULL) 4725 return -ENOMEM; 4726 } 4727 4728 memset(mz->addr, 0, mz->len); 4729 mz_phys_addr = mz->iova; 4730 4731 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4732 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4733 rmem->dma_arr[i] = mz_phys_addr + sz; 4734 4735 if (rmem->nr_pages > 1) { 4736 if (i == rmem->nr_pages - 2 && 4737 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4738 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4739 else if (i == rmem->nr_pages - 1 && 4740 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4741 valid_bits |= PTU_PTE_LAST; 4742 4743 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4744 valid_bits); 4745 } 4746 } 4747 4748 rmem->mz = mz; 4749 if (rmem->vmem_size) 4750 rmem->vmem = (void **)mz->addr; 4751 rmem->dma_arr[0] = mz_phys_addr; 4752 return 0; 4753 } 4754 4755 static void bnxt_free_ctx_mem(struct bnxt *bp) 4756 { 4757 int i; 4758 4759 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4760 return; 4761 4762 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4763 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4764 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4765 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4766 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4767 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4768 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4769 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4770 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4771 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4772 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4773 4774 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4775 if (bp->ctx->tqm_mem[i]) 4776 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4777 } 4778 4779 rte_free(bp->ctx); 4780 bp->ctx = NULL; 4781 } 4782 4783 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4784 4785 #define min_t(type, x, y) ({ \ 4786 type __min1 = (x); \ 4787 type __min2 = (y); \ 4788 __min1 < __min2 ? __min1 : __min2; }) 4789 4790 #define max_t(type, x, y) ({ \ 4791 type __max1 = (x); \ 4792 type __max2 = (y); \ 4793 __max1 > __max2 ? __max1 : __max2; }) 4794 4795 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4796 4797 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4798 { 4799 struct bnxt_ctx_pg_info *ctx_pg; 4800 struct bnxt_ctx_mem_info *ctx; 4801 uint32_t mem_size, ena, entries; 4802 uint32_t entries_sp, min; 4803 int i, rc; 4804 4805 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4806 if (rc) { 4807 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4808 return rc; 4809 } 4810 ctx = bp->ctx; 4811 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4812 return 0; 4813 4814 ctx_pg = &ctx->qp_mem; 4815 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4816 if (ctx->qp_entry_size) { 4817 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4818 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4819 if (rc) 4820 return rc; 4821 } 4822 4823 ctx_pg = &ctx->srq_mem; 4824 ctx_pg->entries = ctx->srq_max_l2_entries; 4825 if (ctx->srq_entry_size) { 4826 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4827 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4828 if (rc) 4829 return rc; 4830 } 4831 4832 ctx_pg = &ctx->cq_mem; 4833 ctx_pg->entries = ctx->cq_max_l2_entries; 4834 if (ctx->cq_entry_size) { 4835 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4836 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4837 if (rc) 4838 return rc; 4839 } 4840 4841 ctx_pg = &ctx->vnic_mem; 4842 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4843 ctx->vnic_max_ring_table_entries; 4844 if (ctx->vnic_entry_size) { 4845 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4846 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4847 if (rc) 4848 return rc; 4849 } 4850 4851 ctx_pg = &ctx->stat_mem; 4852 ctx_pg->entries = ctx->stat_max_entries; 4853 if (ctx->stat_entry_size) { 4854 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4855 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4856 if (rc) 4857 return rc; 4858 } 4859 4860 min = ctx->tqm_min_entries_per_ring; 4861 4862 entries_sp = ctx->qp_max_l2_entries + 4863 ctx->vnic_max_vnic_entries + 4864 2 * ctx->qp_min_qp1_entries + min; 4865 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4866 4867 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4868 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4869 entries = clamp_t(uint32_t, entries, min, 4870 ctx->tqm_max_entries_per_ring); 4871 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4872 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4873 * i > 8 is other ext rings. 4874 */ 4875 ctx_pg = ctx->tqm_mem[i]; 4876 ctx_pg->entries = i ? entries : entries_sp; 4877 if (ctx->tqm_entry_size) { 4878 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4879 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4880 "tqm_mem", i); 4881 if (rc) 4882 return rc; 4883 } 4884 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4885 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4886 else 4887 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4888 } 4889 4890 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4891 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4892 if (rc) 4893 PMD_DRV_LOG(ERR, 4894 "Failed to configure context mem: rc = %d\n", rc); 4895 else 4896 ctx->flags |= BNXT_CTX_FLAG_INITED; 4897 4898 return rc; 4899 } 4900 4901 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4902 { 4903 struct rte_pci_device *pci_dev = bp->pdev; 4904 char mz_name[RTE_MEMZONE_NAMESIZE]; 4905 const struct rte_memzone *mz = NULL; 4906 uint32_t total_alloc_len; 4907 rte_iova_t mz_phys_addr; 4908 4909 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4910 return 0; 4911 4912 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4913 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4914 pci_dev->addr.bus, pci_dev->addr.devid, 4915 pci_dev->addr.function, "rx_port_stats"); 4916 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4917 mz = rte_memzone_lookup(mz_name); 4918 total_alloc_len = 4919 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4920 sizeof(struct rx_port_stats_ext) + 512); 4921 if (!mz) { 4922 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4923 SOCKET_ID_ANY, 4924 RTE_MEMZONE_2MB | 4925 RTE_MEMZONE_SIZE_HINT_ONLY | 4926 RTE_MEMZONE_IOVA_CONTIG); 4927 if (mz == NULL) 4928 return -ENOMEM; 4929 } 4930 memset(mz->addr, 0, mz->len); 4931 mz_phys_addr = mz->iova; 4932 4933 bp->rx_mem_zone = (const void *)mz; 4934 bp->hw_rx_port_stats = mz->addr; 4935 bp->hw_rx_port_stats_map = mz_phys_addr; 4936 4937 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4938 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4939 pci_dev->addr.bus, pci_dev->addr.devid, 4940 pci_dev->addr.function, "tx_port_stats"); 4941 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4942 mz = rte_memzone_lookup(mz_name); 4943 total_alloc_len = 4944 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4945 sizeof(struct tx_port_stats_ext) + 512); 4946 if (!mz) { 4947 mz = rte_memzone_reserve(mz_name, 4948 total_alloc_len, 4949 SOCKET_ID_ANY, 4950 RTE_MEMZONE_2MB | 4951 RTE_MEMZONE_SIZE_HINT_ONLY | 4952 RTE_MEMZONE_IOVA_CONTIG); 4953 if (mz == NULL) 4954 return -ENOMEM; 4955 } 4956 memset(mz->addr, 0, mz->len); 4957 mz_phys_addr = mz->iova; 4958 4959 bp->tx_mem_zone = (const void *)mz; 4960 bp->hw_tx_port_stats = mz->addr; 4961 bp->hw_tx_port_stats_map = mz_phys_addr; 4962 bp->flags |= BNXT_FLAG_PORT_STATS; 4963 4964 /* Display extended statistics if FW supports it */ 4965 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4966 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4967 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4968 return 0; 4969 4970 bp->hw_rx_port_stats_ext = (void *) 4971 ((uint8_t *)bp->hw_rx_port_stats + 4972 sizeof(struct rx_port_stats)); 4973 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4974 sizeof(struct rx_port_stats); 4975 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4976 4977 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4978 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4979 bp->hw_tx_port_stats_ext = (void *) 4980 ((uint8_t *)bp->hw_tx_port_stats + 4981 sizeof(struct tx_port_stats)); 4982 bp->hw_tx_port_stats_ext_map = 4983 bp->hw_tx_port_stats_map + 4984 sizeof(struct tx_port_stats); 4985 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4986 } 4987 4988 return 0; 4989 } 4990 4991 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4992 { 4993 struct bnxt *bp = eth_dev->data->dev_private; 4994 int rc = 0; 4995 4996 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4997 RTE_ETHER_ADDR_LEN * 4998 bp->max_l2_ctx, 4999 0); 5000 if (eth_dev->data->mac_addrs == NULL) { 5001 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 5002 return -ENOMEM; 5003 } 5004 5005 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 5006 if (BNXT_PF(bp)) 5007 return -EINVAL; 5008 5009 /* Generate a random MAC address, if none was assigned by PF */ 5010 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 5011 bnxt_eth_hw_addr_random(bp->mac_addr); 5012 PMD_DRV_LOG(INFO, 5013 "Assign random MAC:" RTE_ETHER_ADDR_PRT_FMT "\n", 5014 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 5015 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 5016 5017 rc = bnxt_hwrm_set_mac(bp); 5018 if (rc) 5019 return rc; 5020 } 5021 5022 /* Copy the permanent MAC from the FUNC_QCAPS response */ 5023 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 5024 5025 return rc; 5026 } 5027 5028 static int bnxt_restore_dflt_mac(struct bnxt *bp) 5029 { 5030 int rc = 0; 5031 5032 /* MAC is already configured in FW */ 5033 if (BNXT_HAS_DFLT_MAC_SET(bp)) 5034 return 0; 5035 5036 /* Restore the old MAC configured */ 5037 rc = bnxt_hwrm_set_mac(bp); 5038 if (rc) 5039 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 5040 5041 return rc; 5042 } 5043 5044 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 5045 { 5046 if (!BNXT_PF(bp)) 5047 return; 5048 5049 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 5050 5051 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 5052 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 5053 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 5054 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 5055 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 5056 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 5057 } 5058 5059 struct bnxt * 5060 bnxt_get_bp(uint16_t port) 5061 { 5062 struct bnxt *bp; 5063 struct rte_eth_dev *dev; 5064 5065 if (!rte_eth_dev_is_valid_port(port)) { 5066 PMD_DRV_LOG(ERR, "Invalid port %d\n", port); 5067 return NULL; 5068 } 5069 5070 dev = &rte_eth_devices[port]; 5071 if (!is_bnxt_supported(dev)) { 5072 PMD_DRV_LOG(ERR, "Device %d not supported\n", port); 5073 return NULL; 5074 } 5075 5076 bp = (struct bnxt *)dev->data->dev_private; 5077 if (!BNXT_TRUFLOW_EN(bp)) { 5078 PMD_DRV_LOG(ERR, "TRUFLOW not enabled\n"); 5079 return NULL; 5080 } 5081 5082 return bp; 5083 } 5084 5085 uint16_t 5086 bnxt_get_svif(uint16_t port_id, bool func_svif, 5087 enum bnxt_ulp_intf_type type) 5088 { 5089 struct rte_eth_dev *eth_dev; 5090 struct bnxt *bp; 5091 5092 eth_dev = &rte_eth_devices[port_id]; 5093 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5094 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5095 if (!vfr) 5096 return 0; 5097 5098 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5099 return vfr->svif; 5100 5101 eth_dev = vfr->parent_dev; 5102 } 5103 5104 bp = eth_dev->data->dev_private; 5105 5106 return func_svif ? bp->func_svif : bp->port_svif; 5107 } 5108 5109 void 5110 bnxt_get_iface_mac(uint16_t port, enum bnxt_ulp_intf_type type, 5111 uint8_t *mac, uint8_t *parent_mac) 5112 { 5113 struct rte_eth_dev *eth_dev; 5114 struct bnxt *bp; 5115 5116 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF && 5117 type != BNXT_ULP_INTF_TYPE_PF) 5118 return; 5119 5120 eth_dev = &rte_eth_devices[port]; 5121 bp = eth_dev->data->dev_private; 5122 memcpy(mac, bp->mac_addr, RTE_ETHER_ADDR_LEN); 5123 5124 if (type == BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5125 memcpy(parent_mac, bp->parent->mac_addr, RTE_ETHER_ADDR_LEN); 5126 } 5127 5128 uint16_t 5129 bnxt_get_parent_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5130 { 5131 struct rte_eth_dev *eth_dev; 5132 struct bnxt *bp; 5133 5134 if (type != BNXT_ULP_INTF_TYPE_TRUSTED_VF) 5135 return 0; 5136 5137 eth_dev = &rte_eth_devices[port]; 5138 bp = eth_dev->data->dev_private; 5139 5140 return bp->parent->vnic; 5141 } 5142 uint16_t 5143 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 5144 { 5145 struct rte_eth_dev *eth_dev; 5146 struct bnxt_vnic_info *vnic; 5147 struct bnxt *bp; 5148 5149 eth_dev = &rte_eth_devices[port]; 5150 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5151 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5152 if (!vfr) 5153 return 0; 5154 5155 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5156 return vfr->dflt_vnic_id; 5157 5158 eth_dev = vfr->parent_dev; 5159 } 5160 5161 bp = eth_dev->data->dev_private; 5162 5163 vnic = BNXT_GET_DEFAULT_VNIC(bp); 5164 5165 return vnic->fw_vnic_id; 5166 } 5167 5168 uint16_t 5169 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 5170 { 5171 struct rte_eth_dev *eth_dev; 5172 struct bnxt *bp; 5173 5174 eth_dev = &rte_eth_devices[port]; 5175 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5176 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5177 if (!vfr) 5178 return 0; 5179 5180 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5181 return vfr->fw_fid; 5182 5183 eth_dev = vfr->parent_dev; 5184 } 5185 5186 bp = eth_dev->data->dev_private; 5187 5188 return bp->fw_fid; 5189 } 5190 5191 enum bnxt_ulp_intf_type 5192 bnxt_get_interface_type(uint16_t port) 5193 { 5194 struct rte_eth_dev *eth_dev; 5195 struct bnxt *bp; 5196 5197 eth_dev = &rte_eth_devices[port]; 5198 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 5199 return BNXT_ULP_INTF_TYPE_VF_REP; 5200 5201 bp = eth_dev->data->dev_private; 5202 if (BNXT_PF(bp)) 5203 return BNXT_ULP_INTF_TYPE_PF; 5204 else if (BNXT_VF_IS_TRUSTED(bp)) 5205 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 5206 else if (BNXT_VF(bp)) 5207 return BNXT_ULP_INTF_TYPE_VF; 5208 5209 return BNXT_ULP_INTF_TYPE_INVALID; 5210 } 5211 5212 uint16_t 5213 bnxt_get_phy_port_id(uint16_t port_id) 5214 { 5215 struct bnxt_representor *vfr; 5216 struct rte_eth_dev *eth_dev; 5217 struct bnxt *bp; 5218 5219 eth_dev = &rte_eth_devices[port_id]; 5220 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5221 vfr = eth_dev->data->dev_private; 5222 if (!vfr) 5223 return 0; 5224 5225 eth_dev = vfr->parent_dev; 5226 } 5227 5228 bp = eth_dev->data->dev_private; 5229 5230 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 5231 } 5232 5233 uint16_t 5234 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 5235 { 5236 struct rte_eth_dev *eth_dev; 5237 struct bnxt *bp; 5238 5239 eth_dev = &rte_eth_devices[port_id]; 5240 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 5241 struct bnxt_representor *vfr = eth_dev->data->dev_private; 5242 if (!vfr) 5243 return 0; 5244 5245 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 5246 return vfr->fw_fid - 1; 5247 5248 eth_dev = vfr->parent_dev; 5249 } 5250 5251 bp = eth_dev->data->dev_private; 5252 5253 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 5254 } 5255 5256 uint16_t 5257 bnxt_get_vport(uint16_t port_id) 5258 { 5259 return (1 << bnxt_get_phy_port_id(port_id)); 5260 } 5261 5262 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 5263 { 5264 struct bnxt_error_recovery_info *info = bp->recovery_info; 5265 5266 if (info) { 5267 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 5268 memset(info, 0, sizeof(*info)); 5269 return; 5270 } 5271 5272 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 5273 return; 5274 5275 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5276 sizeof(*info), 0); 5277 if (!info) 5278 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5279 5280 bp->recovery_info = info; 5281 } 5282 5283 static void bnxt_check_fw_status(struct bnxt *bp) 5284 { 5285 uint32_t fw_status; 5286 5287 if (!(bp->recovery_info && 5288 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 5289 return; 5290 5291 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 5292 if (fw_status != BNXT_FW_STATUS_HEALTHY) 5293 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 5294 fw_status); 5295 } 5296 5297 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 5298 { 5299 struct bnxt_error_recovery_info *info = bp->recovery_info; 5300 uint32_t status_loc; 5301 uint32_t sig_ver; 5302 5303 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 5304 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5305 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5306 BNXT_GRCP_WINDOW_2_BASE + 5307 offsetof(struct hcomm_status, 5308 sig_ver))); 5309 /* If the signature is absent, then FW does not support this feature */ 5310 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 5311 HCOMM_STATUS_SIGNATURE_VAL) 5312 return 0; 5313 5314 if (!info) { 5315 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 5316 sizeof(*info), 0); 5317 if (!info) 5318 return -ENOMEM; 5319 bp->recovery_info = info; 5320 } else { 5321 memset(info, 0, sizeof(*info)); 5322 } 5323 5324 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 5325 BNXT_GRCP_WINDOW_2_BASE + 5326 offsetof(struct hcomm_status, 5327 fw_status_loc))); 5328 5329 /* Only pre-map the FW health status GRC register */ 5330 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 5331 return 0; 5332 5333 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 5334 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 5335 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 5336 5337 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 5338 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 5339 5340 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 5341 5342 return 0; 5343 } 5344 5345 /* This function gets the FW version along with the 5346 * capabilities(MAX and current) of the function, vnic, 5347 * error recovery, phy and other chip related info 5348 */ 5349 static int bnxt_get_config(struct bnxt *bp) 5350 { 5351 uint16_t mtu; 5352 int rc = 0; 5353 5354 bp->fw_cap = 0; 5355 5356 rc = bnxt_map_hcomm_fw_status_reg(bp); 5357 if (rc) 5358 return rc; 5359 5360 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 5361 if (rc) { 5362 bnxt_check_fw_status(bp); 5363 return rc; 5364 } 5365 5366 rc = bnxt_hwrm_func_reset(bp); 5367 if (rc) 5368 return -EIO; 5369 5370 rc = bnxt_hwrm_vnic_qcaps(bp); 5371 if (rc) 5372 return rc; 5373 5374 rc = bnxt_hwrm_queue_qportcfg(bp); 5375 if (rc) 5376 return rc; 5377 5378 /* Get the MAX capabilities for this function. 5379 * This function also allocates context memory for TQM rings and 5380 * informs the firmware about this allocated backing store memory. 5381 */ 5382 rc = bnxt_hwrm_func_qcaps(bp); 5383 if (rc) 5384 return rc; 5385 5386 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5387 if (rc) 5388 return rc; 5389 5390 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5391 if (rc) 5392 return rc; 5393 5394 bnxt_hwrm_port_mac_qcfg(bp); 5395 5396 bnxt_hwrm_parent_pf_qcfg(bp); 5397 5398 bnxt_hwrm_port_phy_qcaps(bp); 5399 5400 bnxt_alloc_error_recovery_info(bp); 5401 /* Get the adapter error recovery support info */ 5402 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5403 if (rc) 5404 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5405 5406 bnxt_hwrm_port_led_qcaps(bp); 5407 5408 return 0; 5409 } 5410 5411 static int 5412 bnxt_init_locks(struct bnxt *bp) 5413 { 5414 int err; 5415 5416 err = pthread_mutex_init(&bp->flow_lock, NULL); 5417 if (err) { 5418 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5419 return err; 5420 } 5421 5422 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5423 if (err) { 5424 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5425 return err; 5426 } 5427 5428 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5429 if (err) { 5430 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5431 return err; 5432 } 5433 5434 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5435 if (err) 5436 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5437 5438 return err; 5439 } 5440 5441 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5442 { 5443 int rc = 0; 5444 5445 rc = bnxt_get_config(bp); 5446 if (rc) 5447 return rc; 5448 5449 if (!reconfig_dev) { 5450 rc = bnxt_setup_mac_addr(bp->eth_dev); 5451 if (rc) 5452 return rc; 5453 } else { 5454 rc = bnxt_restore_dflt_mac(bp); 5455 if (rc) 5456 return rc; 5457 } 5458 5459 bnxt_config_vf_req_fwd(bp); 5460 5461 rc = bnxt_hwrm_func_driver_register(bp); 5462 if (rc) { 5463 PMD_DRV_LOG(ERR, "Failed to register driver"); 5464 return -EBUSY; 5465 } 5466 5467 if (BNXT_PF(bp)) { 5468 if (bp->pdev->max_vfs) { 5469 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5470 if (rc) { 5471 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5472 return rc; 5473 } 5474 } else { 5475 rc = bnxt_hwrm_allocate_pf_only(bp); 5476 if (rc) { 5477 PMD_DRV_LOG(ERR, 5478 "Failed to allocate PF resources"); 5479 return rc; 5480 } 5481 } 5482 } 5483 5484 rc = bnxt_alloc_mem(bp, reconfig_dev); 5485 if (rc) 5486 return rc; 5487 5488 rc = bnxt_setup_int(bp); 5489 if (rc) 5490 return rc; 5491 5492 rc = bnxt_request_int(bp); 5493 if (rc) 5494 return rc; 5495 5496 rc = bnxt_init_ctx_mem(bp); 5497 if (rc) { 5498 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5499 return rc; 5500 } 5501 5502 return 0; 5503 } 5504 5505 static int 5506 bnxt_parse_devarg_accum_stats(__rte_unused const char *key, 5507 const char *value, void *opaque_arg) 5508 { 5509 struct bnxt *bp = opaque_arg; 5510 unsigned long accum_stats; 5511 char *end = NULL; 5512 5513 if (!value || !opaque_arg) { 5514 PMD_DRV_LOG(ERR, 5515 "Invalid parameter passed to accum-stats devargs.\n"); 5516 return -EINVAL; 5517 } 5518 5519 accum_stats = strtoul(value, &end, 10); 5520 if (end == NULL || *end != '\0' || 5521 (accum_stats == ULONG_MAX && errno == ERANGE)) { 5522 PMD_DRV_LOG(ERR, 5523 "Invalid parameter passed to accum-stats devargs.\n"); 5524 return -EINVAL; 5525 } 5526 5527 if (BNXT_DEVARG_ACCUM_STATS_INVALID(accum_stats)) { 5528 PMD_DRV_LOG(ERR, 5529 "Invalid value passed to accum-stats devargs.\n"); 5530 return -EINVAL; 5531 } 5532 5533 if (accum_stats) { 5534 bp->flags2 |= BNXT_FLAGS2_ACCUM_STATS_EN; 5535 PMD_DRV_LOG(INFO, "Host-based accum-stats feature enabled.\n"); 5536 } else { 5537 bp->flags2 &= ~BNXT_FLAGS2_ACCUM_STATS_EN; 5538 PMD_DRV_LOG(INFO, "Host-based accum-stats feature disabled.\n"); 5539 } 5540 5541 return 0; 5542 } 5543 5544 static int 5545 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5546 const char *value, void *opaque_arg) 5547 { 5548 struct bnxt *bp = opaque_arg; 5549 unsigned long flow_xstat; 5550 char *end = NULL; 5551 5552 if (!value || !opaque_arg) { 5553 PMD_DRV_LOG(ERR, 5554 "Invalid parameter passed to flow_xstat devarg.\n"); 5555 return -EINVAL; 5556 } 5557 5558 flow_xstat = strtoul(value, &end, 10); 5559 if (end == NULL || *end != '\0' || 5560 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5561 PMD_DRV_LOG(ERR, 5562 "Invalid parameter passed to flow_xstat devarg.\n"); 5563 return -EINVAL; 5564 } 5565 5566 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5567 PMD_DRV_LOG(ERR, 5568 "Invalid value passed to flow_xstat devarg.\n"); 5569 return -EINVAL; 5570 } 5571 5572 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5573 if (BNXT_FLOW_XSTATS_EN(bp)) 5574 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5575 5576 return 0; 5577 } 5578 5579 static int 5580 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5581 const char *value, void *opaque_arg) 5582 { 5583 struct bnxt *bp = opaque_arg; 5584 unsigned long max_num_kflows; 5585 char *end = NULL; 5586 5587 if (!value || !opaque_arg) { 5588 PMD_DRV_LOG(ERR, 5589 "Invalid parameter passed to max_num_kflows devarg.\n"); 5590 return -EINVAL; 5591 } 5592 5593 max_num_kflows = strtoul(value, &end, 10); 5594 if (end == NULL || *end != '\0' || 5595 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5596 PMD_DRV_LOG(ERR, 5597 "Invalid parameter passed to max_num_kflows devarg.\n"); 5598 return -EINVAL; 5599 } 5600 5601 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5602 PMD_DRV_LOG(ERR, 5603 "Invalid value passed to max_num_kflows devarg.\n"); 5604 return -EINVAL; 5605 } 5606 5607 bp->max_num_kflows = max_num_kflows; 5608 if (bp->max_num_kflows) 5609 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5610 max_num_kflows); 5611 5612 return 0; 5613 } 5614 5615 static int 5616 bnxt_parse_devarg_app_id(__rte_unused const char *key, 5617 const char *value, void *opaque_arg) 5618 { 5619 struct bnxt *bp = opaque_arg; 5620 unsigned long app_id; 5621 char *end = NULL; 5622 5623 if (!value || !opaque_arg) { 5624 PMD_DRV_LOG(ERR, 5625 "Invalid parameter passed to app-id " 5626 "devargs.\n"); 5627 return -EINVAL; 5628 } 5629 5630 app_id = strtoul(value, &end, 10); 5631 if (end == NULL || *end != '\0' || 5632 (app_id == ULONG_MAX && errno == ERANGE)) { 5633 PMD_DRV_LOG(ERR, 5634 "Invalid parameter passed to app_id " 5635 "devargs.\n"); 5636 return -EINVAL; 5637 } 5638 5639 if (BNXT_DEVARG_APP_ID_INVALID(app_id)) { 5640 PMD_DRV_LOG(ERR, "Invalid app-id(%d) devargs.\n", 5641 (uint16_t)app_id); 5642 return -EINVAL; 5643 } 5644 5645 bp->app_id = app_id; 5646 PMD_DRV_LOG(INFO, "app-id=%d feature enabled.\n", (uint16_t)app_id); 5647 5648 return 0; 5649 } 5650 5651 static int 5652 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5653 const char *value, void *opaque_arg) 5654 { 5655 struct bnxt_representor *vfr_bp = opaque_arg; 5656 unsigned long rep_is_pf; 5657 char *end = NULL; 5658 5659 if (!value || !opaque_arg) { 5660 PMD_DRV_LOG(ERR, 5661 "Invalid parameter passed to rep_is_pf devargs.\n"); 5662 return -EINVAL; 5663 } 5664 5665 rep_is_pf = strtoul(value, &end, 10); 5666 if (end == NULL || *end != '\0' || 5667 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5668 PMD_DRV_LOG(ERR, 5669 "Invalid parameter passed to rep_is_pf devargs.\n"); 5670 return -EINVAL; 5671 } 5672 5673 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5674 PMD_DRV_LOG(ERR, 5675 "Invalid value passed to rep_is_pf devargs.\n"); 5676 return -EINVAL; 5677 } 5678 5679 vfr_bp->flags |= rep_is_pf; 5680 if (BNXT_REP_PF(vfr_bp)) 5681 PMD_DRV_LOG(INFO, "PF representor\n"); 5682 else 5683 PMD_DRV_LOG(INFO, "VF representor\n"); 5684 5685 return 0; 5686 } 5687 5688 static int 5689 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5690 const char *value, void *opaque_arg) 5691 { 5692 struct bnxt_representor *vfr_bp = opaque_arg; 5693 unsigned long rep_based_pf; 5694 char *end = NULL; 5695 5696 if (!value || !opaque_arg) { 5697 PMD_DRV_LOG(ERR, 5698 "Invalid parameter passed to rep_based_pf " 5699 "devargs.\n"); 5700 return -EINVAL; 5701 } 5702 5703 rep_based_pf = strtoul(value, &end, 10); 5704 if (end == NULL || *end != '\0' || 5705 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5706 PMD_DRV_LOG(ERR, 5707 "Invalid parameter passed to rep_based_pf " 5708 "devargs.\n"); 5709 return -EINVAL; 5710 } 5711 5712 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5713 PMD_DRV_LOG(ERR, 5714 "Invalid value passed to rep_based_pf devargs.\n"); 5715 return -EINVAL; 5716 } 5717 5718 vfr_bp->rep_based_pf = rep_based_pf; 5719 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5720 5721 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5722 5723 return 0; 5724 } 5725 5726 static int 5727 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5728 const char *value, void *opaque_arg) 5729 { 5730 struct bnxt_representor *vfr_bp = opaque_arg; 5731 unsigned long rep_q_r2f; 5732 char *end = NULL; 5733 5734 if (!value || !opaque_arg) { 5735 PMD_DRV_LOG(ERR, 5736 "Invalid parameter passed to rep_q_r2f " 5737 "devargs.\n"); 5738 return -EINVAL; 5739 } 5740 5741 rep_q_r2f = strtoul(value, &end, 10); 5742 if (end == NULL || *end != '\0' || 5743 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5744 PMD_DRV_LOG(ERR, 5745 "Invalid parameter passed to rep_q_r2f " 5746 "devargs.\n"); 5747 return -EINVAL; 5748 } 5749 5750 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5751 PMD_DRV_LOG(ERR, 5752 "Invalid value passed to rep_q_r2f devargs.\n"); 5753 return -EINVAL; 5754 } 5755 5756 vfr_bp->rep_q_r2f = rep_q_r2f; 5757 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5758 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5759 5760 return 0; 5761 } 5762 5763 static int 5764 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5765 const char *value, void *opaque_arg) 5766 { 5767 struct bnxt_representor *vfr_bp = opaque_arg; 5768 unsigned long rep_q_f2r; 5769 char *end = NULL; 5770 5771 if (!value || !opaque_arg) { 5772 PMD_DRV_LOG(ERR, 5773 "Invalid parameter passed to rep_q_f2r " 5774 "devargs.\n"); 5775 return -EINVAL; 5776 } 5777 5778 rep_q_f2r = strtoul(value, &end, 10); 5779 if (end == NULL || *end != '\0' || 5780 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5781 PMD_DRV_LOG(ERR, 5782 "Invalid parameter passed to rep_q_f2r " 5783 "devargs.\n"); 5784 return -EINVAL; 5785 } 5786 5787 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5788 PMD_DRV_LOG(ERR, 5789 "Invalid value passed to rep_q_f2r devargs.\n"); 5790 return -EINVAL; 5791 } 5792 5793 vfr_bp->rep_q_f2r = rep_q_f2r; 5794 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5795 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5796 5797 return 0; 5798 } 5799 5800 static int 5801 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5802 const char *value, void *opaque_arg) 5803 { 5804 struct bnxt_representor *vfr_bp = opaque_arg; 5805 unsigned long rep_fc_r2f; 5806 char *end = NULL; 5807 5808 if (!value || !opaque_arg) { 5809 PMD_DRV_LOG(ERR, 5810 "Invalid parameter passed to rep_fc_r2f " 5811 "devargs.\n"); 5812 return -EINVAL; 5813 } 5814 5815 rep_fc_r2f = strtoul(value, &end, 10); 5816 if (end == NULL || *end != '\0' || 5817 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5818 PMD_DRV_LOG(ERR, 5819 "Invalid parameter passed to rep_fc_r2f " 5820 "devargs.\n"); 5821 return -EINVAL; 5822 } 5823 5824 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5825 PMD_DRV_LOG(ERR, 5826 "Invalid value passed to rep_fc_r2f devargs.\n"); 5827 return -EINVAL; 5828 } 5829 5830 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5831 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5832 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5833 5834 return 0; 5835 } 5836 5837 static int 5838 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5839 const char *value, void *opaque_arg) 5840 { 5841 struct bnxt_representor *vfr_bp = opaque_arg; 5842 unsigned long rep_fc_f2r; 5843 char *end = NULL; 5844 5845 if (!value || !opaque_arg) { 5846 PMD_DRV_LOG(ERR, 5847 "Invalid parameter passed to rep_fc_f2r " 5848 "devargs.\n"); 5849 return -EINVAL; 5850 } 5851 5852 rep_fc_f2r = strtoul(value, &end, 10); 5853 if (end == NULL || *end != '\0' || 5854 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5855 PMD_DRV_LOG(ERR, 5856 "Invalid parameter passed to rep_fc_f2r " 5857 "devargs.\n"); 5858 return -EINVAL; 5859 } 5860 5861 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5862 PMD_DRV_LOG(ERR, 5863 "Invalid value passed to rep_fc_f2r devargs.\n"); 5864 return -EINVAL; 5865 } 5866 5867 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5868 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5869 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5870 5871 return 0; 5872 } 5873 5874 static int 5875 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5876 { 5877 struct rte_kvargs *kvlist; 5878 int ret; 5879 5880 if (devargs == NULL) 5881 return 0; 5882 5883 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5884 if (kvlist == NULL) 5885 return -EINVAL; 5886 5887 /* 5888 * Handler for "flow_xstat" devarg. 5889 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5890 */ 5891 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5892 bnxt_parse_devarg_flow_xstat, bp); 5893 if (ret) 5894 goto err; 5895 5896 /* 5897 * Handler for "accum-stats" devarg. 5898 * Invoked as for ex: "-a 0000:00:0d.0,accum-stats=1" 5899 */ 5900 rte_kvargs_process(kvlist, BNXT_DEVARG_ACCUM_STATS, 5901 bnxt_parse_devarg_accum_stats, bp); 5902 /* 5903 * Handler for "max_num_kflows" devarg. 5904 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5905 */ 5906 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5907 bnxt_parse_devarg_max_num_kflows, bp); 5908 if (ret) 5909 goto err; 5910 5911 err: 5912 /* 5913 * Handler for "app-id" devarg. 5914 * Invoked as for ex: "-a 000:00:0d.0,app-id=1" 5915 */ 5916 rte_kvargs_process(kvlist, BNXT_DEVARG_APP_ID, 5917 bnxt_parse_devarg_app_id, bp); 5918 5919 rte_kvargs_free(kvlist); 5920 return ret; 5921 } 5922 5923 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5924 { 5925 int rc = 0; 5926 5927 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5928 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5929 if (rc) 5930 PMD_DRV_LOG(ERR, 5931 "Failed to alloc switch domain: %d\n", rc); 5932 else 5933 PMD_DRV_LOG(INFO, 5934 "Switch domain allocated %d\n", 5935 bp->switch_domain_id); 5936 } 5937 5938 return rc; 5939 } 5940 5941 /* Allocate and initialize various fields in bnxt struct that 5942 * need to be allocated/destroyed only once in the lifetime of the driver 5943 */ 5944 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5945 { 5946 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5947 struct bnxt *bp = eth_dev->data->dev_private; 5948 int rc = 0; 5949 5950 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5951 5952 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5953 bp->flags |= BNXT_FLAG_VF; 5954 5955 if (bnxt_p5_device(pci_dev->id.device_id)) 5956 bp->flags |= BNXT_FLAG_CHIP_P5; 5957 5958 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5959 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5960 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5961 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5962 bp->flags |= BNXT_FLAG_STINGRAY; 5963 5964 if (BNXT_TRUFLOW_EN(bp)) { 5965 /* extra mbuf field is required to store CFA code from mark */ 5966 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5967 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5968 .size = sizeof(bnxt_cfa_code_dynfield_t), 5969 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5970 }; 5971 bnxt_cfa_code_dynfield_offset = 5972 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5973 if (bnxt_cfa_code_dynfield_offset < 0) { 5974 PMD_DRV_LOG(ERR, 5975 "Failed to register mbuf field for TruFlow mark\n"); 5976 return -rte_errno; 5977 } 5978 } 5979 5980 rc = bnxt_map_pci_bars(eth_dev); 5981 if (rc) { 5982 PMD_DRV_LOG(ERR, 5983 "Failed to initialize board rc: %x\n", rc); 5984 return rc; 5985 } 5986 5987 rc = bnxt_alloc_pf_info(bp); 5988 if (rc) 5989 return rc; 5990 5991 rc = bnxt_alloc_link_info(bp); 5992 if (rc) 5993 return rc; 5994 5995 rc = bnxt_alloc_parent_info(bp); 5996 if (rc) 5997 return rc; 5998 5999 rc = bnxt_alloc_hwrm_resources(bp); 6000 if (rc) { 6001 PMD_DRV_LOG(ERR, 6002 "Failed to allocate response buffer rc: %x\n", rc); 6003 return rc; 6004 } 6005 rc = bnxt_alloc_leds_info(bp); 6006 if (rc) 6007 return rc; 6008 6009 rc = bnxt_alloc_cos_queues(bp); 6010 if (rc) 6011 return rc; 6012 6013 rc = bnxt_init_locks(bp); 6014 if (rc) 6015 return rc; 6016 6017 rc = bnxt_alloc_switch_domain(bp); 6018 if (rc) 6019 return rc; 6020 6021 return rc; 6022 } 6023 6024 static int 6025 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 6026 { 6027 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 6028 static int version_printed; 6029 struct bnxt *bp; 6030 int rc; 6031 6032 if (version_printed++ == 0) 6033 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 6034 6035 eth_dev->dev_ops = &bnxt_dev_ops; 6036 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 6037 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 6038 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 6039 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 6040 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 6041 6042 /* 6043 * For secondary processes, we don't initialise any further 6044 * as primary has already done this work. 6045 */ 6046 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6047 return 0; 6048 6049 rte_eth_copy_pci_info(eth_dev, pci_dev); 6050 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 6051 6052 bp = eth_dev->data->dev_private; 6053 6054 /* Parse dev arguments passed on when starting the DPDK application. */ 6055 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 6056 if (rc) 6057 goto error_free; 6058 6059 rc = bnxt_drv_init(eth_dev); 6060 if (rc) 6061 goto error_free; 6062 6063 rc = bnxt_init_resources(bp, false); 6064 if (rc) 6065 goto error_free; 6066 6067 rc = bnxt_alloc_stats_mem(bp); 6068 if (rc) 6069 goto error_free; 6070 6071 PMD_DRV_LOG(INFO, 6072 "Found %s device at mem %" PRIX64 ", node addr %pM\n", 6073 DRV_MODULE_NAME, 6074 pci_dev->mem_resource[0].phys_addr, 6075 pci_dev->mem_resource[0].addr); 6076 6077 return 0; 6078 6079 error_free: 6080 bnxt_dev_uninit(eth_dev); 6081 return rc; 6082 } 6083 6084 6085 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 6086 { 6087 if (!ctx) 6088 return; 6089 6090 if (ctx->va) 6091 rte_free(ctx->va); 6092 6093 ctx->va = NULL; 6094 ctx->dma = RTE_BAD_IOVA; 6095 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 6096 } 6097 6098 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 6099 { 6100 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 6101 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6102 bp->flow_stat->rx_fc_out_tbl.ctx_id, 6103 bp->flow_stat->max_fc, 6104 false); 6105 6106 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 6107 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 6108 bp->flow_stat->tx_fc_out_tbl.ctx_id, 6109 bp->flow_stat->max_fc, 6110 false); 6111 6112 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6113 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 6114 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6115 6116 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6117 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 6118 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6119 6120 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6121 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 6122 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6123 6124 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 6125 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 6126 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 6127 } 6128 6129 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 6130 { 6131 bnxt_unregister_fc_ctx_mem(bp); 6132 6133 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 6134 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 6135 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 6136 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 6137 } 6138 6139 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 6140 { 6141 if (BNXT_FLOW_XSTATS_EN(bp)) 6142 bnxt_uninit_fc_ctx_mem(bp); 6143 } 6144 6145 static void 6146 bnxt_free_error_recovery_info(struct bnxt *bp) 6147 { 6148 rte_free(bp->recovery_info); 6149 bp->recovery_info = NULL; 6150 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 6151 } 6152 6153 static int 6154 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 6155 { 6156 int rc; 6157 6158 bnxt_free_int(bp); 6159 bnxt_free_mem(bp, reconfig_dev); 6160 6161 bnxt_hwrm_func_buf_unrgtr(bp); 6162 if (bp->pf != NULL) { 6163 rte_free(bp->pf->vf_req_buf); 6164 bp->pf->vf_req_buf = NULL; 6165 } 6166 6167 rc = bnxt_hwrm_func_driver_unregister(bp); 6168 bp->flags &= ~BNXT_FLAG_REGISTERED; 6169 bnxt_free_ctx_mem(bp); 6170 if (!reconfig_dev) { 6171 bnxt_free_hwrm_resources(bp); 6172 bnxt_free_error_recovery_info(bp); 6173 } 6174 6175 bnxt_uninit_ctx_mem(bp); 6176 6177 bnxt_free_flow_stats_info(bp); 6178 if (bp->rep_info != NULL) 6179 bnxt_free_switch_domain(bp); 6180 bnxt_free_rep_info(bp); 6181 rte_free(bp->ptp_cfg); 6182 bp->ptp_cfg = NULL; 6183 return rc; 6184 } 6185 6186 static int 6187 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 6188 { 6189 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 6190 return -EPERM; 6191 6192 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 6193 6194 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 6195 bnxt_dev_close_op(eth_dev); 6196 6197 return 0; 6198 } 6199 6200 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 6201 { 6202 struct bnxt *bp = eth_dev->data->dev_private; 6203 struct rte_eth_dev *vf_rep_eth_dev; 6204 int ret = 0, i; 6205 6206 if (!bp) 6207 return -EINVAL; 6208 6209 for (i = 0; i < bp->num_reps; i++) { 6210 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 6211 if (!vf_rep_eth_dev) 6212 continue; 6213 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 6214 vf_rep_eth_dev->data->port_id); 6215 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 6216 } 6217 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 6218 eth_dev->data->port_id); 6219 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 6220 6221 return ret; 6222 } 6223 6224 static void bnxt_free_rep_info(struct bnxt *bp) 6225 { 6226 rte_free(bp->rep_info); 6227 bp->rep_info = NULL; 6228 rte_free(bp->cfa_code_map); 6229 bp->cfa_code_map = NULL; 6230 } 6231 6232 static int bnxt_init_rep_info(struct bnxt *bp) 6233 { 6234 int i = 0, rc; 6235 6236 if (bp->rep_info) 6237 return 0; 6238 6239 bp->rep_info = rte_zmalloc("bnxt_rep_info", 6240 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 6241 0); 6242 if (!bp->rep_info) { 6243 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 6244 return -ENOMEM; 6245 } 6246 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 6247 sizeof(*bp->cfa_code_map) * 6248 BNXT_MAX_CFA_CODE, 0); 6249 if (!bp->cfa_code_map) { 6250 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 6251 bnxt_free_rep_info(bp); 6252 return -ENOMEM; 6253 } 6254 6255 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 6256 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 6257 6258 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 6259 if (rc) { 6260 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 6261 bnxt_free_rep_info(bp); 6262 return rc; 6263 } 6264 6265 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 6266 if (rc) { 6267 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 6268 bnxt_free_rep_info(bp); 6269 return rc; 6270 } 6271 6272 return rc; 6273 } 6274 6275 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 6276 struct rte_eth_devargs *eth_da, 6277 struct rte_eth_dev *backing_eth_dev, 6278 const char *dev_args) 6279 { 6280 struct rte_eth_dev *vf_rep_eth_dev; 6281 char name[RTE_ETH_NAME_MAX_LEN]; 6282 struct bnxt *backing_bp; 6283 uint16_t num_rep; 6284 int i, ret = 0; 6285 struct rte_kvargs *kvlist = NULL; 6286 6287 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 6288 return 0; 6289 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 6290 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 6291 eth_da->type); 6292 return -ENOTSUP; 6293 } 6294 num_rep = eth_da->nb_representor_ports; 6295 if (num_rep > BNXT_MAX_VF_REPS) { 6296 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 6297 num_rep, BNXT_MAX_VF_REPS); 6298 return -EINVAL; 6299 } 6300 6301 if (num_rep >= RTE_MAX_ETHPORTS) { 6302 PMD_DRV_LOG(ERR, 6303 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 6304 num_rep, RTE_MAX_ETHPORTS); 6305 return -EINVAL; 6306 } 6307 6308 backing_bp = backing_eth_dev->data->dev_private; 6309 6310 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 6311 PMD_DRV_LOG(ERR, 6312 "Not a PF or trusted VF. No Representor support\n"); 6313 /* Returning an error is not an option. 6314 * Applications are not handling this correctly 6315 */ 6316 return 0; 6317 } 6318 6319 if (bnxt_init_rep_info(backing_bp)) 6320 return 0; 6321 6322 for (i = 0; i < num_rep; i++) { 6323 struct bnxt_representor representor = { 6324 .vf_id = eth_da->representor_ports[i], 6325 .switch_domain_id = backing_bp->switch_domain_id, 6326 .parent_dev = backing_eth_dev 6327 }; 6328 6329 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 6330 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 6331 representor.vf_id, BNXT_MAX_VF_REPS); 6332 continue; 6333 } 6334 6335 /* representor port net_bdf_port */ 6336 snprintf(name, sizeof(name), "net_%s_representor_%d", 6337 pci_dev->device.name, eth_da->representor_ports[i]); 6338 6339 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 6340 if (kvlist) { 6341 /* 6342 * Handler for "rep_is_pf" devarg. 6343 * Invoked as for ex: "-a 000:00:0d.0, 6344 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6345 */ 6346 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 6347 bnxt_parse_devarg_rep_is_pf, 6348 (void *)&representor); 6349 if (ret) { 6350 ret = -EINVAL; 6351 goto err; 6352 } 6353 /* 6354 * Handler for "rep_based_pf" devarg. 6355 * Invoked as for ex: "-a 000:00:0d.0, 6356 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6357 */ 6358 ret = rte_kvargs_process(kvlist, 6359 BNXT_DEVARG_REP_BASED_PF, 6360 bnxt_parse_devarg_rep_based_pf, 6361 (void *)&representor); 6362 if (ret) { 6363 ret = -EINVAL; 6364 goto err; 6365 } 6366 /* 6367 * Handler for "rep_based_pf" devarg. 6368 * Invoked as for ex: "-a 000:00:0d.0, 6369 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6370 */ 6371 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 6372 bnxt_parse_devarg_rep_q_r2f, 6373 (void *)&representor); 6374 if (ret) { 6375 ret = -EINVAL; 6376 goto err; 6377 } 6378 /* 6379 * Handler for "rep_based_pf" devarg. 6380 * Invoked as for ex: "-a 000:00:0d.0, 6381 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6382 */ 6383 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 6384 bnxt_parse_devarg_rep_q_f2r, 6385 (void *)&representor); 6386 if (ret) { 6387 ret = -EINVAL; 6388 goto err; 6389 } 6390 /* 6391 * Handler for "rep_based_pf" devarg. 6392 * Invoked as for ex: "-a 000:00:0d.0, 6393 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6394 */ 6395 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 6396 bnxt_parse_devarg_rep_fc_r2f, 6397 (void *)&representor); 6398 if (ret) { 6399 ret = -EINVAL; 6400 goto err; 6401 } 6402 /* 6403 * Handler for "rep_based_pf" devarg. 6404 * Invoked as for ex: "-a 000:00:0d.0, 6405 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 6406 */ 6407 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 6408 bnxt_parse_devarg_rep_fc_f2r, 6409 (void *)&representor); 6410 if (ret) { 6411 ret = -EINVAL; 6412 goto err; 6413 } 6414 } 6415 6416 ret = rte_eth_dev_create(&pci_dev->device, name, 6417 sizeof(struct bnxt_representor), 6418 NULL, NULL, 6419 bnxt_representor_init, 6420 &representor); 6421 if (ret) { 6422 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6423 "representor %s.", name); 6424 goto err; 6425 } 6426 6427 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6428 if (!vf_rep_eth_dev) { 6429 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6430 " for VF-Rep: %s.", name); 6431 ret = -ENODEV; 6432 goto err; 6433 } 6434 6435 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6436 backing_eth_dev->data->port_id); 6437 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6438 vf_rep_eth_dev; 6439 backing_bp->num_reps++; 6440 6441 } 6442 6443 rte_kvargs_free(kvlist); 6444 return 0; 6445 6446 err: 6447 /* If num_rep > 1, then rollback already created 6448 * ports, since we'll be failing the probe anyway 6449 */ 6450 if (num_rep > 1) 6451 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6452 rte_errno = -ret; 6453 rte_kvargs_free(kvlist); 6454 6455 return ret; 6456 } 6457 6458 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6459 struct rte_pci_device *pci_dev) 6460 { 6461 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6462 struct rte_eth_dev *backing_eth_dev; 6463 uint16_t num_rep; 6464 int ret = 0; 6465 6466 if (pci_dev->device.devargs) { 6467 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6468 ð_da); 6469 if (ret) 6470 return ret; 6471 } 6472 6473 num_rep = eth_da.nb_representor_ports; 6474 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6475 num_rep); 6476 6477 /* We could come here after first level of probe is already invoked 6478 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6479 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6480 */ 6481 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6482 if (backing_eth_dev == NULL) { 6483 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6484 sizeof(struct bnxt), 6485 eth_dev_pci_specific_init, pci_dev, 6486 bnxt_dev_init, NULL); 6487 6488 if (ret || !num_rep) 6489 return ret; 6490 6491 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6492 } 6493 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6494 backing_eth_dev->data->port_id); 6495 6496 if (!num_rep) 6497 return ret; 6498 6499 /* probe representor ports now */ 6500 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6501 pci_dev->device.devargs->args); 6502 6503 return ret; 6504 } 6505 6506 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6507 { 6508 struct rte_eth_dev *eth_dev; 6509 6510 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6511 if (!eth_dev) 6512 return 0; /* Invoked typically only by OVS-DPDK, by the 6513 * time it comes here the eth_dev is already 6514 * deleted by rte_eth_dev_close(), so returning 6515 * +ve value will at least help in proper cleanup 6516 */ 6517 6518 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6519 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6520 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6521 return rte_eth_dev_destroy(eth_dev, 6522 bnxt_representor_uninit); 6523 else 6524 return rte_eth_dev_destroy(eth_dev, 6525 bnxt_dev_uninit); 6526 } else { 6527 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6528 } 6529 } 6530 6531 static struct rte_pci_driver bnxt_rte_pmd = { 6532 .id_table = bnxt_pci_id_map, 6533 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6534 RTE_PCI_DRV_INTR_RMV | 6535 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6536 * and OVS-DPDK 6537 */ 6538 .probe = bnxt_pci_probe, 6539 .remove = bnxt_pci_remove, 6540 }; 6541 6542 static bool 6543 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6544 { 6545 if (strcmp(dev->device->driver->name, drv->driver.name)) 6546 return false; 6547 6548 return true; 6549 } 6550 6551 bool is_bnxt_supported(struct rte_eth_dev *dev) 6552 { 6553 return is_device_supported(dev, &bnxt_rte_pmd); 6554 } 6555 6556 RTE_LOG_REGISTER_SUFFIX(bnxt_logtype_driver, driver, NOTICE); 6557 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6558 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6559 6560