1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2021 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <ethdev_driver.h> 11 #include <ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 #include <rte_kvargs.h> 16 #include <rte_vect.h> 17 18 #include "bnxt.h" 19 #include "bnxt_filter.h" 20 #include "bnxt_hwrm.h" 21 #include "bnxt_irq.h" 22 #include "bnxt_reps.h" 23 #include "bnxt_ring.h" 24 #include "bnxt_rxq.h" 25 #include "bnxt_rxr.h" 26 #include "bnxt_stats.h" 27 #include "bnxt_txq.h" 28 #include "bnxt_txr.h" 29 #include "bnxt_vnic.h" 30 #include "hsi_struct_def_dpdk.h" 31 #include "bnxt_nvm_defs.h" 32 #include "bnxt_tf_common.h" 33 #include "ulp_flow_db.h" 34 #include "rte_pmd_bnxt.h" 35 36 #define DRV_MODULE_NAME "bnxt" 37 static const char bnxt_version[] = 38 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 39 40 /* 41 * The set of PCI devices this driver supports 42 */ 43 static const struct rte_pci_id bnxt_pci_id_map[] = { 44 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 45 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 46 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 47 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 48 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 49 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 50 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 51 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 52 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 53 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 54 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 55 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 56 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 57 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 58 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 59 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 60 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 61 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 62 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 63 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 64 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 65 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 66 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 67 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 68 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 69 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 70 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 71 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 72 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 73 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 74 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 75 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 76 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 77 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF1) }, 78 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF1) }, 79 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF1) }, 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508_MF2) }, 81 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504_MF2) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502_MF2) }, 83 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58812) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58814) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58818_VF) }, 87 { .vendor_id = 0, /* sentinel */ }, 88 }; 89 90 #define BNXT_DEVARG_TRUFLOW "host-based-truflow" 91 #define BNXT_DEVARG_FLOW_XSTAT "flow-xstat" 92 #define BNXT_DEVARG_MAX_NUM_KFLOWS "max-num-kflows" 93 #define BNXT_DEVARG_REPRESENTOR "representor" 94 #define BNXT_DEVARG_REP_BASED_PF "rep-based-pf" 95 #define BNXT_DEVARG_REP_IS_PF "rep-is-pf" 96 #define BNXT_DEVARG_REP_Q_R2F "rep-q-r2f" 97 #define BNXT_DEVARG_REP_Q_F2R "rep-q-f2r" 98 #define BNXT_DEVARG_REP_FC_R2F "rep-fc-r2f" 99 #define BNXT_DEVARG_REP_FC_F2R "rep-fc-f2r" 100 101 static const char *const bnxt_dev_args[] = { 102 BNXT_DEVARG_REPRESENTOR, 103 BNXT_DEVARG_TRUFLOW, 104 BNXT_DEVARG_FLOW_XSTAT, 105 BNXT_DEVARG_MAX_NUM_KFLOWS, 106 BNXT_DEVARG_REP_BASED_PF, 107 BNXT_DEVARG_REP_IS_PF, 108 BNXT_DEVARG_REP_Q_R2F, 109 BNXT_DEVARG_REP_Q_F2R, 110 BNXT_DEVARG_REP_FC_R2F, 111 BNXT_DEVARG_REP_FC_F2R, 112 NULL 113 }; 114 115 /* 116 * truflow == false to disable the feature 117 * truflow == true to enable the feature 118 */ 119 #define BNXT_DEVARG_TRUFLOW_INVALID(truflow) ((truflow) > 1) 120 121 /* 122 * flow_xstat == false to disable the feature 123 * flow_xstat == true to enable the feature 124 */ 125 #define BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat) ((flow_xstat) > 1) 126 127 /* 128 * rep_is_pf == false to indicate VF representor 129 * rep_is_pf == true to indicate PF representor 130 */ 131 #define BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf) ((rep_is_pf) > 1) 132 133 /* 134 * rep_based_pf == Physical index of the PF 135 */ 136 #define BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf) ((rep_based_pf) > 15) 137 /* 138 * rep_q_r2f == Logical COS Queue index for the rep to endpoint direction 139 */ 140 #define BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f) ((rep_q_r2f) > 3) 141 142 /* 143 * rep_q_f2r == Logical COS Queue index for the endpoint to rep direction 144 */ 145 #define BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r) ((rep_q_f2r) > 3) 146 147 /* 148 * rep_fc_r2f == Flow control for the representor to endpoint direction 149 */ 150 #define BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f) ((rep_fc_r2f) > 1) 151 152 /* 153 * rep_fc_f2r == Flow control for the endpoint to representor direction 154 */ 155 #define BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r) ((rep_fc_f2r) > 1) 156 157 int bnxt_cfa_code_dynfield_offset = -1; 158 159 /* 160 * max_num_kflows must be >= 32 161 * and must be a power-of-2 supported value 162 * return: 1 -> invalid 163 * 0 -> valid 164 */ 165 static int bnxt_devarg_max_num_kflow_invalid(uint16_t max_num_kflows) 166 { 167 if (max_num_kflows < 32 || !rte_is_power_of_2(max_num_kflows)) 168 return 1; 169 return 0; 170 } 171 172 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 173 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 174 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 175 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 176 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 177 static int bnxt_restore_vlan_filters(struct bnxt *bp); 178 static void bnxt_dev_recover(void *arg); 179 static void bnxt_free_error_recovery_info(struct bnxt *bp); 180 static void bnxt_free_rep_info(struct bnxt *bp); 181 182 int is_bnxt_in_error(struct bnxt *bp) 183 { 184 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 185 return -EIO; 186 if (bp->flags & BNXT_FLAG_FW_RESET) 187 return -EBUSY; 188 189 return 0; 190 } 191 192 /***********************/ 193 194 /* 195 * High level utility functions 196 */ 197 198 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 199 { 200 unsigned int num_rss_rings = RTE_MIN(bp->rx_nr_rings, 201 BNXT_RSS_TBL_SIZE_P5); 202 203 if (!BNXT_CHIP_P5(bp)) 204 return 1; 205 206 return RTE_ALIGN_MUL_CEIL(num_rss_rings, 207 BNXT_RSS_ENTRIES_PER_CTX_P5) / 208 BNXT_RSS_ENTRIES_PER_CTX_P5; 209 } 210 211 uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 212 { 213 if (!BNXT_CHIP_P5(bp)) 214 return HW_HASH_INDEX_SIZE; 215 216 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_P5; 217 } 218 219 static void bnxt_free_parent_info(struct bnxt *bp) 220 { 221 rte_free(bp->parent); 222 } 223 224 static void bnxt_free_pf_info(struct bnxt *bp) 225 { 226 rte_free(bp->pf); 227 } 228 229 static void bnxt_free_link_info(struct bnxt *bp) 230 { 231 rte_free(bp->link_info); 232 } 233 234 static void bnxt_free_leds_info(struct bnxt *bp) 235 { 236 if (BNXT_VF(bp)) 237 return; 238 239 rte_free(bp->leds); 240 bp->leds = NULL; 241 } 242 243 static void bnxt_free_flow_stats_info(struct bnxt *bp) 244 { 245 rte_free(bp->flow_stat); 246 bp->flow_stat = NULL; 247 } 248 249 static void bnxt_free_cos_queues(struct bnxt *bp) 250 { 251 rte_free(bp->rx_cos_queue); 252 rte_free(bp->tx_cos_queue); 253 } 254 255 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 256 { 257 bnxt_free_filter_mem(bp); 258 bnxt_free_vnic_attributes(bp); 259 bnxt_free_vnic_mem(bp); 260 261 /* tx/rx rings are configured as part of *_queue_setup callbacks. 262 * If the number of rings change across fw update, 263 * we don't have much choice except to warn the user. 264 */ 265 if (!reconfig) { 266 bnxt_free_stats(bp); 267 bnxt_free_tx_rings(bp); 268 bnxt_free_rx_rings(bp); 269 } 270 bnxt_free_async_cp_ring(bp); 271 bnxt_free_rxtx_nq_ring(bp); 272 273 rte_free(bp->grp_info); 274 bp->grp_info = NULL; 275 } 276 277 static int bnxt_alloc_parent_info(struct bnxt *bp) 278 { 279 bp->parent = rte_zmalloc("bnxt_parent_info", 280 sizeof(struct bnxt_parent_info), 0); 281 if (bp->parent == NULL) 282 return -ENOMEM; 283 284 return 0; 285 } 286 287 static int bnxt_alloc_pf_info(struct bnxt *bp) 288 { 289 bp->pf = rte_zmalloc("bnxt_pf_info", sizeof(struct bnxt_pf_info), 0); 290 if (bp->pf == NULL) 291 return -ENOMEM; 292 293 return 0; 294 } 295 296 static int bnxt_alloc_link_info(struct bnxt *bp) 297 { 298 bp->link_info = 299 rte_zmalloc("bnxt_link_info", sizeof(struct bnxt_link_info), 0); 300 if (bp->link_info == NULL) 301 return -ENOMEM; 302 303 return 0; 304 } 305 306 static int bnxt_alloc_leds_info(struct bnxt *bp) 307 { 308 if (BNXT_VF(bp)) 309 return 0; 310 311 bp->leds = rte_zmalloc("bnxt_leds", 312 BNXT_MAX_LED * sizeof(struct bnxt_led_info), 313 0); 314 if (bp->leds == NULL) 315 return -ENOMEM; 316 317 return 0; 318 } 319 320 static int bnxt_alloc_cos_queues(struct bnxt *bp) 321 { 322 bp->rx_cos_queue = 323 rte_zmalloc("bnxt_rx_cosq", 324 BNXT_COS_QUEUE_COUNT * 325 sizeof(struct bnxt_cos_queue_info), 326 0); 327 if (bp->rx_cos_queue == NULL) 328 return -ENOMEM; 329 330 bp->tx_cos_queue = 331 rte_zmalloc("bnxt_tx_cosq", 332 BNXT_COS_QUEUE_COUNT * 333 sizeof(struct bnxt_cos_queue_info), 334 0); 335 if (bp->tx_cos_queue == NULL) 336 return -ENOMEM; 337 338 return 0; 339 } 340 341 static int bnxt_alloc_flow_stats_info(struct bnxt *bp) 342 { 343 bp->flow_stat = rte_zmalloc("bnxt_flow_xstat", 344 sizeof(struct bnxt_flow_stat_info), 0); 345 if (bp->flow_stat == NULL) 346 return -ENOMEM; 347 348 return 0; 349 } 350 351 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 352 { 353 int rc; 354 355 rc = bnxt_alloc_ring_grps(bp); 356 if (rc) 357 goto alloc_mem_err; 358 359 rc = bnxt_alloc_async_ring_struct(bp); 360 if (rc) 361 goto alloc_mem_err; 362 363 rc = bnxt_alloc_vnic_mem(bp); 364 if (rc) 365 goto alloc_mem_err; 366 367 rc = bnxt_alloc_vnic_attributes(bp); 368 if (rc) 369 goto alloc_mem_err; 370 371 rc = bnxt_alloc_filter_mem(bp); 372 if (rc) 373 goto alloc_mem_err; 374 375 rc = bnxt_alloc_async_cp_ring(bp); 376 if (rc) 377 goto alloc_mem_err; 378 379 rc = bnxt_alloc_rxtx_nq_ring(bp); 380 if (rc) 381 goto alloc_mem_err; 382 383 if (BNXT_FLOW_XSTATS_EN(bp)) { 384 rc = bnxt_alloc_flow_stats_info(bp); 385 if (rc) 386 goto alloc_mem_err; 387 } 388 389 return 0; 390 391 alloc_mem_err: 392 bnxt_free_mem(bp, reconfig); 393 return rc; 394 } 395 396 static int bnxt_setup_one_vnic(struct bnxt *bp, uint16_t vnic_id) 397 { 398 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 399 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 400 uint64_t rx_offloads = dev_conf->rxmode.offloads; 401 struct bnxt_rx_queue *rxq; 402 unsigned int j; 403 int rc; 404 405 rc = bnxt_vnic_grp_alloc(bp, vnic); 406 if (rc) 407 goto err_out; 408 409 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 410 vnic_id, vnic, vnic->fw_grp_ids); 411 412 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 413 if (rc) 414 goto err_out; 415 416 /* Alloc RSS context only if RSS mode is enabled */ 417 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 418 int j, nr_ctxs = bnxt_rss_ctxts(bp); 419 420 if (bp->rx_nr_rings > BNXT_RSS_TBL_SIZE_P5) { 421 PMD_DRV_LOG(ERR, "RxQ cnt %d > reta_size %d\n", 422 bp->rx_nr_rings, BNXT_RSS_TBL_SIZE_P5); 423 PMD_DRV_LOG(ERR, 424 "Only queues 0-%d will be in RSS table\n", 425 BNXT_RSS_TBL_SIZE_P5 - 1); 426 } 427 428 rc = 0; 429 for (j = 0; j < nr_ctxs; j++) { 430 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 431 if (rc) 432 break; 433 } 434 if (rc) { 435 PMD_DRV_LOG(ERR, 436 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 437 vnic_id, j, rc); 438 goto err_out; 439 } 440 vnic->num_lb_ctxts = nr_ctxs; 441 } 442 443 /* 444 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 445 * setting is not available at this time, it will not be 446 * configured correctly in the CFA. 447 */ 448 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 449 vnic->vlan_strip = true; 450 else 451 vnic->vlan_strip = false; 452 453 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 454 if (rc) 455 goto err_out; 456 457 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 458 if (rc) 459 goto err_out; 460 461 for (j = 0; j < bp->rx_num_qs_per_vnic; j++) { 462 rxq = bp->eth_dev->data->rx_queues[j]; 463 464 PMD_DRV_LOG(DEBUG, 465 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 466 j, rxq->vnic, rxq->vnic->fw_grp_ids); 467 468 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 469 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 470 else 471 vnic->rx_queue_cnt++; 472 } 473 474 PMD_DRV_LOG(DEBUG, "vnic->rx_queue_cnt = %d\n", vnic->rx_queue_cnt); 475 476 rc = bnxt_vnic_rss_configure(bp, vnic); 477 if (rc) 478 goto err_out; 479 480 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 481 482 if (rx_offloads & DEV_RX_OFFLOAD_TCP_LRO) 483 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 484 else 485 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 486 487 return 0; 488 err_out: 489 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 490 vnic_id, rc); 491 return rc; 492 } 493 494 static int bnxt_register_fc_ctx_mem(struct bnxt *bp) 495 { 496 int rc = 0; 497 498 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_in_tbl.dma, 499 &bp->flow_stat->rx_fc_in_tbl.ctx_id); 500 if (rc) 501 return rc; 502 503 PMD_DRV_LOG(DEBUG, 504 "rx_fc_in_tbl.va = %p rx_fc_in_tbl.dma = %p" 505 " rx_fc_in_tbl.ctx_id = %d\n", 506 bp->flow_stat->rx_fc_in_tbl.va, 507 (void *)((uintptr_t)bp->flow_stat->rx_fc_in_tbl.dma), 508 bp->flow_stat->rx_fc_in_tbl.ctx_id); 509 510 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->rx_fc_out_tbl.dma, 511 &bp->flow_stat->rx_fc_out_tbl.ctx_id); 512 if (rc) 513 return rc; 514 515 PMD_DRV_LOG(DEBUG, 516 "rx_fc_out_tbl.va = %p rx_fc_out_tbl.dma = %p" 517 " rx_fc_out_tbl.ctx_id = %d\n", 518 bp->flow_stat->rx_fc_out_tbl.va, 519 (void *)((uintptr_t)bp->flow_stat->rx_fc_out_tbl.dma), 520 bp->flow_stat->rx_fc_out_tbl.ctx_id); 521 522 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_in_tbl.dma, 523 &bp->flow_stat->tx_fc_in_tbl.ctx_id); 524 if (rc) 525 return rc; 526 527 PMD_DRV_LOG(DEBUG, 528 "tx_fc_in_tbl.va = %p tx_fc_in_tbl.dma = %p" 529 " tx_fc_in_tbl.ctx_id = %d\n", 530 bp->flow_stat->tx_fc_in_tbl.va, 531 (void *)((uintptr_t)bp->flow_stat->tx_fc_in_tbl.dma), 532 bp->flow_stat->tx_fc_in_tbl.ctx_id); 533 534 rc = bnxt_hwrm_ctx_rgtr(bp, bp->flow_stat->tx_fc_out_tbl.dma, 535 &bp->flow_stat->tx_fc_out_tbl.ctx_id); 536 if (rc) 537 return rc; 538 539 PMD_DRV_LOG(DEBUG, 540 "tx_fc_out_tbl.va = %p tx_fc_out_tbl.dma = %p" 541 " tx_fc_out_tbl.ctx_id = %d\n", 542 bp->flow_stat->tx_fc_out_tbl.va, 543 (void *)((uintptr_t)bp->flow_stat->tx_fc_out_tbl.dma), 544 bp->flow_stat->tx_fc_out_tbl.ctx_id); 545 546 memset(bp->flow_stat->rx_fc_out_tbl.va, 547 0, 548 bp->flow_stat->rx_fc_out_tbl.size); 549 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 550 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 551 bp->flow_stat->rx_fc_out_tbl.ctx_id, 552 bp->flow_stat->max_fc, 553 true); 554 if (rc) 555 return rc; 556 557 memset(bp->flow_stat->tx_fc_out_tbl.va, 558 0, 559 bp->flow_stat->tx_fc_out_tbl.size); 560 rc = bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 561 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 562 bp->flow_stat->tx_fc_out_tbl.ctx_id, 563 bp->flow_stat->max_fc, 564 true); 565 566 return rc; 567 } 568 569 static int bnxt_alloc_ctx_mem_buf(char *type, size_t size, 570 struct bnxt_ctx_mem_buf_info *ctx) 571 { 572 if (!ctx) 573 return -EINVAL; 574 575 ctx->va = rte_zmalloc(type, size, 0); 576 if (ctx->va == NULL) 577 return -ENOMEM; 578 rte_mem_lock_page(ctx->va); 579 ctx->size = size; 580 ctx->dma = rte_mem_virt2iova(ctx->va); 581 if (ctx->dma == RTE_BAD_IOVA) 582 return -ENOMEM; 583 584 return 0; 585 } 586 587 static int bnxt_init_fc_ctx_mem(struct bnxt *bp) 588 { 589 struct rte_pci_device *pdev = bp->pdev; 590 char type[RTE_MEMZONE_NAMESIZE]; 591 uint16_t max_fc; 592 int rc = 0; 593 594 max_fc = bp->flow_stat->max_fc; 595 596 sprintf(type, "bnxt_rx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 597 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 598 /* 4 bytes for each counter-id */ 599 rc = bnxt_alloc_ctx_mem_buf(type, 600 max_fc * 4, 601 &bp->flow_stat->rx_fc_in_tbl); 602 if (rc) 603 return rc; 604 605 sprintf(type, "bnxt_rx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 606 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 607 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 608 rc = bnxt_alloc_ctx_mem_buf(type, 609 max_fc * 16, 610 &bp->flow_stat->rx_fc_out_tbl); 611 if (rc) 612 return rc; 613 614 sprintf(type, "bnxt_tx_fc_in_" PCI_PRI_FMT, pdev->addr.domain, 615 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 616 /* 4 bytes for each counter-id */ 617 rc = bnxt_alloc_ctx_mem_buf(type, 618 max_fc * 4, 619 &bp->flow_stat->tx_fc_in_tbl); 620 if (rc) 621 return rc; 622 623 sprintf(type, "bnxt_tx_fc_out_" PCI_PRI_FMT, pdev->addr.domain, 624 pdev->addr.bus, pdev->addr.devid, pdev->addr.function); 625 /* 16 bytes for each counter - 8 bytes pkt_count, 8 bytes byte_count */ 626 rc = bnxt_alloc_ctx_mem_buf(type, 627 max_fc * 16, 628 &bp->flow_stat->tx_fc_out_tbl); 629 if (rc) 630 return rc; 631 632 rc = bnxt_register_fc_ctx_mem(bp); 633 634 return rc; 635 } 636 637 static int bnxt_init_ctx_mem(struct bnxt *bp) 638 { 639 int rc = 0; 640 641 if (!(bp->fw_cap & BNXT_FW_CAP_ADV_FLOW_COUNTERS) || 642 !(BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) || 643 !BNXT_FLOW_XSTATS_EN(bp)) 644 return 0; 645 646 rc = bnxt_hwrm_cfa_counter_qcaps(bp, &bp->flow_stat->max_fc); 647 if (rc) 648 return rc; 649 650 rc = bnxt_init_fc_ctx_mem(bp); 651 652 return rc; 653 } 654 655 static int bnxt_update_phy_setting(struct bnxt *bp) 656 { 657 struct rte_eth_link new; 658 int rc; 659 660 rc = bnxt_get_hwrm_link_config(bp, &new); 661 if (rc) { 662 PMD_DRV_LOG(ERR, "Failed to get link settings\n"); 663 return rc; 664 } 665 666 /* 667 * On BCM957508-N2100 adapters, FW will not allow any user other 668 * than BMC to shutdown the port. bnxt_get_hwrm_link_config() call 669 * always returns link up. Force phy update always in that case. 670 */ 671 if (!new.link_status || IS_BNXT_DEV_957508_N2100(bp)) { 672 rc = bnxt_set_hwrm_link_config(bp, true); 673 if (rc) { 674 PMD_DRV_LOG(ERR, "Failed to update PHY settings\n"); 675 return rc; 676 } 677 } 678 679 return rc; 680 } 681 682 static int bnxt_start_nic(struct bnxt *bp) 683 { 684 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 685 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 686 uint32_t intr_vector = 0; 687 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 688 uint32_t vec = BNXT_MISC_VEC_ID; 689 unsigned int i, j; 690 int rc; 691 692 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 693 bp->eth_dev->data->dev_conf.rxmode.offloads |= 694 DEV_RX_OFFLOAD_JUMBO_FRAME; 695 bp->flags |= BNXT_FLAG_JUMBO; 696 } else { 697 bp->eth_dev->data->dev_conf.rxmode.offloads &= 698 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 699 bp->flags &= ~BNXT_FLAG_JUMBO; 700 } 701 702 /* THOR does not support ring groups. 703 * But we will use the array to save RSS context IDs. 704 */ 705 if (BNXT_CHIP_P5(bp)) 706 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_P5; 707 708 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 709 if (rc) { 710 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 711 goto err_out; 712 } 713 714 rc = bnxt_alloc_hwrm_rings(bp); 715 if (rc) { 716 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 717 goto err_out; 718 } 719 720 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 721 if (rc) { 722 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 723 goto err_out; 724 } 725 726 if (!(bp->vnic_cap_flags & BNXT_VNIC_CAP_COS_CLASSIFY)) 727 goto skip_cosq_cfg; 728 729 for (j = 0, i = 0; i < BNXT_COS_QUEUE_COUNT; i++) { 730 if (bp->rx_cos_queue[i].id != 0xff) { 731 struct bnxt_vnic_info *vnic = &bp->vnic_info[j++]; 732 733 if (!vnic) { 734 PMD_DRV_LOG(ERR, 735 "Num pools more than FW profile\n"); 736 rc = -EINVAL; 737 goto err_out; 738 } 739 vnic->cos_queue_id = bp->rx_cos_queue[i].id; 740 bp->rx_cosq_cnt++; 741 } 742 } 743 744 skip_cosq_cfg: 745 rc = bnxt_mq_rx_configure(bp); 746 if (rc) { 747 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 748 goto err_out; 749 } 750 751 /* default vnic 0 */ 752 rc = bnxt_setup_one_vnic(bp, 0); 753 if (rc) 754 goto err_out; 755 /* VNIC configuration */ 756 if (BNXT_RFS_NEEDS_VNIC(bp)) { 757 for (i = 1; i < bp->nr_vnics; i++) { 758 rc = bnxt_setup_one_vnic(bp, i); 759 if (rc) 760 goto err_out; 761 } 762 } 763 764 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 765 if (rc) { 766 PMD_DRV_LOG(ERR, 767 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 768 goto err_out; 769 } 770 771 /* check and configure queue intr-vector mapping */ 772 if ((rte_intr_cap_multiple(intr_handle) || 773 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 774 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 775 intr_vector = bp->eth_dev->data->nb_rx_queues; 776 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 777 if (intr_vector > bp->rx_cp_nr_rings) { 778 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 779 bp->rx_cp_nr_rings); 780 return -ENOTSUP; 781 } 782 rc = rte_intr_efd_enable(intr_handle, intr_vector); 783 if (rc) 784 return rc; 785 } 786 787 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 788 intr_handle->intr_vec = 789 rte_zmalloc("intr_vec", 790 bp->eth_dev->data->nb_rx_queues * 791 sizeof(int), 0); 792 if (intr_handle->intr_vec == NULL) { 793 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 794 " intr_vec", bp->eth_dev->data->nb_rx_queues); 795 rc = -ENOMEM; 796 goto err_disable; 797 } 798 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 799 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 800 intr_handle->intr_vec, intr_handle->nb_efd, 801 intr_handle->max_intr); 802 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 803 queue_id++) { 804 intr_handle->intr_vec[queue_id] = 805 vec + BNXT_RX_VEC_START; 806 if (vec < base + intr_handle->nb_efd - 1) 807 vec++; 808 } 809 } 810 811 /* enable uio/vfio intr/eventfd mapping */ 812 rc = rte_intr_enable(intr_handle); 813 #ifndef RTE_EXEC_ENV_FREEBSD 814 /* In FreeBSD OS, nic_uio driver does not support interrupts */ 815 if (rc) 816 goto err_free; 817 #endif 818 819 rc = bnxt_update_phy_setting(bp); 820 if (rc) 821 goto err_free; 822 823 bp->mark_table = rte_zmalloc("bnxt_mark_table", BNXT_MARK_TABLE_SZ, 0); 824 if (!bp->mark_table) 825 PMD_DRV_LOG(ERR, "Allocation of mark table failed\n"); 826 827 return 0; 828 829 err_free: 830 rte_free(intr_handle->intr_vec); 831 err_disable: 832 rte_intr_efd_disable(intr_handle); 833 err_out: 834 /* Some of the error status returned by FW may not be from errno.h */ 835 if (rc > 0) 836 rc = -EIO; 837 838 return rc; 839 } 840 841 static int bnxt_shutdown_nic(struct bnxt *bp) 842 { 843 bnxt_free_all_hwrm_resources(bp); 844 bnxt_free_all_filters(bp); 845 bnxt_free_all_vnics(bp); 846 return 0; 847 } 848 849 /* 850 * Device configuration and status function 851 */ 852 853 uint32_t bnxt_get_speed_capabilities(struct bnxt *bp) 854 { 855 uint32_t link_speed = bp->link_info->support_speeds; 856 uint32_t speed_capa = 0; 857 858 /* If PAM4 is configured, use PAM4 supported speed */ 859 if (link_speed == 0 && bp->link_info->support_pam4_speeds > 0) 860 link_speed = bp->link_info->support_pam4_speeds; 861 862 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_LINK_SPEED_100MB) 863 speed_capa |= ETH_LINK_SPEED_100M; 864 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100MBHD) 865 speed_capa |= ETH_LINK_SPEED_100M_HD; 866 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_1GB) 867 speed_capa |= ETH_LINK_SPEED_1G; 868 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_2_5GB) 869 speed_capa |= ETH_LINK_SPEED_2_5G; 870 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_10GB) 871 speed_capa |= ETH_LINK_SPEED_10G; 872 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_20GB) 873 speed_capa |= ETH_LINK_SPEED_20G; 874 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_25GB) 875 speed_capa |= ETH_LINK_SPEED_25G; 876 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_40GB) 877 speed_capa |= ETH_LINK_SPEED_40G; 878 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_50GB) 879 speed_capa |= ETH_LINK_SPEED_50G; 880 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_SPEEDS_100GB) 881 speed_capa |= ETH_LINK_SPEED_100G; 882 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_50G) 883 speed_capa |= ETH_LINK_SPEED_50G; 884 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_100G) 885 speed_capa |= ETH_LINK_SPEED_100G; 886 if (link_speed & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_PAM4_SPEEDS_200G) 887 speed_capa |= ETH_LINK_SPEED_200G; 888 889 if (bp->link_info->auto_mode == 890 HWRM_PORT_PHY_QCFG_OUTPUT_AUTO_MODE_NONE) 891 speed_capa |= ETH_LINK_SPEED_FIXED; 892 else 893 speed_capa |= ETH_LINK_SPEED_AUTONEG; 894 895 return speed_capa; 896 } 897 898 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 899 struct rte_eth_dev_info *dev_info) 900 { 901 struct rte_pci_device *pdev = RTE_DEV_TO_PCI(eth_dev->device); 902 struct bnxt *bp = eth_dev->data->dev_private; 903 uint16_t max_vnics, i, j, vpool, vrxq; 904 unsigned int max_rx_rings; 905 int rc; 906 907 rc = is_bnxt_in_error(bp); 908 if (rc) 909 return rc; 910 911 /* MAC Specifics */ 912 dev_info->max_mac_addrs = bp->max_l2_ctx; 913 dev_info->max_hash_mac_addrs = 0; 914 915 /* PF/VF specifics */ 916 if (BNXT_PF(bp)) 917 dev_info->max_vfs = pdev->max_vfs; 918 919 max_rx_rings = bnxt_max_rings(bp); 920 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 921 dev_info->max_rx_queues = max_rx_rings; 922 dev_info->max_tx_queues = max_rx_rings; 923 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 924 dev_info->hash_key_size = 40; 925 max_vnics = bp->max_vnics; 926 927 /* MTU specifics */ 928 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 929 dev_info->max_mtu = BNXT_MAX_MTU; 930 931 /* Fast path specifics */ 932 dev_info->min_rx_bufsize = 1; 933 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 934 935 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 936 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 937 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 938 dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE; 939 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT | 940 dev_info->tx_queue_offload_capa; 941 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 942 943 dev_info->speed_capa = bnxt_get_speed_capabilities(bp); 944 945 /* *INDENT-OFF* */ 946 dev_info->default_rxconf = (struct rte_eth_rxconf) { 947 .rx_thresh = { 948 .pthresh = 8, 949 .hthresh = 8, 950 .wthresh = 0, 951 }, 952 .rx_free_thresh = 32, 953 .rx_drop_en = BNXT_DEFAULT_RX_DROP_EN, 954 }; 955 956 dev_info->default_txconf = (struct rte_eth_txconf) { 957 .tx_thresh = { 958 .pthresh = 32, 959 .hthresh = 0, 960 .wthresh = 0, 961 }, 962 .tx_free_thresh = 32, 963 .tx_rs_thresh = 32, 964 }; 965 eth_dev->data->dev_conf.intr_conf.lsc = 1; 966 967 eth_dev->data->dev_conf.intr_conf.rxq = 1; 968 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 969 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 970 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 971 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 972 973 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 974 dev_info->switch_info.name = eth_dev->device->name; 975 dev_info->switch_info.domain_id = bp->switch_domain_id; 976 dev_info->switch_info.port_id = 977 BNXT_PF(bp) ? BNXT_SWITCH_PORT_ID_PF : 978 BNXT_SWITCH_PORT_ID_TRUSTED_VF; 979 } 980 981 /* *INDENT-ON* */ 982 983 /* 984 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 985 * need further investigation. 986 */ 987 988 /* VMDq resources */ 989 vpool = 64; /* ETH_64_POOLS */ 990 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 991 for (i = 0; i < 4; vpool >>= 1, i++) { 992 if (max_vnics > vpool) { 993 for (j = 0; j < 5; vrxq >>= 1, j++) { 994 if (dev_info->max_rx_queues > vrxq) { 995 if (vpool > vrxq) 996 vpool = vrxq; 997 goto found; 998 } 999 } 1000 /* Not enough resources to support VMDq */ 1001 break; 1002 } 1003 } 1004 /* Not enough resources to support VMDq */ 1005 vpool = 0; 1006 vrxq = 0; 1007 found: 1008 dev_info->max_vmdq_pools = vpool; 1009 dev_info->vmdq_queue_num = vrxq; 1010 1011 dev_info->vmdq_pool_base = 0; 1012 dev_info->vmdq_queue_base = 0; 1013 1014 return 0; 1015 } 1016 1017 /* Configure the device based on the configuration provided */ 1018 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 1019 { 1020 struct bnxt *bp = eth_dev->data->dev_private; 1021 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1022 int rc; 1023 1024 bp->rx_queues = (void *)eth_dev->data->rx_queues; 1025 bp->tx_queues = (void *)eth_dev->data->tx_queues; 1026 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 1027 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 1028 1029 rc = is_bnxt_in_error(bp); 1030 if (rc) 1031 return rc; 1032 1033 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 1034 rc = bnxt_hwrm_check_vf_rings(bp); 1035 if (rc) { 1036 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 1037 return -ENOSPC; 1038 } 1039 1040 /* If a resource has already been allocated - in this case 1041 * it is the async completion ring, free it. Reallocate it after 1042 * resource reservation. This will ensure the resource counts 1043 * are calculated correctly. 1044 */ 1045 1046 pthread_mutex_lock(&bp->def_cp_lock); 1047 1048 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1049 bnxt_disable_int(bp); 1050 bnxt_free_cp_ring(bp, bp->async_cp_ring); 1051 } 1052 1053 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 1054 if (rc) { 1055 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 1056 pthread_mutex_unlock(&bp->def_cp_lock); 1057 return -ENOSPC; 1058 } 1059 1060 if (!BNXT_HAS_NQ(bp) && bp->async_cp_ring) { 1061 rc = bnxt_alloc_async_cp_ring(bp); 1062 if (rc) { 1063 pthread_mutex_unlock(&bp->def_cp_lock); 1064 return rc; 1065 } 1066 bnxt_enable_int(bp); 1067 } 1068 1069 pthread_mutex_unlock(&bp->def_cp_lock); 1070 } 1071 1072 /* Inherit new configurations */ 1073 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 1074 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 1075 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 1076 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 1077 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 1078 bp->max_stat_ctx) 1079 goto resource_error; 1080 1081 if (BNXT_HAS_RING_GRPS(bp) && 1082 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 1083 goto resource_error; 1084 1085 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 1086 bp->max_vnics < eth_dev->data->nb_rx_queues) 1087 goto resource_error; 1088 1089 bp->rx_cp_nr_rings = bp->rx_nr_rings; 1090 bp->tx_cp_nr_rings = bp->tx_nr_rings; 1091 1092 if (eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) 1093 rx_offloads |= DEV_RX_OFFLOAD_RSS_HASH; 1094 eth_dev->data->dev_conf.rxmode.offloads = rx_offloads; 1095 1096 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 1097 eth_dev->data->mtu = 1098 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 1099 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 1100 BNXT_NUM_VLANS; 1101 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 1102 } 1103 return 0; 1104 1105 resource_error: 1106 PMD_DRV_LOG(ERR, 1107 "Insufficient resources to support requested config\n"); 1108 PMD_DRV_LOG(ERR, 1109 "Num Queues Requested: Tx %d, Rx %d\n", 1110 eth_dev->data->nb_tx_queues, 1111 eth_dev->data->nb_rx_queues); 1112 PMD_DRV_LOG(ERR, 1113 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 1114 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 1115 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 1116 return -ENOSPC; 1117 } 1118 1119 void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 1120 { 1121 struct rte_eth_link *link = ð_dev->data->dev_link; 1122 1123 if (link->link_status) 1124 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 1125 eth_dev->data->port_id, 1126 (uint32_t)link->link_speed, 1127 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 1128 ("full-duplex") : ("half-duplex\n")); 1129 else 1130 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 1131 eth_dev->data->port_id); 1132 } 1133 1134 /* 1135 * Determine whether the current configuration requires support for scattered 1136 * receive; return 1 if scattered receive is required and 0 if not. 1137 */ 1138 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 1139 { 1140 uint16_t buf_size; 1141 int i; 1142 1143 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_SCATTER) 1144 return 1; 1145 1146 if (eth_dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_TCP_LRO) 1147 return 1; 1148 1149 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 1150 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 1151 1152 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 1153 RTE_PKTMBUF_HEADROOM); 1154 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 1155 return 1; 1156 } 1157 return 0; 1158 } 1159 1160 static eth_rx_burst_t 1161 bnxt_receive_function(struct rte_eth_dev *eth_dev) 1162 { 1163 struct bnxt *bp = eth_dev->data->dev_private; 1164 1165 /* Disable vector mode RX for Stingray2 for now */ 1166 if (BNXT_CHIP_SR2(bp)) { 1167 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1168 return bnxt_recv_pkts; 1169 } 1170 1171 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1172 #ifndef RTE_LIBRTE_IEEE1588 1173 /* 1174 * Vector mode receive can be enabled only if scatter rx is not 1175 * in use and rx offloads are limited to VLAN stripping and 1176 * CRC stripping. 1177 */ 1178 if (!eth_dev->data->scattered_rx && 1179 !(eth_dev->data->dev_conf.rxmode.offloads & 1180 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 1181 DEV_RX_OFFLOAD_KEEP_CRC | 1182 DEV_RX_OFFLOAD_JUMBO_FRAME | 1183 DEV_RX_OFFLOAD_IPV4_CKSUM | 1184 DEV_RX_OFFLOAD_UDP_CKSUM | 1185 DEV_RX_OFFLOAD_TCP_CKSUM | 1186 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 1187 DEV_RX_OFFLOAD_OUTER_UDP_CKSUM | 1188 DEV_RX_OFFLOAD_RSS_HASH | 1189 DEV_RX_OFFLOAD_VLAN_FILTER)) && 1190 !BNXT_TRUFLOW_EN(bp) && BNXT_NUM_ASYNC_CPR(bp) && 1191 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1192 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 1193 eth_dev->data->port_id); 1194 bp->flags |= BNXT_FLAG_RX_VECTOR_PKT_MODE; 1195 return bnxt_recv_pkts_vec; 1196 } 1197 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 1198 eth_dev->data->port_id); 1199 PMD_DRV_LOG(INFO, 1200 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 1201 eth_dev->data->port_id, 1202 eth_dev->data->scattered_rx, 1203 eth_dev->data->dev_conf.rxmode.offloads); 1204 #endif 1205 #endif 1206 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1207 return bnxt_recv_pkts; 1208 } 1209 1210 static eth_tx_burst_t 1211 bnxt_transmit_function(struct rte_eth_dev *eth_dev) 1212 { 1213 struct bnxt *bp = eth_dev->data->dev_private; 1214 1215 /* Disable vector mode TX for Stingray2 for now */ 1216 if (BNXT_CHIP_SR2(bp)) 1217 return bnxt_xmit_pkts; 1218 1219 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 1220 #ifndef RTE_LIBRTE_IEEE1588 1221 uint64_t offloads = eth_dev->data->dev_conf.txmode.offloads; 1222 1223 /* 1224 * Vector mode transmit can be enabled only if not using scatter rx 1225 * or tx offloads. 1226 */ 1227 if (!eth_dev->data->scattered_rx && 1228 !(offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) && 1229 !BNXT_TRUFLOW_EN(bp) && 1230 rte_vect_get_max_simd_bitwidth() >= RTE_VECT_SIMD_128) { 1231 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 1232 eth_dev->data->port_id); 1233 return bnxt_xmit_pkts_vec; 1234 } 1235 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 1236 eth_dev->data->port_id); 1237 PMD_DRV_LOG(INFO, 1238 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 1239 eth_dev->data->port_id, 1240 eth_dev->data->scattered_rx, 1241 offloads); 1242 #endif 1243 #endif 1244 return bnxt_xmit_pkts; 1245 } 1246 1247 static int bnxt_handle_if_change_status(struct bnxt *bp) 1248 { 1249 int rc; 1250 1251 /* Since fw has undergone a reset and lost all contexts, 1252 * set fatal flag to not issue hwrm during cleanup 1253 */ 1254 bp->flags |= BNXT_FLAG_FATAL_ERROR; 1255 bnxt_uninit_resources(bp, true); 1256 1257 /* clear fatal flag so that re-init happens */ 1258 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 1259 rc = bnxt_init_resources(bp, true); 1260 1261 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 1262 1263 return rc; 1264 } 1265 1266 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 1267 { 1268 struct bnxt *bp = eth_dev->data->dev_private; 1269 int rc = 0; 1270 1271 if (!BNXT_SINGLE_PF(bp)) 1272 return -ENOTSUP; 1273 1274 if (!bp->link_info->link_up) 1275 rc = bnxt_set_hwrm_link_config(bp, true); 1276 if (!rc) 1277 eth_dev->data->dev_link.link_status = 1; 1278 1279 bnxt_print_link_info(eth_dev); 1280 return rc; 1281 } 1282 1283 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 1284 { 1285 struct bnxt *bp = eth_dev->data->dev_private; 1286 1287 if (!BNXT_SINGLE_PF(bp)) 1288 return -ENOTSUP; 1289 1290 eth_dev->data->dev_link.link_status = 0; 1291 bnxt_set_hwrm_link_config(bp, false); 1292 bp->link_info->link_up = 0; 1293 1294 return 0; 1295 } 1296 1297 static void bnxt_free_switch_domain(struct bnxt *bp) 1298 { 1299 int rc = 0; 1300 1301 if (bp->switch_domain_id) { 1302 rc = rte_eth_switch_domain_free(bp->switch_domain_id); 1303 if (rc) 1304 PMD_DRV_LOG(ERR, "free switch domain:%d fail: %d\n", 1305 bp->switch_domain_id, rc); 1306 } 1307 } 1308 1309 static void bnxt_ptp_get_current_time(void *arg) 1310 { 1311 struct bnxt *bp = arg; 1312 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1313 int rc; 1314 1315 rc = is_bnxt_in_error(bp); 1316 if (rc) 1317 return; 1318 1319 if (!ptp) 1320 return; 1321 1322 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1323 &ptp->current_time); 1324 1325 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1326 if (rc != 0) { 1327 PMD_DRV_LOG(ERR, "Failed to re-schedule PTP alarm\n"); 1328 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1329 } 1330 } 1331 1332 static int bnxt_schedule_ptp_alarm(struct bnxt *bp) 1333 { 1334 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 1335 int rc; 1336 1337 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) 1338 return 0; 1339 1340 bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 1341 &ptp->current_time); 1342 1343 rc = rte_eal_alarm_set(US_PER_S, bnxt_ptp_get_current_time, (void *)bp); 1344 return rc; 1345 } 1346 1347 static void bnxt_cancel_ptp_alarm(struct bnxt *bp) 1348 { 1349 if (bp->flags2 & BNXT_FLAGS2_PTP_ALARM_SCHEDULED) { 1350 rte_eal_alarm_cancel(bnxt_ptp_get_current_time, (void *)bp); 1351 bp->flags2 &= ~BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1352 } 1353 } 1354 1355 static void bnxt_ptp_stop(struct bnxt *bp) 1356 { 1357 bnxt_cancel_ptp_alarm(bp); 1358 bp->flags2 &= ~BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1359 } 1360 1361 static int bnxt_ptp_start(struct bnxt *bp) 1362 { 1363 int rc; 1364 1365 rc = bnxt_schedule_ptp_alarm(bp); 1366 if (rc != 0) { 1367 PMD_DRV_LOG(ERR, "Failed to schedule PTP alarm\n"); 1368 } else { 1369 bp->flags2 |= BNXT_FLAGS2_PTP_TIMESYNC_ENABLED; 1370 bp->flags2 |= BNXT_FLAGS2_PTP_ALARM_SCHEDULED; 1371 } 1372 1373 return rc; 1374 } 1375 1376 static int bnxt_dev_stop(struct rte_eth_dev *eth_dev) 1377 { 1378 struct bnxt *bp = eth_dev->data->dev_private; 1379 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 1380 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 1381 struct rte_eth_link link; 1382 int ret; 1383 1384 eth_dev->data->dev_started = 0; 1385 eth_dev->data->scattered_rx = 0; 1386 1387 /* Prevent crashes when queues are still in use */ 1388 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 1389 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 1390 1391 bnxt_disable_int(bp); 1392 1393 /* disable uio/vfio intr/eventfd mapping */ 1394 rte_intr_disable(intr_handle); 1395 1396 /* Stop the child representors for this device */ 1397 ret = bnxt_rep_stop_all(bp); 1398 if (ret != 0) 1399 return ret; 1400 1401 /* delete the bnxt ULP port details */ 1402 bnxt_ulp_port_deinit(bp); 1403 1404 bnxt_cancel_fw_health_check(bp); 1405 1406 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1407 bnxt_cancel_ptp_alarm(bp); 1408 1409 /* Do not bring link down during reset recovery */ 1410 if (!is_bnxt_in_error(bp)) { 1411 bnxt_dev_set_link_down_op(eth_dev); 1412 /* Wait for link to be reset */ 1413 if (BNXT_SINGLE_PF(bp)) 1414 rte_delay_ms(500); 1415 /* clear the recorded link status */ 1416 memset(&link, 0, sizeof(link)); 1417 rte_eth_linkstatus_set(eth_dev, &link); 1418 } 1419 1420 /* Clean queue intr-vector mapping */ 1421 rte_intr_efd_disable(intr_handle); 1422 if (intr_handle->intr_vec != NULL) { 1423 rte_free(intr_handle->intr_vec); 1424 intr_handle->intr_vec = NULL; 1425 } 1426 1427 bnxt_hwrm_port_clr_stats(bp); 1428 bnxt_free_tx_mbufs(bp); 1429 bnxt_free_rx_mbufs(bp); 1430 /* Process any remaining notifications in default completion queue */ 1431 bnxt_int_handler(eth_dev); 1432 bnxt_shutdown_nic(bp); 1433 bnxt_hwrm_if_change(bp, false); 1434 1435 rte_free(bp->mark_table); 1436 bp->mark_table = NULL; 1437 1438 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 1439 bp->rx_cosq_cnt = 0; 1440 /* All filters are deleted on a port stop. */ 1441 if (BNXT_FLOW_XSTATS_EN(bp)) 1442 bp->flow_stat->flow_count = 0; 1443 1444 return 0; 1445 } 1446 1447 /* Unload the driver, release resources */ 1448 static int bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 1449 { 1450 struct bnxt *bp = eth_dev->data->dev_private; 1451 1452 pthread_mutex_lock(&bp->err_recovery_lock); 1453 if (bp->flags & BNXT_FLAG_FW_RESET) { 1454 PMD_DRV_LOG(ERR, 1455 "Adapter recovering from error..Please retry\n"); 1456 pthread_mutex_unlock(&bp->err_recovery_lock); 1457 return -EAGAIN; 1458 } 1459 pthread_mutex_unlock(&bp->err_recovery_lock); 1460 1461 return bnxt_dev_stop(eth_dev); 1462 } 1463 1464 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 1465 { 1466 struct bnxt *bp = eth_dev->data->dev_private; 1467 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 1468 int vlan_mask = 0; 1469 int rc, retry_cnt = BNXT_IF_CHANGE_RETRY_COUNT; 1470 1471 if (!eth_dev->data->nb_tx_queues || !eth_dev->data->nb_rx_queues) { 1472 PMD_DRV_LOG(ERR, "Queues are not configured yet!\n"); 1473 return -EINVAL; 1474 } 1475 1476 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) 1477 PMD_DRV_LOG(ERR, 1478 "RxQ cnt %d > RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 1479 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 1480 1481 do { 1482 rc = bnxt_hwrm_if_change(bp, true); 1483 if (rc == 0 || rc != -EAGAIN) 1484 break; 1485 1486 rte_delay_ms(BNXT_IF_CHANGE_RETRY_INTERVAL); 1487 } while (retry_cnt--); 1488 1489 if (rc) 1490 return rc; 1491 1492 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 1493 rc = bnxt_handle_if_change_status(bp); 1494 if (rc) 1495 return rc; 1496 } 1497 1498 bnxt_enable_int(bp); 1499 1500 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 1501 1502 rc = bnxt_start_nic(bp); 1503 if (rc) 1504 goto error; 1505 1506 eth_dev->data->dev_started = 1; 1507 1508 bnxt_link_update_op(eth_dev, 1); 1509 1510 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 1511 vlan_mask |= ETH_VLAN_FILTER_MASK; 1512 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1513 vlan_mask |= ETH_VLAN_STRIP_MASK; 1514 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 1515 if (rc) 1516 goto error; 1517 1518 /* Initialize bnxt ULP port details */ 1519 rc = bnxt_ulp_port_init(bp); 1520 if (rc) 1521 goto error; 1522 1523 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 1524 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 1525 1526 bnxt_schedule_fw_health_check(bp); 1527 1528 if (BNXT_P5_PTP_TIMESYNC_ENABLED(bp)) 1529 bnxt_schedule_ptp_alarm(bp); 1530 1531 return 0; 1532 1533 error: 1534 bnxt_dev_stop(eth_dev); 1535 return rc; 1536 } 1537 1538 static void 1539 bnxt_uninit_locks(struct bnxt *bp) 1540 { 1541 pthread_mutex_destroy(&bp->flow_lock); 1542 pthread_mutex_destroy(&bp->def_cp_lock); 1543 pthread_mutex_destroy(&bp->health_check_lock); 1544 pthread_mutex_destroy(&bp->err_recovery_lock); 1545 if (bp->rep_info) { 1546 pthread_mutex_destroy(&bp->rep_info->vfr_lock); 1547 pthread_mutex_destroy(&bp->rep_info->vfr_start_lock); 1548 } 1549 } 1550 1551 static void bnxt_drv_uninit(struct bnxt *bp) 1552 { 1553 bnxt_free_switch_domain(bp); 1554 bnxt_free_leds_info(bp); 1555 bnxt_free_cos_queues(bp); 1556 bnxt_free_link_info(bp); 1557 bnxt_free_pf_info(bp); 1558 bnxt_free_parent_info(bp); 1559 bnxt_uninit_locks(bp); 1560 1561 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 1562 bp->tx_mem_zone = NULL; 1563 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 1564 bp->rx_mem_zone = NULL; 1565 1566 bnxt_free_vf_info(bp); 1567 1568 rte_free(bp->grp_info); 1569 bp->grp_info = NULL; 1570 } 1571 1572 static int bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 1573 { 1574 struct bnxt *bp = eth_dev->data->dev_private; 1575 int ret = 0; 1576 1577 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 1578 return 0; 1579 1580 pthread_mutex_lock(&bp->err_recovery_lock); 1581 if (bp->flags & BNXT_FLAG_FW_RESET) { 1582 PMD_DRV_LOG(ERR, 1583 "Adapter recovering from error...Please retry\n"); 1584 pthread_mutex_unlock(&bp->err_recovery_lock); 1585 return -EAGAIN; 1586 } 1587 pthread_mutex_unlock(&bp->err_recovery_lock); 1588 1589 /* cancel the recovery handler before remove dev */ 1590 rte_eal_alarm_cancel(bnxt_dev_reset_and_resume, (void *)bp); 1591 rte_eal_alarm_cancel(bnxt_dev_recover, (void *)bp); 1592 bnxt_cancel_fc_thread(bp); 1593 1594 if (eth_dev->data->dev_started) 1595 ret = bnxt_dev_stop(eth_dev); 1596 1597 bnxt_uninit_resources(bp, false); 1598 1599 bnxt_drv_uninit(bp); 1600 1601 return ret; 1602 } 1603 1604 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 1605 uint32_t index) 1606 { 1607 struct bnxt *bp = eth_dev->data->dev_private; 1608 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 1609 struct bnxt_vnic_info *vnic; 1610 struct bnxt_filter_info *filter, *temp_filter; 1611 uint32_t i; 1612 1613 if (is_bnxt_in_error(bp)) 1614 return; 1615 1616 /* 1617 * Loop through all VNICs from the specified filter flow pools to 1618 * remove the corresponding MAC addr filter 1619 */ 1620 for (i = 0; i < bp->nr_vnics; i++) { 1621 if (!(pool_mask & (1ULL << i))) 1622 continue; 1623 1624 vnic = &bp->vnic_info[i]; 1625 filter = STAILQ_FIRST(&vnic->filter); 1626 while (filter) { 1627 temp_filter = STAILQ_NEXT(filter, next); 1628 if (filter->mac_index == index) { 1629 STAILQ_REMOVE(&vnic->filter, filter, 1630 bnxt_filter_info, next); 1631 bnxt_hwrm_clear_l2_filter(bp, filter); 1632 bnxt_free_filter(bp, filter); 1633 } 1634 filter = temp_filter; 1635 } 1636 } 1637 } 1638 1639 static int bnxt_add_mac_filter(struct bnxt *bp, struct bnxt_vnic_info *vnic, 1640 struct rte_ether_addr *mac_addr, uint32_t index, 1641 uint32_t pool) 1642 { 1643 struct bnxt_filter_info *filter; 1644 int rc = 0; 1645 1646 /* Attach requested MAC address to the new l2_filter */ 1647 STAILQ_FOREACH(filter, &vnic->filter, next) { 1648 if (filter->mac_index == index) { 1649 PMD_DRV_LOG(DEBUG, 1650 "MAC addr already existed for pool %d\n", 1651 pool); 1652 return 0; 1653 } 1654 } 1655 1656 filter = bnxt_alloc_filter(bp); 1657 if (!filter) { 1658 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1659 return -ENODEV; 1660 } 1661 1662 /* bnxt_alloc_filter copies default MAC to filter->l2_addr. So, 1663 * if the MAC that's been programmed now is a different one, then, 1664 * copy that addr to filter->l2_addr 1665 */ 1666 if (mac_addr) 1667 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1668 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 1669 1670 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1671 if (!rc) { 1672 filter->mac_index = index; 1673 if (filter->mac_index == 0) 1674 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 1675 else 1676 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1677 } else { 1678 bnxt_free_filter(bp, filter); 1679 } 1680 1681 return rc; 1682 } 1683 1684 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1685 struct rte_ether_addr *mac_addr, 1686 uint32_t index, uint32_t pool) 1687 { 1688 struct bnxt *bp = eth_dev->data->dev_private; 1689 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1690 int rc = 0; 1691 1692 rc = is_bnxt_in_error(bp); 1693 if (rc) 1694 return rc; 1695 1696 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) { 1697 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1698 return -ENOTSUP; 1699 } 1700 1701 if (!vnic) { 1702 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1703 return -EINVAL; 1704 } 1705 1706 /* Filter settings will get applied when port is started */ 1707 if (!eth_dev->data->dev_started) 1708 return 0; 1709 1710 rc = bnxt_add_mac_filter(bp, vnic, mac_addr, index, pool); 1711 1712 return rc; 1713 } 1714 1715 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1716 { 1717 int rc = 0; 1718 struct bnxt *bp = eth_dev->data->dev_private; 1719 struct rte_eth_link new; 1720 int cnt = wait_to_complete ? BNXT_MAX_LINK_WAIT_CNT : 1721 BNXT_MIN_LINK_WAIT_CNT; 1722 1723 rc = is_bnxt_in_error(bp); 1724 if (rc) 1725 return rc; 1726 1727 memset(&new, 0, sizeof(new)); 1728 do { 1729 /* Retrieve link info from hardware */ 1730 rc = bnxt_get_hwrm_link_config(bp, &new); 1731 if (rc) { 1732 new.link_speed = ETH_LINK_SPEED_100M; 1733 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1734 PMD_DRV_LOG(ERR, 1735 "Failed to retrieve link rc = 0x%x!\n", rc); 1736 goto out; 1737 } 1738 1739 if (!wait_to_complete || new.link_status) 1740 break; 1741 1742 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1743 } while (cnt--); 1744 1745 /* Only single function PF can bring phy down. 1746 * When port is stopped, report link down for VF/MH/NPAR functions. 1747 */ 1748 if (!BNXT_SINGLE_PF(bp) && !eth_dev->data->dev_started) 1749 memset(&new, 0, sizeof(new)); 1750 1751 out: 1752 /* Timed out or success */ 1753 if (new.link_status != eth_dev->data->dev_link.link_status || 1754 new.link_speed != eth_dev->data->dev_link.link_speed) { 1755 rte_eth_linkstatus_set(eth_dev, &new); 1756 1757 rte_eth_dev_callback_process(eth_dev, 1758 RTE_ETH_EVENT_INTR_LSC, 1759 NULL); 1760 1761 bnxt_print_link_info(eth_dev); 1762 } 1763 1764 return rc; 1765 } 1766 1767 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1768 { 1769 struct bnxt *bp = eth_dev->data->dev_private; 1770 struct bnxt_vnic_info *vnic; 1771 uint32_t old_flags; 1772 int rc; 1773 1774 rc = is_bnxt_in_error(bp); 1775 if (rc) 1776 return rc; 1777 1778 /* Filter settings will get applied when port is started */ 1779 if (!eth_dev->data->dev_started) 1780 return 0; 1781 1782 if (bp->vnic_info == NULL) 1783 return 0; 1784 1785 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1786 1787 old_flags = vnic->flags; 1788 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1789 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1790 if (rc != 0) 1791 vnic->flags = old_flags; 1792 1793 return rc; 1794 } 1795 1796 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1797 { 1798 struct bnxt *bp = eth_dev->data->dev_private; 1799 struct bnxt_vnic_info *vnic; 1800 uint32_t old_flags; 1801 int rc; 1802 1803 rc = is_bnxt_in_error(bp); 1804 if (rc) 1805 return rc; 1806 1807 /* Filter settings will get applied when port is started */ 1808 if (!eth_dev->data->dev_started) 1809 return 0; 1810 1811 if (bp->vnic_info == NULL) 1812 return 0; 1813 1814 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1815 1816 old_flags = vnic->flags; 1817 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1818 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1819 if (rc != 0) 1820 vnic->flags = old_flags; 1821 1822 return rc; 1823 } 1824 1825 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1826 { 1827 struct bnxt *bp = eth_dev->data->dev_private; 1828 struct bnxt_vnic_info *vnic; 1829 uint32_t old_flags; 1830 int rc; 1831 1832 rc = is_bnxt_in_error(bp); 1833 if (rc) 1834 return rc; 1835 1836 /* Filter settings will get applied when port is started */ 1837 if (!eth_dev->data->dev_started) 1838 return 0; 1839 1840 if (bp->vnic_info == NULL) 1841 return 0; 1842 1843 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1844 1845 old_flags = vnic->flags; 1846 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1847 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1848 if (rc != 0) 1849 vnic->flags = old_flags; 1850 1851 return rc; 1852 } 1853 1854 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1855 { 1856 struct bnxt *bp = eth_dev->data->dev_private; 1857 struct bnxt_vnic_info *vnic; 1858 uint32_t old_flags; 1859 int rc; 1860 1861 rc = is_bnxt_in_error(bp); 1862 if (rc) 1863 return rc; 1864 1865 /* Filter settings will get applied when port is started */ 1866 if (!eth_dev->data->dev_started) 1867 return 0; 1868 1869 if (bp->vnic_info == NULL) 1870 return 0; 1871 1872 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1873 1874 old_flags = vnic->flags; 1875 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1876 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1877 if (rc != 0) 1878 vnic->flags = old_flags; 1879 1880 return rc; 1881 } 1882 1883 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1884 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1885 { 1886 if (qid >= bp->rx_nr_rings) 1887 return NULL; 1888 1889 return bp->eth_dev->data->rx_queues[qid]; 1890 } 1891 1892 /* Return rxq corresponding to a given rss table ring/group ID. */ 1893 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1894 { 1895 struct bnxt_rx_queue *rxq; 1896 unsigned int i; 1897 1898 if (!BNXT_HAS_RING_GRPS(bp)) { 1899 for (i = 0; i < bp->rx_nr_rings; i++) { 1900 rxq = bp->eth_dev->data->rx_queues[i]; 1901 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1902 return rxq->index; 1903 } 1904 } else { 1905 for (i = 0; i < bp->rx_nr_rings; i++) { 1906 if (bp->grp_info[i].fw_grp_id == fwr) 1907 return i; 1908 } 1909 } 1910 1911 return INVALID_HW_RING_ID; 1912 } 1913 1914 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1915 struct rte_eth_rss_reta_entry64 *reta_conf, 1916 uint16_t reta_size) 1917 { 1918 struct bnxt *bp = eth_dev->data->dev_private; 1919 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1920 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1921 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1922 uint16_t idx, sft; 1923 int i, rc; 1924 1925 rc = is_bnxt_in_error(bp); 1926 if (rc) 1927 return rc; 1928 1929 if (!vnic->rss_table) 1930 return -EINVAL; 1931 1932 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1933 return -EINVAL; 1934 1935 if (reta_size != tbl_size) { 1936 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1937 "(%d) must equal the size supported by the hardware " 1938 "(%d)\n", reta_size, tbl_size); 1939 return -EINVAL; 1940 } 1941 1942 for (i = 0; i < reta_size; i++) { 1943 struct bnxt_rx_queue *rxq; 1944 1945 idx = i / RTE_RETA_GROUP_SIZE; 1946 sft = i % RTE_RETA_GROUP_SIZE; 1947 1948 if (!(reta_conf[idx].mask & (1ULL << sft))) 1949 continue; 1950 1951 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1952 if (!rxq) { 1953 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1954 return -EINVAL; 1955 } 1956 1957 if (BNXT_CHIP_P5(bp)) { 1958 vnic->rss_table[i * 2] = 1959 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1960 vnic->rss_table[i * 2 + 1] = 1961 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1962 } else { 1963 vnic->rss_table[i] = 1964 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1965 } 1966 } 1967 1968 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1969 return rc; 1970 } 1971 1972 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1973 struct rte_eth_rss_reta_entry64 *reta_conf, 1974 uint16_t reta_size) 1975 { 1976 struct bnxt *bp = eth_dev->data->dev_private; 1977 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 1978 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1979 uint16_t idx, sft, i; 1980 int rc; 1981 1982 rc = is_bnxt_in_error(bp); 1983 if (rc) 1984 return rc; 1985 1986 /* Retrieve from the default VNIC */ 1987 if (!vnic) 1988 return -EINVAL; 1989 if (!vnic->rss_table) 1990 return -EINVAL; 1991 1992 if (reta_size != tbl_size) { 1993 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1994 "(%d) must equal the size supported by the hardware " 1995 "(%d)\n", reta_size, tbl_size); 1996 return -EINVAL; 1997 } 1998 1999 for (idx = 0, i = 0; i < reta_size; i++) { 2000 idx = i / RTE_RETA_GROUP_SIZE; 2001 sft = i % RTE_RETA_GROUP_SIZE; 2002 2003 if (reta_conf[idx].mask & (1ULL << sft)) { 2004 uint16_t qid; 2005 2006 if (BNXT_CHIP_P5(bp)) 2007 qid = bnxt_rss_to_qid(bp, 2008 vnic->rss_table[i * 2]); 2009 else 2010 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 2011 2012 if (qid == INVALID_HW_RING_ID) { 2013 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 2014 return -EINVAL; 2015 } 2016 reta_conf[idx].reta[sft] = qid; 2017 } 2018 } 2019 2020 return 0; 2021 } 2022 2023 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 2024 struct rte_eth_rss_conf *rss_conf) 2025 { 2026 struct bnxt *bp = eth_dev->data->dev_private; 2027 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 2028 struct bnxt_vnic_info *vnic; 2029 int rc; 2030 2031 rc = is_bnxt_in_error(bp); 2032 if (rc) 2033 return rc; 2034 2035 /* 2036 * If RSS enablement were different than dev_configure, 2037 * then return -EINVAL 2038 */ 2039 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 2040 if (!rss_conf->rss_hf) 2041 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 2042 } else { 2043 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 2044 return -EINVAL; 2045 } 2046 2047 bp->flags |= BNXT_FLAG_UPDATE_HASH; 2048 memcpy(ð_dev->data->dev_conf.rx_adv_conf.rss_conf, 2049 rss_conf, 2050 sizeof(*rss_conf)); 2051 2052 /* Update the default RSS VNIC(s) */ 2053 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2054 vnic->hash_type = bnxt_rte_to_hwrm_hash_types(rss_conf->rss_hf); 2055 vnic->hash_mode = 2056 bnxt_rte_to_hwrm_hash_level(bp, rss_conf->rss_hf, 2057 ETH_RSS_LEVEL(rss_conf->rss_hf)); 2058 2059 /* 2060 * If hashkey is not specified, use the previously configured 2061 * hashkey 2062 */ 2063 if (!rss_conf->rss_key) 2064 goto rss_config; 2065 2066 if (rss_conf->rss_key_len != HW_HASH_KEY_SIZE) { 2067 PMD_DRV_LOG(ERR, 2068 "Invalid hashkey length, should be 16 bytes\n"); 2069 return -EINVAL; 2070 } 2071 memcpy(vnic->rss_hash_key, rss_conf->rss_key, rss_conf->rss_key_len); 2072 2073 rss_config: 2074 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 2075 return rc; 2076 } 2077 2078 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 2079 struct rte_eth_rss_conf *rss_conf) 2080 { 2081 struct bnxt *bp = eth_dev->data->dev_private; 2082 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2083 int len, rc; 2084 uint32_t hash_types; 2085 2086 rc = is_bnxt_in_error(bp); 2087 if (rc) 2088 return rc; 2089 2090 /* RSS configuration is the same for all VNICs */ 2091 if (vnic && vnic->rss_hash_key) { 2092 if (rss_conf->rss_key) { 2093 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 2094 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 2095 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 2096 } 2097 2098 hash_types = vnic->hash_type; 2099 rss_conf->rss_hf = 0; 2100 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 2101 rss_conf->rss_hf |= ETH_RSS_IPV4; 2102 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 2103 } 2104 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 2105 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 2106 hash_types &= 2107 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 2108 } 2109 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 2110 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 2111 hash_types &= 2112 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 2113 } 2114 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 2115 rss_conf->rss_hf |= ETH_RSS_IPV6; 2116 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 2117 } 2118 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 2119 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 2120 hash_types &= 2121 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 2122 } 2123 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 2124 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 2125 hash_types &= 2126 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 2127 } 2128 2129 rss_conf->rss_hf |= 2130 bnxt_hwrm_to_rte_rss_level(bp, vnic->hash_mode); 2131 2132 if (hash_types) { 2133 PMD_DRV_LOG(ERR, 2134 "Unknown RSS config from firmware (%08x), RSS disabled", 2135 vnic->hash_type); 2136 return -ENOTSUP; 2137 } 2138 } else { 2139 rss_conf->rss_hf = 0; 2140 } 2141 return 0; 2142 } 2143 2144 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 2145 struct rte_eth_fc_conf *fc_conf) 2146 { 2147 struct bnxt *bp = dev->data->dev_private; 2148 struct rte_eth_link link_info; 2149 int rc; 2150 2151 rc = is_bnxt_in_error(bp); 2152 if (rc) 2153 return rc; 2154 2155 rc = bnxt_get_hwrm_link_config(bp, &link_info); 2156 if (rc) 2157 return rc; 2158 2159 memset(fc_conf, 0, sizeof(*fc_conf)); 2160 if (bp->link_info->auto_pause) 2161 fc_conf->autoneg = 1; 2162 switch (bp->link_info->pause) { 2163 case 0: 2164 fc_conf->mode = RTE_FC_NONE; 2165 break; 2166 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 2167 fc_conf->mode = RTE_FC_TX_PAUSE; 2168 break; 2169 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 2170 fc_conf->mode = RTE_FC_RX_PAUSE; 2171 break; 2172 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 2173 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 2174 fc_conf->mode = RTE_FC_FULL; 2175 break; 2176 } 2177 return 0; 2178 } 2179 2180 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 2181 struct rte_eth_fc_conf *fc_conf) 2182 { 2183 struct bnxt *bp = dev->data->dev_private; 2184 int rc; 2185 2186 rc = is_bnxt_in_error(bp); 2187 if (rc) 2188 return rc; 2189 2190 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2191 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 2192 return -ENOTSUP; 2193 } 2194 2195 switch (fc_conf->mode) { 2196 case RTE_FC_NONE: 2197 bp->link_info->auto_pause = 0; 2198 bp->link_info->force_pause = 0; 2199 break; 2200 case RTE_FC_RX_PAUSE: 2201 if (fc_conf->autoneg) { 2202 bp->link_info->auto_pause = 2203 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2204 bp->link_info->force_pause = 0; 2205 } else { 2206 bp->link_info->auto_pause = 0; 2207 bp->link_info->force_pause = 2208 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2209 } 2210 break; 2211 case RTE_FC_TX_PAUSE: 2212 if (fc_conf->autoneg) { 2213 bp->link_info->auto_pause = 2214 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 2215 bp->link_info->force_pause = 0; 2216 } else { 2217 bp->link_info->auto_pause = 0; 2218 bp->link_info->force_pause = 2219 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 2220 } 2221 break; 2222 case RTE_FC_FULL: 2223 if (fc_conf->autoneg) { 2224 bp->link_info->auto_pause = 2225 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 2226 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 2227 bp->link_info->force_pause = 0; 2228 } else { 2229 bp->link_info->auto_pause = 0; 2230 bp->link_info->force_pause = 2231 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 2232 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 2233 } 2234 break; 2235 } 2236 return bnxt_set_hwrm_link_config(bp, true); 2237 } 2238 2239 /* Add UDP tunneling port */ 2240 static int 2241 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 2242 struct rte_eth_udp_tunnel *udp_tunnel) 2243 { 2244 struct bnxt *bp = eth_dev->data->dev_private; 2245 uint16_t tunnel_type = 0; 2246 int rc = 0; 2247 2248 rc = is_bnxt_in_error(bp); 2249 if (rc) 2250 return rc; 2251 2252 switch (udp_tunnel->prot_type) { 2253 case RTE_TUNNEL_TYPE_VXLAN: 2254 if (bp->vxlan_port_cnt) { 2255 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2256 udp_tunnel->udp_port); 2257 if (bp->vxlan_port != udp_tunnel->udp_port) { 2258 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2259 return -ENOSPC; 2260 } 2261 bp->vxlan_port_cnt++; 2262 return 0; 2263 } 2264 tunnel_type = 2265 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 2266 bp->vxlan_port_cnt++; 2267 break; 2268 case RTE_TUNNEL_TYPE_GENEVE: 2269 if (bp->geneve_port_cnt) { 2270 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 2271 udp_tunnel->udp_port); 2272 if (bp->geneve_port != udp_tunnel->udp_port) { 2273 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 2274 return -ENOSPC; 2275 } 2276 bp->geneve_port_cnt++; 2277 return 0; 2278 } 2279 tunnel_type = 2280 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 2281 bp->geneve_port_cnt++; 2282 break; 2283 default: 2284 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2285 return -ENOTSUP; 2286 } 2287 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 2288 tunnel_type); 2289 return rc; 2290 } 2291 2292 static int 2293 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 2294 struct rte_eth_udp_tunnel *udp_tunnel) 2295 { 2296 struct bnxt *bp = eth_dev->data->dev_private; 2297 uint16_t tunnel_type = 0; 2298 uint16_t port = 0; 2299 int rc = 0; 2300 2301 rc = is_bnxt_in_error(bp); 2302 if (rc) 2303 return rc; 2304 2305 switch (udp_tunnel->prot_type) { 2306 case RTE_TUNNEL_TYPE_VXLAN: 2307 if (!bp->vxlan_port_cnt) { 2308 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2309 return -EINVAL; 2310 } 2311 if (bp->vxlan_port != udp_tunnel->udp_port) { 2312 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2313 udp_tunnel->udp_port, bp->vxlan_port); 2314 return -EINVAL; 2315 } 2316 if (--bp->vxlan_port_cnt) 2317 return 0; 2318 2319 tunnel_type = 2320 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 2321 port = bp->vxlan_fw_dst_port_id; 2322 break; 2323 case RTE_TUNNEL_TYPE_GENEVE: 2324 if (!bp->geneve_port_cnt) { 2325 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 2326 return -EINVAL; 2327 } 2328 if (bp->geneve_port != udp_tunnel->udp_port) { 2329 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 2330 udp_tunnel->udp_port, bp->geneve_port); 2331 return -EINVAL; 2332 } 2333 if (--bp->geneve_port_cnt) 2334 return 0; 2335 2336 tunnel_type = 2337 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 2338 port = bp->geneve_fw_dst_port_id; 2339 break; 2340 default: 2341 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 2342 return -ENOTSUP; 2343 } 2344 2345 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 2346 return rc; 2347 } 2348 2349 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2350 { 2351 struct bnxt_filter_info *filter; 2352 struct bnxt_vnic_info *vnic; 2353 int rc = 0; 2354 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2355 2356 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2357 filter = STAILQ_FIRST(&vnic->filter); 2358 while (filter) { 2359 /* Search for this matching MAC+VLAN filter */ 2360 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) { 2361 /* Delete the filter */ 2362 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2363 if (rc) 2364 return rc; 2365 STAILQ_REMOVE(&vnic->filter, filter, 2366 bnxt_filter_info, next); 2367 bnxt_free_filter(bp, filter); 2368 PMD_DRV_LOG(INFO, 2369 "Deleted vlan filter for %d\n", 2370 vlan_id); 2371 return 0; 2372 } 2373 filter = STAILQ_NEXT(filter, next); 2374 } 2375 return -ENOENT; 2376 } 2377 2378 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 2379 { 2380 struct bnxt_filter_info *filter; 2381 struct bnxt_vnic_info *vnic; 2382 int rc = 0; 2383 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 2384 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 2385 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 2386 2387 /* Implementation notes on the use of VNIC in this command: 2388 * 2389 * By default, these filters belong to default vnic for the function. 2390 * Once these filters are set up, only destination VNIC can be modified. 2391 * If the destination VNIC is not specified in this command, 2392 * then the HWRM shall only create an l2 context id. 2393 */ 2394 2395 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2396 filter = STAILQ_FIRST(&vnic->filter); 2397 /* Check if the VLAN has already been added */ 2398 while (filter) { 2399 if (bnxt_vlan_filter_exists(bp, filter, chk, vlan_id)) 2400 return -EEXIST; 2401 2402 filter = STAILQ_NEXT(filter, next); 2403 } 2404 2405 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 2406 * command to create MAC+VLAN filter with the right flags, enables set. 2407 */ 2408 filter = bnxt_alloc_filter(bp); 2409 if (!filter) { 2410 PMD_DRV_LOG(ERR, 2411 "MAC/VLAN filter alloc failed\n"); 2412 return -ENOMEM; 2413 } 2414 /* MAC + VLAN ID filter */ 2415 /* If l2_ivlan == 0 and l2_ivlan_mask != 0, only 2416 * untagged packets are received 2417 * 2418 * If l2_ivlan != 0 and l2_ivlan_mask != 0, untagged 2419 * packets and only the programmed vlan's packets are received 2420 */ 2421 filter->l2_ivlan = vlan_id; 2422 filter->l2_ivlan_mask = 0x0FFF; 2423 filter->enables |= en; 2424 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_OUTERMOST; 2425 2426 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 2427 if (rc) { 2428 /* Free the newly allocated filter as we were 2429 * not able to create the filter in hardware. 2430 */ 2431 bnxt_free_filter(bp, filter); 2432 return rc; 2433 } 2434 2435 filter->mac_index = 0; 2436 /* Add this new filter to the list */ 2437 if (vlan_id == 0) 2438 STAILQ_INSERT_HEAD(&vnic->filter, filter, next); 2439 else 2440 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2441 2442 PMD_DRV_LOG(INFO, 2443 "Added Vlan filter for %d\n", vlan_id); 2444 return rc; 2445 } 2446 2447 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 2448 uint16_t vlan_id, int on) 2449 { 2450 struct bnxt *bp = eth_dev->data->dev_private; 2451 int rc; 2452 2453 rc = is_bnxt_in_error(bp); 2454 if (rc) 2455 return rc; 2456 2457 if (!eth_dev->data->dev_started) { 2458 PMD_DRV_LOG(ERR, "port must be started before setting vlan\n"); 2459 return -EINVAL; 2460 } 2461 2462 /* These operations apply to ALL existing MAC/VLAN filters */ 2463 if (on) 2464 return bnxt_add_vlan_filter(bp, vlan_id); 2465 else 2466 return bnxt_del_vlan_filter(bp, vlan_id); 2467 } 2468 2469 static int bnxt_del_dflt_mac_filter(struct bnxt *bp, 2470 struct bnxt_vnic_info *vnic) 2471 { 2472 struct bnxt_filter_info *filter; 2473 int rc; 2474 2475 filter = STAILQ_FIRST(&vnic->filter); 2476 while (filter) { 2477 if (filter->mac_index == 0 && 2478 !memcmp(filter->l2_addr, bp->mac_addr, 2479 RTE_ETHER_ADDR_LEN)) { 2480 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 2481 if (!rc) { 2482 STAILQ_REMOVE(&vnic->filter, filter, 2483 bnxt_filter_info, next); 2484 bnxt_free_filter(bp, filter); 2485 } 2486 return rc; 2487 } 2488 filter = STAILQ_NEXT(filter, next); 2489 } 2490 return 0; 2491 } 2492 2493 static int 2494 bnxt_config_vlan_hw_filter(struct bnxt *bp, uint64_t rx_offloads) 2495 { 2496 struct bnxt_vnic_info *vnic; 2497 unsigned int i; 2498 int rc; 2499 2500 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2501 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 2502 /* Remove any VLAN filters programmed */ 2503 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2504 bnxt_del_vlan_filter(bp, i); 2505 2506 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2507 if (rc) 2508 return rc; 2509 } else { 2510 /* Default filter will allow packets that match the 2511 * dest mac. So, it has to be deleted, otherwise, we 2512 * will endup receiving vlan packets for which the 2513 * filter is not programmed, when hw-vlan-filter 2514 * configuration is ON 2515 */ 2516 bnxt_del_dflt_mac_filter(bp, vnic); 2517 /* This filter will allow only untagged packets */ 2518 bnxt_add_vlan_filter(bp, 0); 2519 } 2520 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 2521 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 2522 2523 return 0; 2524 } 2525 2526 static int bnxt_free_one_vnic(struct bnxt *bp, uint16_t vnic_id) 2527 { 2528 struct bnxt_vnic_info *vnic = &bp->vnic_info[vnic_id]; 2529 unsigned int i; 2530 int rc; 2531 2532 /* Destroy vnic filters and vnic */ 2533 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2534 DEV_RX_OFFLOAD_VLAN_FILTER) { 2535 for (i = 0; i < RTE_ETHER_MAX_VLAN_ID; i++) 2536 bnxt_del_vlan_filter(bp, i); 2537 } 2538 bnxt_del_dflt_mac_filter(bp, vnic); 2539 2540 rc = bnxt_hwrm_vnic_ctx_free(bp, vnic); 2541 if (rc) 2542 return rc; 2543 2544 rc = bnxt_hwrm_vnic_free(bp, vnic); 2545 if (rc) 2546 return rc; 2547 2548 rte_free(vnic->fw_grp_ids); 2549 vnic->fw_grp_ids = NULL; 2550 2551 vnic->rx_queue_cnt = 0; 2552 2553 return 0; 2554 } 2555 2556 static int 2557 bnxt_config_vlan_hw_stripping(struct bnxt *bp, uint64_t rx_offloads) 2558 { 2559 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2560 int rc; 2561 2562 /* Destroy, recreate and reconfigure the default vnic */ 2563 rc = bnxt_free_one_vnic(bp, 0); 2564 if (rc) 2565 return rc; 2566 2567 /* default vnic 0 */ 2568 rc = bnxt_setup_one_vnic(bp, 0); 2569 if (rc) 2570 return rc; 2571 2572 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 2573 DEV_RX_OFFLOAD_VLAN_FILTER) { 2574 rc = bnxt_add_vlan_filter(bp, 0); 2575 if (rc) 2576 return rc; 2577 rc = bnxt_restore_vlan_filters(bp); 2578 if (rc) 2579 return rc; 2580 } else { 2581 rc = bnxt_add_mac_filter(bp, vnic, NULL, 0, 0); 2582 if (rc) 2583 return rc; 2584 } 2585 2586 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2587 if (rc) 2588 return rc; 2589 2590 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 2591 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 2592 2593 return rc; 2594 } 2595 2596 static int 2597 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 2598 { 2599 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 2600 struct bnxt *bp = dev->data->dev_private; 2601 int rc; 2602 2603 rc = is_bnxt_in_error(bp); 2604 if (rc) 2605 return rc; 2606 2607 /* Filter settings will get applied when port is started */ 2608 if (!dev->data->dev_started) 2609 return 0; 2610 2611 if (mask & ETH_VLAN_FILTER_MASK) { 2612 /* Enable or disable VLAN filtering */ 2613 rc = bnxt_config_vlan_hw_filter(bp, rx_offloads); 2614 if (rc) 2615 return rc; 2616 } 2617 2618 if (mask & ETH_VLAN_STRIP_MASK) { 2619 /* Enable or disable VLAN stripping */ 2620 rc = bnxt_config_vlan_hw_stripping(bp, rx_offloads); 2621 if (rc) 2622 return rc; 2623 } 2624 2625 if (mask & ETH_VLAN_EXTEND_MASK) { 2626 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) 2627 PMD_DRV_LOG(DEBUG, "Extend VLAN supported\n"); 2628 else 2629 PMD_DRV_LOG(INFO, "Extend VLAN unsupported\n"); 2630 } 2631 2632 return 0; 2633 } 2634 2635 static int 2636 bnxt_vlan_tpid_set_op(struct rte_eth_dev *dev, enum rte_vlan_type vlan_type, 2637 uint16_t tpid) 2638 { 2639 struct bnxt *bp = dev->data->dev_private; 2640 int qinq = dev->data->dev_conf.rxmode.offloads & 2641 DEV_RX_OFFLOAD_VLAN_EXTEND; 2642 2643 if (vlan_type != ETH_VLAN_TYPE_INNER && 2644 vlan_type != ETH_VLAN_TYPE_OUTER) { 2645 PMD_DRV_LOG(ERR, 2646 "Unsupported vlan type."); 2647 return -EINVAL; 2648 } 2649 if (!qinq) { 2650 PMD_DRV_LOG(ERR, 2651 "QinQ not enabled. Needs to be ON as we can " 2652 "accelerate only outer vlan\n"); 2653 return -EINVAL; 2654 } 2655 2656 if (vlan_type == ETH_VLAN_TYPE_OUTER) { 2657 switch (tpid) { 2658 case RTE_ETHER_TYPE_QINQ: 2659 bp->outer_tpid_bd = 2660 TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8; 2661 break; 2662 case RTE_ETHER_TYPE_VLAN: 2663 bp->outer_tpid_bd = 2664 TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100; 2665 break; 2666 case RTE_ETHER_TYPE_QINQ1: 2667 bp->outer_tpid_bd = 2668 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100; 2669 break; 2670 case RTE_ETHER_TYPE_QINQ2: 2671 bp->outer_tpid_bd = 2672 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200; 2673 break; 2674 case RTE_ETHER_TYPE_QINQ3: 2675 bp->outer_tpid_bd = 2676 TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300; 2677 break; 2678 default: 2679 PMD_DRV_LOG(ERR, "Invalid TPID: %x\n", tpid); 2680 return -EINVAL; 2681 } 2682 bp->outer_tpid_bd |= tpid; 2683 PMD_DRV_LOG(INFO, "outer_tpid_bd = %x\n", bp->outer_tpid_bd); 2684 } else if (vlan_type == ETH_VLAN_TYPE_INNER) { 2685 PMD_DRV_LOG(ERR, 2686 "Can accelerate only outer vlan in QinQ\n"); 2687 return -EINVAL; 2688 } 2689 2690 return 0; 2691 } 2692 2693 static int 2694 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 2695 struct rte_ether_addr *addr) 2696 { 2697 struct bnxt *bp = dev->data->dev_private; 2698 /* Default Filter is tied to VNIC 0 */ 2699 struct bnxt_vnic_info *vnic = BNXT_GET_DEFAULT_VNIC(bp); 2700 int rc; 2701 2702 rc = is_bnxt_in_error(bp); 2703 if (rc) 2704 return rc; 2705 2706 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 2707 return -EPERM; 2708 2709 if (rte_is_zero_ether_addr(addr)) 2710 return -EINVAL; 2711 2712 /* Filter settings will get applied when port is started */ 2713 if (!dev->data->dev_started) 2714 return 0; 2715 2716 /* Check if the requested MAC is already added */ 2717 if (memcmp(addr, bp->mac_addr, RTE_ETHER_ADDR_LEN) == 0) 2718 return 0; 2719 2720 /* Destroy filter and re-create it */ 2721 bnxt_del_dflt_mac_filter(bp, vnic); 2722 2723 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 2724 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_VLAN_FILTER) { 2725 /* This filter will allow only untagged packets */ 2726 rc = bnxt_add_vlan_filter(bp, 0); 2727 } else { 2728 rc = bnxt_add_mac_filter(bp, vnic, addr, 0, 0); 2729 } 2730 2731 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 2732 return rc; 2733 } 2734 2735 static int 2736 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 2737 struct rte_ether_addr *mc_addr_set, 2738 uint32_t nb_mc_addr) 2739 { 2740 struct bnxt *bp = eth_dev->data->dev_private; 2741 char *mc_addr_list = (char *)mc_addr_set; 2742 struct bnxt_vnic_info *vnic; 2743 uint32_t off = 0, i = 0; 2744 int rc; 2745 2746 rc = is_bnxt_in_error(bp); 2747 if (rc) 2748 return rc; 2749 2750 vnic = BNXT_GET_DEFAULT_VNIC(bp); 2751 2752 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 2753 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 2754 goto allmulti; 2755 } 2756 2757 /* TODO Check for Duplicate mcast addresses */ 2758 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 2759 for (i = 0; i < nb_mc_addr; i++) { 2760 memcpy(vnic->mc_list + off, &mc_addr_list[i], 2761 RTE_ETHER_ADDR_LEN); 2762 off += RTE_ETHER_ADDR_LEN; 2763 } 2764 2765 vnic->mc_addr_cnt = i; 2766 if (vnic->mc_addr_cnt) 2767 vnic->flags |= BNXT_VNIC_INFO_MCAST; 2768 else 2769 vnic->flags &= ~BNXT_VNIC_INFO_MCAST; 2770 2771 allmulti: 2772 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 2773 } 2774 2775 static int 2776 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 2777 { 2778 struct bnxt *bp = dev->data->dev_private; 2779 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 2780 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 2781 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 2782 uint8_t fw_rsvd = bp->fw_ver & 0xff; 2783 int ret; 2784 2785 ret = snprintf(fw_version, fw_size, "%d.%d.%d.%d", 2786 fw_major, fw_minor, fw_updt, fw_rsvd); 2787 2788 ret += 1; /* add the size of '\0' */ 2789 if (fw_size < (uint32_t)ret) 2790 return ret; 2791 else 2792 return 0; 2793 } 2794 2795 static void 2796 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2797 struct rte_eth_rxq_info *qinfo) 2798 { 2799 struct bnxt *bp = dev->data->dev_private; 2800 struct bnxt_rx_queue *rxq; 2801 2802 if (is_bnxt_in_error(bp)) 2803 return; 2804 2805 rxq = dev->data->rx_queues[queue_id]; 2806 2807 qinfo->mp = rxq->mb_pool; 2808 qinfo->scattered_rx = dev->data->scattered_rx; 2809 qinfo->nb_desc = rxq->nb_rx_desc; 2810 2811 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 2812 qinfo->conf.rx_drop_en = rxq->drop_en; 2813 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 2814 qinfo->conf.offloads = dev->data->dev_conf.rxmode.offloads; 2815 } 2816 2817 static void 2818 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 2819 struct rte_eth_txq_info *qinfo) 2820 { 2821 struct bnxt *bp = dev->data->dev_private; 2822 struct bnxt_tx_queue *txq; 2823 2824 if (is_bnxt_in_error(bp)) 2825 return; 2826 2827 txq = dev->data->tx_queues[queue_id]; 2828 2829 qinfo->nb_desc = txq->nb_tx_desc; 2830 2831 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 2832 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 2833 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 2834 2835 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 2836 qinfo->conf.tx_rs_thresh = 0; 2837 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 2838 qinfo->conf.offloads = txq->offloads; 2839 } 2840 2841 static const struct { 2842 eth_rx_burst_t pkt_burst; 2843 const char *info; 2844 } bnxt_rx_burst_info[] = { 2845 {bnxt_recv_pkts, "Scalar"}, 2846 #if defined(RTE_ARCH_X86) 2847 {bnxt_recv_pkts_vec, "Vector SSE"}, 2848 #elif defined(RTE_ARCH_ARM64) 2849 {bnxt_recv_pkts_vec, "Vector Neon"}, 2850 #endif 2851 }; 2852 2853 static int 2854 bnxt_rx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2855 struct rte_eth_burst_mode *mode) 2856 { 2857 eth_rx_burst_t pkt_burst = dev->rx_pkt_burst; 2858 size_t i; 2859 2860 for (i = 0; i < RTE_DIM(bnxt_rx_burst_info); i++) { 2861 if (pkt_burst == bnxt_rx_burst_info[i].pkt_burst) { 2862 snprintf(mode->info, sizeof(mode->info), "%s", 2863 bnxt_rx_burst_info[i].info); 2864 return 0; 2865 } 2866 } 2867 2868 return -EINVAL; 2869 } 2870 2871 static const struct { 2872 eth_tx_burst_t pkt_burst; 2873 const char *info; 2874 } bnxt_tx_burst_info[] = { 2875 {bnxt_xmit_pkts, "Scalar"}, 2876 #if defined(RTE_ARCH_X86) 2877 {bnxt_xmit_pkts_vec, "Vector SSE"}, 2878 #elif defined(RTE_ARCH_ARM64) 2879 {bnxt_xmit_pkts_vec, "Vector Neon"}, 2880 #endif 2881 }; 2882 2883 static int 2884 bnxt_tx_burst_mode_get(struct rte_eth_dev *dev, __rte_unused uint16_t queue_id, 2885 struct rte_eth_burst_mode *mode) 2886 { 2887 eth_tx_burst_t pkt_burst = dev->tx_pkt_burst; 2888 size_t i; 2889 2890 for (i = 0; i < RTE_DIM(bnxt_tx_burst_info); i++) { 2891 if (pkt_burst == bnxt_tx_burst_info[i].pkt_burst) { 2892 snprintf(mode->info, sizeof(mode->info), "%s", 2893 bnxt_tx_burst_info[i].info); 2894 return 0; 2895 } 2896 } 2897 2898 return -EINVAL; 2899 } 2900 2901 int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 2902 { 2903 struct bnxt *bp = eth_dev->data->dev_private; 2904 uint32_t new_pkt_size; 2905 uint32_t rc = 0; 2906 uint32_t i; 2907 2908 rc = is_bnxt_in_error(bp); 2909 if (rc) 2910 return rc; 2911 2912 /* Exit if receive queues are not configured yet */ 2913 if (!eth_dev->data->nb_rx_queues) 2914 return rc; 2915 2916 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 2917 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 2918 2919 /* 2920 * Disallow any MTU change that would require scattered receive support 2921 * if it is not already enabled. 2922 */ 2923 if (eth_dev->data->dev_started && 2924 !eth_dev->data->scattered_rx && 2925 (new_pkt_size > 2926 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 2927 PMD_DRV_LOG(ERR, 2928 "MTU change would require scattered rx support. "); 2929 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2930 return -EINVAL; 2931 } 2932 2933 if (new_mtu > RTE_ETHER_MTU) { 2934 bp->flags |= BNXT_FLAG_JUMBO; 2935 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2936 DEV_RX_OFFLOAD_JUMBO_FRAME; 2937 } else { 2938 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2939 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2940 bp->flags &= ~BNXT_FLAG_JUMBO; 2941 } 2942 2943 /* Is there a change in mtu setting? */ 2944 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len == new_pkt_size) 2945 return rc; 2946 2947 for (i = 0; i < bp->nr_vnics; i++) { 2948 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2949 uint16_t size = 0; 2950 2951 vnic->mru = BNXT_VNIC_MRU(new_mtu); 2952 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2953 if (rc) 2954 break; 2955 2956 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2957 size -= RTE_PKTMBUF_HEADROOM; 2958 2959 if (size < new_mtu) { 2960 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2961 if (rc) 2962 return rc; 2963 } 2964 } 2965 2966 if (!rc) 2967 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2968 2969 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2970 2971 return rc; 2972 } 2973 2974 static int 2975 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2976 { 2977 struct bnxt *bp = dev->data->dev_private; 2978 uint16_t vlan = bp->vlan; 2979 int rc; 2980 2981 rc = is_bnxt_in_error(bp); 2982 if (rc) 2983 return rc; 2984 2985 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2986 PMD_DRV_LOG(ERR, 2987 "PVID cannot be modified for this function\n"); 2988 return -ENOTSUP; 2989 } 2990 bp->vlan = on ? pvid : 0; 2991 2992 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2993 if (rc) 2994 bp->vlan = vlan; 2995 return rc; 2996 } 2997 2998 static int 2999 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 3000 { 3001 struct bnxt *bp = dev->data->dev_private; 3002 int rc; 3003 3004 rc = is_bnxt_in_error(bp); 3005 if (rc) 3006 return rc; 3007 3008 return bnxt_hwrm_port_led_cfg(bp, true); 3009 } 3010 3011 static int 3012 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 3013 { 3014 struct bnxt *bp = dev->data->dev_private; 3015 int rc; 3016 3017 rc = is_bnxt_in_error(bp); 3018 if (rc) 3019 return rc; 3020 3021 return bnxt_hwrm_port_led_cfg(bp, false); 3022 } 3023 3024 static uint32_t 3025 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 3026 { 3027 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 3028 struct bnxt_cp_ring_info *cpr; 3029 uint32_t desc = 0, raw_cons; 3030 struct bnxt_rx_queue *rxq; 3031 struct rx_pkt_cmpl *rxcmp; 3032 int rc; 3033 3034 rc = is_bnxt_in_error(bp); 3035 if (rc) 3036 return rc; 3037 3038 rxq = dev->data->rx_queues[rx_queue_id]; 3039 cpr = rxq->cp_ring; 3040 raw_cons = cpr->cp_raw_cons; 3041 3042 while (1) { 3043 uint32_t agg_cnt, cons, cmpl_type; 3044 3045 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3046 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3047 3048 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3049 break; 3050 3051 cmpl_type = CMP_TYPE(rxcmp); 3052 3053 switch (cmpl_type) { 3054 case CMPL_BASE_TYPE_RX_L2: 3055 case CMPL_BASE_TYPE_RX_L2_V2: 3056 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3057 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3058 desc++; 3059 break; 3060 3061 case CMPL_BASE_TYPE_RX_TPA_END: 3062 if (BNXT_CHIP_P5(rxq->bp)) { 3063 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3064 3065 p5_tpa_end = (void *)rxcmp; 3066 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3067 } else { 3068 struct rx_tpa_end_cmpl *tpa_end; 3069 3070 tpa_end = (void *)rxcmp; 3071 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3072 } 3073 3074 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3075 desc++; 3076 break; 3077 3078 default: 3079 raw_cons += CMP_LEN(cmpl_type); 3080 } 3081 } 3082 3083 return desc; 3084 } 3085 3086 static int 3087 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 3088 { 3089 struct bnxt_rx_queue *rxq = rx_queue; 3090 struct bnxt_cp_ring_info *cpr; 3091 struct bnxt_rx_ring_info *rxr; 3092 uint32_t desc, raw_cons; 3093 struct bnxt *bp = rxq->bp; 3094 struct rx_pkt_cmpl *rxcmp; 3095 int rc; 3096 3097 rc = is_bnxt_in_error(bp); 3098 if (rc) 3099 return rc; 3100 3101 if (offset >= rxq->nb_rx_desc) 3102 return -EINVAL; 3103 3104 rxr = rxq->rx_ring; 3105 cpr = rxq->cp_ring; 3106 3107 /* 3108 * For the vector receive case, the completion at the requested 3109 * offset can be indexed directly. 3110 */ 3111 #if defined(RTE_ARCH_X86) || defined(RTE_ARCH_ARM64) 3112 if (bp->flags & BNXT_FLAG_RX_VECTOR_PKT_MODE) { 3113 struct rx_pkt_cmpl *rxcmp; 3114 uint32_t cons; 3115 3116 /* Check status of completion descriptor. */ 3117 raw_cons = cpr->cp_raw_cons + 3118 offset * CMP_LEN(CMPL_BASE_TYPE_RX_L2); 3119 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3120 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3121 3122 if (CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3123 return RTE_ETH_RX_DESC_DONE; 3124 3125 /* Check whether rx desc has an mbuf attached. */ 3126 cons = RING_CMP(rxr->rx_ring_struct, raw_cons / 2); 3127 if (cons >= rxq->rxrearm_start && 3128 cons < rxq->rxrearm_start + rxq->rxrearm_nb) { 3129 return RTE_ETH_RX_DESC_UNAVAIL; 3130 } 3131 3132 return RTE_ETH_RX_DESC_AVAIL; 3133 } 3134 #endif 3135 3136 /* 3137 * For the non-vector receive case, scan the completion ring to 3138 * locate the completion descriptor for the requested offset. 3139 */ 3140 raw_cons = cpr->cp_raw_cons; 3141 desc = 0; 3142 while (1) { 3143 uint32_t agg_cnt, cons, cmpl_type; 3144 3145 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 3146 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3147 3148 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) 3149 break; 3150 3151 cmpl_type = CMP_TYPE(rxcmp); 3152 3153 switch (cmpl_type) { 3154 case CMPL_BASE_TYPE_RX_L2: 3155 case CMPL_BASE_TYPE_RX_L2_V2: 3156 if (desc == offset) { 3157 cons = rxcmp->opaque; 3158 if (rxr->rx_buf_ring[cons]) 3159 return RTE_ETH_RX_DESC_DONE; 3160 else 3161 return RTE_ETH_RX_DESC_UNAVAIL; 3162 } 3163 agg_cnt = BNXT_RX_L2_AGG_BUFS(rxcmp); 3164 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3165 desc++; 3166 break; 3167 3168 case CMPL_BASE_TYPE_RX_TPA_END: 3169 if (desc == offset) 3170 return RTE_ETH_RX_DESC_DONE; 3171 3172 if (BNXT_CHIP_P5(rxq->bp)) { 3173 struct rx_tpa_v2_end_cmpl_hi *p5_tpa_end; 3174 3175 p5_tpa_end = (void *)rxcmp; 3176 agg_cnt = BNXT_TPA_END_AGG_BUFS_TH(p5_tpa_end); 3177 } else { 3178 struct rx_tpa_end_cmpl *tpa_end; 3179 3180 tpa_end = (void *)rxcmp; 3181 agg_cnt = BNXT_TPA_END_AGG_BUFS(tpa_end); 3182 } 3183 3184 raw_cons = raw_cons + CMP_LEN(cmpl_type) + agg_cnt; 3185 desc++; 3186 break; 3187 3188 default: 3189 raw_cons += CMP_LEN(cmpl_type); 3190 } 3191 } 3192 3193 return RTE_ETH_RX_DESC_AVAIL; 3194 } 3195 3196 static int 3197 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 3198 { 3199 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 3200 struct bnxt_tx_ring_info *txr; 3201 struct bnxt_cp_ring_info *cpr; 3202 struct rte_mbuf **tx_buf; 3203 struct tx_pkt_cmpl *txcmp; 3204 uint32_t cons, cp_cons; 3205 int rc; 3206 3207 if (!txq) 3208 return -EINVAL; 3209 3210 rc = is_bnxt_in_error(txq->bp); 3211 if (rc) 3212 return rc; 3213 3214 cpr = txq->cp_ring; 3215 txr = txq->tx_ring; 3216 3217 if (offset >= txq->nb_tx_desc) 3218 return -EINVAL; 3219 3220 cons = RING_CMP(cpr->cp_ring_struct, offset); 3221 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 3222 cp_cons = cpr->cp_raw_cons; 3223 3224 if (cons > cp_cons) { 3225 if (CMPL_VALID(txcmp, cpr->valid)) 3226 return RTE_ETH_TX_DESC_UNAVAIL; 3227 } else { 3228 if (CMPL_VALID(txcmp, !cpr->valid)) 3229 return RTE_ETH_TX_DESC_UNAVAIL; 3230 } 3231 tx_buf = &txr->tx_buf_ring[cons]; 3232 if (*tx_buf == NULL) 3233 return RTE_ETH_TX_DESC_DONE; 3234 3235 return RTE_ETH_TX_DESC_FULL; 3236 } 3237 3238 int 3239 bnxt_flow_ops_get_op(struct rte_eth_dev *dev, 3240 const struct rte_flow_ops **ops) 3241 { 3242 struct bnxt *bp = dev->data->dev_private; 3243 int ret = 0; 3244 3245 if (!bp) 3246 return -EIO; 3247 3248 if (BNXT_ETH_DEV_IS_REPRESENTOR(dev)) { 3249 struct bnxt_representor *vfr = dev->data->dev_private; 3250 bp = vfr->parent_dev->data->dev_private; 3251 /* parent is deleted while children are still valid */ 3252 if (!bp) { 3253 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR Error\n", 3254 dev->data->port_id); 3255 return -EIO; 3256 } 3257 } 3258 3259 ret = is_bnxt_in_error(bp); 3260 if (ret) 3261 return ret; 3262 3263 /* PMD supports thread-safe flow operations. rte_flow API 3264 * functions can avoid mutex for multi-thread safety. 3265 */ 3266 dev->data->dev_flags |= RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE; 3267 3268 if (BNXT_TRUFLOW_EN(bp)) 3269 *ops = &bnxt_ulp_rte_flow_ops; 3270 else 3271 *ops = &bnxt_flow_ops; 3272 3273 return ret; 3274 } 3275 3276 static const uint32_t * 3277 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3278 { 3279 static const uint32_t ptypes[] = { 3280 RTE_PTYPE_L2_ETHER_VLAN, 3281 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3282 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3283 RTE_PTYPE_L4_ICMP, 3284 RTE_PTYPE_L4_TCP, 3285 RTE_PTYPE_L4_UDP, 3286 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3287 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3288 RTE_PTYPE_INNER_L4_ICMP, 3289 RTE_PTYPE_INNER_L4_TCP, 3290 RTE_PTYPE_INNER_L4_UDP, 3291 RTE_PTYPE_UNKNOWN 3292 }; 3293 3294 if (!dev->rx_pkt_burst) 3295 return NULL; 3296 3297 return ptypes; 3298 } 3299 3300 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3301 int reg_win) 3302 { 3303 uint32_t reg_base = *reg_arr & 0xfffff000; 3304 uint32_t win_off; 3305 int i; 3306 3307 for (i = 0; i < count; i++) { 3308 if ((reg_arr[i] & 0xfffff000) != reg_base) 3309 return -ERANGE; 3310 } 3311 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3312 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3313 return 0; 3314 } 3315 3316 static int bnxt_map_ptp_regs(struct bnxt *bp) 3317 { 3318 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3319 uint32_t *reg_arr; 3320 int rc, i; 3321 3322 reg_arr = ptp->rx_regs; 3323 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3324 if (rc) 3325 return rc; 3326 3327 reg_arr = ptp->tx_regs; 3328 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3329 if (rc) 3330 return rc; 3331 3332 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3333 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3334 3335 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3336 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3337 3338 return 0; 3339 } 3340 3341 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3342 { 3343 rte_write32(0, (uint8_t *)bp->bar0 + 3344 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3345 rte_write32(0, (uint8_t *)bp->bar0 + 3346 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3347 } 3348 3349 static uint64_t bnxt_cc_read(struct bnxt *bp) 3350 { 3351 uint64_t ns; 3352 3353 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3354 BNXT_GRCPF_REG_SYNC_TIME)); 3355 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3356 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3357 return ns; 3358 } 3359 3360 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3361 { 3362 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3363 uint32_t fifo; 3364 3365 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3366 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3367 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3368 return -EAGAIN; 3369 3370 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3371 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3372 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3373 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3374 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3375 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3376 rte_read32((uint8_t *)bp->bar0 + ptp->tx_mapped_regs[BNXT_PTP_TX_SEQ]); 3377 3378 return 0; 3379 } 3380 3381 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3382 { 3383 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3384 struct bnxt_pf_info *pf = bp->pf; 3385 uint16_t port_id; 3386 uint32_t fifo; 3387 3388 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3389 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3390 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3391 return -EAGAIN; 3392 3393 port_id = pf->port_id; 3394 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3395 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3396 3397 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3398 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3399 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3400 /* bnxt_clr_rx_ts(bp); TBD */ 3401 return -EBUSY; 3402 } 3403 3404 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3405 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3406 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3407 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3408 3409 return 0; 3410 } 3411 3412 static int 3413 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3414 { 3415 uint64_t ns; 3416 struct bnxt *bp = dev->data->dev_private; 3417 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3418 3419 if (!ptp) 3420 return -ENOTSUP; 3421 3422 ns = rte_timespec_to_ns(ts); 3423 /* Set the timecounters to a new value. */ 3424 ptp->tc.nsec = ns; 3425 ptp->tx_tstamp_tc.nsec = ns; 3426 ptp->rx_tstamp_tc.nsec = ns; 3427 3428 return 0; 3429 } 3430 3431 static int 3432 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3433 { 3434 struct bnxt *bp = dev->data->dev_private; 3435 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3436 uint64_t ns, systime_cycles = 0; 3437 int rc = 0; 3438 3439 if (!ptp) 3440 return -ENOTSUP; 3441 3442 if (BNXT_CHIP_P5(bp)) 3443 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3444 &systime_cycles); 3445 else 3446 systime_cycles = bnxt_cc_read(bp); 3447 3448 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3449 *ts = rte_ns_to_timespec(ns); 3450 3451 return rc; 3452 } 3453 static int 3454 bnxt_timesync_enable(struct rte_eth_dev *dev) 3455 { 3456 struct bnxt *bp = dev->data->dev_private; 3457 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3458 uint32_t shift = 0; 3459 int rc; 3460 3461 if (!ptp) 3462 return -ENOTSUP; 3463 3464 ptp->rx_filter = 1; 3465 ptp->tx_tstamp_en = 1; 3466 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3467 3468 rc = bnxt_hwrm_ptp_cfg(bp); 3469 if (rc) 3470 return rc; 3471 3472 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3473 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3474 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3475 3476 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3477 ptp->tc.cc_shift = shift; 3478 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3479 3480 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3481 ptp->rx_tstamp_tc.cc_shift = shift; 3482 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3483 3484 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3485 ptp->tx_tstamp_tc.cc_shift = shift; 3486 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3487 3488 if (!BNXT_CHIP_P5(bp)) 3489 bnxt_map_ptp_regs(bp); 3490 else 3491 rc = bnxt_ptp_start(bp); 3492 3493 return rc; 3494 } 3495 3496 static int 3497 bnxt_timesync_disable(struct rte_eth_dev *dev) 3498 { 3499 struct bnxt *bp = dev->data->dev_private; 3500 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3501 3502 if (!ptp) 3503 return -ENOTSUP; 3504 3505 ptp->rx_filter = 0; 3506 ptp->tx_tstamp_en = 0; 3507 ptp->rxctl = 0; 3508 3509 bnxt_hwrm_ptp_cfg(bp); 3510 3511 if (!BNXT_CHIP_P5(bp)) 3512 bnxt_unmap_ptp_regs(bp); 3513 else 3514 bnxt_ptp_stop(bp); 3515 3516 return 0; 3517 } 3518 3519 static int 3520 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3521 struct timespec *timestamp, 3522 uint32_t flags __rte_unused) 3523 { 3524 struct bnxt *bp = dev->data->dev_private; 3525 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3526 uint64_t rx_tstamp_cycles = 0; 3527 uint64_t ns; 3528 3529 if (!ptp) 3530 return -ENOTSUP; 3531 3532 if (BNXT_CHIP_P5(bp)) 3533 rx_tstamp_cycles = ptp->rx_timestamp; 3534 else 3535 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3536 3537 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3538 *timestamp = rte_ns_to_timespec(ns); 3539 return 0; 3540 } 3541 3542 static int 3543 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3544 struct timespec *timestamp) 3545 { 3546 struct bnxt *bp = dev->data->dev_private; 3547 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3548 uint64_t tx_tstamp_cycles = 0; 3549 uint64_t ns; 3550 int rc = 0; 3551 3552 if (!ptp) 3553 return -ENOTSUP; 3554 3555 if (BNXT_CHIP_P5(bp)) 3556 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3557 &tx_tstamp_cycles); 3558 else 3559 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3560 3561 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3562 *timestamp = rte_ns_to_timespec(ns); 3563 3564 return rc; 3565 } 3566 3567 static int 3568 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3569 { 3570 struct bnxt *bp = dev->data->dev_private; 3571 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3572 3573 if (!ptp) 3574 return -ENOTSUP; 3575 3576 ptp->tc.nsec += delta; 3577 ptp->tx_tstamp_tc.nsec += delta; 3578 ptp->rx_tstamp_tc.nsec += delta; 3579 3580 return 0; 3581 } 3582 3583 static int 3584 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3585 { 3586 struct bnxt *bp = dev->data->dev_private; 3587 int rc; 3588 uint32_t dir_entries; 3589 uint32_t entry_length; 3590 3591 rc = is_bnxt_in_error(bp); 3592 if (rc) 3593 return rc; 3594 3595 PMD_DRV_LOG(INFO, PCI_PRI_FMT "\n", 3596 bp->pdev->addr.domain, bp->pdev->addr.bus, 3597 bp->pdev->addr.devid, bp->pdev->addr.function); 3598 3599 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3600 if (rc != 0) 3601 return rc; 3602 3603 return dir_entries * entry_length; 3604 } 3605 3606 static int 3607 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3608 struct rte_dev_eeprom_info *in_eeprom) 3609 { 3610 struct bnxt *bp = dev->data->dev_private; 3611 uint32_t index; 3612 uint32_t offset; 3613 int rc; 3614 3615 rc = is_bnxt_in_error(bp); 3616 if (rc) 3617 return rc; 3618 3619 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3620 bp->pdev->addr.domain, bp->pdev->addr.bus, 3621 bp->pdev->addr.devid, bp->pdev->addr.function, 3622 in_eeprom->offset, in_eeprom->length); 3623 3624 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3625 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3626 in_eeprom->data); 3627 3628 index = in_eeprom->offset >> 24; 3629 offset = in_eeprom->offset & 0xffffff; 3630 3631 if (index != 0) 3632 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3633 in_eeprom->length, in_eeprom->data); 3634 3635 return 0; 3636 } 3637 3638 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3639 { 3640 switch (dir_type) { 3641 case BNX_DIR_TYPE_CHIMP_PATCH: 3642 case BNX_DIR_TYPE_BOOTCODE: 3643 case BNX_DIR_TYPE_BOOTCODE_2: 3644 case BNX_DIR_TYPE_APE_FW: 3645 case BNX_DIR_TYPE_APE_PATCH: 3646 case BNX_DIR_TYPE_KONG_FW: 3647 case BNX_DIR_TYPE_KONG_PATCH: 3648 case BNX_DIR_TYPE_BONO_FW: 3649 case BNX_DIR_TYPE_BONO_PATCH: 3650 /* FALLTHROUGH */ 3651 return true; 3652 } 3653 3654 return false; 3655 } 3656 3657 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3658 { 3659 switch (dir_type) { 3660 case BNX_DIR_TYPE_AVS: 3661 case BNX_DIR_TYPE_EXP_ROM_MBA: 3662 case BNX_DIR_TYPE_PCIE: 3663 case BNX_DIR_TYPE_TSCF_UCODE: 3664 case BNX_DIR_TYPE_EXT_PHY: 3665 case BNX_DIR_TYPE_CCM: 3666 case BNX_DIR_TYPE_ISCSI_BOOT: 3667 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3668 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3669 /* FALLTHROUGH */ 3670 return true; 3671 } 3672 3673 return false; 3674 } 3675 3676 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3677 { 3678 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3679 bnxt_dir_type_is_other_exec_format(dir_type); 3680 } 3681 3682 static int 3683 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3684 struct rte_dev_eeprom_info *in_eeprom) 3685 { 3686 struct bnxt *bp = dev->data->dev_private; 3687 uint8_t index, dir_op; 3688 uint16_t type, ext, ordinal, attr; 3689 int rc; 3690 3691 rc = is_bnxt_in_error(bp); 3692 if (rc) 3693 return rc; 3694 3695 PMD_DRV_LOG(INFO, PCI_PRI_FMT " in_eeprom->offset = %d len = %d\n", 3696 bp->pdev->addr.domain, bp->pdev->addr.bus, 3697 bp->pdev->addr.devid, bp->pdev->addr.function, 3698 in_eeprom->offset, in_eeprom->length); 3699 3700 if (!BNXT_PF(bp)) { 3701 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3702 return -EINVAL; 3703 } 3704 3705 type = in_eeprom->magic >> 16; 3706 3707 if (type == 0xffff) { /* special value for directory operations */ 3708 index = in_eeprom->magic & 0xff; 3709 dir_op = in_eeprom->magic >> 8; 3710 if (index == 0) 3711 return -EINVAL; 3712 switch (dir_op) { 3713 case 0x0e: /* erase */ 3714 if (in_eeprom->offset != ~in_eeprom->magic) 3715 return -EINVAL; 3716 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3717 default: 3718 return -EINVAL; 3719 } 3720 } 3721 3722 /* Create or re-write an NVM item: */ 3723 if (bnxt_dir_type_is_executable(type) == true) 3724 return -EOPNOTSUPP; 3725 ext = in_eeprom->magic & 0xffff; 3726 ordinal = in_eeprom->offset >> 16; 3727 attr = in_eeprom->offset & 0xffff; 3728 3729 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3730 in_eeprom->data, in_eeprom->length); 3731 } 3732 3733 /* 3734 * Initialization 3735 */ 3736 3737 static const struct eth_dev_ops bnxt_dev_ops = { 3738 .dev_infos_get = bnxt_dev_info_get_op, 3739 .dev_close = bnxt_dev_close_op, 3740 .dev_configure = bnxt_dev_configure_op, 3741 .dev_start = bnxt_dev_start_op, 3742 .dev_stop = bnxt_dev_stop_op, 3743 .dev_set_link_up = bnxt_dev_set_link_up_op, 3744 .dev_set_link_down = bnxt_dev_set_link_down_op, 3745 .stats_get = bnxt_stats_get_op, 3746 .stats_reset = bnxt_stats_reset_op, 3747 .rx_queue_setup = bnxt_rx_queue_setup_op, 3748 .rx_queue_release = bnxt_rx_queue_release_op, 3749 .tx_queue_setup = bnxt_tx_queue_setup_op, 3750 .tx_queue_release = bnxt_tx_queue_release_op, 3751 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3752 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3753 .reta_update = bnxt_reta_update_op, 3754 .reta_query = bnxt_reta_query_op, 3755 .rss_hash_update = bnxt_rss_hash_update_op, 3756 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3757 .link_update = bnxt_link_update_op, 3758 .promiscuous_enable = bnxt_promiscuous_enable_op, 3759 .promiscuous_disable = bnxt_promiscuous_disable_op, 3760 .allmulticast_enable = bnxt_allmulticast_enable_op, 3761 .allmulticast_disable = bnxt_allmulticast_disable_op, 3762 .mac_addr_add = bnxt_mac_addr_add_op, 3763 .mac_addr_remove = bnxt_mac_addr_remove_op, 3764 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3765 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3766 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3767 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3768 .vlan_filter_set = bnxt_vlan_filter_set_op, 3769 .vlan_offload_set = bnxt_vlan_offload_set_op, 3770 .vlan_tpid_set = bnxt_vlan_tpid_set_op, 3771 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3772 .mtu_set = bnxt_mtu_set_op, 3773 .mac_addr_set = bnxt_set_default_mac_addr_op, 3774 .xstats_get = bnxt_dev_xstats_get_op, 3775 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3776 .xstats_reset = bnxt_dev_xstats_reset_op, 3777 .fw_version_get = bnxt_fw_version_get, 3778 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3779 .rxq_info_get = bnxt_rxq_info_get_op, 3780 .txq_info_get = bnxt_txq_info_get_op, 3781 .rx_burst_mode_get = bnxt_rx_burst_mode_get, 3782 .tx_burst_mode_get = bnxt_tx_burst_mode_get, 3783 .dev_led_on = bnxt_dev_led_on_op, 3784 .dev_led_off = bnxt_dev_led_off_op, 3785 .rx_queue_start = bnxt_rx_queue_start, 3786 .rx_queue_stop = bnxt_rx_queue_stop, 3787 .tx_queue_start = bnxt_tx_queue_start, 3788 .tx_queue_stop = bnxt_tx_queue_stop, 3789 .flow_ops_get = bnxt_flow_ops_get_op, 3790 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3791 .get_eeprom_length = bnxt_get_eeprom_length_op, 3792 .get_eeprom = bnxt_get_eeprom_op, 3793 .set_eeprom = bnxt_set_eeprom_op, 3794 .timesync_enable = bnxt_timesync_enable, 3795 .timesync_disable = bnxt_timesync_disable, 3796 .timesync_read_time = bnxt_timesync_read_time, 3797 .timesync_write_time = bnxt_timesync_write_time, 3798 .timesync_adjust_time = bnxt_timesync_adjust_time, 3799 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3800 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3801 }; 3802 3803 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3804 { 3805 uint32_t offset; 3806 3807 /* Only pre-map the reset GRC registers using window 3 */ 3808 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3809 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3810 3811 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3812 3813 return offset; 3814 } 3815 3816 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3817 { 3818 struct bnxt_error_recovery_info *info = bp->recovery_info; 3819 uint32_t reg_base = 0xffffffff; 3820 int i; 3821 3822 /* Only pre-map the monitoring GRC registers using window 2 */ 3823 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3824 uint32_t reg = info->status_regs[i]; 3825 3826 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3827 continue; 3828 3829 if (reg_base == 0xffffffff) 3830 reg_base = reg & 0xfffff000; 3831 if ((reg & 0xfffff000) != reg_base) 3832 return -ERANGE; 3833 3834 /* Use mask 0xffc as the Lower 2 bits indicates 3835 * address space location 3836 */ 3837 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3838 (reg & 0xffc); 3839 } 3840 3841 if (reg_base == 0xffffffff) 3842 return 0; 3843 3844 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3845 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3846 3847 return 0; 3848 } 3849 3850 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3851 { 3852 struct bnxt_error_recovery_info *info = bp->recovery_info; 3853 uint32_t delay = info->delay_after_reset[index]; 3854 uint32_t val = info->reset_reg_val[index]; 3855 uint32_t reg = info->reset_reg[index]; 3856 uint32_t type, offset; 3857 int ret; 3858 3859 type = BNXT_FW_STATUS_REG_TYPE(reg); 3860 offset = BNXT_FW_STATUS_REG_OFF(reg); 3861 3862 switch (type) { 3863 case BNXT_FW_STATUS_REG_TYPE_CFG: 3864 ret = rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3865 if (ret < 0) { 3866 PMD_DRV_LOG(ERR, "Failed to write %#x at PCI offset %#x", 3867 val, offset); 3868 return; 3869 } 3870 break; 3871 case BNXT_FW_STATUS_REG_TYPE_GRC: 3872 offset = bnxt_map_reset_regs(bp, offset); 3873 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3874 break; 3875 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3876 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3877 break; 3878 } 3879 /* wait on a specific interval of time until core reset is complete */ 3880 if (delay) 3881 rte_delay_ms(delay); 3882 } 3883 3884 static void bnxt_dev_cleanup(struct bnxt *bp) 3885 { 3886 bp->eth_dev->data->dev_link.link_status = 0; 3887 bp->link_info->link_up = 0; 3888 if (bp->eth_dev->data->dev_started) 3889 bnxt_dev_stop(bp->eth_dev); 3890 3891 bnxt_uninit_resources(bp, true); 3892 } 3893 3894 static int 3895 bnxt_check_fw_reset_done(struct bnxt *bp) 3896 { 3897 int timeout = bp->fw_reset_max_msecs; 3898 uint16_t val = 0; 3899 int rc; 3900 3901 do { 3902 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 3903 if (rc < 0) { 3904 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 3905 return rc; 3906 } 3907 if (val != 0xffff) 3908 break; 3909 rte_delay_ms(1); 3910 } while (timeout--); 3911 3912 if (val == 0xffff) { 3913 PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); 3914 return -1; 3915 } 3916 3917 return 0; 3918 } 3919 3920 static int bnxt_restore_vlan_filters(struct bnxt *bp) 3921 { 3922 struct rte_eth_dev *dev = bp->eth_dev; 3923 struct rte_vlan_filter_conf *vfc; 3924 int vidx, vbit, rc; 3925 uint16_t vlan_id; 3926 3927 for (vlan_id = 1; vlan_id <= RTE_ETHER_MAX_VLAN_ID; vlan_id++) { 3928 vfc = &dev->data->vlan_filter_conf; 3929 vidx = vlan_id / 64; 3930 vbit = vlan_id % 64; 3931 3932 /* Each bit corresponds to a VLAN id */ 3933 if (vfc->ids[vidx] & (UINT64_C(1) << vbit)) { 3934 rc = bnxt_add_vlan_filter(bp, vlan_id); 3935 if (rc) 3936 return rc; 3937 } 3938 } 3939 3940 return 0; 3941 } 3942 3943 static int bnxt_restore_mac_filters(struct bnxt *bp) 3944 { 3945 struct rte_eth_dev *dev = bp->eth_dev; 3946 struct rte_eth_dev_info dev_info; 3947 struct rte_ether_addr *addr; 3948 uint64_t pool_mask; 3949 uint32_t pool = 0; 3950 uint16_t i; 3951 int rc; 3952 3953 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 3954 return 0; 3955 3956 rc = bnxt_dev_info_get_op(dev, &dev_info); 3957 if (rc) 3958 return rc; 3959 3960 /* replay MAC address configuration */ 3961 for (i = 1; i < dev_info.max_mac_addrs; i++) { 3962 addr = &dev->data->mac_addrs[i]; 3963 3964 /* skip zero address */ 3965 if (rte_is_zero_ether_addr(addr)) 3966 continue; 3967 3968 pool = 0; 3969 pool_mask = dev->data->mac_pool_sel[i]; 3970 3971 do { 3972 if (pool_mask & 1ULL) { 3973 rc = bnxt_mac_addr_add_op(dev, addr, i, pool); 3974 if (rc) 3975 return rc; 3976 } 3977 pool_mask >>= 1; 3978 pool++; 3979 } while (pool_mask); 3980 } 3981 3982 return 0; 3983 } 3984 3985 static int bnxt_restore_filters(struct bnxt *bp) 3986 { 3987 struct rte_eth_dev *dev = bp->eth_dev; 3988 int ret = 0; 3989 3990 if (dev->data->all_multicast) { 3991 ret = bnxt_allmulticast_enable_op(dev); 3992 if (ret) 3993 return ret; 3994 } 3995 if (dev->data->promiscuous) { 3996 ret = bnxt_promiscuous_enable_op(dev); 3997 if (ret) 3998 return ret; 3999 } 4000 4001 ret = bnxt_restore_mac_filters(bp); 4002 if (ret) 4003 return ret; 4004 4005 ret = bnxt_restore_vlan_filters(bp); 4006 /* TODO restore other filters as well */ 4007 return ret; 4008 } 4009 4010 static int bnxt_check_fw_ready(struct bnxt *bp) 4011 { 4012 int timeout = bp->fw_reset_max_msecs; 4013 int rc = 0; 4014 4015 do { 4016 rc = bnxt_hwrm_poll_ver_get(bp); 4017 if (rc == 0) 4018 break; 4019 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 4020 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 4021 } while (rc && timeout > 0); 4022 4023 if (rc) 4024 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 4025 4026 return rc; 4027 } 4028 4029 static void bnxt_dev_recover(void *arg) 4030 { 4031 struct bnxt *bp = arg; 4032 int rc = 0; 4033 4034 pthread_mutex_lock(&bp->err_recovery_lock); 4035 4036 if (!bp->fw_reset_min_msecs) { 4037 rc = bnxt_check_fw_reset_done(bp); 4038 if (rc) 4039 goto err; 4040 } 4041 4042 /* Clear Error flag so that device re-init should happen */ 4043 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 4044 4045 rc = bnxt_check_fw_ready(bp); 4046 if (rc) 4047 goto err; 4048 4049 rc = bnxt_init_resources(bp, true); 4050 if (rc) { 4051 PMD_DRV_LOG(ERR, 4052 "Failed to initialize resources after reset\n"); 4053 goto err; 4054 } 4055 /* clear reset flag as the device is initialized now */ 4056 bp->flags &= ~BNXT_FLAG_FW_RESET; 4057 4058 rc = bnxt_dev_start_op(bp->eth_dev); 4059 if (rc) { 4060 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 4061 goto err_start; 4062 } 4063 4064 rc = bnxt_restore_filters(bp); 4065 if (rc) 4066 goto err_start; 4067 4068 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 4069 pthread_mutex_unlock(&bp->err_recovery_lock); 4070 4071 return; 4072 err_start: 4073 bnxt_dev_stop(bp->eth_dev); 4074 err: 4075 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4076 bnxt_uninit_resources(bp, false); 4077 pthread_mutex_unlock(&bp->err_recovery_lock); 4078 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 4079 } 4080 4081 void bnxt_dev_reset_and_resume(void *arg) 4082 { 4083 struct bnxt *bp = arg; 4084 uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; 4085 uint16_t val = 0; 4086 int rc; 4087 4088 bnxt_dev_cleanup(bp); 4089 4090 bnxt_wait_for_device_shutdown(bp); 4091 4092 /* During some fatal firmware error conditions, the PCI config space 4093 * register 0x2e which normally contains the subsystem ID will become 4094 * 0xffff. This register will revert back to the normal value after 4095 * the chip has completed core reset. If we detect this condition, 4096 * we can poll this config register immediately for the value to revert. 4097 */ 4098 if (bp->flags & BNXT_FLAG_FATAL_ERROR) { 4099 rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); 4100 if (rc < 0) { 4101 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); 4102 return; 4103 } 4104 if (val == 0xffff) { 4105 bp->fw_reset_min_msecs = 0; 4106 us = 1; 4107 } 4108 } 4109 4110 rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); 4111 if (rc) 4112 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 4113 } 4114 4115 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 4116 { 4117 struct bnxt_error_recovery_info *info = bp->recovery_info; 4118 uint32_t reg = info->status_regs[index]; 4119 uint32_t type, offset, val = 0; 4120 4121 type = BNXT_FW_STATUS_REG_TYPE(reg); 4122 offset = BNXT_FW_STATUS_REG_OFF(reg); 4123 4124 switch (type) { 4125 case BNXT_FW_STATUS_REG_TYPE_CFG: 4126 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 4127 break; 4128 case BNXT_FW_STATUS_REG_TYPE_GRC: 4129 offset = info->mapped_status_regs[index]; 4130 /* FALLTHROUGH */ 4131 case BNXT_FW_STATUS_REG_TYPE_BAR0: 4132 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4133 offset)); 4134 break; 4135 } 4136 4137 return val; 4138 } 4139 4140 static int bnxt_fw_reset_all(struct bnxt *bp) 4141 { 4142 struct bnxt_error_recovery_info *info = bp->recovery_info; 4143 uint32_t i; 4144 int rc = 0; 4145 4146 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4147 /* Reset through master function driver */ 4148 for (i = 0; i < info->reg_array_cnt; i++) 4149 bnxt_write_fw_reset_reg(bp, i); 4150 /* Wait for time specified by FW after triggering reset */ 4151 rte_delay_ms(info->master_func_wait_period_after_reset); 4152 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 4153 /* Reset with the help of Kong processor */ 4154 rc = bnxt_hwrm_fw_reset(bp); 4155 if (rc) 4156 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 4157 } 4158 4159 return rc; 4160 } 4161 4162 static void bnxt_fw_reset_cb(void *arg) 4163 { 4164 struct bnxt *bp = arg; 4165 struct bnxt_error_recovery_info *info = bp->recovery_info; 4166 int rc = 0; 4167 4168 /* Only Master function can do FW reset */ 4169 if (bnxt_is_master_func(bp) && 4170 bnxt_is_recovery_enabled(bp)) { 4171 rc = bnxt_fw_reset_all(bp); 4172 if (rc) { 4173 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 4174 return; 4175 } 4176 } 4177 4178 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 4179 * EXCEPTION_FATAL_ASYNC event to all the functions 4180 * (including MASTER FUNC). After receiving this Async, all the active 4181 * drivers should treat this case as FW initiated recovery 4182 */ 4183 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 4184 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 4185 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 4186 4187 /* To recover from error */ 4188 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 4189 (void *)bp); 4190 } 4191 } 4192 4193 /* Driver should poll FW heartbeat, reset_counter with the frequency 4194 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 4195 * When the driver detects heartbeat stop or change in reset_counter, 4196 * it has to trigger a reset to recover from the error condition. 4197 * A “master PF” is the function who will have the privilege to 4198 * initiate the chimp reset. The master PF will be elected by the 4199 * firmware and will be notified through async message. 4200 */ 4201 static void bnxt_check_fw_health(void *arg) 4202 { 4203 struct bnxt *bp = arg; 4204 struct bnxt_error_recovery_info *info = bp->recovery_info; 4205 uint32_t val = 0, wait_msec; 4206 4207 if (!info || !bnxt_is_recovery_enabled(bp) || 4208 is_bnxt_in_error(bp)) 4209 return; 4210 4211 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 4212 if (val == info->last_heart_beat) 4213 goto reset; 4214 4215 info->last_heart_beat = val; 4216 4217 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 4218 if (val != info->last_reset_counter) 4219 goto reset; 4220 4221 info->last_reset_counter = val; 4222 4223 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 4224 bnxt_check_fw_health, (void *)bp); 4225 4226 return; 4227 reset: 4228 /* Stop DMA to/from device */ 4229 bp->flags |= BNXT_FLAG_FATAL_ERROR; 4230 bp->flags |= BNXT_FLAG_FW_RESET; 4231 4232 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 4233 4234 if (bnxt_is_master_func(bp)) 4235 wait_msec = info->master_func_wait_period; 4236 else 4237 wait_msec = info->normal_func_wait_period; 4238 4239 rte_eal_alarm_set(US_PER_MS * wait_msec, 4240 bnxt_fw_reset_cb, (void *)bp); 4241 } 4242 4243 void bnxt_schedule_fw_health_check(struct bnxt *bp) 4244 { 4245 uint32_t polling_freq; 4246 4247 pthread_mutex_lock(&bp->health_check_lock); 4248 4249 if (!bnxt_is_recovery_enabled(bp)) 4250 goto done; 4251 4252 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 4253 goto done; 4254 4255 polling_freq = bp->recovery_info->driver_polling_freq; 4256 4257 rte_eal_alarm_set(US_PER_MS * polling_freq, 4258 bnxt_check_fw_health, (void *)bp); 4259 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4260 4261 done: 4262 pthread_mutex_unlock(&bp->health_check_lock); 4263 } 4264 4265 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 4266 { 4267 if (!bnxt_is_recovery_enabled(bp)) 4268 return; 4269 4270 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 4271 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 4272 } 4273 4274 static bool bnxt_vf_pciid(uint16_t device_id) 4275 { 4276 switch (device_id) { 4277 case BROADCOM_DEV_ID_57304_VF: 4278 case BROADCOM_DEV_ID_57406_VF: 4279 case BROADCOM_DEV_ID_5731X_VF: 4280 case BROADCOM_DEV_ID_5741X_VF: 4281 case BROADCOM_DEV_ID_57414_VF: 4282 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4283 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4284 case BROADCOM_DEV_ID_58802_VF: 4285 case BROADCOM_DEV_ID_57500_VF1: 4286 case BROADCOM_DEV_ID_57500_VF2: 4287 case BROADCOM_DEV_ID_58818_VF: 4288 /* FALLTHROUGH */ 4289 return true; 4290 default: 4291 return false; 4292 } 4293 } 4294 4295 /* Phase 5 device */ 4296 static bool bnxt_p5_device(uint16_t device_id) 4297 { 4298 switch (device_id) { 4299 case BROADCOM_DEV_ID_57508: 4300 case BROADCOM_DEV_ID_57504: 4301 case BROADCOM_DEV_ID_57502: 4302 case BROADCOM_DEV_ID_57508_MF1: 4303 case BROADCOM_DEV_ID_57504_MF1: 4304 case BROADCOM_DEV_ID_57502_MF1: 4305 case BROADCOM_DEV_ID_57508_MF2: 4306 case BROADCOM_DEV_ID_57504_MF2: 4307 case BROADCOM_DEV_ID_57502_MF2: 4308 case BROADCOM_DEV_ID_57500_VF1: 4309 case BROADCOM_DEV_ID_57500_VF2: 4310 case BROADCOM_DEV_ID_58812: 4311 case BROADCOM_DEV_ID_58814: 4312 case BROADCOM_DEV_ID_58818: 4313 case BROADCOM_DEV_ID_58818_VF: 4314 /* FALLTHROUGH */ 4315 return true; 4316 default: 4317 return false; 4318 } 4319 } 4320 4321 bool bnxt_stratus_device(struct bnxt *bp) 4322 { 4323 uint16_t device_id = bp->pdev->id.device_id; 4324 4325 switch (device_id) { 4326 case BROADCOM_DEV_ID_STRATUS_NIC: 4327 case BROADCOM_DEV_ID_STRATUS_NIC_VF1: 4328 case BROADCOM_DEV_ID_STRATUS_NIC_VF2: 4329 /* FALLTHROUGH */ 4330 return true; 4331 default: 4332 return false; 4333 } 4334 } 4335 4336 static int bnxt_map_pci_bars(struct rte_eth_dev *eth_dev) 4337 { 4338 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4339 struct bnxt *bp = eth_dev->data->dev_private; 4340 4341 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 4342 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 4343 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 4344 if (!bp->bar0 || !bp->doorbell_base) { 4345 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 4346 return -ENODEV; 4347 } 4348 4349 bp->eth_dev = eth_dev; 4350 bp->pdev = pci_dev; 4351 4352 return 0; 4353 } 4354 4355 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, 4356 struct bnxt_ctx_pg_info *ctx_pg, 4357 uint32_t mem_size, 4358 const char *suffix, 4359 uint16_t idx) 4360 { 4361 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 4362 const struct rte_memzone *mz = NULL; 4363 char mz_name[RTE_MEMZONE_NAMESIZE]; 4364 rte_iova_t mz_phys_addr; 4365 uint64_t valid_bits = 0; 4366 uint32_t sz; 4367 int i; 4368 4369 if (!mem_size) 4370 return 0; 4371 4372 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 4373 BNXT_PAGE_SIZE; 4374 rmem->page_size = BNXT_PAGE_SIZE; 4375 rmem->pg_arr = ctx_pg->ctx_pg_arr; 4376 rmem->dma_arr = ctx_pg->ctx_dma_arr; 4377 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 4378 4379 valid_bits = PTU_PTE_VALID; 4380 4381 if (rmem->nr_pages > 1) { 4382 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4383 "bnxt_ctx_pg_tbl%s_%x_%d", 4384 suffix, idx, bp->eth_dev->data->port_id); 4385 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4386 mz = rte_memzone_lookup(mz_name); 4387 if (!mz) { 4388 mz = rte_memzone_reserve_aligned(mz_name, 4389 rmem->nr_pages * 8, 4390 SOCKET_ID_ANY, 4391 RTE_MEMZONE_2MB | 4392 RTE_MEMZONE_SIZE_HINT_ONLY | 4393 RTE_MEMZONE_IOVA_CONTIG, 4394 BNXT_PAGE_SIZE); 4395 if (mz == NULL) 4396 return -ENOMEM; 4397 } 4398 4399 memset(mz->addr, 0, mz->len); 4400 mz_phys_addr = mz->iova; 4401 4402 rmem->pg_tbl = mz->addr; 4403 rmem->pg_tbl_map = mz_phys_addr; 4404 rmem->pg_tbl_mz = mz; 4405 } 4406 4407 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 4408 suffix, idx, bp->eth_dev->data->port_id); 4409 mz = rte_memzone_lookup(mz_name); 4410 if (!mz) { 4411 mz = rte_memzone_reserve_aligned(mz_name, 4412 mem_size, 4413 SOCKET_ID_ANY, 4414 RTE_MEMZONE_1GB | 4415 RTE_MEMZONE_SIZE_HINT_ONLY | 4416 RTE_MEMZONE_IOVA_CONTIG, 4417 BNXT_PAGE_SIZE); 4418 if (mz == NULL) 4419 return -ENOMEM; 4420 } 4421 4422 memset(mz->addr, 0, mz->len); 4423 mz_phys_addr = mz->iova; 4424 4425 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4426 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4427 rmem->dma_arr[i] = mz_phys_addr + sz; 4428 4429 if (rmem->nr_pages > 1) { 4430 if (i == rmem->nr_pages - 2 && 4431 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4432 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4433 else if (i == rmem->nr_pages - 1 && 4434 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4435 valid_bits |= PTU_PTE_LAST; 4436 4437 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4438 valid_bits); 4439 } 4440 } 4441 4442 rmem->mz = mz; 4443 if (rmem->vmem_size) 4444 rmem->vmem = (void **)mz->addr; 4445 rmem->dma_arr[0] = mz_phys_addr; 4446 return 0; 4447 } 4448 4449 static void bnxt_free_ctx_mem(struct bnxt *bp) 4450 { 4451 int i; 4452 4453 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4454 return; 4455 4456 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4457 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4458 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4459 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4460 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4461 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4462 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4463 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4464 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4465 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4466 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4467 4468 for (i = 0; i < bp->ctx->tqm_fp_rings_count + 1; i++) { 4469 if (bp->ctx->tqm_mem[i]) 4470 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4471 } 4472 4473 rte_free(bp->ctx); 4474 bp->ctx = NULL; 4475 } 4476 4477 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4478 4479 #define min_t(type, x, y) ({ \ 4480 type __min1 = (x); \ 4481 type __min2 = (y); \ 4482 __min1 < __min2 ? __min1 : __min2; }) 4483 4484 #define max_t(type, x, y) ({ \ 4485 type __max1 = (x); \ 4486 type __max2 = (y); \ 4487 __max1 > __max2 ? __max1 : __max2; }) 4488 4489 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4490 4491 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4492 { 4493 struct bnxt_ctx_pg_info *ctx_pg; 4494 struct bnxt_ctx_mem_info *ctx; 4495 uint32_t mem_size, ena, entries; 4496 uint32_t entries_sp, min; 4497 int i, rc; 4498 4499 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4500 if (rc) { 4501 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4502 return rc; 4503 } 4504 ctx = bp->ctx; 4505 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4506 return 0; 4507 4508 ctx_pg = &ctx->qp_mem; 4509 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4510 if (ctx->qp_entry_size) { 4511 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4512 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4513 if (rc) 4514 return rc; 4515 } 4516 4517 ctx_pg = &ctx->srq_mem; 4518 ctx_pg->entries = ctx->srq_max_l2_entries; 4519 if (ctx->srq_entry_size) { 4520 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4521 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4522 if (rc) 4523 return rc; 4524 } 4525 4526 ctx_pg = &ctx->cq_mem; 4527 ctx_pg->entries = ctx->cq_max_l2_entries; 4528 if (ctx->cq_entry_size) { 4529 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4530 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4531 if (rc) 4532 return rc; 4533 } 4534 4535 ctx_pg = &ctx->vnic_mem; 4536 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4537 ctx->vnic_max_ring_table_entries; 4538 if (ctx->vnic_entry_size) { 4539 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4540 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4541 if (rc) 4542 return rc; 4543 } 4544 4545 ctx_pg = &ctx->stat_mem; 4546 ctx_pg->entries = ctx->stat_max_entries; 4547 if (ctx->stat_entry_size) { 4548 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4549 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4550 if (rc) 4551 return rc; 4552 } 4553 4554 min = ctx->tqm_min_entries_per_ring; 4555 4556 entries_sp = ctx->qp_max_l2_entries + 4557 ctx->vnic_max_vnic_entries + 4558 2 * ctx->qp_min_qp1_entries + min; 4559 entries_sp = bnxt_roundup(entries_sp, ctx->tqm_entries_multiple); 4560 4561 entries = ctx->qp_max_l2_entries + ctx->qp_min_qp1_entries; 4562 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4563 entries = clamp_t(uint32_t, entries, min, 4564 ctx->tqm_max_entries_per_ring); 4565 for (i = 0, ena = 0; i < ctx->tqm_fp_rings_count + 1; i++) { 4566 /* i=0 is for TQM_SP. i=1 to i=8 applies to RING0 to RING7. 4567 * i > 8 is other ext rings. 4568 */ 4569 ctx_pg = ctx->tqm_mem[i]; 4570 ctx_pg->entries = i ? entries : entries_sp; 4571 if (ctx->tqm_entry_size) { 4572 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4573 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, 4574 "tqm_mem", i); 4575 if (rc) 4576 return rc; 4577 } 4578 if (i < BNXT_MAX_TQM_LEGACY_RINGS) 4579 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4580 else 4581 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8; 4582 } 4583 4584 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4585 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4586 if (rc) 4587 PMD_DRV_LOG(ERR, 4588 "Failed to configure context mem: rc = %d\n", rc); 4589 else 4590 ctx->flags |= BNXT_CTX_FLAG_INITED; 4591 4592 return rc; 4593 } 4594 4595 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4596 { 4597 struct rte_pci_device *pci_dev = bp->pdev; 4598 char mz_name[RTE_MEMZONE_NAMESIZE]; 4599 const struct rte_memzone *mz = NULL; 4600 uint32_t total_alloc_len; 4601 rte_iova_t mz_phys_addr; 4602 4603 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4604 return 0; 4605 4606 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4607 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4608 pci_dev->addr.bus, pci_dev->addr.devid, 4609 pci_dev->addr.function, "rx_port_stats"); 4610 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4611 mz = rte_memzone_lookup(mz_name); 4612 total_alloc_len = 4613 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4614 sizeof(struct rx_port_stats_ext) + 512); 4615 if (!mz) { 4616 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4617 SOCKET_ID_ANY, 4618 RTE_MEMZONE_2MB | 4619 RTE_MEMZONE_SIZE_HINT_ONLY | 4620 RTE_MEMZONE_IOVA_CONTIG); 4621 if (mz == NULL) 4622 return -ENOMEM; 4623 } 4624 memset(mz->addr, 0, mz->len); 4625 mz_phys_addr = mz->iova; 4626 4627 bp->rx_mem_zone = (const void *)mz; 4628 bp->hw_rx_port_stats = mz->addr; 4629 bp->hw_rx_port_stats_map = mz_phys_addr; 4630 4631 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4632 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4633 pci_dev->addr.bus, pci_dev->addr.devid, 4634 pci_dev->addr.function, "tx_port_stats"); 4635 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4636 mz = rte_memzone_lookup(mz_name); 4637 total_alloc_len = 4638 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4639 sizeof(struct tx_port_stats_ext) + 512); 4640 if (!mz) { 4641 mz = rte_memzone_reserve(mz_name, 4642 total_alloc_len, 4643 SOCKET_ID_ANY, 4644 RTE_MEMZONE_2MB | 4645 RTE_MEMZONE_SIZE_HINT_ONLY | 4646 RTE_MEMZONE_IOVA_CONTIG); 4647 if (mz == NULL) 4648 return -ENOMEM; 4649 } 4650 memset(mz->addr, 0, mz->len); 4651 mz_phys_addr = mz->iova; 4652 4653 bp->tx_mem_zone = (const void *)mz; 4654 bp->hw_tx_port_stats = mz->addr; 4655 bp->hw_tx_port_stats_map = mz_phys_addr; 4656 bp->flags |= BNXT_FLAG_PORT_STATS; 4657 4658 /* Display extended statistics if FW supports it */ 4659 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4660 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4661 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4662 return 0; 4663 4664 bp->hw_rx_port_stats_ext = (void *) 4665 ((uint8_t *)bp->hw_rx_port_stats + 4666 sizeof(struct rx_port_stats)); 4667 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4668 sizeof(struct rx_port_stats); 4669 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4670 4671 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4672 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4673 bp->hw_tx_port_stats_ext = (void *) 4674 ((uint8_t *)bp->hw_tx_port_stats + 4675 sizeof(struct tx_port_stats)); 4676 bp->hw_tx_port_stats_ext_map = 4677 bp->hw_tx_port_stats_map + 4678 sizeof(struct tx_port_stats); 4679 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4680 } 4681 4682 return 0; 4683 } 4684 4685 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4686 { 4687 struct bnxt *bp = eth_dev->data->dev_private; 4688 int rc = 0; 4689 4690 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4691 RTE_ETHER_ADDR_LEN * 4692 bp->max_l2_ctx, 4693 0); 4694 if (eth_dev->data->mac_addrs == NULL) { 4695 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4696 return -ENOMEM; 4697 } 4698 4699 if (!BNXT_HAS_DFLT_MAC_SET(bp)) { 4700 if (BNXT_PF(bp)) 4701 return -EINVAL; 4702 4703 /* Generate a random MAC address, if none was assigned by PF */ 4704 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4705 bnxt_eth_hw_addr_random(bp->mac_addr); 4706 PMD_DRV_LOG(INFO, 4707 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4708 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4709 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4710 4711 rc = bnxt_hwrm_set_mac(bp); 4712 if (rc) 4713 return rc; 4714 } 4715 4716 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4717 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4718 4719 return rc; 4720 } 4721 4722 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4723 { 4724 int rc = 0; 4725 4726 /* MAC is already configured in FW */ 4727 if (BNXT_HAS_DFLT_MAC_SET(bp)) 4728 return 0; 4729 4730 /* Restore the old MAC configured */ 4731 rc = bnxt_hwrm_set_mac(bp); 4732 if (rc) 4733 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4734 4735 return rc; 4736 } 4737 4738 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4739 { 4740 if (!BNXT_PF(bp)) 4741 return; 4742 4743 memset(bp->pf->vf_req_fwd, 0, sizeof(bp->pf->vf_req_fwd)); 4744 4745 if (!(bp->fw_cap & BNXT_FW_CAP_LINK_ADMIN)) 4746 BNXT_HWRM_CMD_TO_FORWARD(HWRM_PORT_PHY_QCFG); 4747 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_CFG); 4748 BNXT_HWRM_CMD_TO_FORWARD(HWRM_FUNC_VF_CFG); 4749 BNXT_HWRM_CMD_TO_FORWARD(HWRM_CFA_L2_FILTER_ALLOC); 4750 BNXT_HWRM_CMD_TO_FORWARD(HWRM_OEM_CMD); 4751 } 4752 4753 uint16_t 4754 bnxt_get_svif(uint16_t port_id, bool func_svif, 4755 enum bnxt_ulp_intf_type type) 4756 { 4757 struct rte_eth_dev *eth_dev; 4758 struct bnxt *bp; 4759 4760 eth_dev = &rte_eth_devices[port_id]; 4761 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4762 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4763 if (!vfr) 4764 return 0; 4765 4766 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4767 return vfr->svif; 4768 4769 eth_dev = vfr->parent_dev; 4770 } 4771 4772 bp = eth_dev->data->dev_private; 4773 4774 return func_svif ? bp->func_svif : bp->port_svif; 4775 } 4776 4777 uint16_t 4778 bnxt_get_vnic_id(uint16_t port, enum bnxt_ulp_intf_type type) 4779 { 4780 struct rte_eth_dev *eth_dev; 4781 struct bnxt_vnic_info *vnic; 4782 struct bnxt *bp; 4783 4784 eth_dev = &rte_eth_devices[port]; 4785 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4786 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4787 if (!vfr) 4788 return 0; 4789 4790 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4791 return vfr->dflt_vnic_id; 4792 4793 eth_dev = vfr->parent_dev; 4794 } 4795 4796 bp = eth_dev->data->dev_private; 4797 4798 vnic = BNXT_GET_DEFAULT_VNIC(bp); 4799 4800 return vnic->fw_vnic_id; 4801 } 4802 4803 uint16_t 4804 bnxt_get_fw_func_id(uint16_t port, enum bnxt_ulp_intf_type type) 4805 { 4806 struct rte_eth_dev *eth_dev; 4807 struct bnxt *bp; 4808 4809 eth_dev = &rte_eth_devices[port]; 4810 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4811 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4812 if (!vfr) 4813 return 0; 4814 4815 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4816 return vfr->fw_fid; 4817 4818 eth_dev = vfr->parent_dev; 4819 } 4820 4821 bp = eth_dev->data->dev_private; 4822 4823 return bp->fw_fid; 4824 } 4825 4826 enum bnxt_ulp_intf_type 4827 bnxt_get_interface_type(uint16_t port) 4828 { 4829 struct rte_eth_dev *eth_dev; 4830 struct bnxt *bp; 4831 4832 eth_dev = &rte_eth_devices[port]; 4833 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) 4834 return BNXT_ULP_INTF_TYPE_VF_REP; 4835 4836 bp = eth_dev->data->dev_private; 4837 if (BNXT_PF(bp)) 4838 return BNXT_ULP_INTF_TYPE_PF; 4839 else if (BNXT_VF_IS_TRUSTED(bp)) 4840 return BNXT_ULP_INTF_TYPE_TRUSTED_VF; 4841 else if (BNXT_VF(bp)) 4842 return BNXT_ULP_INTF_TYPE_VF; 4843 4844 return BNXT_ULP_INTF_TYPE_INVALID; 4845 } 4846 4847 uint16_t 4848 bnxt_get_phy_port_id(uint16_t port_id) 4849 { 4850 struct bnxt_representor *vfr; 4851 struct rte_eth_dev *eth_dev; 4852 struct bnxt *bp; 4853 4854 eth_dev = &rte_eth_devices[port_id]; 4855 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4856 vfr = eth_dev->data->dev_private; 4857 if (!vfr) 4858 return 0; 4859 4860 eth_dev = vfr->parent_dev; 4861 } 4862 4863 bp = eth_dev->data->dev_private; 4864 4865 return BNXT_PF(bp) ? bp->pf->port_id : bp->parent->port_id; 4866 } 4867 4868 uint16_t 4869 bnxt_get_parif(uint16_t port_id, enum bnxt_ulp_intf_type type) 4870 { 4871 struct rte_eth_dev *eth_dev; 4872 struct bnxt *bp; 4873 4874 eth_dev = &rte_eth_devices[port_id]; 4875 if (BNXT_ETH_DEV_IS_REPRESENTOR(eth_dev)) { 4876 struct bnxt_representor *vfr = eth_dev->data->dev_private; 4877 if (!vfr) 4878 return 0; 4879 4880 if (type == BNXT_ULP_INTF_TYPE_VF_REP) 4881 return vfr->fw_fid - 1; 4882 4883 eth_dev = vfr->parent_dev; 4884 } 4885 4886 bp = eth_dev->data->dev_private; 4887 4888 return BNXT_PF(bp) ? bp->fw_fid - 1 : bp->parent->fid - 1; 4889 } 4890 4891 uint16_t 4892 bnxt_get_vport(uint16_t port_id) 4893 { 4894 return (1 << bnxt_get_phy_port_id(port_id)); 4895 } 4896 4897 static void bnxt_alloc_error_recovery_info(struct bnxt *bp) 4898 { 4899 struct bnxt_error_recovery_info *info = bp->recovery_info; 4900 4901 if (info) { 4902 if (!(bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS)) 4903 memset(info, 0, sizeof(*info)); 4904 return; 4905 } 4906 4907 if (!(bp->fw_cap & BNXT_FW_CAP_ERROR_RECOVERY)) 4908 return; 4909 4910 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4911 sizeof(*info), 0); 4912 if (!info) 4913 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 4914 4915 bp->recovery_info = info; 4916 } 4917 4918 static void bnxt_check_fw_status(struct bnxt *bp) 4919 { 4920 uint32_t fw_status; 4921 4922 if (!(bp->recovery_info && 4923 (bp->fw_cap & BNXT_FW_CAP_HCOMM_FW_STATUS))) 4924 return; 4925 4926 fw_status = bnxt_read_fw_status_reg(bp, BNXT_FW_STATUS_REG); 4927 if (fw_status != BNXT_FW_STATUS_HEALTHY) 4928 PMD_DRV_LOG(ERR, "Firmware not responding, status: %#x\n", 4929 fw_status); 4930 } 4931 4932 static int bnxt_map_hcomm_fw_status_reg(struct bnxt *bp) 4933 { 4934 struct bnxt_error_recovery_info *info = bp->recovery_info; 4935 uint32_t status_loc; 4936 uint32_t sig_ver; 4937 4938 rte_write32(HCOMM_STATUS_STRUCT_LOC, (uint8_t *)bp->bar0 + 4939 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4940 sig_ver = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4941 BNXT_GRCP_WINDOW_2_BASE + 4942 offsetof(struct hcomm_status, 4943 sig_ver))); 4944 /* If the signature is absent, then FW does not support this feature */ 4945 if ((sig_ver & HCOMM_STATUS_SIGNATURE_MASK) != 4946 HCOMM_STATUS_SIGNATURE_VAL) 4947 return 0; 4948 4949 if (!info) { 4950 info = rte_zmalloc("bnxt_hwrm_error_recovery_qcfg", 4951 sizeof(*info), 0); 4952 if (!info) 4953 return -ENOMEM; 4954 bp->recovery_info = info; 4955 } else { 4956 memset(info, 0, sizeof(*info)); 4957 } 4958 4959 status_loc = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 4960 BNXT_GRCP_WINDOW_2_BASE + 4961 offsetof(struct hcomm_status, 4962 fw_status_loc))); 4963 4964 /* Only pre-map the FW health status GRC register */ 4965 if (BNXT_FW_STATUS_REG_TYPE(status_loc) != BNXT_FW_STATUS_REG_TYPE_GRC) 4966 return 0; 4967 4968 info->status_regs[BNXT_FW_STATUS_REG] = status_loc; 4969 info->mapped_status_regs[BNXT_FW_STATUS_REG] = 4970 BNXT_GRCP_WINDOW_2_BASE + (status_loc & BNXT_GRCP_OFFSET_MASK); 4971 4972 rte_write32((status_loc & BNXT_GRCP_BASE_MASK), (uint8_t *)bp->bar0 + 4973 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 4974 4975 bp->fw_cap |= BNXT_FW_CAP_HCOMM_FW_STATUS; 4976 4977 return 0; 4978 } 4979 4980 /* This function gets the FW version along with the 4981 * capabilities(MAX and current) of the function, vnic, 4982 * error recovery, phy and other chip related info 4983 */ 4984 static int bnxt_get_config(struct bnxt *bp) 4985 { 4986 uint16_t mtu; 4987 int rc = 0; 4988 4989 bp->fw_cap = 0; 4990 4991 rc = bnxt_map_hcomm_fw_status_reg(bp); 4992 if (rc) 4993 return rc; 4994 4995 rc = bnxt_hwrm_ver_get(bp, DFLT_HWRM_CMD_TIMEOUT); 4996 if (rc) { 4997 bnxt_check_fw_status(bp); 4998 return rc; 4999 } 5000 5001 rc = bnxt_hwrm_func_reset(bp); 5002 if (rc) 5003 return -EIO; 5004 5005 rc = bnxt_hwrm_vnic_qcaps(bp); 5006 if (rc) 5007 return rc; 5008 5009 rc = bnxt_hwrm_queue_qportcfg(bp); 5010 if (rc) 5011 return rc; 5012 5013 /* Get the MAX capabilities for this function. 5014 * This function also allocates context memory for TQM rings and 5015 * informs the firmware about this allocated backing store memory. 5016 */ 5017 rc = bnxt_hwrm_func_qcaps(bp); 5018 if (rc) 5019 return rc; 5020 5021 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 5022 if (rc) 5023 return rc; 5024 5025 rc = bnxt_hwrm_cfa_adv_flow_mgmt_qcaps(bp); 5026 if (rc) 5027 return rc; 5028 5029 bnxt_hwrm_port_mac_qcfg(bp); 5030 5031 bnxt_hwrm_parent_pf_qcfg(bp); 5032 5033 bnxt_hwrm_port_phy_qcaps(bp); 5034 5035 bnxt_alloc_error_recovery_info(bp); 5036 /* Get the adapter error recovery support info */ 5037 rc = bnxt_hwrm_error_recovery_qcfg(bp); 5038 if (rc) 5039 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5040 5041 bnxt_hwrm_port_led_qcaps(bp); 5042 5043 return 0; 5044 } 5045 5046 static int 5047 bnxt_init_locks(struct bnxt *bp) 5048 { 5049 int err; 5050 5051 err = pthread_mutex_init(&bp->flow_lock, NULL); 5052 if (err) { 5053 PMD_DRV_LOG(ERR, "Unable to initialize flow_lock\n"); 5054 return err; 5055 } 5056 5057 err = pthread_mutex_init(&bp->def_cp_lock, NULL); 5058 if (err) { 5059 PMD_DRV_LOG(ERR, "Unable to initialize def_cp_lock\n"); 5060 return err; 5061 } 5062 5063 err = pthread_mutex_init(&bp->health_check_lock, NULL); 5064 if (err) { 5065 PMD_DRV_LOG(ERR, "Unable to initialize health_check_lock\n"); 5066 return err; 5067 } 5068 5069 err = pthread_mutex_init(&bp->err_recovery_lock, NULL); 5070 if (err) 5071 PMD_DRV_LOG(ERR, "Unable to initialize err_recovery_lock\n"); 5072 5073 return err; 5074 } 5075 5076 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 5077 { 5078 int rc = 0; 5079 5080 rc = bnxt_get_config(bp); 5081 if (rc) 5082 return rc; 5083 5084 if (!reconfig_dev) { 5085 rc = bnxt_setup_mac_addr(bp->eth_dev); 5086 if (rc) 5087 return rc; 5088 } else { 5089 rc = bnxt_restore_dflt_mac(bp); 5090 if (rc) 5091 return rc; 5092 } 5093 5094 bnxt_config_vf_req_fwd(bp); 5095 5096 rc = bnxt_hwrm_func_driver_register(bp); 5097 if (rc) { 5098 PMD_DRV_LOG(ERR, "Failed to register driver"); 5099 return -EBUSY; 5100 } 5101 5102 if (BNXT_PF(bp)) { 5103 if (bp->pdev->max_vfs) { 5104 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 5105 if (rc) { 5106 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 5107 return rc; 5108 } 5109 } else { 5110 rc = bnxt_hwrm_allocate_pf_only(bp); 5111 if (rc) { 5112 PMD_DRV_LOG(ERR, 5113 "Failed to allocate PF resources"); 5114 return rc; 5115 } 5116 } 5117 } 5118 5119 rc = bnxt_alloc_mem(bp, reconfig_dev); 5120 if (rc) 5121 return rc; 5122 5123 rc = bnxt_setup_int(bp); 5124 if (rc) 5125 return rc; 5126 5127 rc = bnxt_request_int(bp); 5128 if (rc) 5129 return rc; 5130 5131 rc = bnxt_init_ctx_mem(bp); 5132 if (rc) { 5133 PMD_DRV_LOG(ERR, "Failed to init adv_flow_counters\n"); 5134 return rc; 5135 } 5136 5137 return 0; 5138 } 5139 5140 static int 5141 bnxt_parse_devarg_truflow(__rte_unused const char *key, 5142 const char *value, void *opaque_arg) 5143 { 5144 struct bnxt *bp = opaque_arg; 5145 unsigned long truflow; 5146 char *end = NULL; 5147 5148 if (!value || !opaque_arg) { 5149 PMD_DRV_LOG(ERR, 5150 "Invalid parameter passed to truflow devargs.\n"); 5151 return -EINVAL; 5152 } 5153 5154 truflow = strtoul(value, &end, 10); 5155 if (end == NULL || *end != '\0' || 5156 (truflow == ULONG_MAX && errno == ERANGE)) { 5157 PMD_DRV_LOG(ERR, 5158 "Invalid parameter passed to truflow devargs.\n"); 5159 return -EINVAL; 5160 } 5161 5162 if (BNXT_DEVARG_TRUFLOW_INVALID(truflow)) { 5163 PMD_DRV_LOG(ERR, 5164 "Invalid value passed to truflow devargs.\n"); 5165 return -EINVAL; 5166 } 5167 5168 if (truflow) { 5169 bp->flags |= BNXT_FLAG_TRUFLOW_EN; 5170 PMD_DRV_LOG(INFO, "Host-based truflow feature enabled.\n"); 5171 } else { 5172 bp->flags &= ~BNXT_FLAG_TRUFLOW_EN; 5173 PMD_DRV_LOG(INFO, "Host-based truflow feature disabled.\n"); 5174 } 5175 5176 return 0; 5177 } 5178 5179 static int 5180 bnxt_parse_devarg_flow_xstat(__rte_unused const char *key, 5181 const char *value, void *opaque_arg) 5182 { 5183 struct bnxt *bp = opaque_arg; 5184 unsigned long flow_xstat; 5185 char *end = NULL; 5186 5187 if (!value || !opaque_arg) { 5188 PMD_DRV_LOG(ERR, 5189 "Invalid parameter passed to flow_xstat devarg.\n"); 5190 return -EINVAL; 5191 } 5192 5193 flow_xstat = strtoul(value, &end, 10); 5194 if (end == NULL || *end != '\0' || 5195 (flow_xstat == ULONG_MAX && errno == ERANGE)) { 5196 PMD_DRV_LOG(ERR, 5197 "Invalid parameter passed to flow_xstat devarg.\n"); 5198 return -EINVAL; 5199 } 5200 5201 if (BNXT_DEVARG_FLOW_XSTAT_INVALID(flow_xstat)) { 5202 PMD_DRV_LOG(ERR, 5203 "Invalid value passed to flow_xstat devarg.\n"); 5204 return -EINVAL; 5205 } 5206 5207 bp->flags |= BNXT_FLAG_FLOW_XSTATS_EN; 5208 if (BNXT_FLOW_XSTATS_EN(bp)) 5209 PMD_DRV_LOG(INFO, "flow_xstat feature enabled.\n"); 5210 5211 return 0; 5212 } 5213 5214 static int 5215 bnxt_parse_devarg_max_num_kflows(__rte_unused const char *key, 5216 const char *value, void *opaque_arg) 5217 { 5218 struct bnxt *bp = opaque_arg; 5219 unsigned long max_num_kflows; 5220 char *end = NULL; 5221 5222 if (!value || !opaque_arg) { 5223 PMD_DRV_LOG(ERR, 5224 "Invalid parameter passed to max_num_kflows devarg.\n"); 5225 return -EINVAL; 5226 } 5227 5228 max_num_kflows = strtoul(value, &end, 10); 5229 if (end == NULL || *end != '\0' || 5230 (max_num_kflows == ULONG_MAX && errno == ERANGE)) { 5231 PMD_DRV_LOG(ERR, 5232 "Invalid parameter passed to max_num_kflows devarg.\n"); 5233 return -EINVAL; 5234 } 5235 5236 if (bnxt_devarg_max_num_kflow_invalid(max_num_kflows)) { 5237 PMD_DRV_LOG(ERR, 5238 "Invalid value passed to max_num_kflows devarg.\n"); 5239 return -EINVAL; 5240 } 5241 5242 bp->max_num_kflows = max_num_kflows; 5243 if (bp->max_num_kflows) 5244 PMD_DRV_LOG(INFO, "max_num_kflows set as %ldK.\n", 5245 max_num_kflows); 5246 5247 return 0; 5248 } 5249 5250 static int 5251 bnxt_parse_devarg_rep_is_pf(__rte_unused const char *key, 5252 const char *value, void *opaque_arg) 5253 { 5254 struct bnxt_representor *vfr_bp = opaque_arg; 5255 unsigned long rep_is_pf; 5256 char *end = NULL; 5257 5258 if (!value || !opaque_arg) { 5259 PMD_DRV_LOG(ERR, 5260 "Invalid parameter passed to rep_is_pf devargs.\n"); 5261 return -EINVAL; 5262 } 5263 5264 rep_is_pf = strtoul(value, &end, 10); 5265 if (end == NULL || *end != '\0' || 5266 (rep_is_pf == ULONG_MAX && errno == ERANGE)) { 5267 PMD_DRV_LOG(ERR, 5268 "Invalid parameter passed to rep_is_pf devargs.\n"); 5269 return -EINVAL; 5270 } 5271 5272 if (BNXT_DEVARG_REP_IS_PF_INVALID(rep_is_pf)) { 5273 PMD_DRV_LOG(ERR, 5274 "Invalid value passed to rep_is_pf devargs.\n"); 5275 return -EINVAL; 5276 } 5277 5278 vfr_bp->flags |= rep_is_pf; 5279 if (BNXT_REP_PF(vfr_bp)) 5280 PMD_DRV_LOG(INFO, "PF representor\n"); 5281 else 5282 PMD_DRV_LOG(INFO, "VF representor\n"); 5283 5284 return 0; 5285 } 5286 5287 static int 5288 bnxt_parse_devarg_rep_based_pf(__rte_unused const char *key, 5289 const char *value, void *opaque_arg) 5290 { 5291 struct bnxt_representor *vfr_bp = opaque_arg; 5292 unsigned long rep_based_pf; 5293 char *end = NULL; 5294 5295 if (!value || !opaque_arg) { 5296 PMD_DRV_LOG(ERR, 5297 "Invalid parameter passed to rep_based_pf " 5298 "devargs.\n"); 5299 return -EINVAL; 5300 } 5301 5302 rep_based_pf = strtoul(value, &end, 10); 5303 if (end == NULL || *end != '\0' || 5304 (rep_based_pf == ULONG_MAX && errno == ERANGE)) { 5305 PMD_DRV_LOG(ERR, 5306 "Invalid parameter passed to rep_based_pf " 5307 "devargs.\n"); 5308 return -EINVAL; 5309 } 5310 5311 if (BNXT_DEVARG_REP_BASED_PF_INVALID(rep_based_pf)) { 5312 PMD_DRV_LOG(ERR, 5313 "Invalid value passed to rep_based_pf devargs.\n"); 5314 return -EINVAL; 5315 } 5316 5317 vfr_bp->rep_based_pf = rep_based_pf; 5318 vfr_bp->flags |= BNXT_REP_BASED_PF_VALID; 5319 5320 PMD_DRV_LOG(INFO, "rep-based-pf = %d\n", vfr_bp->rep_based_pf); 5321 5322 return 0; 5323 } 5324 5325 static int 5326 bnxt_parse_devarg_rep_q_r2f(__rte_unused const char *key, 5327 const char *value, void *opaque_arg) 5328 { 5329 struct bnxt_representor *vfr_bp = opaque_arg; 5330 unsigned long rep_q_r2f; 5331 char *end = NULL; 5332 5333 if (!value || !opaque_arg) { 5334 PMD_DRV_LOG(ERR, 5335 "Invalid parameter passed to rep_q_r2f " 5336 "devargs.\n"); 5337 return -EINVAL; 5338 } 5339 5340 rep_q_r2f = strtoul(value, &end, 10); 5341 if (end == NULL || *end != '\0' || 5342 (rep_q_r2f == ULONG_MAX && errno == ERANGE)) { 5343 PMD_DRV_LOG(ERR, 5344 "Invalid parameter passed to rep_q_r2f " 5345 "devargs.\n"); 5346 return -EINVAL; 5347 } 5348 5349 if (BNXT_DEVARG_REP_Q_R2F_INVALID(rep_q_r2f)) { 5350 PMD_DRV_LOG(ERR, 5351 "Invalid value passed to rep_q_r2f devargs.\n"); 5352 return -EINVAL; 5353 } 5354 5355 vfr_bp->rep_q_r2f = rep_q_r2f; 5356 vfr_bp->flags |= BNXT_REP_Q_R2F_VALID; 5357 PMD_DRV_LOG(INFO, "rep-q-r2f = %d\n", vfr_bp->rep_q_r2f); 5358 5359 return 0; 5360 } 5361 5362 static int 5363 bnxt_parse_devarg_rep_q_f2r(__rte_unused const char *key, 5364 const char *value, void *opaque_arg) 5365 { 5366 struct bnxt_representor *vfr_bp = opaque_arg; 5367 unsigned long rep_q_f2r; 5368 char *end = NULL; 5369 5370 if (!value || !opaque_arg) { 5371 PMD_DRV_LOG(ERR, 5372 "Invalid parameter passed to rep_q_f2r " 5373 "devargs.\n"); 5374 return -EINVAL; 5375 } 5376 5377 rep_q_f2r = strtoul(value, &end, 10); 5378 if (end == NULL || *end != '\0' || 5379 (rep_q_f2r == ULONG_MAX && errno == ERANGE)) { 5380 PMD_DRV_LOG(ERR, 5381 "Invalid parameter passed to rep_q_f2r " 5382 "devargs.\n"); 5383 return -EINVAL; 5384 } 5385 5386 if (BNXT_DEVARG_REP_Q_F2R_INVALID(rep_q_f2r)) { 5387 PMD_DRV_LOG(ERR, 5388 "Invalid value passed to rep_q_f2r devargs.\n"); 5389 return -EINVAL; 5390 } 5391 5392 vfr_bp->rep_q_f2r = rep_q_f2r; 5393 vfr_bp->flags |= BNXT_REP_Q_F2R_VALID; 5394 PMD_DRV_LOG(INFO, "rep-q-f2r = %d\n", vfr_bp->rep_q_f2r); 5395 5396 return 0; 5397 } 5398 5399 static int 5400 bnxt_parse_devarg_rep_fc_r2f(__rte_unused const char *key, 5401 const char *value, void *opaque_arg) 5402 { 5403 struct bnxt_representor *vfr_bp = opaque_arg; 5404 unsigned long rep_fc_r2f; 5405 char *end = NULL; 5406 5407 if (!value || !opaque_arg) { 5408 PMD_DRV_LOG(ERR, 5409 "Invalid parameter passed to rep_fc_r2f " 5410 "devargs.\n"); 5411 return -EINVAL; 5412 } 5413 5414 rep_fc_r2f = strtoul(value, &end, 10); 5415 if (end == NULL || *end != '\0' || 5416 (rep_fc_r2f == ULONG_MAX && errno == ERANGE)) { 5417 PMD_DRV_LOG(ERR, 5418 "Invalid parameter passed to rep_fc_r2f " 5419 "devargs.\n"); 5420 return -EINVAL; 5421 } 5422 5423 if (BNXT_DEVARG_REP_FC_R2F_INVALID(rep_fc_r2f)) { 5424 PMD_DRV_LOG(ERR, 5425 "Invalid value passed to rep_fc_r2f devargs.\n"); 5426 return -EINVAL; 5427 } 5428 5429 vfr_bp->flags |= BNXT_REP_FC_R2F_VALID; 5430 vfr_bp->rep_fc_r2f = rep_fc_r2f; 5431 PMD_DRV_LOG(INFO, "rep-fc-r2f = %lu\n", rep_fc_r2f); 5432 5433 return 0; 5434 } 5435 5436 static int 5437 bnxt_parse_devarg_rep_fc_f2r(__rte_unused const char *key, 5438 const char *value, void *opaque_arg) 5439 { 5440 struct bnxt_representor *vfr_bp = opaque_arg; 5441 unsigned long rep_fc_f2r; 5442 char *end = NULL; 5443 5444 if (!value || !opaque_arg) { 5445 PMD_DRV_LOG(ERR, 5446 "Invalid parameter passed to rep_fc_f2r " 5447 "devargs.\n"); 5448 return -EINVAL; 5449 } 5450 5451 rep_fc_f2r = strtoul(value, &end, 10); 5452 if (end == NULL || *end != '\0' || 5453 (rep_fc_f2r == ULONG_MAX && errno == ERANGE)) { 5454 PMD_DRV_LOG(ERR, 5455 "Invalid parameter passed to rep_fc_f2r " 5456 "devargs.\n"); 5457 return -EINVAL; 5458 } 5459 5460 if (BNXT_DEVARG_REP_FC_F2R_INVALID(rep_fc_f2r)) { 5461 PMD_DRV_LOG(ERR, 5462 "Invalid value passed to rep_fc_f2r devargs.\n"); 5463 return -EINVAL; 5464 } 5465 5466 vfr_bp->flags |= BNXT_REP_FC_F2R_VALID; 5467 vfr_bp->rep_fc_f2r = rep_fc_f2r; 5468 PMD_DRV_LOG(INFO, "rep-fc-f2r = %lu\n", rep_fc_f2r); 5469 5470 return 0; 5471 } 5472 5473 static int 5474 bnxt_parse_dev_args(struct bnxt *bp, struct rte_devargs *devargs) 5475 { 5476 struct rte_kvargs *kvlist; 5477 int ret; 5478 5479 if (devargs == NULL) 5480 return 0; 5481 5482 kvlist = rte_kvargs_parse(devargs->args, bnxt_dev_args); 5483 if (kvlist == NULL) 5484 return -EINVAL; 5485 5486 /* 5487 * Handler for "truflow" devarg. 5488 * Invoked as for ex: "-a 0000:00:0d.0,host-based-truflow=1" 5489 */ 5490 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_TRUFLOW, 5491 bnxt_parse_devarg_truflow, bp); 5492 if (ret) 5493 goto err; 5494 5495 /* 5496 * Handler for "flow_xstat" devarg. 5497 * Invoked as for ex: "-a 0000:00:0d.0,flow_xstat=1" 5498 */ 5499 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_FLOW_XSTAT, 5500 bnxt_parse_devarg_flow_xstat, bp); 5501 if (ret) 5502 goto err; 5503 5504 /* 5505 * Handler for "max_num_kflows" devarg. 5506 * Invoked as for ex: "-a 000:00:0d.0,max_num_kflows=32" 5507 */ 5508 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_MAX_NUM_KFLOWS, 5509 bnxt_parse_devarg_max_num_kflows, bp); 5510 if (ret) 5511 goto err; 5512 5513 err: 5514 rte_kvargs_free(kvlist); 5515 return ret; 5516 } 5517 5518 static int bnxt_alloc_switch_domain(struct bnxt *bp) 5519 { 5520 int rc = 0; 5521 5522 if (BNXT_PF(bp) || BNXT_VF_IS_TRUSTED(bp)) { 5523 rc = rte_eth_switch_domain_alloc(&bp->switch_domain_id); 5524 if (rc) 5525 PMD_DRV_LOG(ERR, 5526 "Failed to alloc switch domain: %d\n", rc); 5527 else 5528 PMD_DRV_LOG(INFO, 5529 "Switch domain allocated %d\n", 5530 bp->switch_domain_id); 5531 } 5532 5533 return rc; 5534 } 5535 5536 /* Allocate and initialize various fields in bnxt struct that 5537 * need to be allocated/destroyed only once in the lifetime of the driver 5538 */ 5539 static int bnxt_drv_init(struct rte_eth_dev *eth_dev) 5540 { 5541 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5542 struct bnxt *bp = eth_dev->data->dev_private; 5543 int rc = 0; 5544 5545 bp->flags &= ~BNXT_FLAG_RX_VECTOR_PKT_MODE; 5546 5547 if (bnxt_vf_pciid(pci_dev->id.device_id)) 5548 bp->flags |= BNXT_FLAG_VF; 5549 5550 if (bnxt_p5_device(pci_dev->id.device_id)) 5551 bp->flags |= BNXT_FLAG_CHIP_P5; 5552 5553 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 5554 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 5555 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 5556 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 5557 bp->flags |= BNXT_FLAG_STINGRAY; 5558 5559 if (BNXT_TRUFLOW_EN(bp)) { 5560 /* extra mbuf field is required to store CFA code from mark */ 5561 static const struct rte_mbuf_dynfield bnxt_cfa_code_dynfield_desc = { 5562 .name = RTE_PMD_BNXT_CFA_CODE_DYNFIELD_NAME, 5563 .size = sizeof(bnxt_cfa_code_dynfield_t), 5564 .align = __alignof__(bnxt_cfa_code_dynfield_t), 5565 }; 5566 bnxt_cfa_code_dynfield_offset = 5567 rte_mbuf_dynfield_register(&bnxt_cfa_code_dynfield_desc); 5568 if (bnxt_cfa_code_dynfield_offset < 0) { 5569 PMD_DRV_LOG(ERR, 5570 "Failed to register mbuf field for TruFlow mark\n"); 5571 return -rte_errno; 5572 } 5573 } 5574 5575 rc = bnxt_map_pci_bars(eth_dev); 5576 if (rc) { 5577 PMD_DRV_LOG(ERR, 5578 "Failed to initialize board rc: %x\n", rc); 5579 return rc; 5580 } 5581 5582 rc = bnxt_alloc_pf_info(bp); 5583 if (rc) 5584 return rc; 5585 5586 rc = bnxt_alloc_link_info(bp); 5587 if (rc) 5588 return rc; 5589 5590 rc = bnxt_alloc_parent_info(bp); 5591 if (rc) 5592 return rc; 5593 5594 rc = bnxt_alloc_hwrm_resources(bp); 5595 if (rc) { 5596 PMD_DRV_LOG(ERR, 5597 "Failed to allocate response buffer rc: %x\n", rc); 5598 return rc; 5599 } 5600 rc = bnxt_alloc_leds_info(bp); 5601 if (rc) 5602 return rc; 5603 5604 rc = bnxt_alloc_cos_queues(bp); 5605 if (rc) 5606 return rc; 5607 5608 rc = bnxt_init_locks(bp); 5609 if (rc) 5610 return rc; 5611 5612 rc = bnxt_alloc_switch_domain(bp); 5613 if (rc) 5614 return rc; 5615 5616 return rc; 5617 } 5618 5619 static int 5620 bnxt_dev_init(struct rte_eth_dev *eth_dev, void *params __rte_unused) 5621 { 5622 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 5623 static int version_printed; 5624 struct bnxt *bp; 5625 int rc; 5626 5627 if (version_printed++ == 0) 5628 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 5629 5630 eth_dev->dev_ops = &bnxt_dev_ops; 5631 eth_dev->rx_queue_count = bnxt_rx_queue_count_op; 5632 eth_dev->rx_descriptor_status = bnxt_rx_descriptor_status_op; 5633 eth_dev->tx_descriptor_status = bnxt_tx_descriptor_status_op; 5634 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 5635 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 5636 5637 /* 5638 * For secondary processes, we don't initialise any further 5639 * as primary has already done this work. 5640 */ 5641 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5642 return 0; 5643 5644 rte_eth_copy_pci_info(eth_dev, pci_dev); 5645 eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS; 5646 5647 bp = eth_dev->data->dev_private; 5648 5649 /* Parse dev arguments passed on when starting the DPDK application. */ 5650 rc = bnxt_parse_dev_args(bp, pci_dev->device.devargs); 5651 if (rc) 5652 goto error_free; 5653 5654 rc = bnxt_drv_init(eth_dev); 5655 if (rc) 5656 goto error_free; 5657 5658 rc = bnxt_init_resources(bp, false); 5659 if (rc) 5660 goto error_free; 5661 5662 rc = bnxt_alloc_stats_mem(bp); 5663 if (rc) 5664 goto error_free; 5665 5666 PMD_DRV_LOG(INFO, 5667 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 5668 pci_dev->mem_resource[0].phys_addr, 5669 pci_dev->mem_resource[0].addr); 5670 5671 return 0; 5672 5673 error_free: 5674 bnxt_dev_uninit(eth_dev); 5675 return rc; 5676 } 5677 5678 5679 static void bnxt_free_ctx_mem_buf(struct bnxt_ctx_mem_buf_info *ctx) 5680 { 5681 if (!ctx) 5682 return; 5683 5684 if (ctx->va) 5685 rte_free(ctx->va); 5686 5687 ctx->va = NULL; 5688 ctx->dma = RTE_BAD_IOVA; 5689 ctx->ctx_id = BNXT_CTX_VAL_INVAL; 5690 } 5691 5692 static void bnxt_unregister_fc_ctx_mem(struct bnxt *bp) 5693 { 5694 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_RX, 5695 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5696 bp->flow_stat->rx_fc_out_tbl.ctx_id, 5697 bp->flow_stat->max_fc, 5698 false); 5699 5700 bnxt_hwrm_cfa_counter_cfg(bp, BNXT_DIR_TX, 5701 CFA_COUNTER_CFG_IN_COUNTER_TYPE_FC, 5702 bp->flow_stat->tx_fc_out_tbl.ctx_id, 5703 bp->flow_stat->max_fc, 5704 false); 5705 5706 if (bp->flow_stat->rx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5707 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_in_tbl.ctx_id); 5708 bp->flow_stat->rx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5709 5710 if (bp->flow_stat->rx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5711 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->rx_fc_out_tbl.ctx_id); 5712 bp->flow_stat->rx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5713 5714 if (bp->flow_stat->tx_fc_in_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5715 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_in_tbl.ctx_id); 5716 bp->flow_stat->tx_fc_in_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5717 5718 if (bp->flow_stat->tx_fc_out_tbl.ctx_id != BNXT_CTX_VAL_INVAL) 5719 bnxt_hwrm_ctx_unrgtr(bp, bp->flow_stat->tx_fc_out_tbl.ctx_id); 5720 bp->flow_stat->tx_fc_out_tbl.ctx_id = BNXT_CTX_VAL_INVAL; 5721 } 5722 5723 static void bnxt_uninit_fc_ctx_mem(struct bnxt *bp) 5724 { 5725 bnxt_unregister_fc_ctx_mem(bp); 5726 5727 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_in_tbl); 5728 bnxt_free_ctx_mem_buf(&bp->flow_stat->rx_fc_out_tbl); 5729 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_in_tbl); 5730 bnxt_free_ctx_mem_buf(&bp->flow_stat->tx_fc_out_tbl); 5731 } 5732 5733 static void bnxt_uninit_ctx_mem(struct bnxt *bp) 5734 { 5735 if (BNXT_FLOW_XSTATS_EN(bp)) 5736 bnxt_uninit_fc_ctx_mem(bp); 5737 } 5738 5739 static void 5740 bnxt_free_error_recovery_info(struct bnxt *bp) 5741 { 5742 rte_free(bp->recovery_info); 5743 bp->recovery_info = NULL; 5744 bp->fw_cap &= ~BNXT_FW_CAP_ERROR_RECOVERY; 5745 } 5746 5747 static int 5748 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 5749 { 5750 int rc; 5751 5752 bnxt_free_int(bp); 5753 bnxt_free_mem(bp, reconfig_dev); 5754 5755 bnxt_hwrm_func_buf_unrgtr(bp); 5756 rte_free(bp->pf->vf_req_buf); 5757 5758 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 5759 bp->flags &= ~BNXT_FLAG_REGISTERED; 5760 bnxt_free_ctx_mem(bp); 5761 if (!reconfig_dev) { 5762 bnxt_free_hwrm_resources(bp); 5763 bnxt_free_error_recovery_info(bp); 5764 } 5765 5766 bnxt_uninit_ctx_mem(bp); 5767 5768 bnxt_free_flow_stats_info(bp); 5769 bnxt_free_rep_info(bp); 5770 rte_free(bp->ptp_cfg); 5771 bp->ptp_cfg = NULL; 5772 return rc; 5773 } 5774 5775 static int 5776 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 5777 { 5778 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 5779 return -EPERM; 5780 5781 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 5782 5783 if (eth_dev->state != RTE_ETH_DEV_UNUSED) 5784 bnxt_dev_close_op(eth_dev); 5785 5786 return 0; 5787 } 5788 5789 static int bnxt_pci_remove_dev_with_reps(struct rte_eth_dev *eth_dev) 5790 { 5791 struct bnxt *bp = eth_dev->data->dev_private; 5792 struct rte_eth_dev *vf_rep_eth_dev; 5793 int ret = 0, i; 5794 5795 if (!bp) 5796 return -EINVAL; 5797 5798 for (i = 0; i < bp->num_reps; i++) { 5799 vf_rep_eth_dev = bp->rep_info[i].vfr_eth_dev; 5800 if (!vf_rep_eth_dev) 5801 continue; 5802 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci remove\n", 5803 vf_rep_eth_dev->data->port_id); 5804 rte_eth_dev_destroy(vf_rep_eth_dev, bnxt_representor_uninit); 5805 } 5806 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", 5807 eth_dev->data->port_id); 5808 ret = rte_eth_dev_destroy(eth_dev, bnxt_dev_uninit); 5809 5810 return ret; 5811 } 5812 5813 static void bnxt_free_rep_info(struct bnxt *bp) 5814 { 5815 rte_free(bp->rep_info); 5816 bp->rep_info = NULL; 5817 rte_free(bp->cfa_code_map); 5818 bp->cfa_code_map = NULL; 5819 } 5820 5821 static int bnxt_init_rep_info(struct bnxt *bp) 5822 { 5823 int i = 0, rc; 5824 5825 if (bp->rep_info) 5826 return 0; 5827 5828 bp->rep_info = rte_zmalloc("bnxt_rep_info", 5829 sizeof(bp->rep_info[0]) * BNXT_MAX_VF_REPS, 5830 0); 5831 if (!bp->rep_info) { 5832 PMD_DRV_LOG(ERR, "Failed to alloc memory for rep info\n"); 5833 return -ENOMEM; 5834 } 5835 bp->cfa_code_map = rte_zmalloc("bnxt_cfa_code_map", 5836 sizeof(*bp->cfa_code_map) * 5837 BNXT_MAX_CFA_CODE, 0); 5838 if (!bp->cfa_code_map) { 5839 PMD_DRV_LOG(ERR, "Failed to alloc memory for cfa_code_map\n"); 5840 bnxt_free_rep_info(bp); 5841 return -ENOMEM; 5842 } 5843 5844 for (i = 0; i < BNXT_MAX_CFA_CODE; i++) 5845 bp->cfa_code_map[i] = BNXT_VF_IDX_INVALID; 5846 5847 rc = pthread_mutex_init(&bp->rep_info->vfr_lock, NULL); 5848 if (rc) { 5849 PMD_DRV_LOG(ERR, "Unable to initialize vfr_lock\n"); 5850 bnxt_free_rep_info(bp); 5851 return rc; 5852 } 5853 5854 rc = pthread_mutex_init(&bp->rep_info->vfr_start_lock, NULL); 5855 if (rc) { 5856 PMD_DRV_LOG(ERR, "Unable to initialize vfr_start_lock\n"); 5857 bnxt_free_rep_info(bp); 5858 return rc; 5859 } 5860 5861 return rc; 5862 } 5863 5864 static int bnxt_rep_port_probe(struct rte_pci_device *pci_dev, 5865 struct rte_eth_devargs *eth_da, 5866 struct rte_eth_dev *backing_eth_dev, 5867 const char *dev_args) 5868 { 5869 struct rte_eth_dev *vf_rep_eth_dev; 5870 char name[RTE_ETH_NAME_MAX_LEN]; 5871 struct bnxt *backing_bp; 5872 uint16_t num_rep; 5873 int i, ret = 0; 5874 struct rte_kvargs *kvlist = NULL; 5875 5876 if (eth_da->type == RTE_ETH_REPRESENTOR_NONE) 5877 return 0; 5878 if (eth_da->type != RTE_ETH_REPRESENTOR_VF) { 5879 PMD_DRV_LOG(ERR, "unsupported representor type %d\n", 5880 eth_da->type); 5881 return -ENOTSUP; 5882 } 5883 num_rep = eth_da->nb_representor_ports; 5884 if (num_rep > BNXT_MAX_VF_REPS) { 5885 PMD_DRV_LOG(ERR, "nb_representor_ports = %d > %d MAX VF REPS\n", 5886 num_rep, BNXT_MAX_VF_REPS); 5887 return -EINVAL; 5888 } 5889 5890 if (num_rep >= RTE_MAX_ETHPORTS) { 5891 PMD_DRV_LOG(ERR, 5892 "nb_representor_ports = %d > %d MAX ETHPORTS\n", 5893 num_rep, RTE_MAX_ETHPORTS); 5894 return -EINVAL; 5895 } 5896 5897 backing_bp = backing_eth_dev->data->dev_private; 5898 5899 if (!(BNXT_PF(backing_bp) || BNXT_VF_IS_TRUSTED(backing_bp))) { 5900 PMD_DRV_LOG(ERR, 5901 "Not a PF or trusted VF. No Representor support\n"); 5902 /* Returning an error is not an option. 5903 * Applications are not handling this correctly 5904 */ 5905 return 0; 5906 } 5907 5908 if (bnxt_init_rep_info(backing_bp)) 5909 return 0; 5910 5911 for (i = 0; i < num_rep; i++) { 5912 struct bnxt_representor representor = { 5913 .vf_id = eth_da->representor_ports[i], 5914 .switch_domain_id = backing_bp->switch_domain_id, 5915 .parent_dev = backing_eth_dev 5916 }; 5917 5918 if (representor.vf_id >= BNXT_MAX_VF_REPS) { 5919 PMD_DRV_LOG(ERR, "VF-Rep id %d >= %d MAX VF ID\n", 5920 representor.vf_id, BNXT_MAX_VF_REPS); 5921 continue; 5922 } 5923 5924 /* representor port net_bdf_port */ 5925 snprintf(name, sizeof(name), "net_%s_representor_%d", 5926 pci_dev->device.name, eth_da->representor_ports[i]); 5927 5928 kvlist = rte_kvargs_parse(dev_args, bnxt_dev_args); 5929 if (kvlist) { 5930 /* 5931 * Handler for "rep_is_pf" devarg. 5932 * Invoked as for ex: "-a 000:00:0d.0, 5933 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5934 */ 5935 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_IS_PF, 5936 bnxt_parse_devarg_rep_is_pf, 5937 (void *)&representor); 5938 if (ret) { 5939 ret = -EINVAL; 5940 goto err; 5941 } 5942 /* 5943 * Handler for "rep_based_pf" devarg. 5944 * Invoked as for ex: "-a 000:00:0d.0, 5945 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5946 */ 5947 ret = rte_kvargs_process(kvlist, 5948 BNXT_DEVARG_REP_BASED_PF, 5949 bnxt_parse_devarg_rep_based_pf, 5950 (void *)&representor); 5951 if (ret) { 5952 ret = -EINVAL; 5953 goto err; 5954 } 5955 /* 5956 * Handler for "rep_based_pf" devarg. 5957 * Invoked as for ex: "-a 000:00:0d.0, 5958 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5959 */ 5960 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_R2F, 5961 bnxt_parse_devarg_rep_q_r2f, 5962 (void *)&representor); 5963 if (ret) { 5964 ret = -EINVAL; 5965 goto err; 5966 } 5967 /* 5968 * Handler for "rep_based_pf" devarg. 5969 * Invoked as for ex: "-a 000:00:0d.0, 5970 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5971 */ 5972 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_Q_F2R, 5973 bnxt_parse_devarg_rep_q_f2r, 5974 (void *)&representor); 5975 if (ret) { 5976 ret = -EINVAL; 5977 goto err; 5978 } 5979 /* 5980 * Handler for "rep_based_pf" devarg. 5981 * Invoked as for ex: "-a 000:00:0d.0, 5982 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5983 */ 5984 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_R2F, 5985 bnxt_parse_devarg_rep_fc_r2f, 5986 (void *)&representor); 5987 if (ret) { 5988 ret = -EINVAL; 5989 goto err; 5990 } 5991 /* 5992 * Handler for "rep_based_pf" devarg. 5993 * Invoked as for ex: "-a 000:00:0d.0, 5994 * rep-based-pf=<pf index> rep-is-pf=<VF=0 or PF=1>" 5995 */ 5996 ret = rte_kvargs_process(kvlist, BNXT_DEVARG_REP_FC_F2R, 5997 bnxt_parse_devarg_rep_fc_f2r, 5998 (void *)&representor); 5999 if (ret) { 6000 ret = -EINVAL; 6001 goto err; 6002 } 6003 } 6004 6005 ret = rte_eth_dev_create(&pci_dev->device, name, 6006 sizeof(struct bnxt_representor), 6007 NULL, NULL, 6008 bnxt_representor_init, 6009 &representor); 6010 if (ret) { 6011 PMD_DRV_LOG(ERR, "failed to create bnxt vf " 6012 "representor %s.", name); 6013 goto err; 6014 } 6015 6016 vf_rep_eth_dev = rte_eth_dev_allocated(name); 6017 if (!vf_rep_eth_dev) { 6018 PMD_DRV_LOG(ERR, "Failed to find the eth_dev" 6019 " for VF-Rep: %s.", name); 6020 ret = -ENODEV; 6021 goto err; 6022 } 6023 6024 PMD_DRV_LOG(DEBUG, "BNXT Port:%d VFR pci probe\n", 6025 backing_eth_dev->data->port_id); 6026 backing_bp->rep_info[representor.vf_id].vfr_eth_dev = 6027 vf_rep_eth_dev; 6028 backing_bp->num_reps++; 6029 6030 } 6031 6032 rte_kvargs_free(kvlist); 6033 return 0; 6034 6035 err: 6036 /* If num_rep > 1, then rollback already created 6037 * ports, since we'll be failing the probe anyway 6038 */ 6039 if (num_rep > 1) 6040 bnxt_pci_remove_dev_with_reps(backing_eth_dev); 6041 rte_errno = -ret; 6042 rte_kvargs_free(kvlist); 6043 6044 return ret; 6045 } 6046 6047 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 6048 struct rte_pci_device *pci_dev) 6049 { 6050 struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 }; 6051 struct rte_eth_dev *backing_eth_dev; 6052 uint16_t num_rep; 6053 int ret = 0; 6054 6055 if (pci_dev->device.devargs) { 6056 ret = rte_eth_devargs_parse(pci_dev->device.devargs->args, 6057 ð_da); 6058 if (ret) 6059 return ret; 6060 } 6061 6062 num_rep = eth_da.nb_representor_ports; 6063 PMD_DRV_LOG(DEBUG, "nb_representor_ports = %d\n", 6064 num_rep); 6065 6066 /* We could come here after first level of probe is already invoked 6067 * as part of an application bringup(OVS-DPDK vswitchd), so first check 6068 * for already allocated eth_dev for the backing device (PF/Trusted VF) 6069 */ 6070 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6071 if (backing_eth_dev == NULL) { 6072 ret = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name, 6073 sizeof(struct bnxt), 6074 eth_dev_pci_specific_init, pci_dev, 6075 bnxt_dev_init, NULL); 6076 6077 if (ret || !num_rep) 6078 return ret; 6079 6080 backing_eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6081 } 6082 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci probe\n", 6083 backing_eth_dev->data->port_id); 6084 6085 if (!num_rep) 6086 return ret; 6087 6088 /* probe representor ports now */ 6089 ret = bnxt_rep_port_probe(pci_dev, ð_da, backing_eth_dev, 6090 pci_dev->device.devargs->args); 6091 6092 return ret; 6093 } 6094 6095 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 6096 { 6097 struct rte_eth_dev *eth_dev; 6098 6099 eth_dev = rte_eth_dev_allocated(pci_dev->device.name); 6100 if (!eth_dev) 6101 return 0; /* Invoked typically only by OVS-DPDK, by the 6102 * time it comes here the eth_dev is already 6103 * deleted by rte_eth_dev_close(), so returning 6104 * +ve value will at least help in proper cleanup 6105 */ 6106 6107 PMD_DRV_LOG(DEBUG, "BNXT Port:%d pci remove\n", eth_dev->data->port_id); 6108 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 6109 if (eth_dev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR) 6110 return rte_eth_dev_destroy(eth_dev, 6111 bnxt_representor_uninit); 6112 else 6113 return rte_eth_dev_destroy(eth_dev, 6114 bnxt_dev_uninit); 6115 } else { 6116 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 6117 } 6118 } 6119 6120 static struct rte_pci_driver bnxt_rte_pmd = { 6121 .id_table = bnxt_pci_id_map, 6122 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC | 6123 RTE_PCI_DRV_PROBE_AGAIN, /* Needed in case of VF-REPs 6124 * and OVS-DPDK 6125 */ 6126 .probe = bnxt_pci_probe, 6127 .remove = bnxt_pci_remove, 6128 }; 6129 6130 static bool 6131 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 6132 { 6133 if (strcmp(dev->device->driver->name, drv->driver.name)) 6134 return false; 6135 6136 return true; 6137 } 6138 6139 bool is_bnxt_supported(struct rte_eth_dev *dev) 6140 { 6141 return is_device_supported(dev, &bnxt_rte_pmd); 6142 } 6143 6144 RTE_LOG_REGISTER(bnxt_logtype_driver, pmd.net.bnxt.driver, NOTICE); 6145 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 6146 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 6147 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 6148