1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 #include <rte_alarm.h> 15 16 #include "bnxt.h" 17 #include "bnxt_cpr.h" 18 #include "bnxt_filter.h" 19 #include "bnxt_hwrm.h" 20 #include "bnxt_irq.h" 21 #include "bnxt_ring.h" 22 #include "bnxt_rxq.h" 23 #include "bnxt_rxr.h" 24 #include "bnxt_stats.h" 25 #include "bnxt_txq.h" 26 #include "bnxt_txr.h" 27 #include "bnxt_vnic.h" 28 #include "hsi_struct_def_dpdk.h" 29 #include "bnxt_nvm_defs.h" 30 #include "bnxt_util.h" 31 32 #define DRV_MODULE_NAME "bnxt" 33 static const char bnxt_version[] = 34 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 35 int bnxt_logtype_driver; 36 37 #define PCI_VENDOR_ID_BROADCOM 0x14E4 38 39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 40 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 41 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 42 #define BROADCOM_DEV_ID_57414_VF 0x16c1 43 #define BROADCOM_DEV_ID_57301 0x16c8 44 #define BROADCOM_DEV_ID_57302 0x16c9 45 #define BROADCOM_DEV_ID_57304_PF 0x16ca 46 #define BROADCOM_DEV_ID_57304_VF 0x16cb 47 #define BROADCOM_DEV_ID_57417_MF 0x16cc 48 #define BROADCOM_DEV_ID_NS2 0x16cd 49 #define BROADCOM_DEV_ID_57311 0x16ce 50 #define BROADCOM_DEV_ID_57312 0x16cf 51 #define BROADCOM_DEV_ID_57402 0x16d0 52 #define BROADCOM_DEV_ID_57404 0x16d1 53 #define BROADCOM_DEV_ID_57406_PF 0x16d2 54 #define BROADCOM_DEV_ID_57406_VF 0x16d3 55 #define BROADCOM_DEV_ID_57402_MF 0x16d4 56 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 57 #define BROADCOM_DEV_ID_57412 0x16d6 58 #define BROADCOM_DEV_ID_57414 0x16d7 59 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 60 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 61 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 62 #define BROADCOM_DEV_ID_57412_MF 0x16de 63 #define BROADCOM_DEV_ID_57314 0x16df 64 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 65 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 66 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 67 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 68 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 69 #define BROADCOM_DEV_ID_57404_MF 0x16e7 70 #define BROADCOM_DEV_ID_57406_MF 0x16e8 71 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 72 #define BROADCOM_DEV_ID_57407_MF 0x16ea 73 #define BROADCOM_DEV_ID_57414_MF 0x16ec 74 #define BROADCOM_DEV_ID_57416_MF 0x16ee 75 #define BROADCOM_DEV_ID_57508 0x1750 76 #define BROADCOM_DEV_ID_57504 0x1751 77 #define BROADCOM_DEV_ID_57502 0x1752 78 #define BROADCOM_DEV_ID_57500_VF1 0x1806 79 #define BROADCOM_DEV_ID_57500_VF2 0x1807 80 #define BROADCOM_DEV_ID_58802 0xd802 81 #define BROADCOM_DEV_ID_58804 0xd804 82 #define BROADCOM_DEV_ID_58808 0x16f0 83 #define BROADCOM_DEV_ID_58802_VF 0xd800 84 85 static const struct rte_pci_id bnxt_pci_id_map[] = { 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 87 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 89 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57508) }, 129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57504) }, 130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57502) }, 131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF1) }, 132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57500_VF2) }, 133 { .vendor_id = 0, /* sentinel */ }, 134 }; 135 136 #define BNXT_ETH_RSS_SUPPORT ( \ 137 ETH_RSS_IPV4 | \ 138 ETH_RSS_NONFRAG_IPV4_TCP | \ 139 ETH_RSS_NONFRAG_IPV4_UDP | \ 140 ETH_RSS_IPV6 | \ 141 ETH_RSS_NONFRAG_IPV6_TCP | \ 142 ETH_RSS_NONFRAG_IPV6_UDP) 143 144 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 145 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 146 DEV_TX_OFFLOAD_TCP_CKSUM | \ 147 DEV_TX_OFFLOAD_UDP_CKSUM | \ 148 DEV_TX_OFFLOAD_TCP_TSO | \ 149 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 150 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 151 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 152 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 153 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 154 DEV_TX_OFFLOAD_MULTI_SEGS) 155 156 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 157 DEV_RX_OFFLOAD_VLAN_STRIP | \ 158 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 159 DEV_RX_OFFLOAD_UDP_CKSUM | \ 160 DEV_RX_OFFLOAD_TCP_CKSUM | \ 161 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 162 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 163 DEV_RX_OFFLOAD_KEEP_CRC | \ 164 DEV_RX_OFFLOAD_TCP_LRO) 165 166 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 167 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 168 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 169 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 170 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev); 171 static int bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev); 172 static void bnxt_cancel_fw_health_check(struct bnxt *bp); 173 174 int is_bnxt_in_error(struct bnxt *bp) 175 { 176 if (bp->flags & BNXT_FLAG_FATAL_ERROR) 177 return -EIO; 178 if (bp->flags & BNXT_FLAG_FW_RESET) 179 return -EBUSY; 180 181 return 0; 182 } 183 184 /***********************/ 185 186 /* 187 * High level utility functions 188 */ 189 190 static uint16_t bnxt_rss_ctxts(const struct bnxt *bp) 191 { 192 if (!BNXT_CHIP_THOR(bp)) 193 return 1; 194 195 return RTE_ALIGN_MUL_CEIL(bp->rx_nr_rings, 196 BNXT_RSS_ENTRIES_PER_CTX_THOR) / 197 BNXT_RSS_ENTRIES_PER_CTX_THOR; 198 } 199 200 static uint16_t bnxt_rss_hash_tbl_size(const struct bnxt *bp) 201 { 202 if (!BNXT_CHIP_THOR(bp)) 203 return HW_HASH_INDEX_SIZE; 204 205 return bnxt_rss_ctxts(bp) * BNXT_RSS_ENTRIES_PER_CTX_THOR; 206 } 207 208 static void bnxt_free_mem(struct bnxt *bp, bool reconfig) 209 { 210 bnxt_free_filter_mem(bp); 211 bnxt_free_vnic_attributes(bp); 212 bnxt_free_vnic_mem(bp); 213 214 /* tx/rx rings are configured as part of *_queue_setup callbacks. 215 * If the number of rings change across fw update, 216 * we don't have much choice except to warn the user. 217 */ 218 if (!reconfig) { 219 bnxt_free_stats(bp); 220 bnxt_free_tx_rings(bp); 221 bnxt_free_rx_rings(bp); 222 } 223 bnxt_free_async_cp_ring(bp); 224 } 225 226 static int bnxt_alloc_mem(struct bnxt *bp, bool reconfig) 227 { 228 int rc; 229 230 rc = bnxt_alloc_ring_grps(bp); 231 if (rc) 232 goto alloc_mem_err; 233 234 rc = bnxt_alloc_async_ring_struct(bp); 235 if (rc) 236 goto alloc_mem_err; 237 238 rc = bnxt_alloc_vnic_mem(bp); 239 if (rc) 240 goto alloc_mem_err; 241 242 rc = bnxt_alloc_vnic_attributes(bp); 243 if (rc) 244 goto alloc_mem_err; 245 246 rc = bnxt_alloc_filter_mem(bp); 247 if (rc) 248 goto alloc_mem_err; 249 250 rc = bnxt_alloc_async_cp_ring(bp); 251 if (rc) 252 goto alloc_mem_err; 253 254 return 0; 255 256 alloc_mem_err: 257 bnxt_free_mem(bp, reconfig); 258 return rc; 259 } 260 261 static int bnxt_init_chip(struct bnxt *bp) 262 { 263 struct bnxt_rx_queue *rxq; 264 struct rte_eth_link new; 265 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 266 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 267 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 268 uint64_t rx_offloads = dev_conf->rxmode.offloads; 269 uint32_t intr_vector = 0; 270 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 271 uint32_t vec = BNXT_MISC_VEC_ID; 272 unsigned int i, j; 273 int rc; 274 275 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 276 bp->eth_dev->data->dev_conf.rxmode.offloads |= 277 DEV_RX_OFFLOAD_JUMBO_FRAME; 278 bp->flags |= BNXT_FLAG_JUMBO; 279 } else { 280 bp->eth_dev->data->dev_conf.rxmode.offloads &= 281 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 282 bp->flags &= ~BNXT_FLAG_JUMBO; 283 } 284 285 /* THOR does not support ring groups. 286 * But we will use the array to save RSS context IDs. 287 */ 288 if (BNXT_CHIP_THOR(bp)) 289 bp->max_ring_grps = BNXT_MAX_RSS_CTXTS_THOR; 290 291 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 292 if (rc) { 293 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 294 goto err_out; 295 } 296 297 rc = bnxt_alloc_hwrm_rings(bp); 298 if (rc) { 299 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 300 goto err_out; 301 } 302 303 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 304 if (rc) { 305 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 306 goto err_out; 307 } 308 309 rc = bnxt_mq_rx_configure(bp); 310 if (rc) { 311 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 312 goto err_out; 313 } 314 315 /* VNIC configuration */ 316 for (i = 0; i < bp->nr_vnics; i++) { 317 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 318 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 319 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps; 320 321 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0); 322 if (!vnic->fw_grp_ids) { 323 PMD_DRV_LOG(ERR, 324 "Failed to alloc %d bytes for group ids\n", 325 size); 326 rc = -ENOMEM; 327 goto err_out; 328 } 329 memset(vnic->fw_grp_ids, -1, size); 330 331 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 332 i, vnic, vnic->fw_grp_ids); 333 334 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 335 if (rc) { 336 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 337 i, rc); 338 goto err_out; 339 } 340 341 /* Alloc RSS context only if RSS mode is enabled */ 342 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 343 int j, nr_ctxs = bnxt_rss_ctxts(bp); 344 345 rc = 0; 346 for (j = 0; j < nr_ctxs; j++) { 347 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic, j); 348 if (rc) 349 break; 350 } 351 if (rc) { 352 PMD_DRV_LOG(ERR, 353 "HWRM vnic %d ctx %d alloc failure rc: %x\n", 354 i, j, rc); 355 goto err_out; 356 } 357 vnic->num_lb_ctxts = nr_ctxs; 358 } 359 360 /* 361 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 362 * setting is not available at this time, it will not be 363 * configured correctly in the CFA. 364 */ 365 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 366 vnic->vlan_strip = true; 367 else 368 vnic->vlan_strip = false; 369 370 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 371 if (rc) { 372 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 373 i, rc); 374 goto err_out; 375 } 376 377 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 378 if (rc) { 379 PMD_DRV_LOG(ERR, 380 "HWRM vnic %d filter failure rc: %x\n", 381 i, rc); 382 goto err_out; 383 } 384 385 for (j = 0; j < bp->rx_nr_rings; j++) { 386 rxq = bp->eth_dev->data->rx_queues[j]; 387 388 PMD_DRV_LOG(DEBUG, 389 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 390 j, rxq->vnic, rxq->vnic->fw_grp_ids); 391 392 if (BNXT_HAS_RING_GRPS(bp) && rxq->rx_deferred_start) 393 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 394 } 395 396 rc = bnxt_vnic_rss_configure(bp, vnic); 397 if (rc) { 398 PMD_DRV_LOG(ERR, 399 "HWRM vnic set RSS failure rc: %x\n", rc); 400 goto err_out; 401 } 402 403 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 404 405 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 406 DEV_RX_OFFLOAD_TCP_LRO) 407 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 408 else 409 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 410 } 411 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 412 if (rc) { 413 PMD_DRV_LOG(ERR, 414 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 415 goto err_out; 416 } 417 418 /* check and configure queue intr-vector mapping */ 419 if ((rte_intr_cap_multiple(intr_handle) || 420 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 421 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 422 intr_vector = bp->eth_dev->data->nb_rx_queues; 423 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 424 if (intr_vector > bp->rx_cp_nr_rings) { 425 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 426 bp->rx_cp_nr_rings); 427 return -ENOTSUP; 428 } 429 rc = rte_intr_efd_enable(intr_handle, intr_vector); 430 if (rc) 431 return rc; 432 } 433 434 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 435 intr_handle->intr_vec = 436 rte_zmalloc("intr_vec", 437 bp->eth_dev->data->nb_rx_queues * 438 sizeof(int), 0); 439 if (intr_handle->intr_vec == NULL) { 440 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 441 " intr_vec", bp->eth_dev->data->nb_rx_queues); 442 rc = -ENOMEM; 443 goto err_disable; 444 } 445 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 446 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 447 intr_handle->intr_vec, intr_handle->nb_efd, 448 intr_handle->max_intr); 449 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 450 queue_id++) { 451 intr_handle->intr_vec[queue_id] = 452 vec + BNXT_RX_VEC_START; 453 if (vec < base + intr_handle->nb_efd - 1) 454 vec++; 455 } 456 } 457 458 /* enable uio/vfio intr/eventfd mapping */ 459 rc = rte_intr_enable(intr_handle); 460 if (rc) 461 goto err_free; 462 463 rc = bnxt_get_hwrm_link_config(bp, &new); 464 if (rc) { 465 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 466 goto err_free; 467 } 468 469 if (!bp->link_info.link_up) { 470 rc = bnxt_set_hwrm_link_config(bp, true); 471 if (rc) { 472 PMD_DRV_LOG(ERR, 473 "HWRM link config failure rc: %x\n", rc); 474 goto err_free; 475 } 476 } 477 bnxt_print_link_info(bp->eth_dev); 478 479 return 0; 480 481 err_free: 482 rte_free(intr_handle->intr_vec); 483 err_disable: 484 rte_intr_efd_disable(intr_handle); 485 err_out: 486 /* Some of the error status returned by FW may not be from errno.h */ 487 if (rc > 0) 488 rc = -EIO; 489 490 return rc; 491 } 492 493 static int bnxt_shutdown_nic(struct bnxt *bp) 494 { 495 bnxt_free_all_hwrm_resources(bp); 496 bnxt_free_all_filters(bp); 497 bnxt_free_all_vnics(bp); 498 return 0; 499 } 500 501 static int bnxt_init_nic(struct bnxt *bp) 502 { 503 int rc; 504 505 if (BNXT_HAS_RING_GRPS(bp)) { 506 rc = bnxt_init_ring_grps(bp); 507 if (rc) 508 return rc; 509 } 510 511 bnxt_init_vnics(bp); 512 bnxt_init_filters(bp); 513 514 return 0; 515 } 516 517 /* 518 * Device configuration and status function 519 */ 520 521 static int bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 522 struct rte_eth_dev_info *dev_info) 523 { 524 struct bnxt *bp = eth_dev->data->dev_private; 525 uint16_t max_vnics, i, j, vpool, vrxq; 526 unsigned int max_rx_rings; 527 int rc; 528 529 rc = is_bnxt_in_error(bp); 530 if (rc) 531 return rc; 532 533 /* MAC Specifics */ 534 dev_info->max_mac_addrs = bp->max_l2_ctx; 535 dev_info->max_hash_mac_addrs = 0; 536 537 /* PF/VF specifics */ 538 if (BNXT_PF(bp)) 539 dev_info->max_vfs = bp->pdev->max_vfs; 540 max_rx_rings = RTE_MIN(bp->max_rx_rings, bp->max_stat_ctx); 541 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 542 dev_info->max_rx_queues = max_rx_rings; 543 dev_info->max_tx_queues = max_rx_rings; 544 dev_info->reta_size = bnxt_rss_hash_tbl_size(bp); 545 dev_info->hash_key_size = 40; 546 max_vnics = bp->max_vnics; 547 548 /* MTU specifics */ 549 dev_info->min_mtu = RTE_ETHER_MIN_MTU; 550 dev_info->max_mtu = BNXT_MAX_MTU; 551 552 /* Fast path specifics */ 553 dev_info->min_rx_bufsize = 1; 554 dev_info->max_rx_pktlen = BNXT_MAX_PKT_LEN; 555 556 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 557 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 558 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 559 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 560 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 561 562 /* *INDENT-OFF* */ 563 dev_info->default_rxconf = (struct rte_eth_rxconf) { 564 .rx_thresh = { 565 .pthresh = 8, 566 .hthresh = 8, 567 .wthresh = 0, 568 }, 569 .rx_free_thresh = 32, 570 /* If no descriptors available, pkts are dropped by default */ 571 .rx_drop_en = 1, 572 }; 573 574 dev_info->default_txconf = (struct rte_eth_txconf) { 575 .tx_thresh = { 576 .pthresh = 32, 577 .hthresh = 0, 578 .wthresh = 0, 579 }, 580 .tx_free_thresh = 32, 581 .tx_rs_thresh = 32, 582 }; 583 eth_dev->data->dev_conf.intr_conf.lsc = 1; 584 585 eth_dev->data->dev_conf.intr_conf.rxq = 1; 586 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 587 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 588 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 589 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 590 591 /* *INDENT-ON* */ 592 593 /* 594 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 595 * need further investigation. 596 */ 597 598 /* VMDq resources */ 599 vpool = 64; /* ETH_64_POOLS */ 600 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 601 for (i = 0; i < 4; vpool >>= 1, i++) { 602 if (max_vnics > vpool) { 603 for (j = 0; j < 5; vrxq >>= 1, j++) { 604 if (dev_info->max_rx_queues > vrxq) { 605 if (vpool > vrxq) 606 vpool = vrxq; 607 goto found; 608 } 609 } 610 /* Not enough resources to support VMDq */ 611 break; 612 } 613 } 614 /* Not enough resources to support VMDq */ 615 vpool = 0; 616 vrxq = 0; 617 found: 618 dev_info->max_vmdq_pools = vpool; 619 dev_info->vmdq_queue_num = vrxq; 620 621 dev_info->vmdq_pool_base = 0; 622 dev_info->vmdq_queue_base = 0; 623 624 return 0; 625 } 626 627 /* Configure the device based on the configuration provided */ 628 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 629 { 630 struct bnxt *bp = eth_dev->data->dev_private; 631 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 632 int rc; 633 634 bp->rx_queues = (void *)eth_dev->data->rx_queues; 635 bp->tx_queues = (void *)eth_dev->data->tx_queues; 636 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 637 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 638 639 rc = is_bnxt_in_error(bp); 640 if (rc) 641 return rc; 642 643 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 644 rc = bnxt_hwrm_check_vf_rings(bp); 645 if (rc) { 646 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 647 return -ENOSPC; 648 } 649 650 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 651 if (rc) { 652 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 653 return -ENOSPC; 654 } 655 } else { 656 /* legacy driver needs to get updated values */ 657 rc = bnxt_hwrm_func_qcaps(bp); 658 if (rc) { 659 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 660 return rc; 661 } 662 } 663 664 /* Inherit new configurations */ 665 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 666 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 667 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues 668 + BNXT_NUM_ASYNC_CPR(bp) > bp->max_cp_rings || 669 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 670 bp->max_stat_ctx) 671 goto resource_error; 672 673 if (BNXT_HAS_RING_GRPS(bp) && 674 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps) 675 goto resource_error; 676 677 if (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 678 bp->max_vnics < eth_dev->data->nb_rx_queues) 679 goto resource_error; 680 681 bp->rx_cp_nr_rings = bp->rx_nr_rings; 682 bp->tx_cp_nr_rings = bp->tx_nr_rings; 683 684 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 685 eth_dev->data->mtu = 686 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 687 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 688 BNXT_NUM_VLANS; 689 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 690 } 691 return 0; 692 693 resource_error: 694 PMD_DRV_LOG(ERR, 695 "Insufficient resources to support requested config\n"); 696 PMD_DRV_LOG(ERR, 697 "Num Queues Requested: Tx %d, Rx %d\n", 698 eth_dev->data->nb_tx_queues, 699 eth_dev->data->nb_rx_queues); 700 PMD_DRV_LOG(ERR, 701 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 702 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 703 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 704 return -ENOSPC; 705 } 706 707 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 708 { 709 struct rte_eth_link *link = ð_dev->data->dev_link; 710 711 if (link->link_status) 712 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 713 eth_dev->data->port_id, 714 (uint32_t)link->link_speed, 715 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 716 ("full-duplex") : ("half-duplex\n")); 717 else 718 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 719 eth_dev->data->port_id); 720 } 721 722 /* 723 * Determine whether the current configuration requires support for scattered 724 * receive; return 1 if scattered receive is required and 0 if not. 725 */ 726 static int bnxt_scattered_rx(struct rte_eth_dev *eth_dev) 727 { 728 uint16_t buf_size; 729 int i; 730 731 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) { 732 struct bnxt_rx_queue *rxq = eth_dev->data->rx_queues[i]; 733 734 buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mb_pool) - 735 RTE_PKTMBUF_HEADROOM); 736 if (eth_dev->data->dev_conf.rxmode.max_rx_pkt_len > buf_size) 737 return 1; 738 } 739 return 0; 740 } 741 742 static eth_rx_burst_t 743 bnxt_receive_function(__rte_unused struct rte_eth_dev *eth_dev) 744 { 745 #ifdef RTE_ARCH_X86 746 #ifndef RTE_LIBRTE_IEEE1588 747 /* 748 * Vector mode receive can be enabled only if scatter rx is not 749 * in use and rx offloads are limited to VLAN stripping and 750 * CRC stripping. 751 */ 752 if (!eth_dev->data->scattered_rx && 753 !(eth_dev->data->dev_conf.rxmode.offloads & 754 ~(DEV_RX_OFFLOAD_VLAN_STRIP | 755 DEV_RX_OFFLOAD_KEEP_CRC | 756 DEV_RX_OFFLOAD_JUMBO_FRAME | 757 DEV_RX_OFFLOAD_IPV4_CKSUM | 758 DEV_RX_OFFLOAD_UDP_CKSUM | 759 DEV_RX_OFFLOAD_TCP_CKSUM | 760 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | 761 DEV_RX_OFFLOAD_VLAN_FILTER))) { 762 PMD_DRV_LOG(INFO, "Using vector mode receive for port %d\n", 763 eth_dev->data->port_id); 764 return bnxt_recv_pkts_vec; 765 } 766 PMD_DRV_LOG(INFO, "Vector mode receive disabled for port %d\n", 767 eth_dev->data->port_id); 768 PMD_DRV_LOG(INFO, 769 "Port %d scatter: %d rx offload: %" PRIX64 "\n", 770 eth_dev->data->port_id, 771 eth_dev->data->scattered_rx, 772 eth_dev->data->dev_conf.rxmode.offloads); 773 #endif 774 #endif 775 return bnxt_recv_pkts; 776 } 777 778 static eth_tx_burst_t 779 bnxt_transmit_function(__rte_unused struct rte_eth_dev *eth_dev) 780 { 781 #ifdef RTE_ARCH_X86 782 #ifndef RTE_LIBRTE_IEEE1588 783 /* 784 * Vector mode transmit can be enabled only if not using scatter rx 785 * or tx offloads. 786 */ 787 if (!eth_dev->data->scattered_rx && 788 !eth_dev->data->dev_conf.txmode.offloads) { 789 PMD_DRV_LOG(INFO, "Using vector mode transmit for port %d\n", 790 eth_dev->data->port_id); 791 return bnxt_xmit_pkts_vec; 792 } 793 PMD_DRV_LOG(INFO, "Vector mode transmit disabled for port %d\n", 794 eth_dev->data->port_id); 795 PMD_DRV_LOG(INFO, 796 "Port %d scatter: %d tx offload: %" PRIX64 "\n", 797 eth_dev->data->port_id, 798 eth_dev->data->scattered_rx, 799 eth_dev->data->dev_conf.txmode.offloads); 800 #endif 801 #endif 802 return bnxt_xmit_pkts; 803 } 804 805 static int bnxt_handle_if_change_status(struct bnxt *bp) 806 { 807 int rc; 808 809 /* Since fw has undergone a reset and lost all contexts, 810 * set fatal flag to not issue hwrm during cleanup 811 */ 812 bp->flags |= BNXT_FLAG_FATAL_ERROR; 813 bnxt_uninit_resources(bp, true); 814 815 /* clear fatal flag so that re-init happens */ 816 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 817 rc = bnxt_init_resources(bp, true); 818 819 bp->flags &= ~BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE; 820 821 return rc; 822 } 823 824 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 825 { 826 struct bnxt *bp = eth_dev->data->dev_private; 827 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 828 int vlan_mask = 0; 829 int rc; 830 831 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 832 PMD_DRV_LOG(ERR, 833 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 834 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 835 } 836 837 bnxt_enable_int(bp); 838 rc = bnxt_hwrm_if_change(bp, 1); 839 if (!rc) { 840 if (bp->flags & BNXT_FLAG_IF_CHANGE_HOT_FW_RESET_DONE) { 841 rc = bnxt_handle_if_change_status(bp); 842 if (rc) 843 return rc; 844 } 845 } 846 847 rc = bnxt_init_chip(bp); 848 if (rc) 849 goto error; 850 851 eth_dev->data->scattered_rx = bnxt_scattered_rx(eth_dev); 852 853 bnxt_link_update_op(eth_dev, 1); 854 855 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 856 vlan_mask |= ETH_VLAN_FILTER_MASK; 857 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 858 vlan_mask |= ETH_VLAN_STRIP_MASK; 859 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 860 if (rc) 861 goto error; 862 863 eth_dev->rx_pkt_burst = bnxt_receive_function(eth_dev); 864 eth_dev->tx_pkt_burst = bnxt_transmit_function(eth_dev); 865 866 bp->flags |= BNXT_FLAG_INIT_DONE; 867 eth_dev->data->dev_started = 1; 868 bp->dev_stopped = 0; 869 bnxt_schedule_fw_health_check(bp); 870 return 0; 871 872 error: 873 bnxt_hwrm_if_change(bp, 0); 874 bnxt_shutdown_nic(bp); 875 bnxt_free_tx_mbufs(bp); 876 bnxt_free_rx_mbufs(bp); 877 return rc; 878 } 879 880 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 881 { 882 struct bnxt *bp = eth_dev->data->dev_private; 883 int rc = 0; 884 885 if (!bp->link_info.link_up) 886 rc = bnxt_set_hwrm_link_config(bp, true); 887 if (!rc) 888 eth_dev->data->dev_link.link_status = 1; 889 890 bnxt_print_link_info(eth_dev); 891 return 0; 892 } 893 894 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 895 { 896 struct bnxt *bp = eth_dev->data->dev_private; 897 898 eth_dev->data->dev_link.link_status = 0; 899 bnxt_set_hwrm_link_config(bp, false); 900 bp->link_info.link_up = 0; 901 902 return 0; 903 } 904 905 /* Unload the driver, release resources */ 906 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 907 { 908 struct bnxt *bp = eth_dev->data->dev_private; 909 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 910 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 911 912 eth_dev->data->dev_started = 0; 913 /* Prevent crashes when queues are still in use */ 914 eth_dev->rx_pkt_burst = &bnxt_dummy_recv_pkts; 915 eth_dev->tx_pkt_burst = &bnxt_dummy_xmit_pkts; 916 917 bnxt_disable_int(bp); 918 919 /* disable uio/vfio intr/eventfd mapping */ 920 rte_intr_disable(intr_handle); 921 922 bnxt_cancel_fw_health_check(bp); 923 924 bp->flags &= ~BNXT_FLAG_INIT_DONE; 925 if (bp->eth_dev->data->dev_started) { 926 /* TBD: STOP HW queues DMA */ 927 eth_dev->data->dev_link.link_status = 0; 928 } 929 bnxt_dev_set_link_down_op(eth_dev); 930 /* Wait for link to be reset and the async notification to process. */ 931 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL * 2); 932 933 /* Clean queue intr-vector mapping */ 934 rte_intr_efd_disable(intr_handle); 935 if (intr_handle->intr_vec != NULL) { 936 rte_free(intr_handle->intr_vec); 937 intr_handle->intr_vec = NULL; 938 } 939 940 bnxt_hwrm_port_clr_stats(bp); 941 bnxt_free_tx_mbufs(bp); 942 bnxt_free_rx_mbufs(bp); 943 /* Process any remaining notifications in default completion queue */ 944 bnxt_int_handler(eth_dev); 945 bnxt_shutdown_nic(bp); 946 bnxt_hwrm_if_change(bp, 0); 947 bp->dev_stopped = 1; 948 } 949 950 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 951 { 952 struct bnxt *bp = eth_dev->data->dev_private; 953 954 if (bp->dev_stopped == 0) 955 bnxt_dev_stop_op(eth_dev); 956 957 if (eth_dev->data->mac_addrs != NULL) { 958 rte_free(eth_dev->data->mac_addrs); 959 eth_dev->data->mac_addrs = NULL; 960 } 961 if (bp->grp_info != NULL) { 962 rte_free(bp->grp_info); 963 bp->grp_info = NULL; 964 } 965 966 bnxt_dev_uninit(eth_dev); 967 } 968 969 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 970 uint32_t index) 971 { 972 struct bnxt *bp = eth_dev->data->dev_private; 973 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 974 struct bnxt_vnic_info *vnic; 975 struct bnxt_filter_info *filter, *temp_filter; 976 uint32_t i; 977 978 if (is_bnxt_in_error(bp)) 979 return; 980 981 /* 982 * Loop through all VNICs from the specified filter flow pools to 983 * remove the corresponding MAC addr filter 984 */ 985 for (i = 0; i < bp->nr_vnics; i++) { 986 if (!(pool_mask & (1ULL << i))) 987 continue; 988 989 vnic = &bp->vnic_info[i]; 990 filter = STAILQ_FIRST(&vnic->filter); 991 while (filter) { 992 temp_filter = STAILQ_NEXT(filter, next); 993 if (filter->mac_index == index) { 994 STAILQ_REMOVE(&vnic->filter, filter, 995 bnxt_filter_info, next); 996 bnxt_hwrm_clear_l2_filter(bp, filter); 997 filter->mac_index = INVALID_MAC_INDEX; 998 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 999 STAILQ_INSERT_TAIL(&bp->free_filter_list, 1000 filter, next); 1001 } 1002 filter = temp_filter; 1003 } 1004 } 1005 } 1006 1007 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 1008 struct rte_ether_addr *mac_addr, 1009 uint32_t index, uint32_t pool) 1010 { 1011 struct bnxt *bp = eth_dev->data->dev_private; 1012 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 1013 struct bnxt_filter_info *filter; 1014 int rc = 0; 1015 1016 rc = is_bnxt_in_error(bp); 1017 if (rc) 1018 return rc; 1019 1020 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 1021 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 1022 return -ENOTSUP; 1023 } 1024 1025 if (!vnic) { 1026 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 1027 return -EINVAL; 1028 } 1029 /* Attach requested MAC address to the new l2_filter */ 1030 STAILQ_FOREACH(filter, &vnic->filter, next) { 1031 if (filter->mac_index == index) { 1032 PMD_DRV_LOG(ERR, 1033 "MAC addr already existed for pool %d\n", pool); 1034 return 0; 1035 } 1036 } 1037 filter = bnxt_alloc_filter(bp); 1038 if (!filter) { 1039 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 1040 return -ENODEV; 1041 } 1042 1043 filter->mac_index = index; 1044 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 1045 1046 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1047 if (!rc) { 1048 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1049 } else { 1050 filter->mac_index = INVALID_MAC_INDEX; 1051 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 1052 bnxt_free_filter(bp, filter); 1053 } 1054 1055 return rc; 1056 } 1057 1058 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 1059 { 1060 int rc = 0; 1061 struct bnxt *bp = eth_dev->data->dev_private; 1062 struct rte_eth_link new; 1063 unsigned int cnt = BNXT_LINK_WAIT_CNT; 1064 1065 rc = is_bnxt_in_error(bp); 1066 if (rc) 1067 return rc; 1068 1069 memset(&new, 0, sizeof(new)); 1070 do { 1071 /* Retrieve link info from hardware */ 1072 rc = bnxt_get_hwrm_link_config(bp, &new); 1073 if (rc) { 1074 new.link_speed = ETH_LINK_SPEED_100M; 1075 new.link_duplex = ETH_LINK_FULL_DUPLEX; 1076 PMD_DRV_LOG(ERR, 1077 "Failed to retrieve link rc = 0x%x!\n", rc); 1078 goto out; 1079 } 1080 1081 if (!wait_to_complete || new.link_status) 1082 break; 1083 1084 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 1085 } while (cnt--); 1086 1087 out: 1088 /* Timed out or success */ 1089 if (new.link_status != eth_dev->data->dev_link.link_status || 1090 new.link_speed != eth_dev->data->dev_link.link_speed) { 1091 rte_eth_linkstatus_set(eth_dev, &new); 1092 1093 _rte_eth_dev_callback_process(eth_dev, 1094 RTE_ETH_EVENT_INTR_LSC, 1095 NULL); 1096 1097 bnxt_print_link_info(eth_dev); 1098 } 1099 1100 return rc; 1101 } 1102 1103 static int bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 1104 { 1105 struct bnxt *bp = eth_dev->data->dev_private; 1106 struct bnxt_vnic_info *vnic; 1107 uint32_t old_flags; 1108 int rc; 1109 1110 rc = is_bnxt_in_error(bp); 1111 if (rc) 1112 return rc; 1113 1114 if (bp->vnic_info == NULL) 1115 return 0; 1116 1117 vnic = &bp->vnic_info[0]; 1118 1119 old_flags = vnic->flags; 1120 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 1121 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1122 if (rc != 0) 1123 vnic->flags = old_flags; 1124 1125 return rc; 1126 } 1127 1128 static int bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 1129 { 1130 struct bnxt *bp = eth_dev->data->dev_private; 1131 struct bnxt_vnic_info *vnic; 1132 uint32_t old_flags; 1133 int rc; 1134 1135 rc = is_bnxt_in_error(bp); 1136 if (rc) 1137 return rc; 1138 1139 if (bp->vnic_info == NULL) 1140 return 0; 1141 1142 vnic = &bp->vnic_info[0]; 1143 1144 old_flags = vnic->flags; 1145 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 1146 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1147 if (rc != 0) 1148 vnic->flags = old_flags; 1149 1150 return rc; 1151 } 1152 1153 static int bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 1154 { 1155 struct bnxt *bp = eth_dev->data->dev_private; 1156 struct bnxt_vnic_info *vnic; 1157 uint32_t old_flags; 1158 int rc; 1159 1160 rc = is_bnxt_in_error(bp); 1161 if (rc) 1162 return rc; 1163 1164 if (bp->vnic_info == NULL) 1165 return 0; 1166 1167 vnic = &bp->vnic_info[0]; 1168 1169 old_flags = vnic->flags; 1170 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1171 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1172 if (rc != 0) 1173 vnic->flags = old_flags; 1174 1175 return rc; 1176 } 1177 1178 static int bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 1179 { 1180 struct bnxt *bp = eth_dev->data->dev_private; 1181 struct bnxt_vnic_info *vnic; 1182 uint32_t old_flags; 1183 int rc; 1184 1185 rc = is_bnxt_in_error(bp); 1186 if (rc) 1187 return rc; 1188 1189 if (bp->vnic_info == NULL) 1190 return 0; 1191 1192 vnic = &bp->vnic_info[0]; 1193 1194 old_flags = vnic->flags; 1195 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1196 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1197 if (rc != 0) 1198 vnic->flags = old_flags; 1199 1200 return rc; 1201 } 1202 1203 /* Return bnxt_rx_queue pointer corresponding to a given rxq. */ 1204 static struct bnxt_rx_queue *bnxt_qid_to_rxq(struct bnxt *bp, uint16_t qid) 1205 { 1206 if (qid >= bp->rx_nr_rings) 1207 return NULL; 1208 1209 return bp->eth_dev->data->rx_queues[qid]; 1210 } 1211 1212 /* Return rxq corresponding to a given rss table ring/group ID. */ 1213 static uint16_t bnxt_rss_to_qid(struct bnxt *bp, uint16_t fwr) 1214 { 1215 struct bnxt_rx_queue *rxq; 1216 unsigned int i; 1217 1218 if (!BNXT_HAS_RING_GRPS(bp)) { 1219 for (i = 0; i < bp->rx_nr_rings; i++) { 1220 rxq = bp->eth_dev->data->rx_queues[i]; 1221 if (rxq->rx_ring->rx_ring_struct->fw_ring_id == fwr) 1222 return rxq->index; 1223 } 1224 } else { 1225 for (i = 0; i < bp->rx_nr_rings; i++) { 1226 if (bp->grp_info[i].fw_grp_id == fwr) 1227 return i; 1228 } 1229 } 1230 1231 return INVALID_HW_RING_ID; 1232 } 1233 1234 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 1235 struct rte_eth_rss_reta_entry64 *reta_conf, 1236 uint16_t reta_size) 1237 { 1238 struct bnxt *bp = eth_dev->data->dev_private; 1239 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1240 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1241 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1242 uint16_t idx, sft; 1243 int i, rc; 1244 1245 rc = is_bnxt_in_error(bp); 1246 if (rc) 1247 return rc; 1248 1249 if (!vnic->rss_table) 1250 return -EINVAL; 1251 1252 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 1253 return -EINVAL; 1254 1255 if (reta_size != tbl_size) { 1256 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1257 "(%d) must equal the size supported by the hardware " 1258 "(%d)\n", reta_size, tbl_size); 1259 return -EINVAL; 1260 } 1261 1262 for (i = 0; i < reta_size; i++) { 1263 struct bnxt_rx_queue *rxq; 1264 1265 idx = i / RTE_RETA_GROUP_SIZE; 1266 sft = i % RTE_RETA_GROUP_SIZE; 1267 1268 if (!(reta_conf[idx].mask & (1ULL << sft))) 1269 continue; 1270 1271 rxq = bnxt_qid_to_rxq(bp, reta_conf[idx].reta[sft]); 1272 if (!rxq) { 1273 PMD_DRV_LOG(ERR, "Invalid ring in reta_conf.\n"); 1274 return -EINVAL; 1275 } 1276 1277 if (BNXT_CHIP_THOR(bp)) { 1278 vnic->rss_table[i * 2] = 1279 rxq->rx_ring->rx_ring_struct->fw_ring_id; 1280 vnic->rss_table[i * 2 + 1] = 1281 rxq->cp_ring->cp_ring_struct->fw_ring_id; 1282 } else { 1283 vnic->rss_table[i] = 1284 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1285 } 1286 1287 vnic->rss_table[i] = 1288 vnic->fw_grp_ids[reta_conf[idx].reta[sft]]; 1289 } 1290 1291 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1292 return 0; 1293 } 1294 1295 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 1296 struct rte_eth_rss_reta_entry64 *reta_conf, 1297 uint16_t reta_size) 1298 { 1299 struct bnxt *bp = eth_dev->data->dev_private; 1300 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1301 uint16_t tbl_size = bnxt_rss_hash_tbl_size(bp); 1302 uint16_t idx, sft, i; 1303 int rc; 1304 1305 rc = is_bnxt_in_error(bp); 1306 if (rc) 1307 return rc; 1308 1309 /* Retrieve from the default VNIC */ 1310 if (!vnic) 1311 return -EINVAL; 1312 if (!vnic->rss_table) 1313 return -EINVAL; 1314 1315 if (reta_size != tbl_size) { 1316 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 1317 "(%d) must equal the size supported by the hardware " 1318 "(%d)\n", reta_size, tbl_size); 1319 return -EINVAL; 1320 } 1321 1322 for (idx = 0, i = 0; i < reta_size; i++) { 1323 idx = i / RTE_RETA_GROUP_SIZE; 1324 sft = i % RTE_RETA_GROUP_SIZE; 1325 1326 if (reta_conf[idx].mask & (1ULL << sft)) { 1327 uint16_t qid; 1328 1329 if (BNXT_CHIP_THOR(bp)) 1330 qid = bnxt_rss_to_qid(bp, 1331 vnic->rss_table[i * 2]); 1332 else 1333 qid = bnxt_rss_to_qid(bp, vnic->rss_table[i]); 1334 1335 if (qid == INVALID_HW_RING_ID) { 1336 PMD_DRV_LOG(ERR, "Inv. entry in rss table.\n"); 1337 return -EINVAL; 1338 } 1339 reta_conf[idx].reta[sft] = qid; 1340 } 1341 } 1342 1343 return 0; 1344 } 1345 1346 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 1347 struct rte_eth_rss_conf *rss_conf) 1348 { 1349 struct bnxt *bp = eth_dev->data->dev_private; 1350 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 1351 struct bnxt_vnic_info *vnic; 1352 uint16_t hash_type = 0; 1353 unsigned int i; 1354 int rc; 1355 1356 rc = is_bnxt_in_error(bp); 1357 if (rc) 1358 return rc; 1359 1360 /* 1361 * If RSS enablement were different than dev_configure, 1362 * then return -EINVAL 1363 */ 1364 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 1365 if (!rss_conf->rss_hf) 1366 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 1367 } else { 1368 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 1369 return -EINVAL; 1370 } 1371 1372 bp->flags |= BNXT_FLAG_UPDATE_HASH; 1373 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 1374 1375 if (rss_conf->rss_hf & ETH_RSS_IPV4) 1376 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1377 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 1378 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1379 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 1380 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1381 if (rss_conf->rss_hf & ETH_RSS_IPV6) 1382 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1383 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 1384 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1385 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 1386 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1387 1388 /* Update the RSS VNIC(s) */ 1389 for (i = 0; i < bp->nr_vnics; i++) { 1390 vnic = &bp->vnic_info[i]; 1391 vnic->hash_type = hash_type; 1392 1393 /* 1394 * Use the supplied key if the key length is 1395 * acceptable and the rss_key is not NULL 1396 */ 1397 if (rss_conf->rss_key && 1398 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 1399 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 1400 rss_conf->rss_key_len); 1401 1402 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1403 } 1404 return 0; 1405 } 1406 1407 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1408 struct rte_eth_rss_conf *rss_conf) 1409 { 1410 struct bnxt *bp = eth_dev->data->dev_private; 1411 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1412 int len, rc; 1413 uint32_t hash_types; 1414 1415 rc = is_bnxt_in_error(bp); 1416 if (rc) 1417 return rc; 1418 1419 /* RSS configuration is the same for all VNICs */ 1420 if (vnic && vnic->rss_hash_key) { 1421 if (rss_conf->rss_key) { 1422 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1423 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1424 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1425 } 1426 1427 hash_types = vnic->hash_type; 1428 rss_conf->rss_hf = 0; 1429 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1430 rss_conf->rss_hf |= ETH_RSS_IPV4; 1431 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1432 } 1433 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1434 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1435 hash_types &= 1436 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1437 } 1438 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1439 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1440 hash_types &= 1441 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1442 } 1443 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1444 rss_conf->rss_hf |= ETH_RSS_IPV6; 1445 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1446 } 1447 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1448 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1449 hash_types &= 1450 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1451 } 1452 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1453 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1454 hash_types &= 1455 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1456 } 1457 if (hash_types) { 1458 PMD_DRV_LOG(ERR, 1459 "Unknwon RSS config from firmware (%08x), RSS disabled", 1460 vnic->hash_type); 1461 return -ENOTSUP; 1462 } 1463 } else { 1464 rss_conf->rss_hf = 0; 1465 } 1466 return 0; 1467 } 1468 1469 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1470 struct rte_eth_fc_conf *fc_conf) 1471 { 1472 struct bnxt *bp = dev->data->dev_private; 1473 struct rte_eth_link link_info; 1474 int rc; 1475 1476 rc = is_bnxt_in_error(bp); 1477 if (rc) 1478 return rc; 1479 1480 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1481 if (rc) 1482 return rc; 1483 1484 memset(fc_conf, 0, sizeof(*fc_conf)); 1485 if (bp->link_info.auto_pause) 1486 fc_conf->autoneg = 1; 1487 switch (bp->link_info.pause) { 1488 case 0: 1489 fc_conf->mode = RTE_FC_NONE; 1490 break; 1491 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1492 fc_conf->mode = RTE_FC_TX_PAUSE; 1493 break; 1494 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1495 fc_conf->mode = RTE_FC_RX_PAUSE; 1496 break; 1497 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1498 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1499 fc_conf->mode = RTE_FC_FULL; 1500 break; 1501 } 1502 return 0; 1503 } 1504 1505 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1506 struct rte_eth_fc_conf *fc_conf) 1507 { 1508 struct bnxt *bp = dev->data->dev_private; 1509 int rc; 1510 1511 rc = is_bnxt_in_error(bp); 1512 if (rc) 1513 return rc; 1514 1515 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1516 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1517 return -ENOTSUP; 1518 } 1519 1520 switch (fc_conf->mode) { 1521 case RTE_FC_NONE: 1522 bp->link_info.auto_pause = 0; 1523 bp->link_info.force_pause = 0; 1524 break; 1525 case RTE_FC_RX_PAUSE: 1526 if (fc_conf->autoneg) { 1527 bp->link_info.auto_pause = 1528 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1529 bp->link_info.force_pause = 0; 1530 } else { 1531 bp->link_info.auto_pause = 0; 1532 bp->link_info.force_pause = 1533 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1534 } 1535 break; 1536 case RTE_FC_TX_PAUSE: 1537 if (fc_conf->autoneg) { 1538 bp->link_info.auto_pause = 1539 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1540 bp->link_info.force_pause = 0; 1541 } else { 1542 bp->link_info.auto_pause = 0; 1543 bp->link_info.force_pause = 1544 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1545 } 1546 break; 1547 case RTE_FC_FULL: 1548 if (fc_conf->autoneg) { 1549 bp->link_info.auto_pause = 1550 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1551 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1552 bp->link_info.force_pause = 0; 1553 } else { 1554 bp->link_info.auto_pause = 0; 1555 bp->link_info.force_pause = 1556 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1557 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1558 } 1559 break; 1560 } 1561 return bnxt_set_hwrm_link_config(bp, true); 1562 } 1563 1564 /* Add UDP tunneling port */ 1565 static int 1566 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1567 struct rte_eth_udp_tunnel *udp_tunnel) 1568 { 1569 struct bnxt *bp = eth_dev->data->dev_private; 1570 uint16_t tunnel_type = 0; 1571 int rc = 0; 1572 1573 rc = is_bnxt_in_error(bp); 1574 if (rc) 1575 return rc; 1576 1577 switch (udp_tunnel->prot_type) { 1578 case RTE_TUNNEL_TYPE_VXLAN: 1579 if (bp->vxlan_port_cnt) { 1580 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1581 udp_tunnel->udp_port); 1582 if (bp->vxlan_port != udp_tunnel->udp_port) { 1583 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1584 return -ENOSPC; 1585 } 1586 bp->vxlan_port_cnt++; 1587 return 0; 1588 } 1589 tunnel_type = 1590 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1591 bp->vxlan_port_cnt++; 1592 break; 1593 case RTE_TUNNEL_TYPE_GENEVE: 1594 if (bp->geneve_port_cnt) { 1595 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1596 udp_tunnel->udp_port); 1597 if (bp->geneve_port != udp_tunnel->udp_port) { 1598 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1599 return -ENOSPC; 1600 } 1601 bp->geneve_port_cnt++; 1602 return 0; 1603 } 1604 tunnel_type = 1605 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1606 bp->geneve_port_cnt++; 1607 break; 1608 default: 1609 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1610 return -ENOTSUP; 1611 } 1612 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1613 tunnel_type); 1614 return rc; 1615 } 1616 1617 static int 1618 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1619 struct rte_eth_udp_tunnel *udp_tunnel) 1620 { 1621 struct bnxt *bp = eth_dev->data->dev_private; 1622 uint16_t tunnel_type = 0; 1623 uint16_t port = 0; 1624 int rc = 0; 1625 1626 rc = is_bnxt_in_error(bp); 1627 if (rc) 1628 return rc; 1629 1630 switch (udp_tunnel->prot_type) { 1631 case RTE_TUNNEL_TYPE_VXLAN: 1632 if (!bp->vxlan_port_cnt) { 1633 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1634 return -EINVAL; 1635 } 1636 if (bp->vxlan_port != udp_tunnel->udp_port) { 1637 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1638 udp_tunnel->udp_port, bp->vxlan_port); 1639 return -EINVAL; 1640 } 1641 if (--bp->vxlan_port_cnt) 1642 return 0; 1643 1644 tunnel_type = 1645 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1646 port = bp->vxlan_fw_dst_port_id; 1647 break; 1648 case RTE_TUNNEL_TYPE_GENEVE: 1649 if (!bp->geneve_port_cnt) { 1650 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1651 return -EINVAL; 1652 } 1653 if (bp->geneve_port != udp_tunnel->udp_port) { 1654 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1655 udp_tunnel->udp_port, bp->geneve_port); 1656 return -EINVAL; 1657 } 1658 if (--bp->geneve_port_cnt) 1659 return 0; 1660 1661 tunnel_type = 1662 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1663 port = bp->geneve_fw_dst_port_id; 1664 break; 1665 default: 1666 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1667 return -ENOTSUP; 1668 } 1669 1670 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1671 if (!rc) { 1672 if (tunnel_type == 1673 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1674 bp->vxlan_port = 0; 1675 if (tunnel_type == 1676 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1677 bp->geneve_port = 0; 1678 } 1679 return rc; 1680 } 1681 1682 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1683 { 1684 struct bnxt_filter_info *filter; 1685 struct bnxt_vnic_info *vnic; 1686 int rc = 0; 1687 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1688 1689 /* if VLAN exists && VLAN matches vlan_id 1690 * remove the MAC+VLAN filter 1691 * add a new MAC only filter 1692 * else 1693 * VLAN filter doesn't exist, just skip and continue 1694 */ 1695 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1696 filter = STAILQ_FIRST(&vnic->filter); 1697 while (filter) { 1698 /* Search for this matching MAC+VLAN filter */ 1699 if (filter->enables & chk && filter->l2_ivlan == vlan_id && 1700 !memcmp(filter->l2_addr, 1701 bp->mac_addr, 1702 RTE_ETHER_ADDR_LEN)) { 1703 /* Delete the filter */ 1704 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1705 if (rc) 1706 return rc; 1707 STAILQ_REMOVE(&vnic->filter, filter, 1708 bnxt_filter_info, next); 1709 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next); 1710 1711 PMD_DRV_LOG(INFO, 1712 "Del Vlan filter for %d\n", 1713 vlan_id); 1714 return rc; 1715 } 1716 filter = STAILQ_NEXT(filter, next); 1717 } 1718 return -ENOENT; 1719 } 1720 1721 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1722 { 1723 struct bnxt_filter_info *filter; 1724 struct bnxt_vnic_info *vnic; 1725 int rc = 0; 1726 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1727 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1728 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1729 1730 /* Implementation notes on the use of VNIC in this command: 1731 * 1732 * By default, these filters belong to default vnic for the function. 1733 * Once these filters are set up, only destination VNIC can be modified. 1734 * If the destination VNIC is not specified in this command, 1735 * then the HWRM shall only create an l2 context id. 1736 */ 1737 1738 vnic = BNXT_GET_DEFAULT_VNIC(bp); 1739 filter = STAILQ_FIRST(&vnic->filter); 1740 /* Check if the VLAN has already been added */ 1741 while (filter) { 1742 if (filter->enables & chk && filter->l2_ivlan == vlan_id && 1743 !memcmp(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN)) 1744 return -EEXIST; 1745 1746 filter = STAILQ_NEXT(filter, next); 1747 } 1748 1749 /* No match found. Alloc a fresh filter and issue the L2_FILTER_ALLOC 1750 * command to create MAC+VLAN filter with the right flags, enables set. 1751 */ 1752 filter = bnxt_alloc_filter(bp); 1753 if (!filter) { 1754 PMD_DRV_LOG(ERR, 1755 "MAC/VLAN filter alloc failed\n"); 1756 return -ENOMEM; 1757 } 1758 /* MAC + VLAN ID filter */ 1759 filter->l2_ivlan = vlan_id; 1760 filter->l2_ivlan_mask = 0x0FFF; 1761 filter->enables |= en; 1762 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1763 if (rc) { 1764 /* Free the newly allocated filter as we were 1765 * not able to create the filter in hardware. 1766 */ 1767 filter->fw_l2_filter_id = UINT64_MAX; 1768 STAILQ_INSERT_TAIL(&bp->free_filter_list, filter, next); 1769 return rc; 1770 } 1771 1772 /* Add this new filter to the list */ 1773 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 1774 PMD_DRV_LOG(INFO, 1775 "Added Vlan filter for %d\n", vlan_id); 1776 return rc; 1777 } 1778 1779 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1780 uint16_t vlan_id, int on) 1781 { 1782 struct bnxt *bp = eth_dev->data->dev_private; 1783 int rc; 1784 1785 rc = is_bnxt_in_error(bp); 1786 if (rc) 1787 return rc; 1788 1789 /* These operations apply to ALL existing MAC/VLAN filters */ 1790 if (on) 1791 return bnxt_add_vlan_filter(bp, vlan_id); 1792 else 1793 return bnxt_del_vlan_filter(bp, vlan_id); 1794 } 1795 1796 static int 1797 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1798 { 1799 struct bnxt *bp = dev->data->dev_private; 1800 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1801 unsigned int i; 1802 int rc; 1803 1804 rc = is_bnxt_in_error(bp); 1805 if (rc) 1806 return rc; 1807 1808 if (mask & ETH_VLAN_FILTER_MASK) { 1809 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1810 /* Remove any VLAN filters programmed */ 1811 for (i = 0; i < 4095; i++) 1812 bnxt_del_vlan_filter(bp, i); 1813 } 1814 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1815 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1816 } 1817 1818 if (mask & ETH_VLAN_STRIP_MASK) { 1819 /* Enable or disable VLAN stripping */ 1820 for (i = 0; i < bp->nr_vnics; i++) { 1821 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1822 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1823 vnic->vlan_strip = true; 1824 else 1825 vnic->vlan_strip = false; 1826 bnxt_hwrm_vnic_cfg(bp, vnic); 1827 } 1828 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1829 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1830 } 1831 1832 if (mask & ETH_VLAN_EXTEND_MASK) 1833 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n"); 1834 1835 return 0; 1836 } 1837 1838 static int 1839 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 1840 struct rte_ether_addr *addr) 1841 { 1842 struct bnxt *bp = dev->data->dev_private; 1843 /* Default Filter is tied to VNIC 0 */ 1844 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1845 struct bnxt_filter_info *filter; 1846 int rc; 1847 1848 rc = is_bnxt_in_error(bp); 1849 if (rc) 1850 return rc; 1851 1852 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 1853 return -EPERM; 1854 1855 if (rte_is_zero_ether_addr(addr)) 1856 return -EINVAL; 1857 1858 STAILQ_FOREACH(filter, &vnic->filter, next) { 1859 /* Default Filter is at Index 0 */ 1860 if (filter->mac_index != 0) 1861 continue; 1862 1863 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN); 1864 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN); 1865 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX; 1866 filter->enables |= 1867 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 1868 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 1869 1870 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1871 if (rc) 1872 return rc; 1873 1874 memcpy(bp->mac_addr, addr, RTE_ETHER_ADDR_LEN); 1875 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 1876 return 0; 1877 } 1878 1879 return 0; 1880 } 1881 1882 static int 1883 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 1884 struct rte_ether_addr *mc_addr_set, 1885 uint32_t nb_mc_addr) 1886 { 1887 struct bnxt *bp = eth_dev->data->dev_private; 1888 char *mc_addr_list = (char *)mc_addr_set; 1889 struct bnxt_vnic_info *vnic; 1890 uint32_t off = 0, i = 0; 1891 int rc; 1892 1893 rc = is_bnxt_in_error(bp); 1894 if (rc) 1895 return rc; 1896 1897 vnic = &bp->vnic_info[0]; 1898 1899 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 1900 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1901 goto allmulti; 1902 } 1903 1904 /* TODO Check for Duplicate mcast addresses */ 1905 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1906 for (i = 0; i < nb_mc_addr; i++) { 1907 memcpy(vnic->mc_list + off, &mc_addr_list[i], 1908 RTE_ETHER_ADDR_LEN); 1909 off += RTE_ETHER_ADDR_LEN; 1910 } 1911 1912 vnic->mc_addr_cnt = i; 1913 1914 allmulti: 1915 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1916 } 1917 1918 static int 1919 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 1920 { 1921 struct bnxt *bp = dev->data->dev_private; 1922 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 1923 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 1924 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 1925 int ret; 1926 1927 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 1928 fw_major, fw_minor, fw_updt); 1929 1930 ret += 1; /* add the size of '\0' */ 1931 if (fw_size < (uint32_t)ret) 1932 return ret; 1933 else 1934 return 0; 1935 } 1936 1937 static void 1938 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1939 struct rte_eth_rxq_info *qinfo) 1940 { 1941 struct bnxt_rx_queue *rxq; 1942 1943 rxq = dev->data->rx_queues[queue_id]; 1944 1945 qinfo->mp = rxq->mb_pool; 1946 qinfo->scattered_rx = dev->data->scattered_rx; 1947 qinfo->nb_desc = rxq->nb_rx_desc; 1948 1949 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 1950 qinfo->conf.rx_drop_en = 0; 1951 qinfo->conf.rx_deferred_start = rxq->rx_deferred_start; 1952 } 1953 1954 static void 1955 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1956 struct rte_eth_txq_info *qinfo) 1957 { 1958 struct bnxt_tx_queue *txq; 1959 1960 txq = dev->data->tx_queues[queue_id]; 1961 1962 qinfo->nb_desc = txq->nb_tx_desc; 1963 1964 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 1965 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 1966 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 1967 1968 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 1969 qinfo->conf.tx_rs_thresh = 0; 1970 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1971 } 1972 1973 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 1974 { 1975 struct bnxt *bp = eth_dev->data->dev_private; 1976 uint32_t new_pkt_size; 1977 uint32_t rc = 0; 1978 uint32_t i; 1979 1980 rc = is_bnxt_in_error(bp); 1981 if (rc) 1982 return rc; 1983 1984 new_pkt_size = new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 1985 VLAN_TAG_SIZE * BNXT_NUM_VLANS; 1986 1987 #ifdef RTE_ARCH_X86 1988 /* 1989 * If vector-mode tx/rx is active, disallow any MTU change that would 1990 * require scattered receive support. 1991 */ 1992 if (eth_dev->data->dev_started && 1993 (eth_dev->rx_pkt_burst == bnxt_recv_pkts_vec || 1994 eth_dev->tx_pkt_burst == bnxt_xmit_pkts_vec) && 1995 (new_pkt_size > 1996 eth_dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM)) { 1997 PMD_DRV_LOG(ERR, 1998 "MTU change would require scattered rx support. "); 1999 PMD_DRV_LOG(ERR, "Stop port before changing MTU.\n"); 2000 return -EINVAL; 2001 } 2002 #endif 2003 2004 if (new_mtu > RTE_ETHER_MTU) { 2005 bp->flags |= BNXT_FLAG_JUMBO; 2006 bp->eth_dev->data->dev_conf.rxmode.offloads |= 2007 DEV_RX_OFFLOAD_JUMBO_FRAME; 2008 } else { 2009 bp->eth_dev->data->dev_conf.rxmode.offloads &= 2010 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 2011 bp->flags &= ~BNXT_FLAG_JUMBO; 2012 } 2013 2014 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = new_pkt_size; 2015 2016 for (i = 0; i < bp->nr_vnics; i++) { 2017 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2018 uint16_t size = 0; 2019 2020 vnic->mru = new_mtu + RTE_ETHER_HDR_LEN + 2021 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 2022 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 2023 if (rc) 2024 break; 2025 2026 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 2027 size -= RTE_PKTMBUF_HEADROOM; 2028 2029 if (size < new_mtu) { 2030 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 2031 if (rc) 2032 return rc; 2033 } 2034 } 2035 2036 PMD_DRV_LOG(INFO, "New MTU is %d\n", new_mtu); 2037 2038 return rc; 2039 } 2040 2041 static int 2042 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 2043 { 2044 struct bnxt *bp = dev->data->dev_private; 2045 uint16_t vlan = bp->vlan; 2046 int rc; 2047 2048 rc = is_bnxt_in_error(bp); 2049 if (rc) 2050 return rc; 2051 2052 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 2053 PMD_DRV_LOG(ERR, 2054 "PVID cannot be modified for this function\n"); 2055 return -ENOTSUP; 2056 } 2057 bp->vlan = on ? pvid : 0; 2058 2059 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 2060 if (rc) 2061 bp->vlan = vlan; 2062 return rc; 2063 } 2064 2065 static int 2066 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 2067 { 2068 struct bnxt *bp = dev->data->dev_private; 2069 int rc; 2070 2071 rc = is_bnxt_in_error(bp); 2072 if (rc) 2073 return rc; 2074 2075 return bnxt_hwrm_port_led_cfg(bp, true); 2076 } 2077 2078 static int 2079 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 2080 { 2081 struct bnxt *bp = dev->data->dev_private; 2082 int rc; 2083 2084 rc = is_bnxt_in_error(bp); 2085 if (rc) 2086 return rc; 2087 2088 return bnxt_hwrm_port_led_cfg(bp, false); 2089 } 2090 2091 static uint32_t 2092 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 2093 { 2094 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2095 uint32_t desc = 0, raw_cons = 0, cons; 2096 struct bnxt_cp_ring_info *cpr; 2097 struct bnxt_rx_queue *rxq; 2098 struct rx_pkt_cmpl *rxcmp; 2099 int rc; 2100 2101 rc = is_bnxt_in_error(bp); 2102 if (rc) 2103 return rc; 2104 2105 rxq = dev->data->rx_queues[rx_queue_id]; 2106 cpr = rxq->cp_ring; 2107 raw_cons = cpr->cp_raw_cons; 2108 2109 while (1) { 2110 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 2111 rte_prefetch0(&cpr->cp_desc_ring[cons]); 2112 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2113 2114 if (!CMP_VALID(rxcmp, raw_cons, cpr->cp_ring_struct)) { 2115 break; 2116 } else { 2117 raw_cons++; 2118 desc++; 2119 } 2120 } 2121 2122 return desc; 2123 } 2124 2125 static int 2126 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 2127 { 2128 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 2129 struct bnxt_rx_ring_info *rxr; 2130 struct bnxt_cp_ring_info *cpr; 2131 struct bnxt_sw_rx_bd *rx_buf; 2132 struct rx_pkt_cmpl *rxcmp; 2133 uint32_t cons, cp_cons; 2134 int rc; 2135 2136 if (!rxq) 2137 return -EINVAL; 2138 2139 rc = is_bnxt_in_error(rxq->bp); 2140 if (rc) 2141 return rc; 2142 2143 cpr = rxq->cp_ring; 2144 rxr = rxq->rx_ring; 2145 2146 if (offset >= rxq->nb_rx_desc) 2147 return -EINVAL; 2148 2149 cons = RING_CMP(cpr->cp_ring_struct, offset); 2150 cp_cons = cpr->cp_raw_cons; 2151 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2152 2153 if (cons > cp_cons) { 2154 if (CMPL_VALID(rxcmp, cpr->valid)) 2155 return RTE_ETH_RX_DESC_DONE; 2156 } else { 2157 if (CMPL_VALID(rxcmp, !cpr->valid)) 2158 return RTE_ETH_RX_DESC_DONE; 2159 } 2160 rx_buf = &rxr->rx_buf_ring[cons]; 2161 if (rx_buf->mbuf == NULL) 2162 return RTE_ETH_RX_DESC_UNAVAIL; 2163 2164 2165 return RTE_ETH_RX_DESC_AVAIL; 2166 } 2167 2168 static int 2169 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 2170 { 2171 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 2172 struct bnxt_tx_ring_info *txr; 2173 struct bnxt_cp_ring_info *cpr; 2174 struct bnxt_sw_tx_bd *tx_buf; 2175 struct tx_pkt_cmpl *txcmp; 2176 uint32_t cons, cp_cons; 2177 int rc; 2178 2179 if (!txq) 2180 return -EINVAL; 2181 2182 rc = is_bnxt_in_error(txq->bp); 2183 if (rc) 2184 return rc; 2185 2186 cpr = txq->cp_ring; 2187 txr = txq->tx_ring; 2188 2189 if (offset >= txq->nb_tx_desc) 2190 return -EINVAL; 2191 2192 cons = RING_CMP(cpr->cp_ring_struct, offset); 2193 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 2194 cp_cons = cpr->cp_raw_cons; 2195 2196 if (cons > cp_cons) { 2197 if (CMPL_VALID(txcmp, cpr->valid)) 2198 return RTE_ETH_TX_DESC_UNAVAIL; 2199 } else { 2200 if (CMPL_VALID(txcmp, !cpr->valid)) 2201 return RTE_ETH_TX_DESC_UNAVAIL; 2202 } 2203 tx_buf = &txr->tx_buf_ring[cons]; 2204 if (tx_buf->mbuf == NULL) 2205 return RTE_ETH_TX_DESC_DONE; 2206 2207 return RTE_ETH_TX_DESC_FULL; 2208 } 2209 2210 static struct bnxt_filter_info * 2211 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 2212 struct rte_eth_ethertype_filter *efilter, 2213 struct bnxt_vnic_info *vnic0, 2214 struct bnxt_vnic_info *vnic, 2215 int *ret) 2216 { 2217 struct bnxt_filter_info *mfilter = NULL; 2218 int match = 0; 2219 *ret = 0; 2220 2221 if (efilter->ether_type == RTE_ETHER_TYPE_IPV4 || 2222 efilter->ether_type == RTE_ETHER_TYPE_IPV6) { 2223 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 2224 " ethertype filter.", efilter->ether_type); 2225 *ret = -EINVAL; 2226 goto exit; 2227 } 2228 if (efilter->queue >= bp->rx_nr_rings) { 2229 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2230 *ret = -EINVAL; 2231 goto exit; 2232 } 2233 2234 vnic0 = &bp->vnic_info[0]; 2235 vnic = &bp->vnic_info[efilter->queue]; 2236 if (vnic == NULL) { 2237 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 2238 *ret = -EINVAL; 2239 goto exit; 2240 } 2241 2242 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2243 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 2244 if ((!memcmp(efilter->mac_addr.addr_bytes, 2245 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2246 mfilter->flags == 2247 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 2248 mfilter->ethertype == efilter->ether_type)) { 2249 match = 1; 2250 break; 2251 } 2252 } 2253 } else { 2254 STAILQ_FOREACH(mfilter, &vnic->filter, next) 2255 if ((!memcmp(efilter->mac_addr.addr_bytes, 2256 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 2257 mfilter->ethertype == efilter->ether_type && 2258 mfilter->flags == 2259 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 2260 match = 1; 2261 break; 2262 } 2263 } 2264 2265 if (match) 2266 *ret = -EEXIST; 2267 2268 exit: 2269 return mfilter; 2270 } 2271 2272 static int 2273 bnxt_ethertype_filter(struct rte_eth_dev *dev, 2274 enum rte_filter_op filter_op, 2275 void *arg) 2276 { 2277 struct bnxt *bp = dev->data->dev_private; 2278 struct rte_eth_ethertype_filter *efilter = 2279 (struct rte_eth_ethertype_filter *)arg; 2280 struct bnxt_filter_info *bfilter, *filter1; 2281 struct bnxt_vnic_info *vnic, *vnic0; 2282 int ret; 2283 2284 if (filter_op == RTE_ETH_FILTER_NOP) 2285 return 0; 2286 2287 if (arg == NULL) { 2288 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2289 filter_op); 2290 return -EINVAL; 2291 } 2292 2293 vnic0 = &bp->vnic_info[0]; 2294 vnic = &bp->vnic_info[efilter->queue]; 2295 2296 switch (filter_op) { 2297 case RTE_ETH_FILTER_ADD: 2298 bnxt_match_and_validate_ether_filter(bp, efilter, 2299 vnic0, vnic, &ret); 2300 if (ret < 0) 2301 return ret; 2302 2303 bfilter = bnxt_get_unused_filter(bp); 2304 if (bfilter == NULL) { 2305 PMD_DRV_LOG(ERR, 2306 "Not enough resources for a new filter.\n"); 2307 return -ENOMEM; 2308 } 2309 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2310 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 2311 RTE_ETHER_ADDR_LEN); 2312 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 2313 RTE_ETHER_ADDR_LEN); 2314 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2315 bfilter->ethertype = efilter->ether_type; 2316 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2317 2318 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 2319 if (filter1 == NULL) { 2320 ret = -EINVAL; 2321 goto cleanup; 2322 } 2323 bfilter->enables |= 2324 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2325 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2326 2327 bfilter->dst_id = vnic->fw_vnic_id; 2328 2329 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 2330 bfilter->flags = 2331 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2332 } 2333 2334 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2335 if (ret) 2336 goto cleanup; 2337 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2338 break; 2339 case RTE_ETH_FILTER_DELETE: 2340 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 2341 vnic0, vnic, &ret); 2342 if (ret == -EEXIST) { 2343 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 2344 2345 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 2346 next); 2347 bnxt_free_filter(bp, filter1); 2348 } else if (ret == 0) { 2349 PMD_DRV_LOG(ERR, "No matching filter found\n"); 2350 } 2351 break; 2352 default: 2353 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2354 ret = -EINVAL; 2355 goto error; 2356 } 2357 return ret; 2358 cleanup: 2359 bnxt_free_filter(bp, bfilter); 2360 error: 2361 return ret; 2362 } 2363 2364 static inline int 2365 parse_ntuple_filter(struct bnxt *bp, 2366 struct rte_eth_ntuple_filter *nfilter, 2367 struct bnxt_filter_info *bfilter) 2368 { 2369 uint32_t en = 0; 2370 2371 if (nfilter->queue >= bp->rx_nr_rings) { 2372 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 2373 return -EINVAL; 2374 } 2375 2376 switch (nfilter->dst_port_mask) { 2377 case UINT16_MAX: 2378 bfilter->dst_port_mask = -1; 2379 bfilter->dst_port = nfilter->dst_port; 2380 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 2381 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2382 break; 2383 default: 2384 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 2385 return -EINVAL; 2386 } 2387 2388 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2389 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2390 2391 switch (nfilter->proto_mask) { 2392 case UINT8_MAX: 2393 if (nfilter->proto == 17) /* IPPROTO_UDP */ 2394 bfilter->ip_protocol = 17; 2395 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 2396 bfilter->ip_protocol = 6; 2397 else 2398 return -EINVAL; 2399 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2400 break; 2401 default: 2402 PMD_DRV_LOG(ERR, "invalid protocol mask."); 2403 return -EINVAL; 2404 } 2405 2406 switch (nfilter->dst_ip_mask) { 2407 case UINT32_MAX: 2408 bfilter->dst_ipaddr_mask[0] = -1; 2409 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 2410 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 2411 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2412 break; 2413 default: 2414 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 2415 return -EINVAL; 2416 } 2417 2418 switch (nfilter->src_ip_mask) { 2419 case UINT32_MAX: 2420 bfilter->src_ipaddr_mask[0] = -1; 2421 bfilter->src_ipaddr[0] = nfilter->src_ip; 2422 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 2423 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2424 break; 2425 default: 2426 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2427 return -EINVAL; 2428 } 2429 2430 switch (nfilter->src_port_mask) { 2431 case UINT16_MAX: 2432 bfilter->src_port_mask = -1; 2433 bfilter->src_port = nfilter->src_port; 2434 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2435 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2436 break; 2437 default: 2438 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2439 return -EINVAL; 2440 } 2441 2442 //TODO Priority 2443 //nfilter->priority = (uint8_t)filter->priority; 2444 2445 bfilter->enables = en; 2446 return 0; 2447 } 2448 2449 static struct bnxt_filter_info* 2450 bnxt_match_ntuple_filter(struct bnxt *bp, 2451 struct bnxt_filter_info *bfilter, 2452 struct bnxt_vnic_info **mvnic) 2453 { 2454 struct bnxt_filter_info *mfilter = NULL; 2455 int i; 2456 2457 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2458 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2459 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2460 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2461 bfilter->src_ipaddr_mask[0] == 2462 mfilter->src_ipaddr_mask[0] && 2463 bfilter->src_port == mfilter->src_port && 2464 bfilter->src_port_mask == mfilter->src_port_mask && 2465 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2466 bfilter->dst_ipaddr_mask[0] == 2467 mfilter->dst_ipaddr_mask[0] && 2468 bfilter->dst_port == mfilter->dst_port && 2469 bfilter->dst_port_mask == mfilter->dst_port_mask && 2470 bfilter->flags == mfilter->flags && 2471 bfilter->enables == mfilter->enables) { 2472 if (mvnic) 2473 *mvnic = vnic; 2474 return mfilter; 2475 } 2476 } 2477 } 2478 return NULL; 2479 } 2480 2481 static int 2482 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2483 struct rte_eth_ntuple_filter *nfilter, 2484 enum rte_filter_op filter_op) 2485 { 2486 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2487 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2488 int ret; 2489 2490 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2491 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2492 return -EINVAL; 2493 } 2494 2495 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2496 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2497 return -EINVAL; 2498 } 2499 2500 bfilter = bnxt_get_unused_filter(bp); 2501 if (bfilter == NULL) { 2502 PMD_DRV_LOG(ERR, 2503 "Not enough resources for a new filter.\n"); 2504 return -ENOMEM; 2505 } 2506 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2507 if (ret < 0) 2508 goto free_filter; 2509 2510 vnic = &bp->vnic_info[nfilter->queue]; 2511 vnic0 = &bp->vnic_info[0]; 2512 filter1 = STAILQ_FIRST(&vnic0->filter); 2513 if (filter1 == NULL) { 2514 ret = -EINVAL; 2515 goto free_filter; 2516 } 2517 2518 bfilter->dst_id = vnic->fw_vnic_id; 2519 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2520 bfilter->enables |= 2521 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2522 bfilter->ethertype = 0x800; 2523 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2524 2525 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2526 2527 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2528 bfilter->dst_id == mfilter->dst_id) { 2529 PMD_DRV_LOG(ERR, "filter exists.\n"); 2530 ret = -EEXIST; 2531 goto free_filter; 2532 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2533 bfilter->dst_id != mfilter->dst_id) { 2534 mfilter->dst_id = vnic->fw_vnic_id; 2535 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2536 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2537 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2538 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2539 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2540 goto free_filter; 2541 } 2542 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2543 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2544 ret = -ENOENT; 2545 goto free_filter; 2546 } 2547 2548 if (filter_op == RTE_ETH_FILTER_ADD) { 2549 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2550 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2551 if (ret) 2552 goto free_filter; 2553 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2554 } else { 2555 if (mfilter == NULL) { 2556 /* This should not happen. But for Coverity! */ 2557 ret = -ENOENT; 2558 goto free_filter; 2559 } 2560 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2561 2562 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2563 bnxt_free_filter(bp, mfilter); 2564 mfilter->fw_l2_filter_id = -1; 2565 bnxt_free_filter(bp, bfilter); 2566 bfilter->fw_l2_filter_id = -1; 2567 } 2568 2569 return 0; 2570 free_filter: 2571 bfilter->fw_l2_filter_id = -1; 2572 bnxt_free_filter(bp, bfilter); 2573 return ret; 2574 } 2575 2576 static int 2577 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2578 enum rte_filter_op filter_op, 2579 void *arg) 2580 { 2581 struct bnxt *bp = dev->data->dev_private; 2582 int ret; 2583 2584 if (filter_op == RTE_ETH_FILTER_NOP) 2585 return 0; 2586 2587 if (arg == NULL) { 2588 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2589 filter_op); 2590 return -EINVAL; 2591 } 2592 2593 switch (filter_op) { 2594 case RTE_ETH_FILTER_ADD: 2595 ret = bnxt_cfg_ntuple_filter(bp, 2596 (struct rte_eth_ntuple_filter *)arg, 2597 filter_op); 2598 break; 2599 case RTE_ETH_FILTER_DELETE: 2600 ret = bnxt_cfg_ntuple_filter(bp, 2601 (struct rte_eth_ntuple_filter *)arg, 2602 filter_op); 2603 break; 2604 default: 2605 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2606 ret = -EINVAL; 2607 break; 2608 } 2609 return ret; 2610 } 2611 2612 static int 2613 bnxt_parse_fdir_filter(struct bnxt *bp, 2614 struct rte_eth_fdir_filter *fdir, 2615 struct bnxt_filter_info *filter) 2616 { 2617 enum rte_fdir_mode fdir_mode = 2618 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2619 struct bnxt_vnic_info *vnic0, *vnic; 2620 struct bnxt_filter_info *filter1; 2621 uint32_t en = 0; 2622 int i; 2623 2624 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2625 return -EINVAL; 2626 2627 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2628 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2629 2630 switch (fdir->input.flow_type) { 2631 case RTE_ETH_FLOW_IPV4: 2632 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2633 /* FALLTHROUGH */ 2634 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2635 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2636 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2637 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2638 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2639 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2640 filter->ip_addr_type = 2641 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2642 filter->src_ipaddr_mask[0] = 0xffffffff; 2643 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2644 filter->dst_ipaddr_mask[0] = 0xffffffff; 2645 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2646 filter->ethertype = 0x800; 2647 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2648 break; 2649 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2650 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2651 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2652 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2653 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2654 filter->dst_port_mask = 0xffff; 2655 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2656 filter->src_port_mask = 0xffff; 2657 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2658 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2659 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2660 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2661 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2662 filter->ip_protocol = 6; 2663 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2664 filter->ip_addr_type = 2665 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2666 filter->src_ipaddr_mask[0] = 0xffffffff; 2667 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2668 filter->dst_ipaddr_mask[0] = 0xffffffff; 2669 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2670 filter->ethertype = 0x800; 2671 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2672 break; 2673 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2674 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2675 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2676 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2677 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2678 filter->dst_port_mask = 0xffff; 2679 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2680 filter->src_port_mask = 0xffff; 2681 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2682 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2683 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2684 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2685 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2686 filter->ip_protocol = 17; 2687 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2688 filter->ip_addr_type = 2689 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2690 filter->src_ipaddr_mask[0] = 0xffffffff; 2691 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2692 filter->dst_ipaddr_mask[0] = 0xffffffff; 2693 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2694 filter->ethertype = 0x800; 2695 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2696 break; 2697 case RTE_ETH_FLOW_IPV6: 2698 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2699 /* FALLTHROUGH */ 2700 filter->ip_addr_type = 2701 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2702 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2703 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2704 rte_memcpy(filter->src_ipaddr, 2705 fdir->input.flow.ipv6_flow.src_ip, 16); 2706 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2707 rte_memcpy(filter->dst_ipaddr, 2708 fdir->input.flow.ipv6_flow.dst_ip, 16); 2709 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2710 memset(filter->dst_ipaddr_mask, 0xff, 16); 2711 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2712 memset(filter->src_ipaddr_mask, 0xff, 16); 2713 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2714 filter->ethertype = 0x86dd; 2715 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2716 break; 2717 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2718 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2719 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2720 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2721 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2722 filter->dst_port_mask = 0xffff; 2723 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2724 filter->src_port_mask = 0xffff; 2725 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2726 filter->ip_addr_type = 2727 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2728 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2729 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2730 rte_memcpy(filter->src_ipaddr, 2731 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2732 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2733 rte_memcpy(filter->dst_ipaddr, 2734 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2735 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2736 memset(filter->dst_ipaddr_mask, 0xff, 16); 2737 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2738 memset(filter->src_ipaddr_mask, 0xff, 16); 2739 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2740 filter->ethertype = 0x86dd; 2741 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2742 break; 2743 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2744 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2745 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2746 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2747 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2748 filter->dst_port_mask = 0xffff; 2749 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2750 filter->src_port_mask = 0xffff; 2751 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2752 filter->ip_addr_type = 2753 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2754 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2755 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2756 rte_memcpy(filter->src_ipaddr, 2757 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2758 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2759 rte_memcpy(filter->dst_ipaddr, 2760 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2761 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2762 memset(filter->dst_ipaddr_mask, 0xff, 16); 2763 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2764 memset(filter->src_ipaddr_mask, 0xff, 16); 2765 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2766 filter->ethertype = 0x86dd; 2767 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2768 break; 2769 case RTE_ETH_FLOW_L2_PAYLOAD: 2770 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2771 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2772 break; 2773 case RTE_ETH_FLOW_VXLAN: 2774 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2775 return -EINVAL; 2776 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2777 filter->tunnel_type = 2778 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2779 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2780 break; 2781 case RTE_ETH_FLOW_NVGRE: 2782 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2783 return -EINVAL; 2784 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2785 filter->tunnel_type = 2786 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2787 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2788 break; 2789 case RTE_ETH_FLOW_UNKNOWN: 2790 case RTE_ETH_FLOW_RAW: 2791 case RTE_ETH_FLOW_FRAG_IPV4: 2792 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2793 case RTE_ETH_FLOW_FRAG_IPV6: 2794 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2795 case RTE_ETH_FLOW_IPV6_EX: 2796 case RTE_ETH_FLOW_IPV6_TCP_EX: 2797 case RTE_ETH_FLOW_IPV6_UDP_EX: 2798 case RTE_ETH_FLOW_GENEVE: 2799 /* FALLTHROUGH */ 2800 default: 2801 return -EINVAL; 2802 } 2803 2804 vnic0 = &bp->vnic_info[0]; 2805 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2806 if (vnic == NULL) { 2807 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2808 return -EINVAL; 2809 } 2810 2811 2812 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2813 rte_memcpy(filter->dst_macaddr, 2814 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2815 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2816 } 2817 2818 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2819 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2820 filter1 = STAILQ_FIRST(&vnic0->filter); 2821 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2822 } else { 2823 filter->dst_id = vnic->fw_vnic_id; 2824 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2825 if (filter->dst_macaddr[i] == 0x00) 2826 filter1 = STAILQ_FIRST(&vnic0->filter); 2827 else 2828 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2829 } 2830 2831 if (filter1 == NULL) 2832 return -EINVAL; 2833 2834 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2835 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2836 2837 filter->enables = en; 2838 2839 return 0; 2840 } 2841 2842 static struct bnxt_filter_info * 2843 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 2844 struct bnxt_vnic_info **mvnic) 2845 { 2846 struct bnxt_filter_info *mf = NULL; 2847 int i; 2848 2849 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2850 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2851 2852 STAILQ_FOREACH(mf, &vnic->filter, next) { 2853 if (mf->filter_type == nf->filter_type && 2854 mf->flags == nf->flags && 2855 mf->src_port == nf->src_port && 2856 mf->src_port_mask == nf->src_port_mask && 2857 mf->dst_port == nf->dst_port && 2858 mf->dst_port_mask == nf->dst_port_mask && 2859 mf->ip_protocol == nf->ip_protocol && 2860 mf->ip_addr_type == nf->ip_addr_type && 2861 mf->ethertype == nf->ethertype && 2862 mf->vni == nf->vni && 2863 mf->tunnel_type == nf->tunnel_type && 2864 mf->l2_ovlan == nf->l2_ovlan && 2865 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 2866 mf->l2_ivlan == nf->l2_ivlan && 2867 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 2868 !memcmp(mf->l2_addr, nf->l2_addr, 2869 RTE_ETHER_ADDR_LEN) && 2870 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 2871 RTE_ETHER_ADDR_LEN) && 2872 !memcmp(mf->src_macaddr, nf->src_macaddr, 2873 RTE_ETHER_ADDR_LEN) && 2874 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 2875 RTE_ETHER_ADDR_LEN) && 2876 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 2877 sizeof(nf->src_ipaddr)) && 2878 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 2879 sizeof(nf->src_ipaddr_mask)) && 2880 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 2881 sizeof(nf->dst_ipaddr)) && 2882 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 2883 sizeof(nf->dst_ipaddr_mask))) { 2884 if (mvnic) 2885 *mvnic = vnic; 2886 return mf; 2887 } 2888 } 2889 } 2890 return NULL; 2891 } 2892 2893 static int 2894 bnxt_fdir_filter(struct rte_eth_dev *dev, 2895 enum rte_filter_op filter_op, 2896 void *arg) 2897 { 2898 struct bnxt *bp = dev->data->dev_private; 2899 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 2900 struct bnxt_filter_info *filter, *match; 2901 struct bnxt_vnic_info *vnic, *mvnic; 2902 int ret = 0, i; 2903 2904 if (filter_op == RTE_ETH_FILTER_NOP) 2905 return 0; 2906 2907 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 2908 return -EINVAL; 2909 2910 switch (filter_op) { 2911 case RTE_ETH_FILTER_ADD: 2912 case RTE_ETH_FILTER_DELETE: 2913 /* FALLTHROUGH */ 2914 filter = bnxt_get_unused_filter(bp); 2915 if (filter == NULL) { 2916 PMD_DRV_LOG(ERR, 2917 "Not enough resources for a new flow.\n"); 2918 return -ENOMEM; 2919 } 2920 2921 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 2922 if (ret != 0) 2923 goto free_filter; 2924 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2925 2926 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2927 vnic = &bp->vnic_info[0]; 2928 else 2929 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2930 2931 match = bnxt_match_fdir(bp, filter, &mvnic); 2932 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2933 if (match->dst_id == vnic->fw_vnic_id) { 2934 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 2935 ret = -EEXIST; 2936 goto free_filter; 2937 } else { 2938 match->dst_id = vnic->fw_vnic_id; 2939 ret = bnxt_hwrm_set_ntuple_filter(bp, 2940 match->dst_id, 2941 match); 2942 STAILQ_REMOVE(&mvnic->filter, match, 2943 bnxt_filter_info, next); 2944 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 2945 PMD_DRV_LOG(ERR, 2946 "Filter with matching pattern exist\n"); 2947 PMD_DRV_LOG(ERR, 2948 "Updated it to new destination q\n"); 2949 goto free_filter; 2950 } 2951 } 2952 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2953 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 2954 ret = -ENOENT; 2955 goto free_filter; 2956 } 2957 2958 if (filter_op == RTE_ETH_FILTER_ADD) { 2959 ret = bnxt_hwrm_set_ntuple_filter(bp, 2960 filter->dst_id, 2961 filter); 2962 if (ret) 2963 goto free_filter; 2964 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2965 } else { 2966 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 2967 STAILQ_REMOVE(&vnic->filter, match, 2968 bnxt_filter_info, next); 2969 bnxt_free_filter(bp, match); 2970 filter->fw_l2_filter_id = -1; 2971 bnxt_free_filter(bp, filter); 2972 } 2973 break; 2974 case RTE_ETH_FILTER_FLUSH: 2975 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2976 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2977 2978 STAILQ_FOREACH(filter, &vnic->filter, next) { 2979 if (filter->filter_type == 2980 HWRM_CFA_NTUPLE_FILTER) { 2981 ret = 2982 bnxt_hwrm_clear_ntuple_filter(bp, 2983 filter); 2984 STAILQ_REMOVE(&vnic->filter, filter, 2985 bnxt_filter_info, next); 2986 } 2987 } 2988 } 2989 return ret; 2990 case RTE_ETH_FILTER_UPDATE: 2991 case RTE_ETH_FILTER_STATS: 2992 case RTE_ETH_FILTER_INFO: 2993 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 2994 break; 2995 default: 2996 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 2997 ret = -EINVAL; 2998 break; 2999 } 3000 return ret; 3001 3002 free_filter: 3003 filter->fw_l2_filter_id = -1; 3004 bnxt_free_filter(bp, filter); 3005 return ret; 3006 } 3007 3008 static int 3009 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 3010 enum rte_filter_type filter_type, 3011 enum rte_filter_op filter_op, void *arg) 3012 { 3013 int ret = 0; 3014 3015 ret = is_bnxt_in_error(dev->data->dev_private); 3016 if (ret) 3017 return ret; 3018 3019 switch (filter_type) { 3020 case RTE_ETH_FILTER_TUNNEL: 3021 PMD_DRV_LOG(ERR, 3022 "filter type: %d: To be implemented\n", filter_type); 3023 break; 3024 case RTE_ETH_FILTER_FDIR: 3025 ret = bnxt_fdir_filter(dev, filter_op, arg); 3026 break; 3027 case RTE_ETH_FILTER_NTUPLE: 3028 ret = bnxt_ntuple_filter(dev, filter_op, arg); 3029 break; 3030 case RTE_ETH_FILTER_ETHERTYPE: 3031 ret = bnxt_ethertype_filter(dev, filter_op, arg); 3032 break; 3033 case RTE_ETH_FILTER_GENERIC: 3034 if (filter_op != RTE_ETH_FILTER_GET) 3035 return -EINVAL; 3036 *(const void **)arg = &bnxt_flow_ops; 3037 break; 3038 default: 3039 PMD_DRV_LOG(ERR, 3040 "Filter type (%d) not supported", filter_type); 3041 ret = -EINVAL; 3042 break; 3043 } 3044 return ret; 3045 } 3046 3047 static const uint32_t * 3048 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 3049 { 3050 static const uint32_t ptypes[] = { 3051 RTE_PTYPE_L2_ETHER_VLAN, 3052 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 3053 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 3054 RTE_PTYPE_L4_ICMP, 3055 RTE_PTYPE_L4_TCP, 3056 RTE_PTYPE_L4_UDP, 3057 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 3058 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 3059 RTE_PTYPE_INNER_L4_ICMP, 3060 RTE_PTYPE_INNER_L4_TCP, 3061 RTE_PTYPE_INNER_L4_UDP, 3062 RTE_PTYPE_UNKNOWN 3063 }; 3064 3065 if (!dev->rx_pkt_burst) 3066 return NULL; 3067 3068 return ptypes; 3069 } 3070 3071 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 3072 int reg_win) 3073 { 3074 uint32_t reg_base = *reg_arr & 0xfffff000; 3075 uint32_t win_off; 3076 int i; 3077 3078 for (i = 0; i < count; i++) { 3079 if ((reg_arr[i] & 0xfffff000) != reg_base) 3080 return -ERANGE; 3081 } 3082 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 3083 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 3084 return 0; 3085 } 3086 3087 static int bnxt_map_ptp_regs(struct bnxt *bp) 3088 { 3089 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3090 uint32_t *reg_arr; 3091 int rc, i; 3092 3093 reg_arr = ptp->rx_regs; 3094 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 3095 if (rc) 3096 return rc; 3097 3098 reg_arr = ptp->tx_regs; 3099 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 3100 if (rc) 3101 return rc; 3102 3103 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 3104 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 3105 3106 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 3107 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 3108 3109 return 0; 3110 } 3111 3112 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 3113 { 3114 rte_write32(0, (uint8_t *)bp->bar0 + 3115 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 3116 rte_write32(0, (uint8_t *)bp->bar0 + 3117 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 3118 } 3119 3120 static uint64_t bnxt_cc_read(struct bnxt *bp) 3121 { 3122 uint64_t ns; 3123 3124 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3125 BNXT_GRCPF_REG_SYNC_TIME)); 3126 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3127 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 3128 return ns; 3129 } 3130 3131 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 3132 { 3133 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3134 uint32_t fifo; 3135 3136 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3137 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3138 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 3139 return -EAGAIN; 3140 3141 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3142 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 3143 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3144 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 3145 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3146 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 3147 3148 return 0; 3149 } 3150 3151 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 3152 { 3153 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3154 struct bnxt_pf_info *pf = &bp->pf; 3155 uint16_t port_id; 3156 uint32_t fifo; 3157 3158 if (!ptp) 3159 return -ENODEV; 3160 3161 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3162 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3163 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 3164 return -EAGAIN; 3165 3166 port_id = pf->port_id; 3167 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 3168 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 3169 3170 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3171 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 3172 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 3173 /* bnxt_clr_rx_ts(bp); TBD */ 3174 return -EBUSY; 3175 } 3176 3177 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3178 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 3179 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3180 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 3181 3182 return 0; 3183 } 3184 3185 static int 3186 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 3187 { 3188 uint64_t ns; 3189 struct bnxt *bp = dev->data->dev_private; 3190 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3191 3192 if (!ptp) 3193 return 0; 3194 3195 ns = rte_timespec_to_ns(ts); 3196 /* Set the timecounters to a new value. */ 3197 ptp->tc.nsec = ns; 3198 3199 return 0; 3200 } 3201 3202 static int 3203 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 3204 { 3205 struct bnxt *bp = dev->data->dev_private; 3206 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3207 uint64_t ns, systime_cycles = 0; 3208 int rc = 0; 3209 3210 if (!ptp) 3211 return 0; 3212 3213 if (BNXT_CHIP_THOR(bp)) 3214 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_CURRENT_TIME, 3215 &systime_cycles); 3216 else 3217 systime_cycles = bnxt_cc_read(bp); 3218 3219 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 3220 *ts = rte_ns_to_timespec(ns); 3221 3222 return rc; 3223 } 3224 static int 3225 bnxt_timesync_enable(struct rte_eth_dev *dev) 3226 { 3227 struct bnxt *bp = dev->data->dev_private; 3228 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3229 uint32_t shift = 0; 3230 int rc; 3231 3232 if (!ptp) 3233 return 0; 3234 3235 ptp->rx_filter = 1; 3236 ptp->tx_tstamp_en = 1; 3237 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 3238 3239 rc = bnxt_hwrm_ptp_cfg(bp); 3240 if (rc) 3241 return rc; 3242 3243 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 3244 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3245 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 3246 3247 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3248 ptp->tc.cc_shift = shift; 3249 ptp->tc.nsec_mask = (1ULL << shift) - 1; 3250 3251 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3252 ptp->rx_tstamp_tc.cc_shift = shift; 3253 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3254 3255 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 3256 ptp->tx_tstamp_tc.cc_shift = shift; 3257 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 3258 3259 if (!BNXT_CHIP_THOR(bp)) 3260 bnxt_map_ptp_regs(bp); 3261 3262 return 0; 3263 } 3264 3265 static int 3266 bnxt_timesync_disable(struct rte_eth_dev *dev) 3267 { 3268 struct bnxt *bp = dev->data->dev_private; 3269 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3270 3271 if (!ptp) 3272 return 0; 3273 3274 ptp->rx_filter = 0; 3275 ptp->tx_tstamp_en = 0; 3276 ptp->rxctl = 0; 3277 3278 bnxt_hwrm_ptp_cfg(bp); 3279 3280 if (!BNXT_CHIP_THOR(bp)) 3281 bnxt_unmap_ptp_regs(bp); 3282 3283 return 0; 3284 } 3285 3286 static int 3287 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 3288 struct timespec *timestamp, 3289 uint32_t flags __rte_unused) 3290 { 3291 struct bnxt *bp = dev->data->dev_private; 3292 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3293 uint64_t rx_tstamp_cycles = 0; 3294 uint64_t ns; 3295 3296 if (!ptp) 3297 return 0; 3298 3299 if (BNXT_CHIP_THOR(bp)) 3300 rx_tstamp_cycles = ptp->rx_timestamp; 3301 else 3302 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 3303 3304 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 3305 *timestamp = rte_ns_to_timespec(ns); 3306 return 0; 3307 } 3308 3309 static int 3310 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 3311 struct timespec *timestamp) 3312 { 3313 struct bnxt *bp = dev->data->dev_private; 3314 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3315 uint64_t tx_tstamp_cycles = 0; 3316 uint64_t ns; 3317 int rc = 0; 3318 3319 if (!ptp) 3320 return 0; 3321 3322 if (BNXT_CHIP_THOR(bp)) 3323 rc = bnxt_hwrm_port_ts_query(bp, BNXT_PTP_FLAGS_PATH_TX, 3324 &tx_tstamp_cycles); 3325 else 3326 rc = bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 3327 3328 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 3329 *timestamp = rte_ns_to_timespec(ns); 3330 3331 return rc; 3332 } 3333 3334 static int 3335 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 3336 { 3337 struct bnxt *bp = dev->data->dev_private; 3338 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 3339 3340 if (!ptp) 3341 return 0; 3342 3343 ptp->tc.nsec += delta; 3344 3345 return 0; 3346 } 3347 3348 static int 3349 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 3350 { 3351 struct bnxt *bp = dev->data->dev_private; 3352 int rc; 3353 uint32_t dir_entries; 3354 uint32_t entry_length; 3355 3356 rc = is_bnxt_in_error(bp); 3357 if (rc) 3358 return rc; 3359 3360 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 3361 bp->pdev->addr.domain, bp->pdev->addr.bus, 3362 bp->pdev->addr.devid, bp->pdev->addr.function); 3363 3364 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 3365 if (rc != 0) 3366 return rc; 3367 3368 return dir_entries * entry_length; 3369 } 3370 3371 static int 3372 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 3373 struct rte_dev_eeprom_info *in_eeprom) 3374 { 3375 struct bnxt *bp = dev->data->dev_private; 3376 uint32_t index; 3377 uint32_t offset; 3378 int rc; 3379 3380 rc = is_bnxt_in_error(bp); 3381 if (rc) 3382 return rc; 3383 3384 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3385 "len = %d\n", bp->pdev->addr.domain, 3386 bp->pdev->addr.bus, bp->pdev->addr.devid, 3387 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3388 3389 if (in_eeprom->offset == 0) /* special offset value to get directory */ 3390 return bnxt_get_nvram_directory(bp, in_eeprom->length, 3391 in_eeprom->data); 3392 3393 index = in_eeprom->offset >> 24; 3394 offset = in_eeprom->offset & 0xffffff; 3395 3396 if (index != 0) 3397 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 3398 in_eeprom->length, in_eeprom->data); 3399 3400 return 0; 3401 } 3402 3403 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 3404 { 3405 switch (dir_type) { 3406 case BNX_DIR_TYPE_CHIMP_PATCH: 3407 case BNX_DIR_TYPE_BOOTCODE: 3408 case BNX_DIR_TYPE_BOOTCODE_2: 3409 case BNX_DIR_TYPE_APE_FW: 3410 case BNX_DIR_TYPE_APE_PATCH: 3411 case BNX_DIR_TYPE_KONG_FW: 3412 case BNX_DIR_TYPE_KONG_PATCH: 3413 case BNX_DIR_TYPE_BONO_FW: 3414 case BNX_DIR_TYPE_BONO_PATCH: 3415 /* FALLTHROUGH */ 3416 return true; 3417 } 3418 3419 return false; 3420 } 3421 3422 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 3423 { 3424 switch (dir_type) { 3425 case BNX_DIR_TYPE_AVS: 3426 case BNX_DIR_TYPE_EXP_ROM_MBA: 3427 case BNX_DIR_TYPE_PCIE: 3428 case BNX_DIR_TYPE_TSCF_UCODE: 3429 case BNX_DIR_TYPE_EXT_PHY: 3430 case BNX_DIR_TYPE_CCM: 3431 case BNX_DIR_TYPE_ISCSI_BOOT: 3432 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 3433 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 3434 /* FALLTHROUGH */ 3435 return true; 3436 } 3437 3438 return false; 3439 } 3440 3441 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 3442 { 3443 return bnxt_dir_type_is_ape_bin_format(dir_type) || 3444 bnxt_dir_type_is_other_exec_format(dir_type); 3445 } 3446 3447 static int 3448 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 3449 struct rte_dev_eeprom_info *in_eeprom) 3450 { 3451 struct bnxt *bp = dev->data->dev_private; 3452 uint8_t index, dir_op; 3453 uint16_t type, ext, ordinal, attr; 3454 int rc; 3455 3456 rc = is_bnxt_in_error(bp); 3457 if (rc) 3458 return rc; 3459 3460 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 3461 "len = %d\n", bp->pdev->addr.domain, 3462 bp->pdev->addr.bus, bp->pdev->addr.devid, 3463 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3464 3465 if (!BNXT_PF(bp)) { 3466 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3467 return -EINVAL; 3468 } 3469 3470 type = in_eeprom->magic >> 16; 3471 3472 if (type == 0xffff) { /* special value for directory operations */ 3473 index = in_eeprom->magic & 0xff; 3474 dir_op = in_eeprom->magic >> 8; 3475 if (index == 0) 3476 return -EINVAL; 3477 switch (dir_op) { 3478 case 0x0e: /* erase */ 3479 if (in_eeprom->offset != ~in_eeprom->magic) 3480 return -EINVAL; 3481 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3482 default: 3483 return -EINVAL; 3484 } 3485 } 3486 3487 /* Create or re-write an NVM item: */ 3488 if (bnxt_dir_type_is_executable(type) == true) 3489 return -EOPNOTSUPP; 3490 ext = in_eeprom->magic & 0xffff; 3491 ordinal = in_eeprom->offset >> 16; 3492 attr = in_eeprom->offset & 0xffff; 3493 3494 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3495 in_eeprom->data, in_eeprom->length); 3496 } 3497 3498 /* 3499 * Initialization 3500 */ 3501 3502 static const struct eth_dev_ops bnxt_dev_ops = { 3503 .dev_infos_get = bnxt_dev_info_get_op, 3504 .dev_close = bnxt_dev_close_op, 3505 .dev_configure = bnxt_dev_configure_op, 3506 .dev_start = bnxt_dev_start_op, 3507 .dev_stop = bnxt_dev_stop_op, 3508 .dev_set_link_up = bnxt_dev_set_link_up_op, 3509 .dev_set_link_down = bnxt_dev_set_link_down_op, 3510 .stats_get = bnxt_stats_get_op, 3511 .stats_reset = bnxt_stats_reset_op, 3512 .rx_queue_setup = bnxt_rx_queue_setup_op, 3513 .rx_queue_release = bnxt_rx_queue_release_op, 3514 .tx_queue_setup = bnxt_tx_queue_setup_op, 3515 .tx_queue_release = bnxt_tx_queue_release_op, 3516 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3517 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3518 .reta_update = bnxt_reta_update_op, 3519 .reta_query = bnxt_reta_query_op, 3520 .rss_hash_update = bnxt_rss_hash_update_op, 3521 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3522 .link_update = bnxt_link_update_op, 3523 .promiscuous_enable = bnxt_promiscuous_enable_op, 3524 .promiscuous_disable = bnxt_promiscuous_disable_op, 3525 .allmulticast_enable = bnxt_allmulticast_enable_op, 3526 .allmulticast_disable = bnxt_allmulticast_disable_op, 3527 .mac_addr_add = bnxt_mac_addr_add_op, 3528 .mac_addr_remove = bnxt_mac_addr_remove_op, 3529 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3530 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3531 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3532 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3533 .vlan_filter_set = bnxt_vlan_filter_set_op, 3534 .vlan_offload_set = bnxt_vlan_offload_set_op, 3535 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3536 .mtu_set = bnxt_mtu_set_op, 3537 .mac_addr_set = bnxt_set_default_mac_addr_op, 3538 .xstats_get = bnxt_dev_xstats_get_op, 3539 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3540 .xstats_reset = bnxt_dev_xstats_reset_op, 3541 .fw_version_get = bnxt_fw_version_get, 3542 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3543 .rxq_info_get = bnxt_rxq_info_get_op, 3544 .txq_info_get = bnxt_txq_info_get_op, 3545 .dev_led_on = bnxt_dev_led_on_op, 3546 .dev_led_off = bnxt_dev_led_off_op, 3547 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3548 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3549 .rx_queue_count = bnxt_rx_queue_count_op, 3550 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3551 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3552 .rx_queue_start = bnxt_rx_queue_start, 3553 .rx_queue_stop = bnxt_rx_queue_stop, 3554 .tx_queue_start = bnxt_tx_queue_start, 3555 .tx_queue_stop = bnxt_tx_queue_stop, 3556 .filter_ctrl = bnxt_filter_ctrl_op, 3557 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3558 .get_eeprom_length = bnxt_get_eeprom_length_op, 3559 .get_eeprom = bnxt_get_eeprom_op, 3560 .set_eeprom = bnxt_set_eeprom_op, 3561 .timesync_enable = bnxt_timesync_enable, 3562 .timesync_disable = bnxt_timesync_disable, 3563 .timesync_read_time = bnxt_timesync_read_time, 3564 .timesync_write_time = bnxt_timesync_write_time, 3565 .timesync_adjust_time = bnxt_timesync_adjust_time, 3566 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3567 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3568 }; 3569 3570 static uint32_t bnxt_map_reset_regs(struct bnxt *bp, uint32_t reg) 3571 { 3572 uint32_t offset; 3573 3574 /* Only pre-map the reset GRC registers using window 3 */ 3575 rte_write32(reg & 0xfffff000, (uint8_t *)bp->bar0 + 3576 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 8); 3577 3578 offset = BNXT_GRCP_WINDOW_3_BASE + (reg & 0xffc); 3579 3580 return offset; 3581 } 3582 3583 int bnxt_map_fw_health_status_regs(struct bnxt *bp) 3584 { 3585 struct bnxt_error_recovery_info *info = bp->recovery_info; 3586 uint32_t reg_base = 0xffffffff; 3587 int i; 3588 3589 /* Only pre-map the monitoring GRC registers using window 2 */ 3590 for (i = 0; i < BNXT_FW_STATUS_REG_CNT; i++) { 3591 uint32_t reg = info->status_regs[i]; 3592 3593 if (BNXT_FW_STATUS_REG_TYPE(reg) != BNXT_FW_STATUS_REG_TYPE_GRC) 3594 continue; 3595 3596 if (reg_base == 0xffffffff) 3597 reg_base = reg & 0xfffff000; 3598 if ((reg & 0xfffff000) != reg_base) 3599 return -ERANGE; 3600 3601 /* Use mask 0xffc as the Lower 2 bits indicates 3602 * address space location 3603 */ 3604 info->mapped_status_regs[i] = BNXT_GRCP_WINDOW_2_BASE + 3605 (reg & 0xffc); 3606 } 3607 3608 if (reg_base == 0xffffffff) 3609 return 0; 3610 3611 rte_write32(reg_base, (uint8_t *)bp->bar0 + 3612 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 4); 3613 3614 return 0; 3615 } 3616 3617 static void bnxt_write_fw_reset_reg(struct bnxt *bp, uint32_t index) 3618 { 3619 struct bnxt_error_recovery_info *info = bp->recovery_info; 3620 uint32_t delay = info->delay_after_reset[index]; 3621 uint32_t val = info->reset_reg_val[index]; 3622 uint32_t reg = info->reset_reg[index]; 3623 uint32_t type, offset; 3624 3625 type = BNXT_FW_STATUS_REG_TYPE(reg); 3626 offset = BNXT_FW_STATUS_REG_OFF(reg); 3627 3628 switch (type) { 3629 case BNXT_FW_STATUS_REG_TYPE_CFG: 3630 rte_pci_write_config(bp->pdev, &val, sizeof(val), offset); 3631 break; 3632 case BNXT_FW_STATUS_REG_TYPE_GRC: 3633 offset = bnxt_map_reset_regs(bp, offset); 3634 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3635 break; 3636 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3637 rte_write32(val, (uint8_t *)bp->bar0 + offset); 3638 break; 3639 } 3640 /* wait on a specific interval of time until core reset is complete */ 3641 if (delay) 3642 rte_delay_ms(delay); 3643 } 3644 3645 static void bnxt_dev_cleanup(struct bnxt *bp) 3646 { 3647 bnxt_set_hwrm_link_config(bp, false); 3648 bp->link_info.link_up = 0; 3649 if (bp->dev_stopped == 0) 3650 bnxt_dev_stop_op(bp->eth_dev); 3651 3652 bnxt_uninit_resources(bp, true); 3653 } 3654 3655 static int bnxt_restore_filters(struct bnxt *bp) 3656 { 3657 struct rte_eth_dev *dev = bp->eth_dev; 3658 int ret = 0; 3659 3660 if (dev->data->all_multicast) 3661 ret = bnxt_allmulticast_enable_op(dev); 3662 if (dev->data->promiscuous) 3663 ret = bnxt_promiscuous_enable_op(dev); 3664 3665 /* TODO restore other filters as well */ 3666 return ret; 3667 } 3668 3669 static void bnxt_dev_recover(void *arg) 3670 { 3671 struct bnxt *bp = arg; 3672 int timeout = bp->fw_reset_max_msecs; 3673 int rc = 0; 3674 3675 /* Clear Error flag so that device re-init should happen */ 3676 bp->flags &= ~BNXT_FLAG_FATAL_ERROR; 3677 3678 do { 3679 rc = bnxt_hwrm_ver_get(bp); 3680 if (rc == 0) 3681 break; 3682 rte_delay_ms(BNXT_FW_READY_WAIT_INTERVAL); 3683 timeout -= BNXT_FW_READY_WAIT_INTERVAL; 3684 } while (rc && timeout); 3685 3686 if (rc) { 3687 PMD_DRV_LOG(ERR, "FW is not Ready after reset\n"); 3688 goto err; 3689 } 3690 3691 rc = bnxt_init_resources(bp, true); 3692 if (rc) { 3693 PMD_DRV_LOG(ERR, 3694 "Failed to initialize resources after reset\n"); 3695 goto err; 3696 } 3697 /* clear reset flag as the device is initialized now */ 3698 bp->flags &= ~BNXT_FLAG_FW_RESET; 3699 3700 rc = bnxt_dev_start_op(bp->eth_dev); 3701 if (rc) { 3702 PMD_DRV_LOG(ERR, "Failed to start port after reset\n"); 3703 goto err; 3704 } 3705 3706 rc = bnxt_restore_filters(bp); 3707 if (rc) 3708 goto err; 3709 3710 PMD_DRV_LOG(INFO, "Recovered from FW reset\n"); 3711 return; 3712 err: 3713 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3714 bnxt_uninit_resources(bp, false); 3715 PMD_DRV_LOG(ERR, "Failed to recover from FW reset\n"); 3716 } 3717 3718 void bnxt_dev_reset_and_resume(void *arg) 3719 { 3720 struct bnxt *bp = arg; 3721 int rc; 3722 3723 bnxt_dev_cleanup(bp); 3724 3725 bnxt_wait_for_device_shutdown(bp); 3726 3727 rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, 3728 bnxt_dev_recover, (void *)bp); 3729 if (rc) 3730 PMD_DRV_LOG(ERR, "Error setting recovery alarm"); 3731 } 3732 3733 uint32_t bnxt_read_fw_status_reg(struct bnxt *bp, uint32_t index) 3734 { 3735 struct bnxt_error_recovery_info *info = bp->recovery_info; 3736 uint32_t reg = info->status_regs[index]; 3737 uint32_t type, offset, val = 0; 3738 3739 type = BNXT_FW_STATUS_REG_TYPE(reg); 3740 offset = BNXT_FW_STATUS_REG_OFF(reg); 3741 3742 switch (type) { 3743 case BNXT_FW_STATUS_REG_TYPE_CFG: 3744 rte_pci_read_config(bp->pdev, &val, sizeof(val), offset); 3745 break; 3746 case BNXT_FW_STATUS_REG_TYPE_GRC: 3747 offset = info->mapped_status_regs[index]; 3748 /* FALLTHROUGH */ 3749 case BNXT_FW_STATUS_REG_TYPE_BAR0: 3750 val = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 3751 offset)); 3752 break; 3753 } 3754 3755 return val; 3756 } 3757 3758 static int bnxt_fw_reset_all(struct bnxt *bp) 3759 { 3760 struct bnxt_error_recovery_info *info = bp->recovery_info; 3761 uint32_t i; 3762 int rc = 0; 3763 3764 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3765 /* Reset through master function driver */ 3766 for (i = 0; i < info->reg_array_cnt; i++) 3767 bnxt_write_fw_reset_reg(bp, i); 3768 /* Wait for time specified by FW after triggering reset */ 3769 rte_delay_ms(info->master_func_wait_period_after_reset); 3770 } else if (info->flags & BNXT_FLAG_ERROR_RECOVERY_CO_CPU) { 3771 /* Reset with the help of Kong processor */ 3772 rc = bnxt_hwrm_fw_reset(bp); 3773 if (rc) 3774 PMD_DRV_LOG(ERR, "Failed to reset FW\n"); 3775 } 3776 3777 return rc; 3778 } 3779 3780 static void bnxt_fw_reset_cb(void *arg) 3781 { 3782 struct bnxt *bp = arg; 3783 struct bnxt_error_recovery_info *info = bp->recovery_info; 3784 int rc = 0; 3785 3786 /* Only Master function can do FW reset */ 3787 if (bnxt_is_master_func(bp) && 3788 bnxt_is_recovery_enabled(bp)) { 3789 rc = bnxt_fw_reset_all(bp); 3790 if (rc) { 3791 PMD_DRV_LOG(ERR, "Adapter recovery failed\n"); 3792 return; 3793 } 3794 } 3795 3796 /* if recovery method is ERROR_RECOVERY_CO_CPU, KONG will send 3797 * EXCEPTION_FATAL_ASYNC event to all the functions 3798 * (including MASTER FUNC). After receiving this Async, all the active 3799 * drivers should treat this case as FW initiated recovery 3800 */ 3801 if (info->flags & BNXT_FLAG_ERROR_RECOVERY_HOST) { 3802 bp->fw_reset_min_msecs = BNXT_MIN_FW_READY_TIMEOUT; 3803 bp->fw_reset_max_msecs = BNXT_MAX_FW_RESET_TIMEOUT; 3804 3805 /* To recover from error */ 3806 rte_eal_alarm_set(US_PER_MS, bnxt_dev_reset_and_resume, 3807 (void *)bp); 3808 } 3809 } 3810 3811 /* Driver should poll FW heartbeat, reset_counter with the frequency 3812 * advertised by FW in HWRM_ERROR_RECOVERY_QCFG. 3813 * When the driver detects heartbeat stop or change in reset_counter, 3814 * it has to trigger a reset to recover from the error condition. 3815 * A “master PF” is the function who will have the privilege to 3816 * initiate the chimp reset. The master PF will be elected by the 3817 * firmware and will be notified through async message. 3818 */ 3819 static void bnxt_check_fw_health(void *arg) 3820 { 3821 struct bnxt *bp = arg; 3822 struct bnxt_error_recovery_info *info = bp->recovery_info; 3823 uint32_t val = 0, wait_msec; 3824 3825 if (!info || !bnxt_is_recovery_enabled(bp) || 3826 is_bnxt_in_error(bp)) 3827 return; 3828 3829 val = bnxt_read_fw_status_reg(bp, BNXT_FW_HEARTBEAT_CNT_REG); 3830 if (val == info->last_heart_beat) 3831 goto reset; 3832 3833 info->last_heart_beat = val; 3834 3835 val = bnxt_read_fw_status_reg(bp, BNXT_FW_RECOVERY_CNT_REG); 3836 if (val != info->last_reset_counter) 3837 goto reset; 3838 3839 info->last_reset_counter = val; 3840 3841 rte_eal_alarm_set(US_PER_MS * info->driver_polling_freq, 3842 bnxt_check_fw_health, (void *)bp); 3843 3844 return; 3845 reset: 3846 /* Stop DMA to/from device */ 3847 bp->flags |= BNXT_FLAG_FATAL_ERROR; 3848 bp->flags |= BNXT_FLAG_FW_RESET; 3849 3850 PMD_DRV_LOG(ERR, "Detected FW dead condition\n"); 3851 3852 if (bnxt_is_master_func(bp)) 3853 wait_msec = info->master_func_wait_period; 3854 else 3855 wait_msec = info->normal_func_wait_period; 3856 3857 rte_eal_alarm_set(US_PER_MS * wait_msec, 3858 bnxt_fw_reset_cb, (void *)bp); 3859 } 3860 3861 void bnxt_schedule_fw_health_check(struct bnxt *bp) 3862 { 3863 uint32_t polling_freq; 3864 3865 if (!bnxt_is_recovery_enabled(bp)) 3866 return; 3867 3868 if (bp->flags & BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED) 3869 return; 3870 3871 polling_freq = bp->recovery_info->driver_polling_freq; 3872 3873 rte_eal_alarm_set(US_PER_MS * polling_freq, 3874 bnxt_check_fw_health, (void *)bp); 3875 bp->flags |= BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 3876 } 3877 3878 static void bnxt_cancel_fw_health_check(struct bnxt *bp) 3879 { 3880 if (!bnxt_is_recovery_enabled(bp)) 3881 return; 3882 3883 rte_eal_alarm_cancel(bnxt_check_fw_health, (void *)bp); 3884 bp->flags &= ~BNXT_FLAG_FW_HEALTH_CHECK_SCHEDULED; 3885 } 3886 3887 static bool bnxt_vf_pciid(uint16_t id) 3888 { 3889 if (id == BROADCOM_DEV_ID_57304_VF || 3890 id == BROADCOM_DEV_ID_57406_VF || 3891 id == BROADCOM_DEV_ID_5731X_VF || 3892 id == BROADCOM_DEV_ID_5741X_VF || 3893 id == BROADCOM_DEV_ID_57414_VF || 3894 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3895 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 || 3896 id == BROADCOM_DEV_ID_58802_VF || 3897 id == BROADCOM_DEV_ID_57500_VF1 || 3898 id == BROADCOM_DEV_ID_57500_VF2) 3899 return true; 3900 return false; 3901 } 3902 3903 bool bnxt_stratus_device(struct bnxt *bp) 3904 { 3905 uint16_t id = bp->pdev->id.device_id; 3906 3907 if (id == BROADCOM_DEV_ID_STRATUS_NIC || 3908 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3909 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2) 3910 return true; 3911 return false; 3912 } 3913 3914 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 3915 { 3916 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3917 struct bnxt *bp = eth_dev->data->dev_private; 3918 3919 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 3920 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 3921 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 3922 if (!bp->bar0 || !bp->doorbell_base) { 3923 PMD_DRV_LOG(ERR, "Unable to access Hardware\n"); 3924 return -ENODEV; 3925 } 3926 3927 bp->eth_dev = eth_dev; 3928 bp->pdev = pci_dev; 3929 3930 return 0; 3931 } 3932 3933 static int bnxt_alloc_ctx_mem_blk(__rte_unused struct bnxt *bp, 3934 struct bnxt_ctx_pg_info *ctx_pg, 3935 uint32_t mem_size, 3936 const char *suffix, 3937 uint16_t idx) 3938 { 3939 struct bnxt_ring_mem_info *rmem = &ctx_pg->ring_mem; 3940 const struct rte_memzone *mz = NULL; 3941 char mz_name[RTE_MEMZONE_NAMESIZE]; 3942 rte_iova_t mz_phys_addr; 3943 uint64_t valid_bits = 0; 3944 uint32_t sz; 3945 int i; 3946 3947 if (!mem_size) 3948 return 0; 3949 3950 rmem->nr_pages = RTE_ALIGN_MUL_CEIL(mem_size, BNXT_PAGE_SIZE) / 3951 BNXT_PAGE_SIZE; 3952 rmem->page_size = BNXT_PAGE_SIZE; 3953 rmem->pg_arr = ctx_pg->ctx_pg_arr; 3954 rmem->dma_arr = ctx_pg->ctx_dma_arr; 3955 rmem->flags = BNXT_RMEM_VALID_PTE_FLAG; 3956 3957 valid_bits = PTU_PTE_VALID; 3958 3959 if (rmem->nr_pages > 1) { 3960 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3961 "bnxt_ctx_pg_tbl%s_%x_%d", 3962 suffix, idx, bp->eth_dev->data->port_id); 3963 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3964 mz = rte_memzone_lookup(mz_name); 3965 if (!mz) { 3966 mz = rte_memzone_reserve_aligned(mz_name, 3967 rmem->nr_pages * 8, 3968 SOCKET_ID_ANY, 3969 RTE_MEMZONE_2MB | 3970 RTE_MEMZONE_SIZE_HINT_ONLY | 3971 RTE_MEMZONE_IOVA_CONTIG, 3972 BNXT_PAGE_SIZE); 3973 if (mz == NULL) 3974 return -ENOMEM; 3975 } 3976 3977 memset(mz->addr, 0, mz->len); 3978 mz_phys_addr = mz->iova; 3979 if ((unsigned long)mz->addr == mz_phys_addr) { 3980 PMD_DRV_LOG(DEBUG, 3981 "physical address same as virtual\n"); 3982 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 3983 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3984 if (mz_phys_addr == RTE_BAD_IOVA) { 3985 PMD_DRV_LOG(ERR, 3986 "unable to map addr to phys memory\n"); 3987 return -ENOMEM; 3988 } 3989 } 3990 rte_mem_lock_page(((char *)mz->addr)); 3991 3992 rmem->pg_tbl = mz->addr; 3993 rmem->pg_tbl_map = mz_phys_addr; 3994 rmem->pg_tbl_mz = mz; 3995 } 3996 3997 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, "bnxt_ctx_%s_%x_%d", 3998 suffix, idx, bp->eth_dev->data->port_id); 3999 mz = rte_memzone_lookup(mz_name); 4000 if (!mz) { 4001 mz = rte_memzone_reserve_aligned(mz_name, 4002 mem_size, 4003 SOCKET_ID_ANY, 4004 RTE_MEMZONE_1GB | 4005 RTE_MEMZONE_SIZE_HINT_ONLY | 4006 RTE_MEMZONE_IOVA_CONTIG, 4007 BNXT_PAGE_SIZE); 4008 if (mz == NULL) 4009 return -ENOMEM; 4010 } 4011 4012 memset(mz->addr, 0, mz->len); 4013 mz_phys_addr = mz->iova; 4014 if ((unsigned long)mz->addr == mz_phys_addr) { 4015 PMD_DRV_LOG(DEBUG, 4016 "Memzone physical address same as virtual.\n"); 4017 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4018 for (sz = 0; sz < mem_size; sz += BNXT_PAGE_SIZE) 4019 rte_mem_lock_page(((char *)mz->addr) + sz); 4020 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4021 if (mz_phys_addr == RTE_BAD_IOVA) { 4022 PMD_DRV_LOG(ERR, 4023 "unable to map addr to phys memory\n"); 4024 return -ENOMEM; 4025 } 4026 } 4027 4028 for (sz = 0, i = 0; sz < mem_size; sz += BNXT_PAGE_SIZE, i++) { 4029 rte_mem_lock_page(((char *)mz->addr) + sz); 4030 rmem->pg_arr[i] = ((char *)mz->addr) + sz; 4031 rmem->dma_arr[i] = mz_phys_addr + sz; 4032 4033 if (rmem->nr_pages > 1) { 4034 if (i == rmem->nr_pages - 2 && 4035 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4036 valid_bits |= PTU_PTE_NEXT_TO_LAST; 4037 else if (i == rmem->nr_pages - 1 && 4038 (rmem->flags & BNXT_RMEM_RING_PTE_FLAG)) 4039 valid_bits |= PTU_PTE_LAST; 4040 4041 rmem->pg_tbl[i] = rte_cpu_to_le_64(rmem->dma_arr[i] | 4042 valid_bits); 4043 } 4044 } 4045 4046 rmem->mz = mz; 4047 if (rmem->vmem_size) 4048 rmem->vmem = (void **)mz->addr; 4049 rmem->dma_arr[0] = mz_phys_addr; 4050 return 0; 4051 } 4052 4053 static void bnxt_free_ctx_mem(struct bnxt *bp) 4054 { 4055 int i; 4056 4057 if (!bp->ctx || !(bp->ctx->flags & BNXT_CTX_FLAG_INITED)) 4058 return; 4059 4060 bp->ctx->flags &= ~BNXT_CTX_FLAG_INITED; 4061 rte_memzone_free(bp->ctx->qp_mem.ring_mem.mz); 4062 rte_memzone_free(bp->ctx->srq_mem.ring_mem.mz); 4063 rte_memzone_free(bp->ctx->cq_mem.ring_mem.mz); 4064 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.mz); 4065 rte_memzone_free(bp->ctx->stat_mem.ring_mem.mz); 4066 rte_memzone_free(bp->ctx->qp_mem.ring_mem.pg_tbl_mz); 4067 rte_memzone_free(bp->ctx->srq_mem.ring_mem.pg_tbl_mz); 4068 rte_memzone_free(bp->ctx->cq_mem.ring_mem.pg_tbl_mz); 4069 rte_memzone_free(bp->ctx->vnic_mem.ring_mem.pg_tbl_mz); 4070 rte_memzone_free(bp->ctx->stat_mem.ring_mem.pg_tbl_mz); 4071 4072 for (i = 0; i < BNXT_MAX_Q; i++) { 4073 if (bp->ctx->tqm_mem[i]) 4074 rte_memzone_free(bp->ctx->tqm_mem[i]->ring_mem.mz); 4075 } 4076 4077 rte_free(bp->ctx); 4078 bp->ctx = NULL; 4079 } 4080 4081 #define bnxt_roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 4082 4083 #define min_t(type, x, y) ({ \ 4084 type __min1 = (x); \ 4085 type __min2 = (y); \ 4086 __min1 < __min2 ? __min1 : __min2; }) 4087 4088 #define max_t(type, x, y) ({ \ 4089 type __max1 = (x); \ 4090 type __max2 = (y); \ 4091 __max1 > __max2 ? __max1 : __max2; }) 4092 4093 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 4094 4095 int bnxt_alloc_ctx_mem(struct bnxt *bp) 4096 { 4097 struct bnxt_ctx_pg_info *ctx_pg; 4098 struct bnxt_ctx_mem_info *ctx; 4099 uint32_t mem_size, ena, entries; 4100 int i, rc; 4101 4102 rc = bnxt_hwrm_func_backing_store_qcaps(bp); 4103 if (rc) { 4104 PMD_DRV_LOG(ERR, "Query context mem capability failed\n"); 4105 return rc; 4106 } 4107 ctx = bp->ctx; 4108 if (!ctx || (ctx->flags & BNXT_CTX_FLAG_INITED)) 4109 return 0; 4110 4111 ctx_pg = &ctx->qp_mem; 4112 ctx_pg->entries = ctx->qp_min_qp1_entries + ctx->qp_max_l2_entries; 4113 mem_size = ctx->qp_entry_size * ctx_pg->entries; 4114 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "qp_mem", 0); 4115 if (rc) 4116 return rc; 4117 4118 ctx_pg = &ctx->srq_mem; 4119 ctx_pg->entries = ctx->srq_max_l2_entries; 4120 mem_size = ctx->srq_entry_size * ctx_pg->entries; 4121 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "srq_mem", 0); 4122 if (rc) 4123 return rc; 4124 4125 ctx_pg = &ctx->cq_mem; 4126 ctx_pg->entries = ctx->cq_max_l2_entries; 4127 mem_size = ctx->cq_entry_size * ctx_pg->entries; 4128 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "cq_mem", 0); 4129 if (rc) 4130 return rc; 4131 4132 ctx_pg = &ctx->vnic_mem; 4133 ctx_pg->entries = ctx->vnic_max_vnic_entries + 4134 ctx->vnic_max_ring_table_entries; 4135 mem_size = ctx->vnic_entry_size * ctx_pg->entries; 4136 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "vnic_mem", 0); 4137 if (rc) 4138 return rc; 4139 4140 ctx_pg = &ctx->stat_mem; 4141 ctx_pg->entries = ctx->stat_max_entries; 4142 mem_size = ctx->stat_entry_size * ctx_pg->entries; 4143 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "stat_mem", 0); 4144 if (rc) 4145 return rc; 4146 4147 entries = ctx->qp_max_l2_entries; 4148 entries = bnxt_roundup(entries, ctx->tqm_entries_multiple); 4149 entries = clamp_t(uint32_t, entries, ctx->tqm_min_entries_per_ring, 4150 ctx->tqm_max_entries_per_ring); 4151 for (i = 0, ena = 0; i < BNXT_MAX_Q; i++) { 4152 ctx_pg = ctx->tqm_mem[i]; 4153 /* use min tqm entries for now. */ 4154 ctx_pg->entries = entries; 4155 mem_size = ctx->tqm_entry_size * ctx_pg->entries; 4156 rc = bnxt_alloc_ctx_mem_blk(bp, ctx_pg, mem_size, "tqm_mem", i); 4157 if (rc) 4158 return rc; 4159 ena |= HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_SP << i; 4160 } 4161 4162 ena |= FUNC_BACKING_STORE_CFG_INPUT_DFLT_ENABLES; 4163 rc = bnxt_hwrm_func_backing_store_cfg(bp, ena); 4164 if (rc) 4165 PMD_DRV_LOG(ERR, 4166 "Failed to configure context mem: rc = %d\n", rc); 4167 else 4168 ctx->flags |= BNXT_CTX_FLAG_INITED; 4169 4170 return rc; 4171 } 4172 4173 static int bnxt_alloc_stats_mem(struct bnxt *bp) 4174 { 4175 struct rte_pci_device *pci_dev = bp->pdev; 4176 char mz_name[RTE_MEMZONE_NAMESIZE]; 4177 const struct rte_memzone *mz = NULL; 4178 uint32_t total_alloc_len; 4179 rte_iova_t mz_phys_addr; 4180 4181 if (pci_dev->id.device_id == BROADCOM_DEV_ID_NS2) 4182 return 0; 4183 4184 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4185 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4186 pci_dev->addr.bus, pci_dev->addr.devid, 4187 pci_dev->addr.function, "rx_port_stats"); 4188 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4189 mz = rte_memzone_lookup(mz_name); 4190 total_alloc_len = 4191 RTE_CACHE_LINE_ROUNDUP(sizeof(struct rx_port_stats) + 4192 sizeof(struct rx_port_stats_ext) + 512); 4193 if (!mz) { 4194 mz = rte_memzone_reserve(mz_name, total_alloc_len, 4195 SOCKET_ID_ANY, 4196 RTE_MEMZONE_2MB | 4197 RTE_MEMZONE_SIZE_HINT_ONLY | 4198 RTE_MEMZONE_IOVA_CONTIG); 4199 if (mz == NULL) 4200 return -ENOMEM; 4201 } 4202 memset(mz->addr, 0, mz->len); 4203 mz_phys_addr = mz->iova; 4204 if ((unsigned long)mz->addr == mz_phys_addr) { 4205 PMD_DRV_LOG(DEBUG, 4206 "Memzone physical address same as virtual.\n"); 4207 PMD_DRV_LOG(DEBUG, 4208 "Using rte_mem_virt2iova()\n"); 4209 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4210 if (mz_phys_addr == RTE_BAD_IOVA) { 4211 PMD_DRV_LOG(ERR, 4212 "Can't map address to physical memory\n"); 4213 return -ENOMEM; 4214 } 4215 } 4216 4217 bp->rx_mem_zone = (const void *)mz; 4218 bp->hw_rx_port_stats = mz->addr; 4219 bp->hw_rx_port_stats_map = mz_phys_addr; 4220 4221 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 4222 "bnxt_" PCI_PRI_FMT "-%s", pci_dev->addr.domain, 4223 pci_dev->addr.bus, pci_dev->addr.devid, 4224 pci_dev->addr.function, "tx_port_stats"); 4225 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 4226 mz = rte_memzone_lookup(mz_name); 4227 total_alloc_len = 4228 RTE_CACHE_LINE_ROUNDUP(sizeof(struct tx_port_stats) + 4229 sizeof(struct tx_port_stats_ext) + 512); 4230 if (!mz) { 4231 mz = rte_memzone_reserve(mz_name, 4232 total_alloc_len, 4233 SOCKET_ID_ANY, 4234 RTE_MEMZONE_2MB | 4235 RTE_MEMZONE_SIZE_HINT_ONLY | 4236 RTE_MEMZONE_IOVA_CONTIG); 4237 if (mz == NULL) 4238 return -ENOMEM; 4239 } 4240 memset(mz->addr, 0, mz->len); 4241 mz_phys_addr = mz->iova; 4242 if ((unsigned long)mz->addr == mz_phys_addr) { 4243 PMD_DRV_LOG(DEBUG, 4244 "Memzone physical address same as virtual\n"); 4245 PMD_DRV_LOG(DEBUG, "Using rte_mem_virt2iova()\n"); 4246 mz_phys_addr = rte_mem_virt2iova(mz->addr); 4247 if (mz_phys_addr == RTE_BAD_IOVA) { 4248 PMD_DRV_LOG(ERR, 4249 "Can't map address to physical memory\n"); 4250 return -ENOMEM; 4251 } 4252 } 4253 4254 bp->tx_mem_zone = (const void *)mz; 4255 bp->hw_tx_port_stats = mz->addr; 4256 bp->hw_tx_port_stats_map = mz_phys_addr; 4257 bp->flags |= BNXT_FLAG_PORT_STATS; 4258 4259 /* Display extended statistics if FW supports it */ 4260 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 4261 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0 || 4262 !(bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED)) 4263 return 0; 4264 4265 bp->hw_rx_port_stats_ext = (void *) 4266 ((uint8_t *)bp->hw_rx_port_stats + 4267 sizeof(struct rx_port_stats)); 4268 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 4269 sizeof(struct rx_port_stats); 4270 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 4271 4272 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2 || 4273 bp->flags & BNXT_FLAG_EXT_STATS_SUPPORTED) { 4274 bp->hw_tx_port_stats_ext = (void *) 4275 ((uint8_t *)bp->hw_tx_port_stats + 4276 sizeof(struct tx_port_stats)); 4277 bp->hw_tx_port_stats_ext_map = 4278 bp->hw_tx_port_stats_map + 4279 sizeof(struct tx_port_stats); 4280 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 4281 } 4282 4283 return 0; 4284 } 4285 4286 static int bnxt_setup_mac_addr(struct rte_eth_dev *eth_dev) 4287 { 4288 struct bnxt *bp = eth_dev->data->dev_private; 4289 int rc = 0; 4290 4291 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 4292 RTE_ETHER_ADDR_LEN * 4293 bp->max_l2_ctx, 4294 0); 4295 if (eth_dev->data->mac_addrs == NULL) { 4296 PMD_DRV_LOG(ERR, "Failed to alloc MAC addr tbl\n"); 4297 return -ENOMEM; 4298 } 4299 4300 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) { 4301 if (BNXT_PF(bp)) 4302 return -EINVAL; 4303 4304 /* Generate a random MAC address, if none was assigned by PF */ 4305 PMD_DRV_LOG(INFO, "VF MAC address not assigned by Host PF\n"); 4306 bnxt_eth_hw_addr_random(bp->mac_addr); 4307 PMD_DRV_LOG(INFO, 4308 "Assign random MAC:%02X:%02X:%02X:%02X:%02X:%02X\n", 4309 bp->mac_addr[0], bp->mac_addr[1], bp->mac_addr[2], 4310 bp->mac_addr[3], bp->mac_addr[4], bp->mac_addr[5]); 4311 4312 rc = bnxt_hwrm_set_mac(bp); 4313 if (!rc) 4314 memcpy(&bp->eth_dev->data->mac_addrs[0], bp->mac_addr, 4315 RTE_ETHER_ADDR_LEN); 4316 return rc; 4317 } 4318 4319 /* Copy the permanent MAC from the FUNC_QCAPS response */ 4320 memcpy(bp->mac_addr, bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN); 4321 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 4322 4323 return rc; 4324 } 4325 4326 static int bnxt_restore_dflt_mac(struct bnxt *bp) 4327 { 4328 int rc = 0; 4329 4330 /* MAC is already configured in FW */ 4331 if (!bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) 4332 return 0; 4333 4334 /* Restore the old MAC configured */ 4335 rc = bnxt_hwrm_set_mac(bp); 4336 if (rc) 4337 PMD_DRV_LOG(ERR, "Failed to restore MAC address\n"); 4338 4339 return rc; 4340 } 4341 4342 static void bnxt_config_vf_req_fwd(struct bnxt *bp) 4343 { 4344 if (!BNXT_PF(bp)) 4345 return; 4346 4347 #define ALLOW_FUNC(x) \ 4348 { \ 4349 uint32_t arg = (x); \ 4350 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 4351 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 4352 } 4353 4354 /* Forward all requests if firmware is new enough */ 4355 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 4356 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 4357 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 4358 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 4359 } else { 4360 PMD_DRV_LOG(WARNING, 4361 "Firmware too old for VF mailbox functionality\n"); 4362 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 4363 } 4364 4365 /* 4366 * The following are used for driver cleanup. If we disallow these, 4367 * VF drivers can't clean up cleanly. 4368 */ 4369 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 4370 ALLOW_FUNC(HWRM_VNIC_FREE); 4371 ALLOW_FUNC(HWRM_RING_FREE); 4372 ALLOW_FUNC(HWRM_RING_GRP_FREE); 4373 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 4374 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 4375 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 4376 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 4377 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 4378 } 4379 4380 static int bnxt_init_fw(struct bnxt *bp) 4381 { 4382 uint16_t mtu; 4383 int rc = 0; 4384 4385 rc = bnxt_hwrm_ver_get(bp); 4386 if (rc) 4387 return rc; 4388 4389 rc = bnxt_hwrm_func_reset(bp); 4390 if (rc) 4391 return -EIO; 4392 4393 rc = bnxt_hwrm_queue_qportcfg(bp); 4394 if (rc) 4395 return rc; 4396 4397 /* Get the MAX capabilities for this function */ 4398 rc = bnxt_hwrm_func_qcaps(bp); 4399 if (rc) 4400 return rc; 4401 4402 rc = bnxt_hwrm_func_qcfg(bp, &mtu); 4403 if (rc) 4404 return rc; 4405 4406 /* Get the adapter error recovery support info */ 4407 rc = bnxt_hwrm_error_recovery_qcfg(bp); 4408 if (rc) 4409 bp->flags &= ~BNXT_FLAG_FW_CAP_ERROR_RECOVERY; 4410 4411 if (mtu >= RTE_ETHER_MIN_MTU && mtu <= BNXT_MAX_MTU && 4412 mtu != bp->eth_dev->data->mtu) 4413 bp->eth_dev->data->mtu = mtu; 4414 4415 bnxt_hwrm_port_led_qcaps(bp); 4416 4417 return 0; 4418 } 4419 4420 static int bnxt_init_resources(struct bnxt *bp, bool reconfig_dev) 4421 { 4422 int rc; 4423 4424 rc = bnxt_init_fw(bp); 4425 if (rc) 4426 return rc; 4427 4428 if (!reconfig_dev) { 4429 rc = bnxt_setup_mac_addr(bp->eth_dev); 4430 if (rc) 4431 return rc; 4432 } else { 4433 rc = bnxt_restore_dflt_mac(bp); 4434 if (rc) 4435 return rc; 4436 } 4437 4438 bnxt_config_vf_req_fwd(bp); 4439 4440 rc = bnxt_hwrm_func_driver_register(bp); 4441 if (rc) { 4442 PMD_DRV_LOG(ERR, "Failed to register driver"); 4443 return -EBUSY; 4444 } 4445 4446 if (BNXT_PF(bp)) { 4447 if (bp->pdev->max_vfs) { 4448 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 4449 if (rc) { 4450 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 4451 return rc; 4452 } 4453 } else { 4454 rc = bnxt_hwrm_allocate_pf_only(bp); 4455 if (rc) { 4456 PMD_DRV_LOG(ERR, 4457 "Failed to allocate PF resources"); 4458 return rc; 4459 } 4460 } 4461 } 4462 4463 rc = bnxt_alloc_mem(bp, reconfig_dev); 4464 if (rc) 4465 return rc; 4466 4467 rc = bnxt_setup_int(bp); 4468 if (rc) 4469 return rc; 4470 4471 bnxt_init_nic(bp); 4472 4473 rc = bnxt_request_int(bp); 4474 if (rc) 4475 return rc; 4476 4477 return 0; 4478 } 4479 4480 static int 4481 bnxt_dev_init(struct rte_eth_dev *eth_dev) 4482 { 4483 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 4484 static int version_printed; 4485 struct bnxt *bp; 4486 int rc; 4487 4488 if (version_printed++ == 0) 4489 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 4490 4491 rte_eth_copy_pci_info(eth_dev, pci_dev); 4492 4493 bp = eth_dev->data->dev_private; 4494 4495 bp->dev_stopped = 1; 4496 4497 eth_dev->dev_ops = &bnxt_dev_ops; 4498 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 4499 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 4500 4501 /* 4502 * For secondary processes, we don't initialise any further 4503 * as primary has already done this work. 4504 */ 4505 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4506 return 0; 4507 4508 if (bnxt_vf_pciid(pci_dev->id.device_id)) 4509 bp->flags |= BNXT_FLAG_VF; 4510 4511 if (pci_dev->id.device_id == BROADCOM_DEV_ID_57508 || 4512 pci_dev->id.device_id == BROADCOM_DEV_ID_57504 || 4513 pci_dev->id.device_id == BROADCOM_DEV_ID_57502 || 4514 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF1 || 4515 pci_dev->id.device_id == BROADCOM_DEV_ID_57500_VF2) 4516 bp->flags |= BNXT_FLAG_THOR_CHIP; 4517 4518 if (pci_dev->id.device_id == BROADCOM_DEV_ID_58802 || 4519 pci_dev->id.device_id == BROADCOM_DEV_ID_58804 || 4520 pci_dev->id.device_id == BROADCOM_DEV_ID_58808 || 4521 pci_dev->id.device_id == BROADCOM_DEV_ID_58802_VF) 4522 bp->flags |= BNXT_FLAG_STINGRAY; 4523 4524 rc = bnxt_init_board(eth_dev); 4525 if (rc) { 4526 PMD_DRV_LOG(ERR, 4527 "Failed to initialize board rc: %x\n", rc); 4528 return rc; 4529 } 4530 4531 rc = bnxt_alloc_hwrm_resources(bp); 4532 if (rc) { 4533 PMD_DRV_LOG(ERR, 4534 "Failed to allocate hwrm resource rc: %x\n", rc); 4535 goto error_free; 4536 } 4537 rc = bnxt_init_resources(bp, false); 4538 if (rc) 4539 goto error_free; 4540 4541 rc = bnxt_alloc_stats_mem(bp); 4542 if (rc) 4543 goto error_free; 4544 4545 PMD_DRV_LOG(INFO, 4546 DRV_MODULE_NAME "found at mem %" PRIX64 ", node addr %pM\n", 4547 pci_dev->mem_resource[0].phys_addr, 4548 pci_dev->mem_resource[0].addr); 4549 4550 return 0; 4551 4552 error_free: 4553 bnxt_dev_uninit(eth_dev); 4554 return rc; 4555 } 4556 4557 static int 4558 bnxt_uninit_resources(struct bnxt *bp, bool reconfig_dev) 4559 { 4560 int rc; 4561 4562 bnxt_free_int(bp); 4563 bnxt_free_mem(bp, reconfig_dev); 4564 bnxt_hwrm_func_buf_unrgtr(bp); 4565 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 4566 bp->flags &= ~BNXT_FLAG_REGISTERED; 4567 bnxt_free_ctx_mem(bp); 4568 if (!reconfig_dev) { 4569 bnxt_free_hwrm_resources(bp); 4570 4571 if (bp->recovery_info != NULL) { 4572 rte_free(bp->recovery_info); 4573 bp->recovery_info = NULL; 4574 } 4575 } 4576 4577 rte_free(bp->ptp_cfg); 4578 bp->ptp_cfg = NULL; 4579 return rc; 4580 } 4581 4582 static int 4583 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 4584 { 4585 struct bnxt *bp = eth_dev->data->dev_private; 4586 int rc; 4587 4588 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 4589 return -EPERM; 4590 4591 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 4592 4593 rc = bnxt_uninit_resources(bp, false); 4594 4595 if (bp->grp_info != NULL) { 4596 rte_free(bp->grp_info); 4597 bp->grp_info = NULL; 4598 } 4599 4600 if (bp->tx_mem_zone) { 4601 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 4602 bp->tx_mem_zone = NULL; 4603 } 4604 4605 if (bp->rx_mem_zone) { 4606 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 4607 bp->rx_mem_zone = NULL; 4608 } 4609 4610 if (bp->dev_stopped == 0) 4611 bnxt_dev_close_op(eth_dev); 4612 if (bp->pf.vf_info) 4613 rte_free(bp->pf.vf_info); 4614 eth_dev->dev_ops = NULL; 4615 eth_dev->rx_pkt_burst = NULL; 4616 eth_dev->tx_pkt_burst = NULL; 4617 4618 return rc; 4619 } 4620 4621 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 4622 struct rte_pci_device *pci_dev) 4623 { 4624 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 4625 bnxt_dev_init); 4626 } 4627 4628 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 4629 { 4630 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 4631 return rte_eth_dev_pci_generic_remove(pci_dev, 4632 bnxt_dev_uninit); 4633 else 4634 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 4635 } 4636 4637 static struct rte_pci_driver bnxt_rte_pmd = { 4638 .id_table = bnxt_pci_id_map, 4639 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC, 4640 .probe = bnxt_pci_probe, 4641 .remove = bnxt_pci_remove, 4642 }; 4643 4644 static bool 4645 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 4646 { 4647 if (strcmp(dev->device->driver->name, drv->driver.name)) 4648 return false; 4649 4650 return true; 4651 } 4652 4653 bool is_bnxt_supported(struct rte_eth_dev *dev) 4654 { 4655 return is_device_supported(dev, &bnxt_rte_pmd); 4656 } 4657 4658 RTE_INIT(bnxt_init_log) 4659 { 4660 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 4661 if (bnxt_logtype_driver >= 0) 4662 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 4663 } 4664 4665 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 4666 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 4667 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 4668