1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2014-2018 Broadcom 3 * All rights reserved. 4 */ 5 6 #include <inttypes.h> 7 #include <stdbool.h> 8 9 #include <rte_dev.h> 10 #include <rte_ethdev_driver.h> 11 #include <rte_ethdev_pci.h> 12 #include <rte_malloc.h> 13 #include <rte_cycles.h> 14 15 #include "bnxt.h" 16 #include "bnxt_cpr.h" 17 #include "bnxt_filter.h" 18 #include "bnxt_hwrm.h" 19 #include "bnxt_irq.h" 20 #include "bnxt_ring.h" 21 #include "bnxt_rxq.h" 22 #include "bnxt_rxr.h" 23 #include "bnxt_stats.h" 24 #include "bnxt_txq.h" 25 #include "bnxt_txr.h" 26 #include "bnxt_vnic.h" 27 #include "hsi_struct_def_dpdk.h" 28 #include "bnxt_nvm_defs.h" 29 #include "bnxt_util.h" 30 31 #define DRV_MODULE_NAME "bnxt" 32 static const char bnxt_version[] = 33 "Broadcom NetXtreme driver " DRV_MODULE_NAME; 34 int bnxt_logtype_driver; 35 36 #define PCI_VENDOR_ID_BROADCOM 0x14E4 37 38 #define BROADCOM_DEV_ID_STRATUS_NIC_VF1 0x1606 39 #define BROADCOM_DEV_ID_STRATUS_NIC_VF2 0x1609 40 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 41 #define BROADCOM_DEV_ID_57414_VF 0x16c1 42 #define BROADCOM_DEV_ID_57301 0x16c8 43 #define BROADCOM_DEV_ID_57302 0x16c9 44 #define BROADCOM_DEV_ID_57304_PF 0x16ca 45 #define BROADCOM_DEV_ID_57304_VF 0x16cb 46 #define BROADCOM_DEV_ID_57417_MF 0x16cc 47 #define BROADCOM_DEV_ID_NS2 0x16cd 48 #define BROADCOM_DEV_ID_57311 0x16ce 49 #define BROADCOM_DEV_ID_57312 0x16cf 50 #define BROADCOM_DEV_ID_57402 0x16d0 51 #define BROADCOM_DEV_ID_57404 0x16d1 52 #define BROADCOM_DEV_ID_57406_PF 0x16d2 53 #define BROADCOM_DEV_ID_57406_VF 0x16d3 54 #define BROADCOM_DEV_ID_57402_MF 0x16d4 55 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 56 #define BROADCOM_DEV_ID_57412 0x16d6 57 #define BROADCOM_DEV_ID_57414 0x16d7 58 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 59 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 60 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 61 #define BROADCOM_DEV_ID_57412_MF 0x16de 62 #define BROADCOM_DEV_ID_57314 0x16df 63 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 64 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 65 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 66 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 67 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 68 #define BROADCOM_DEV_ID_57404_MF 0x16e7 69 #define BROADCOM_DEV_ID_57406_MF 0x16e8 70 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 71 #define BROADCOM_DEV_ID_57407_MF 0x16ea 72 #define BROADCOM_DEV_ID_57414_MF 0x16ec 73 #define BROADCOM_DEV_ID_57416_MF 0x16ee 74 #define BROADCOM_DEV_ID_58802 0xd802 75 #define BROADCOM_DEV_ID_58804 0xd804 76 #define BROADCOM_DEV_ID_58808 0x16f0 77 #define BROADCOM_DEV_ID_58802_VF 0xd800 78 79 static const struct rte_pci_id bnxt_pci_id_map[] = { 80 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 81 BROADCOM_DEV_ID_STRATUS_NIC_VF1) }, 82 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 83 BROADCOM_DEV_ID_STRATUS_NIC_VF2) }, 84 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 85 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 86 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 87 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 88 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 89 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 90 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 91 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 92 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 93 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 94 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 95 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 96 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 97 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 98 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 99 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 100 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 102 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58804) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58808) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_58802_VF) }, 122 { .vendor_id = 0, /* sentinel */ }, 123 }; 124 125 #define BNXT_ETH_RSS_SUPPORT ( \ 126 ETH_RSS_IPV4 | \ 127 ETH_RSS_NONFRAG_IPV4_TCP | \ 128 ETH_RSS_NONFRAG_IPV4_UDP | \ 129 ETH_RSS_IPV6 | \ 130 ETH_RSS_NONFRAG_IPV6_TCP | \ 131 ETH_RSS_NONFRAG_IPV6_UDP) 132 133 #define BNXT_DEV_TX_OFFLOAD_SUPPORT (DEV_TX_OFFLOAD_VLAN_INSERT | \ 134 DEV_TX_OFFLOAD_IPV4_CKSUM | \ 135 DEV_TX_OFFLOAD_TCP_CKSUM | \ 136 DEV_TX_OFFLOAD_UDP_CKSUM | \ 137 DEV_TX_OFFLOAD_TCP_TSO | \ 138 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | \ 139 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | \ 140 DEV_TX_OFFLOAD_GRE_TNL_TSO | \ 141 DEV_TX_OFFLOAD_IPIP_TNL_TSO | \ 142 DEV_TX_OFFLOAD_GENEVE_TNL_TSO | \ 143 DEV_TX_OFFLOAD_MULTI_SEGS) 144 145 #define BNXT_DEV_RX_OFFLOAD_SUPPORT (DEV_RX_OFFLOAD_VLAN_FILTER | \ 146 DEV_RX_OFFLOAD_VLAN_STRIP | \ 147 DEV_RX_OFFLOAD_IPV4_CKSUM | \ 148 DEV_RX_OFFLOAD_UDP_CKSUM | \ 149 DEV_RX_OFFLOAD_TCP_CKSUM | \ 150 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM | \ 151 DEV_RX_OFFLOAD_JUMBO_FRAME | \ 152 DEV_RX_OFFLOAD_KEEP_CRC | \ 153 DEV_RX_OFFLOAD_TCP_LRO) 154 155 static int bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 156 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev); 157 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu); 158 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 159 160 /***********************/ 161 162 /* 163 * High level utility functions 164 */ 165 166 static void bnxt_free_mem(struct bnxt *bp) 167 { 168 bnxt_free_filter_mem(bp); 169 bnxt_free_vnic_attributes(bp); 170 bnxt_free_vnic_mem(bp); 171 172 bnxt_free_stats(bp); 173 bnxt_free_tx_rings(bp); 174 bnxt_free_rx_rings(bp); 175 } 176 177 static int bnxt_alloc_mem(struct bnxt *bp) 178 { 179 int rc; 180 181 rc = bnxt_alloc_vnic_mem(bp); 182 if (rc) 183 goto alloc_mem_err; 184 185 rc = bnxt_alloc_vnic_attributes(bp); 186 if (rc) 187 goto alloc_mem_err; 188 189 rc = bnxt_alloc_filter_mem(bp); 190 if (rc) 191 goto alloc_mem_err; 192 193 return 0; 194 195 alloc_mem_err: 196 bnxt_free_mem(bp); 197 return rc; 198 } 199 200 static int bnxt_init_chip(struct bnxt *bp) 201 { 202 struct bnxt_rx_queue *rxq; 203 struct rte_eth_link new; 204 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 205 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 207 uint64_t rx_offloads = dev_conf->rxmode.offloads; 208 uint32_t intr_vector = 0; 209 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 210 uint32_t vec = BNXT_MISC_VEC_ID; 211 unsigned int i, j; 212 int rc; 213 214 /* disable uio/vfio intr/eventfd mapping */ 215 rte_intr_disable(intr_handle); 216 217 if (bp->eth_dev->data->mtu > RTE_ETHER_MTU) { 218 bp->eth_dev->data->dev_conf.rxmode.offloads |= 219 DEV_RX_OFFLOAD_JUMBO_FRAME; 220 bp->flags |= BNXT_FLAG_JUMBO; 221 } else { 222 bp->eth_dev->data->dev_conf.rxmode.offloads &= 223 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 224 bp->flags &= ~BNXT_FLAG_JUMBO; 225 } 226 227 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 228 if (rc) { 229 PMD_DRV_LOG(ERR, "HWRM stat ctx alloc failure rc: %x\n", rc); 230 goto err_out; 231 } 232 233 rc = bnxt_alloc_hwrm_rings(bp); 234 if (rc) { 235 PMD_DRV_LOG(ERR, "HWRM ring alloc failure rc: %x\n", rc); 236 goto err_out; 237 } 238 239 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 240 if (rc) { 241 PMD_DRV_LOG(ERR, "HWRM ring grp alloc failure: %x\n", rc); 242 goto err_out; 243 } 244 245 rc = bnxt_mq_rx_configure(bp); 246 if (rc) { 247 PMD_DRV_LOG(ERR, "MQ mode configure failure rc: %x\n", rc); 248 goto err_out; 249 } 250 251 /* VNIC configuration */ 252 for (i = 0; i < bp->nr_vnics; i++) { 253 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 254 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 255 uint32_t size = sizeof(*vnic->fw_grp_ids) * bp->max_ring_grps; 256 257 vnic->fw_grp_ids = rte_zmalloc("vnic_fw_grp_ids", size, 0); 258 if (!vnic->fw_grp_ids) { 259 PMD_DRV_LOG(ERR, 260 "Failed to alloc %d bytes for group ids\n", 261 size); 262 rc = -ENOMEM; 263 goto err_out; 264 } 265 memset(vnic->fw_grp_ids, -1, size); 266 267 PMD_DRV_LOG(DEBUG, "vnic[%d] = %p vnic->fw_grp_ids = %p\n", 268 i, vnic, vnic->fw_grp_ids); 269 270 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 271 if (rc) { 272 PMD_DRV_LOG(ERR, "HWRM vnic %d alloc failure rc: %x\n", 273 i, rc); 274 goto err_out; 275 } 276 277 /* Alloc RSS context only if RSS mode is enabled */ 278 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS) { 279 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic); 280 if (rc) { 281 PMD_DRV_LOG(ERR, 282 "HWRM vnic %d ctx alloc failure rc: %x\n", 283 i, rc); 284 goto err_out; 285 } 286 } 287 288 /* 289 * Firmware sets pf pair in default vnic cfg. If the VLAN strip 290 * setting is not available at this time, it will not be 291 * configured correctly in the CFA. 292 */ 293 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 294 vnic->vlan_strip = true; 295 else 296 vnic->vlan_strip = false; 297 298 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 299 if (rc) { 300 PMD_DRV_LOG(ERR, "HWRM vnic %d cfg failure rc: %x\n", 301 i, rc); 302 goto err_out; 303 } 304 305 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 306 if (rc) { 307 PMD_DRV_LOG(ERR, 308 "HWRM vnic %d filter failure rc: %x\n", 309 i, rc); 310 goto err_out; 311 } 312 313 for (j = 0; j < bp->rx_nr_rings; j++) { 314 rxq = bp->eth_dev->data->rx_queues[j]; 315 316 PMD_DRV_LOG(DEBUG, 317 "rxq[%d]->vnic=%p vnic->fw_grp_ids=%p\n", 318 j, rxq->vnic, rxq->vnic->fw_grp_ids); 319 320 if (rxq->rx_deferred_start) 321 rxq->vnic->fw_grp_ids[j] = INVALID_HW_RING_ID; 322 } 323 324 rc = bnxt_vnic_rss_configure(bp, vnic); 325 if (rc) { 326 PMD_DRV_LOG(ERR, 327 "HWRM vnic set RSS failure rc: %x\n", rc); 328 goto err_out; 329 } 330 331 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 332 333 if (bp->eth_dev->data->dev_conf.rxmode.offloads & 334 DEV_RX_OFFLOAD_TCP_LRO) 335 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 336 else 337 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 338 } 339 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 340 if (rc) { 341 PMD_DRV_LOG(ERR, 342 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 343 goto err_out; 344 } 345 346 /* check and configure queue intr-vector mapping */ 347 if ((rte_intr_cap_multiple(intr_handle) || 348 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 349 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 350 intr_vector = bp->eth_dev->data->nb_rx_queues; 351 PMD_DRV_LOG(DEBUG, "intr_vector = %d\n", intr_vector); 352 if (intr_vector > bp->rx_cp_nr_rings) { 353 PMD_DRV_LOG(ERR, "At most %d intr queues supported", 354 bp->rx_cp_nr_rings); 355 return -ENOTSUP; 356 } 357 if (rte_intr_efd_enable(intr_handle, intr_vector)) 358 return -1; 359 } 360 361 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 362 intr_handle->intr_vec = 363 rte_zmalloc("intr_vec", 364 bp->eth_dev->data->nb_rx_queues * 365 sizeof(int), 0); 366 if (intr_handle->intr_vec == NULL) { 367 PMD_DRV_LOG(ERR, "Failed to allocate %d rx_queues" 368 " intr_vec", bp->eth_dev->data->nb_rx_queues); 369 return -ENOMEM; 370 } 371 PMD_DRV_LOG(DEBUG, "intr_handle->intr_vec = %p " 372 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 373 intr_handle->intr_vec, intr_handle->nb_efd, 374 intr_handle->max_intr); 375 } 376 377 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 378 queue_id++) { 379 intr_handle->intr_vec[queue_id] = vec; 380 if (vec < base + intr_handle->nb_efd - 1) 381 vec++; 382 } 383 384 /* enable uio/vfio intr/eventfd mapping */ 385 rte_intr_enable(intr_handle); 386 387 rc = bnxt_get_hwrm_link_config(bp, &new); 388 if (rc) { 389 PMD_DRV_LOG(ERR, "HWRM Get link config failure rc: %x\n", rc); 390 goto err_out; 391 } 392 393 if (!bp->link_info.link_up) { 394 rc = bnxt_set_hwrm_link_config(bp, true); 395 if (rc) { 396 PMD_DRV_LOG(ERR, 397 "HWRM link config failure rc: %x\n", rc); 398 goto err_out; 399 } 400 } 401 bnxt_print_link_info(bp->eth_dev); 402 403 return 0; 404 405 err_out: 406 bnxt_free_all_hwrm_resources(bp); 407 408 /* Some of the error status returned by FW may not be from errno.h */ 409 if (rc > 0) 410 rc = -EIO; 411 412 return rc; 413 } 414 415 static int bnxt_shutdown_nic(struct bnxt *bp) 416 { 417 bnxt_free_all_hwrm_resources(bp); 418 bnxt_free_all_filters(bp); 419 bnxt_free_all_vnics(bp); 420 return 0; 421 } 422 423 static int bnxt_init_nic(struct bnxt *bp) 424 { 425 int rc; 426 427 rc = bnxt_init_ring_grps(bp); 428 if (rc) 429 return rc; 430 431 bnxt_init_vnics(bp); 432 bnxt_init_filters(bp); 433 434 return 0; 435 } 436 437 /* 438 * Device configuration and status function 439 */ 440 441 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 442 struct rte_eth_dev_info *dev_info) 443 { 444 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 445 uint16_t max_vnics, i, j, vpool, vrxq; 446 unsigned int max_rx_rings; 447 448 /* MAC Specifics */ 449 dev_info->max_mac_addrs = bp->max_l2_ctx; 450 dev_info->max_hash_mac_addrs = 0; 451 452 /* PF/VF specifics */ 453 if (BNXT_PF(bp)) 454 dev_info->max_vfs = bp->pdev->max_vfs; 455 max_rx_rings = RTE_MIN(bp->max_vnics, bp->max_stat_ctx); 456 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 457 dev_info->max_rx_queues = max_rx_rings; 458 dev_info->max_tx_queues = max_rx_rings; 459 dev_info->reta_size = HW_HASH_INDEX_SIZE; 460 dev_info->hash_key_size = 40; 461 max_vnics = bp->max_vnics; 462 463 /* Fast path specifics */ 464 dev_info->min_rx_bufsize = 1; 465 dev_info->max_rx_pktlen = BNXT_MAX_MTU + RTE_ETHER_HDR_LEN + 466 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 467 468 dev_info->rx_offload_capa = BNXT_DEV_RX_OFFLOAD_SUPPORT; 469 if (bp->flags & BNXT_FLAG_PTP_SUPPORTED) 470 dev_info->rx_offload_capa |= DEV_RX_OFFLOAD_TIMESTAMP; 471 dev_info->tx_offload_capa = BNXT_DEV_TX_OFFLOAD_SUPPORT; 472 dev_info->flow_type_rss_offloads = BNXT_ETH_RSS_SUPPORT; 473 474 /* *INDENT-OFF* */ 475 dev_info->default_rxconf = (struct rte_eth_rxconf) { 476 .rx_thresh = { 477 .pthresh = 8, 478 .hthresh = 8, 479 .wthresh = 0, 480 }, 481 .rx_free_thresh = 32, 482 /* If no descriptors available, pkts are dropped by default */ 483 .rx_drop_en = 1, 484 }; 485 486 dev_info->default_txconf = (struct rte_eth_txconf) { 487 .tx_thresh = { 488 .pthresh = 32, 489 .hthresh = 0, 490 .wthresh = 0, 491 }, 492 .tx_free_thresh = 32, 493 .tx_rs_thresh = 32, 494 }; 495 eth_dev->data->dev_conf.intr_conf.lsc = 1; 496 497 eth_dev->data->dev_conf.intr_conf.rxq = 1; 498 dev_info->rx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 499 dev_info->rx_desc_lim.nb_max = BNXT_MAX_RX_RING_DESC; 500 dev_info->tx_desc_lim.nb_min = BNXT_MIN_RING_DESC; 501 dev_info->tx_desc_lim.nb_max = BNXT_MAX_TX_RING_DESC; 502 503 /* *INDENT-ON* */ 504 505 /* 506 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 507 * need further investigation. 508 */ 509 510 /* VMDq resources */ 511 vpool = 64; /* ETH_64_POOLS */ 512 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 513 for (i = 0; i < 4; vpool >>= 1, i++) { 514 if (max_vnics > vpool) { 515 for (j = 0; j < 5; vrxq >>= 1, j++) { 516 if (dev_info->max_rx_queues > vrxq) { 517 if (vpool > vrxq) 518 vpool = vrxq; 519 goto found; 520 } 521 } 522 /* Not enough resources to support VMDq */ 523 break; 524 } 525 } 526 /* Not enough resources to support VMDq */ 527 vpool = 0; 528 vrxq = 0; 529 found: 530 dev_info->max_vmdq_pools = vpool; 531 dev_info->vmdq_queue_num = vrxq; 532 533 dev_info->vmdq_pool_base = 0; 534 dev_info->vmdq_queue_base = 0; 535 } 536 537 /* Configure the device based on the configuration provided */ 538 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 539 { 540 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 541 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 542 int rc; 543 544 bp->rx_queues = (void *)eth_dev->data->rx_queues; 545 bp->tx_queues = (void *)eth_dev->data->tx_queues; 546 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 547 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 548 549 if (BNXT_VF(bp) && (bp->flags & BNXT_FLAG_NEW_RM)) { 550 rc = bnxt_hwrm_check_vf_rings(bp); 551 if (rc) { 552 PMD_DRV_LOG(ERR, "HWRM insufficient resources\n"); 553 return -ENOSPC; 554 } 555 556 rc = bnxt_hwrm_func_reserve_vf_resc(bp, false); 557 if (rc) { 558 PMD_DRV_LOG(ERR, "HWRM resource alloc fail:%x\n", rc); 559 return -ENOSPC; 560 } 561 } else { 562 /* legacy driver needs to get updated values */ 563 rc = bnxt_hwrm_func_qcaps(bp); 564 if (rc) { 565 PMD_DRV_LOG(ERR, "hwrm func qcaps fail:%d\n", rc); 566 return rc; 567 } 568 } 569 570 /* Inherit new configurations */ 571 if (eth_dev->data->nb_rx_queues > bp->max_rx_rings || 572 eth_dev->data->nb_tx_queues > bp->max_tx_rings || 573 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 574 bp->max_cp_rings || 575 eth_dev->data->nb_rx_queues + eth_dev->data->nb_tx_queues > 576 bp->max_stat_ctx || 577 (uint32_t)(eth_dev->data->nb_rx_queues) > bp->max_ring_grps || 578 (!(eth_dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS) && 579 bp->max_vnics < eth_dev->data->nb_rx_queues)) { 580 PMD_DRV_LOG(ERR, 581 "Insufficient resources to support requested config\n"); 582 PMD_DRV_LOG(ERR, 583 "Num Queues Requested: Tx %d, Rx %d\n", 584 eth_dev->data->nb_tx_queues, 585 eth_dev->data->nb_rx_queues); 586 PMD_DRV_LOG(ERR, 587 "MAX: TxQ %d, RxQ %d, CQ %d Stat %d, Grp %d, Vnic %d\n", 588 bp->max_tx_rings, bp->max_rx_rings, bp->max_cp_rings, 589 bp->max_stat_ctx, bp->max_ring_grps, bp->max_vnics); 590 return -ENOSPC; 591 } 592 593 bp->rx_cp_nr_rings = bp->rx_nr_rings; 594 bp->tx_cp_nr_rings = bp->tx_nr_rings; 595 596 if (rx_offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) { 597 eth_dev->data->mtu = 598 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 599 RTE_ETHER_HDR_LEN - RTE_ETHER_CRC_LEN - VLAN_TAG_SIZE * 600 BNXT_NUM_VLANS; 601 bnxt_mtu_set_op(eth_dev, eth_dev->data->mtu); 602 } 603 return 0; 604 } 605 606 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 607 { 608 struct rte_eth_link *link = ð_dev->data->dev_link; 609 610 if (link->link_status) 611 PMD_DRV_LOG(INFO, "Port %d Link Up - speed %u Mbps - %s\n", 612 eth_dev->data->port_id, 613 (uint32_t)link->link_speed, 614 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 615 ("full-duplex") : ("half-duplex\n")); 616 else 617 PMD_DRV_LOG(INFO, "Port %d Link Down\n", 618 eth_dev->data->port_id); 619 } 620 621 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev) 622 { 623 bnxt_print_link_info(eth_dev); 624 return 0; 625 } 626 627 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 628 { 629 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 630 uint64_t rx_offloads = eth_dev->data->dev_conf.rxmode.offloads; 631 int vlan_mask = 0; 632 int rc; 633 634 if (bp->rx_cp_nr_rings > RTE_ETHDEV_QUEUE_STAT_CNTRS) { 635 PMD_DRV_LOG(ERR, 636 "RxQ cnt %d > CONFIG_RTE_ETHDEV_QUEUE_STAT_CNTRS %d\n", 637 bp->rx_cp_nr_rings, RTE_ETHDEV_QUEUE_STAT_CNTRS); 638 } 639 bp->dev_stopped = 0; 640 641 rc = bnxt_init_chip(bp); 642 if (rc) 643 goto error; 644 645 bnxt_link_update_op(eth_dev, 1); 646 647 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER) 648 vlan_mask |= ETH_VLAN_FILTER_MASK; 649 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 650 vlan_mask |= ETH_VLAN_STRIP_MASK; 651 rc = bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 652 if (rc) 653 goto error; 654 655 bp->flags |= BNXT_FLAG_INIT_DONE; 656 return 0; 657 658 error: 659 bnxt_shutdown_nic(bp); 660 bnxt_free_tx_mbufs(bp); 661 bnxt_free_rx_mbufs(bp); 662 return rc; 663 } 664 665 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 666 { 667 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 668 int rc = 0; 669 670 if (!bp->link_info.link_up) 671 rc = bnxt_set_hwrm_link_config(bp, true); 672 if (!rc) 673 eth_dev->data->dev_link.link_status = 1; 674 675 bnxt_print_link_info(eth_dev); 676 return 0; 677 } 678 679 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 680 { 681 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 682 683 eth_dev->data->dev_link.link_status = 0; 684 bnxt_set_hwrm_link_config(bp, false); 685 bp->link_info.link_up = 0; 686 687 return 0; 688 } 689 690 /* Unload the driver, release resources */ 691 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 692 { 693 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 694 695 bp->flags &= ~BNXT_FLAG_INIT_DONE; 696 if (bp->eth_dev->data->dev_started) { 697 /* TBD: STOP HW queues DMA */ 698 eth_dev->data->dev_link.link_status = 0; 699 } 700 bnxt_set_hwrm_link_config(bp, false); 701 bnxt_hwrm_port_clr_stats(bp); 702 bnxt_free_tx_mbufs(bp); 703 bnxt_free_rx_mbufs(bp); 704 bnxt_shutdown_nic(bp); 705 bp->dev_stopped = 1; 706 } 707 708 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 709 { 710 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 711 712 if (bp->dev_stopped == 0) 713 bnxt_dev_stop_op(eth_dev); 714 715 if (eth_dev->data->mac_addrs != NULL) { 716 rte_free(eth_dev->data->mac_addrs); 717 eth_dev->data->mac_addrs = NULL; 718 } 719 if (bp->grp_info != NULL) { 720 rte_free(bp->grp_info); 721 bp->grp_info = NULL; 722 } 723 724 bnxt_dev_uninit(eth_dev); 725 } 726 727 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 728 uint32_t index) 729 { 730 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 731 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 732 struct bnxt_vnic_info *vnic; 733 struct bnxt_filter_info *filter, *temp_filter; 734 uint32_t i; 735 736 /* 737 * Loop through all VNICs from the specified filter flow pools to 738 * remove the corresponding MAC addr filter 739 */ 740 for (i = 0; i < bp->nr_vnics; i++) { 741 if (!(pool_mask & (1ULL << i))) 742 continue; 743 744 vnic = &bp->vnic_info[i]; 745 filter = STAILQ_FIRST(&vnic->filter); 746 while (filter) { 747 temp_filter = STAILQ_NEXT(filter, next); 748 if (filter->mac_index == index) { 749 STAILQ_REMOVE(&vnic->filter, filter, 750 bnxt_filter_info, next); 751 bnxt_hwrm_clear_l2_filter(bp, filter); 752 filter->mac_index = INVALID_MAC_INDEX; 753 memset(&filter->l2_addr, 0, RTE_ETHER_ADDR_LEN); 754 STAILQ_INSERT_TAIL(&bp->free_filter_list, 755 filter, next); 756 } 757 filter = temp_filter; 758 } 759 } 760 } 761 762 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 763 struct rte_ether_addr *mac_addr, 764 uint32_t index, uint32_t pool) 765 { 766 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 767 struct bnxt_vnic_info *vnic = &bp->vnic_info[pool]; 768 struct bnxt_filter_info *filter; 769 770 if (BNXT_VF(bp) & !BNXT_VF_IS_TRUSTED(bp)) { 771 PMD_DRV_LOG(ERR, "Cannot add MAC address to a VF interface\n"); 772 return -ENOTSUP; 773 } 774 775 if (!vnic) { 776 PMD_DRV_LOG(ERR, "VNIC not found for pool %d!\n", pool); 777 return -EINVAL; 778 } 779 /* Attach requested MAC address to the new l2_filter */ 780 STAILQ_FOREACH(filter, &vnic->filter, next) { 781 if (filter->mac_index == index) { 782 PMD_DRV_LOG(ERR, 783 "MAC addr already existed for pool %d\n", pool); 784 return 0; 785 } 786 } 787 filter = bnxt_alloc_filter(bp); 788 if (!filter) { 789 PMD_DRV_LOG(ERR, "L2 filter alloc failed\n"); 790 return -ENODEV; 791 } 792 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 793 filter->mac_index = index; 794 memcpy(filter->l2_addr, mac_addr, RTE_ETHER_ADDR_LEN); 795 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 796 } 797 798 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 799 { 800 int rc = 0; 801 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 802 struct rte_eth_link new; 803 unsigned int cnt = BNXT_LINK_WAIT_CNT; 804 805 memset(&new, 0, sizeof(new)); 806 do { 807 /* Retrieve link info from hardware */ 808 rc = bnxt_get_hwrm_link_config(bp, &new); 809 if (rc) { 810 new.link_speed = ETH_LINK_SPEED_100M; 811 new.link_duplex = ETH_LINK_FULL_DUPLEX; 812 PMD_DRV_LOG(ERR, 813 "Failed to retrieve link rc = 0x%x!\n", rc); 814 goto out; 815 } 816 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 817 818 if (!wait_to_complete) 819 break; 820 } while (!new.link_status && cnt--); 821 822 out: 823 /* Timed out or success */ 824 if (new.link_status != eth_dev->data->dev_link.link_status || 825 new.link_speed != eth_dev->data->dev_link.link_speed) { 826 memcpy(ð_dev->data->dev_link, &new, 827 sizeof(struct rte_eth_link)); 828 829 _rte_eth_dev_callback_process(eth_dev, 830 RTE_ETH_EVENT_INTR_LSC, 831 NULL); 832 833 bnxt_print_link_info(eth_dev); 834 } 835 836 return rc; 837 } 838 839 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 840 { 841 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 842 struct bnxt_vnic_info *vnic; 843 844 if (bp->vnic_info == NULL) 845 return; 846 847 vnic = &bp->vnic_info[0]; 848 849 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 850 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 851 } 852 853 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 854 { 855 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 856 struct bnxt_vnic_info *vnic; 857 858 if (bp->vnic_info == NULL) 859 return; 860 861 vnic = &bp->vnic_info[0]; 862 863 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 864 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 865 } 866 867 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 868 { 869 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 870 struct bnxt_vnic_info *vnic; 871 872 if (bp->vnic_info == NULL) 873 return; 874 875 vnic = &bp->vnic_info[0]; 876 877 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 878 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 879 } 880 881 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 882 { 883 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 884 struct bnxt_vnic_info *vnic; 885 886 if (bp->vnic_info == NULL) 887 return; 888 889 vnic = &bp->vnic_info[0]; 890 891 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 892 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 893 } 894 895 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 896 struct rte_eth_rss_reta_entry64 *reta_conf, 897 uint16_t reta_size) 898 { 899 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 900 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 901 struct bnxt_vnic_info *vnic; 902 int i; 903 904 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 905 return -EINVAL; 906 907 if (reta_size != HW_HASH_INDEX_SIZE) { 908 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 909 "(%d) must equal the size supported by the hardware " 910 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 911 return -EINVAL; 912 } 913 /* Update the RSS VNIC(s) */ 914 for (i = 0; i < bp->max_vnics; i++) { 915 vnic = &bp->vnic_info[i]; 916 memcpy(vnic->rss_table, reta_conf, reta_size); 917 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 918 } 919 return 0; 920 } 921 922 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 923 struct rte_eth_rss_reta_entry64 *reta_conf, 924 uint16_t reta_size) 925 { 926 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 927 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 928 struct rte_intr_handle *intr_handle 929 = &bp->pdev->intr_handle; 930 931 /* Retrieve from the default VNIC */ 932 if (!vnic) 933 return -EINVAL; 934 if (!vnic->rss_table) 935 return -EINVAL; 936 937 if (reta_size != HW_HASH_INDEX_SIZE) { 938 PMD_DRV_LOG(ERR, "The configured hash table lookup size " 939 "(%d) must equal the size supported by the hardware " 940 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 941 return -EINVAL; 942 } 943 /* EW - need to revisit here copying from uint64_t to uint16_t */ 944 memcpy(reta_conf, vnic->rss_table, reta_size); 945 946 if (rte_intr_allow_others(intr_handle)) { 947 if (eth_dev->data->dev_conf.intr_conf.lsc != 0) 948 bnxt_dev_lsc_intr_setup(eth_dev); 949 } 950 951 return 0; 952 } 953 954 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 955 struct rte_eth_rss_conf *rss_conf) 956 { 957 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 958 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 959 struct bnxt_vnic_info *vnic; 960 uint16_t hash_type = 0; 961 unsigned int i; 962 963 /* 964 * If RSS enablement were different than dev_configure, 965 * then return -EINVAL 966 */ 967 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 968 if (!rss_conf->rss_hf) 969 PMD_DRV_LOG(ERR, "Hash type NONE\n"); 970 } else { 971 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 972 return -EINVAL; 973 } 974 975 bp->flags |= BNXT_FLAG_UPDATE_HASH; 976 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 977 978 if (rss_conf->rss_hf & ETH_RSS_IPV4) 979 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 980 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 981 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 982 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 983 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 984 if (rss_conf->rss_hf & ETH_RSS_IPV6) 985 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 986 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 987 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 988 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 989 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 990 991 /* Update the RSS VNIC(s) */ 992 for (i = 0; i < bp->nr_vnics; i++) { 993 vnic = &bp->vnic_info[i]; 994 vnic->hash_type = hash_type; 995 996 /* 997 * Use the supplied key if the key length is 998 * acceptable and the rss_key is not NULL 999 */ 1000 if (rss_conf->rss_key && 1001 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 1002 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 1003 rss_conf->rss_key_len); 1004 1005 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 1006 } 1007 return 0; 1008 } 1009 1010 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 1011 struct rte_eth_rss_conf *rss_conf) 1012 { 1013 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1014 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1015 int len; 1016 uint32_t hash_types; 1017 1018 /* RSS configuration is the same for all VNICs */ 1019 if (vnic && vnic->rss_hash_key) { 1020 if (rss_conf->rss_key) { 1021 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 1022 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 1023 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 1024 } 1025 1026 hash_types = vnic->hash_type; 1027 rss_conf->rss_hf = 0; 1028 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 1029 rss_conf->rss_hf |= ETH_RSS_IPV4; 1030 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 1031 } 1032 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 1033 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 1034 hash_types &= 1035 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 1036 } 1037 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 1038 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 1039 hash_types &= 1040 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 1041 } 1042 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 1043 rss_conf->rss_hf |= ETH_RSS_IPV6; 1044 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 1045 } 1046 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 1047 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 1048 hash_types &= 1049 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 1050 } 1051 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 1052 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 1053 hash_types &= 1054 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 1055 } 1056 if (hash_types) { 1057 PMD_DRV_LOG(ERR, 1058 "Unknwon RSS config from firmware (%08x), RSS disabled", 1059 vnic->hash_type); 1060 return -ENOTSUP; 1061 } 1062 } else { 1063 rss_conf->rss_hf = 0; 1064 } 1065 return 0; 1066 } 1067 1068 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 1069 struct rte_eth_fc_conf *fc_conf) 1070 { 1071 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1072 struct rte_eth_link link_info; 1073 int rc; 1074 1075 rc = bnxt_get_hwrm_link_config(bp, &link_info); 1076 if (rc) 1077 return rc; 1078 1079 memset(fc_conf, 0, sizeof(*fc_conf)); 1080 if (bp->link_info.auto_pause) 1081 fc_conf->autoneg = 1; 1082 switch (bp->link_info.pause) { 1083 case 0: 1084 fc_conf->mode = RTE_FC_NONE; 1085 break; 1086 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1087 fc_conf->mode = RTE_FC_TX_PAUSE; 1088 break; 1089 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1090 fc_conf->mode = RTE_FC_RX_PAUSE; 1091 break; 1092 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1093 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1094 fc_conf->mode = RTE_FC_FULL; 1095 break; 1096 } 1097 return 0; 1098 } 1099 1100 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1101 struct rte_eth_fc_conf *fc_conf) 1102 { 1103 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1104 1105 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1106 PMD_DRV_LOG(ERR, "Flow Control Settings cannot be modified\n"); 1107 return -ENOTSUP; 1108 } 1109 1110 switch (fc_conf->mode) { 1111 case RTE_FC_NONE: 1112 bp->link_info.auto_pause = 0; 1113 bp->link_info.force_pause = 0; 1114 break; 1115 case RTE_FC_RX_PAUSE: 1116 if (fc_conf->autoneg) { 1117 bp->link_info.auto_pause = 1118 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1119 bp->link_info.force_pause = 0; 1120 } else { 1121 bp->link_info.auto_pause = 0; 1122 bp->link_info.force_pause = 1123 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1124 } 1125 break; 1126 case RTE_FC_TX_PAUSE: 1127 if (fc_conf->autoneg) { 1128 bp->link_info.auto_pause = 1129 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1130 bp->link_info.force_pause = 0; 1131 } else { 1132 bp->link_info.auto_pause = 0; 1133 bp->link_info.force_pause = 1134 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1135 } 1136 break; 1137 case RTE_FC_FULL: 1138 if (fc_conf->autoneg) { 1139 bp->link_info.auto_pause = 1140 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1141 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1142 bp->link_info.force_pause = 0; 1143 } else { 1144 bp->link_info.auto_pause = 0; 1145 bp->link_info.force_pause = 1146 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1147 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1148 } 1149 break; 1150 } 1151 return bnxt_set_hwrm_link_config(bp, true); 1152 } 1153 1154 /* Add UDP tunneling port */ 1155 static int 1156 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1157 struct rte_eth_udp_tunnel *udp_tunnel) 1158 { 1159 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1160 uint16_t tunnel_type = 0; 1161 int rc = 0; 1162 1163 switch (udp_tunnel->prot_type) { 1164 case RTE_TUNNEL_TYPE_VXLAN: 1165 if (bp->vxlan_port_cnt) { 1166 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1167 udp_tunnel->udp_port); 1168 if (bp->vxlan_port != udp_tunnel->udp_port) { 1169 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1170 return -ENOSPC; 1171 } 1172 bp->vxlan_port_cnt++; 1173 return 0; 1174 } 1175 tunnel_type = 1176 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1177 bp->vxlan_port_cnt++; 1178 break; 1179 case RTE_TUNNEL_TYPE_GENEVE: 1180 if (bp->geneve_port_cnt) { 1181 PMD_DRV_LOG(ERR, "Tunnel Port %d already programmed\n", 1182 udp_tunnel->udp_port); 1183 if (bp->geneve_port != udp_tunnel->udp_port) { 1184 PMD_DRV_LOG(ERR, "Only one port allowed\n"); 1185 return -ENOSPC; 1186 } 1187 bp->geneve_port_cnt++; 1188 return 0; 1189 } 1190 tunnel_type = 1191 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1192 bp->geneve_port_cnt++; 1193 break; 1194 default: 1195 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1196 return -ENOTSUP; 1197 } 1198 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1199 tunnel_type); 1200 return rc; 1201 } 1202 1203 static int 1204 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1205 struct rte_eth_udp_tunnel *udp_tunnel) 1206 { 1207 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1208 uint16_t tunnel_type = 0; 1209 uint16_t port = 0; 1210 int rc = 0; 1211 1212 switch (udp_tunnel->prot_type) { 1213 case RTE_TUNNEL_TYPE_VXLAN: 1214 if (!bp->vxlan_port_cnt) { 1215 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1216 return -EINVAL; 1217 } 1218 if (bp->vxlan_port != udp_tunnel->udp_port) { 1219 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1220 udp_tunnel->udp_port, bp->vxlan_port); 1221 return -EINVAL; 1222 } 1223 if (--bp->vxlan_port_cnt) 1224 return 0; 1225 1226 tunnel_type = 1227 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1228 port = bp->vxlan_fw_dst_port_id; 1229 break; 1230 case RTE_TUNNEL_TYPE_GENEVE: 1231 if (!bp->geneve_port_cnt) { 1232 PMD_DRV_LOG(ERR, "No Tunnel port configured yet\n"); 1233 return -EINVAL; 1234 } 1235 if (bp->geneve_port != udp_tunnel->udp_port) { 1236 PMD_DRV_LOG(ERR, "Req Port: %d. Configured port: %d\n", 1237 udp_tunnel->udp_port, bp->geneve_port); 1238 return -EINVAL; 1239 } 1240 if (--bp->geneve_port_cnt) 1241 return 0; 1242 1243 tunnel_type = 1244 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1245 port = bp->geneve_fw_dst_port_id; 1246 break; 1247 default: 1248 PMD_DRV_LOG(ERR, "Tunnel type is not supported\n"); 1249 return -ENOTSUP; 1250 } 1251 1252 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1253 if (!rc) { 1254 if (tunnel_type == 1255 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1256 bp->vxlan_port = 0; 1257 if (tunnel_type == 1258 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1259 bp->geneve_port = 0; 1260 } 1261 return rc; 1262 } 1263 1264 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1265 { 1266 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1267 struct bnxt_vnic_info *vnic; 1268 unsigned int i; 1269 int rc = 0; 1270 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN; 1271 1272 /* Cycle through all VNICs */ 1273 for (i = 0; i < bp->nr_vnics; i++) { 1274 /* 1275 * For each VNIC and each associated filter(s) 1276 * if VLAN exists && VLAN matches vlan_id 1277 * remove the MAC+VLAN filter 1278 * add a new MAC only filter 1279 * else 1280 * VLAN filter doesn't exist, just skip and continue 1281 */ 1282 vnic = &bp->vnic_info[i]; 1283 filter = STAILQ_FIRST(&vnic->filter); 1284 while (filter) { 1285 temp_filter = STAILQ_NEXT(filter, next); 1286 1287 if (filter->enables & chk && 1288 filter->l2_ovlan == vlan_id) { 1289 /* Must delete the filter */ 1290 STAILQ_REMOVE(&vnic->filter, filter, 1291 bnxt_filter_info, next); 1292 bnxt_hwrm_clear_l2_filter(bp, filter); 1293 STAILQ_INSERT_TAIL(&bp->free_filter_list, 1294 filter, next); 1295 1296 /* 1297 * Need to examine to see if the MAC 1298 * filter already existed or not before 1299 * allocating a new one 1300 */ 1301 1302 new_filter = bnxt_alloc_filter(bp); 1303 if (!new_filter) { 1304 PMD_DRV_LOG(ERR, 1305 "MAC/VLAN filter alloc failed\n"); 1306 rc = -ENOMEM; 1307 goto exit; 1308 } 1309 STAILQ_INSERT_TAIL(&vnic->filter, 1310 new_filter, next); 1311 /* Inherit MAC from previous filter */ 1312 new_filter->mac_index = 1313 filter->mac_index; 1314 memcpy(new_filter->l2_addr, filter->l2_addr, 1315 RTE_ETHER_ADDR_LEN); 1316 /* MAC only filter */ 1317 rc = bnxt_hwrm_set_l2_filter(bp, 1318 vnic->fw_vnic_id, 1319 new_filter); 1320 if (rc) 1321 goto exit; 1322 PMD_DRV_LOG(INFO, 1323 "Del Vlan filter for %d\n", 1324 vlan_id); 1325 } 1326 filter = temp_filter; 1327 } 1328 } 1329 exit: 1330 return rc; 1331 } 1332 1333 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1334 { 1335 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1336 struct bnxt_vnic_info *vnic; 1337 unsigned int i; 1338 int rc = 0; 1339 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN | 1340 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN_MASK; 1341 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_IVLAN; 1342 1343 /* Cycle through all VNICs */ 1344 for (i = 0; i < bp->nr_vnics; i++) { 1345 /* 1346 * For each VNIC and each associated filter(s) 1347 * if VLAN exists: 1348 * if VLAN matches vlan_id 1349 * VLAN filter already exists, just skip and continue 1350 * else 1351 * add a new MAC+VLAN filter 1352 * else 1353 * Remove the old MAC only filter 1354 * Add a new MAC+VLAN filter 1355 */ 1356 vnic = &bp->vnic_info[i]; 1357 filter = STAILQ_FIRST(&vnic->filter); 1358 while (filter) { 1359 temp_filter = STAILQ_NEXT(filter, next); 1360 1361 if (filter->enables & chk) { 1362 if (filter->l2_ivlan == vlan_id) 1363 goto cont; 1364 } else { 1365 /* Must delete the MAC filter */ 1366 STAILQ_REMOVE(&vnic->filter, filter, 1367 bnxt_filter_info, next); 1368 bnxt_hwrm_clear_l2_filter(bp, filter); 1369 filter->l2_ovlan = 0; 1370 STAILQ_INSERT_TAIL(&bp->free_filter_list, 1371 filter, next); 1372 } 1373 new_filter = bnxt_alloc_filter(bp); 1374 if (!new_filter) { 1375 PMD_DRV_LOG(ERR, 1376 "MAC/VLAN filter alloc failed\n"); 1377 rc = -ENOMEM; 1378 goto exit; 1379 } 1380 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, next); 1381 /* Inherit MAC from the previous filter */ 1382 new_filter->mac_index = filter->mac_index; 1383 memcpy(new_filter->l2_addr, filter->l2_addr, 1384 RTE_ETHER_ADDR_LEN); 1385 /* MAC + VLAN ID filter */ 1386 new_filter->l2_ivlan = vlan_id; 1387 new_filter->l2_ivlan_mask = 0xF000; 1388 new_filter->enables |= en; 1389 rc = bnxt_hwrm_set_l2_filter(bp, 1390 vnic->fw_vnic_id, 1391 new_filter); 1392 if (rc) 1393 goto exit; 1394 PMD_DRV_LOG(INFO, 1395 "Added Vlan filter for %d\n", vlan_id); 1396 cont: 1397 filter = temp_filter; 1398 } 1399 } 1400 exit: 1401 return rc; 1402 } 1403 1404 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1405 uint16_t vlan_id, int on) 1406 { 1407 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1408 1409 /* These operations apply to ALL existing MAC/VLAN filters */ 1410 if (on) 1411 return bnxt_add_vlan_filter(bp, vlan_id); 1412 else 1413 return bnxt_del_vlan_filter(bp, vlan_id); 1414 } 1415 1416 static int 1417 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1418 { 1419 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1420 uint64_t rx_offloads = dev->data->dev_conf.rxmode.offloads; 1421 unsigned int i; 1422 1423 if (mask & ETH_VLAN_FILTER_MASK) { 1424 if (!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)) { 1425 /* Remove any VLAN filters programmed */ 1426 for (i = 0; i < 4095; i++) 1427 bnxt_del_vlan_filter(bp, i); 1428 } 1429 PMD_DRV_LOG(DEBUG, "VLAN Filtering: %d\n", 1430 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_FILTER)); 1431 } 1432 1433 if (mask & ETH_VLAN_STRIP_MASK) { 1434 /* Enable or disable VLAN stripping */ 1435 for (i = 0; i < bp->nr_vnics; i++) { 1436 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1437 if (rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP) 1438 vnic->vlan_strip = true; 1439 else 1440 vnic->vlan_strip = false; 1441 bnxt_hwrm_vnic_cfg(bp, vnic); 1442 } 1443 PMD_DRV_LOG(DEBUG, "VLAN Strip Offload: %d\n", 1444 !!(rx_offloads & DEV_RX_OFFLOAD_VLAN_STRIP)); 1445 } 1446 1447 if (mask & ETH_VLAN_EXTEND_MASK) 1448 PMD_DRV_LOG(ERR, "Extend VLAN Not supported\n"); 1449 1450 return 0; 1451 } 1452 1453 static int 1454 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, 1455 struct rte_ether_addr *addr) 1456 { 1457 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1458 /* Default Filter is tied to VNIC 0 */ 1459 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1460 struct bnxt_filter_info *filter; 1461 int rc; 1462 1463 if (BNXT_VF(bp) && !BNXT_VF_IS_TRUSTED(bp)) 1464 return -EPERM; 1465 1466 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr)); 1467 1468 STAILQ_FOREACH(filter, &vnic->filter, next) { 1469 /* Default Filter is at Index 0 */ 1470 if (filter->mac_index != 0) 1471 continue; 1472 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1473 if (rc) 1474 return rc; 1475 memcpy(filter->l2_addr, bp->mac_addr, RTE_ETHER_ADDR_LEN); 1476 memset(filter->l2_addr_mask, 0xff, RTE_ETHER_ADDR_LEN); 1477 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX; 1478 filter->enables |= 1479 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 1480 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 1481 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1482 if (rc) 1483 return rc; 1484 filter->mac_index = 0; 1485 PMD_DRV_LOG(DEBUG, "Set MAC addr\n"); 1486 } 1487 1488 return 0; 1489 } 1490 1491 static int 1492 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 1493 struct rte_ether_addr *mc_addr_set, 1494 uint32_t nb_mc_addr) 1495 { 1496 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1497 char *mc_addr_list = (char *)mc_addr_set; 1498 struct bnxt_vnic_info *vnic; 1499 uint32_t off = 0, i = 0; 1500 1501 vnic = &bp->vnic_info[0]; 1502 1503 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 1504 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1505 goto allmulti; 1506 } 1507 1508 /* TODO Check for Duplicate mcast addresses */ 1509 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1510 for (i = 0; i < nb_mc_addr; i++) { 1511 memcpy(vnic->mc_list + off, &mc_addr_list[i], 1512 RTE_ETHER_ADDR_LEN); 1513 off += RTE_ETHER_ADDR_LEN; 1514 } 1515 1516 vnic->mc_addr_cnt = i; 1517 1518 allmulti: 1519 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1520 } 1521 1522 static int 1523 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 1524 { 1525 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1526 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 1527 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 1528 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 1529 int ret; 1530 1531 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 1532 fw_major, fw_minor, fw_updt); 1533 1534 ret += 1; /* add the size of '\0' */ 1535 if (fw_size < (uint32_t)ret) 1536 return ret; 1537 else 1538 return 0; 1539 } 1540 1541 static void 1542 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1543 struct rte_eth_rxq_info *qinfo) 1544 { 1545 struct bnxt_rx_queue *rxq; 1546 1547 rxq = dev->data->rx_queues[queue_id]; 1548 1549 qinfo->mp = rxq->mb_pool; 1550 qinfo->scattered_rx = dev->data->scattered_rx; 1551 qinfo->nb_desc = rxq->nb_rx_desc; 1552 1553 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 1554 qinfo->conf.rx_drop_en = 0; 1555 qinfo->conf.rx_deferred_start = 0; 1556 } 1557 1558 static void 1559 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1560 struct rte_eth_txq_info *qinfo) 1561 { 1562 struct bnxt_tx_queue *txq; 1563 1564 txq = dev->data->tx_queues[queue_id]; 1565 1566 qinfo->nb_desc = txq->nb_tx_desc; 1567 1568 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 1569 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 1570 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 1571 1572 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 1573 qinfo->conf.tx_rs_thresh = 0; 1574 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1575 } 1576 1577 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 1578 { 1579 struct bnxt *bp = eth_dev->data->dev_private; 1580 struct rte_eth_dev_info dev_info; 1581 uint32_t rc = 0; 1582 uint32_t i; 1583 1584 bnxt_dev_info_get_op(eth_dev, &dev_info); 1585 1586 if (new_mtu < RTE_ETHER_MIN_MTU || new_mtu > BNXT_MAX_MTU) { 1587 PMD_DRV_LOG(ERR, "MTU requested must be within (%d, %d)\n", 1588 RTE_ETHER_MIN_MTU, BNXT_MAX_MTU); 1589 return -EINVAL; 1590 } 1591 1592 if (new_mtu > RTE_ETHER_MTU) { 1593 bp->flags |= BNXT_FLAG_JUMBO; 1594 bp->eth_dev->data->dev_conf.rxmode.offloads |= 1595 DEV_RX_OFFLOAD_JUMBO_FRAME; 1596 } else { 1597 bp->eth_dev->data->dev_conf.rxmode.offloads &= 1598 ~DEV_RX_OFFLOAD_JUMBO_FRAME; 1599 bp->flags &= ~BNXT_FLAG_JUMBO; 1600 } 1601 1602 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = 1603 new_mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 1604 VLAN_TAG_SIZE * 2; 1605 1606 eth_dev->data->mtu = new_mtu; 1607 PMD_DRV_LOG(INFO, "New MTU is %d\n", eth_dev->data->mtu); 1608 1609 for (i = 0; i < bp->nr_vnics; i++) { 1610 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1611 uint16_t size = 0; 1612 1613 vnic->mru = bp->eth_dev->data->mtu + RTE_ETHER_HDR_LEN + 1614 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1615 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 1616 if (rc) 1617 break; 1618 1619 size = rte_pktmbuf_data_room_size(bp->rx_queues[0]->mb_pool); 1620 size -= RTE_PKTMBUF_HEADROOM; 1621 1622 if (size < new_mtu) { 1623 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 1624 if (rc) 1625 return rc; 1626 } 1627 } 1628 1629 return rc; 1630 } 1631 1632 static int 1633 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 1634 { 1635 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1636 uint16_t vlan = bp->vlan; 1637 int rc; 1638 1639 if (!BNXT_SINGLE_PF(bp) || BNXT_VF(bp)) { 1640 PMD_DRV_LOG(ERR, 1641 "PVID cannot be modified for this function\n"); 1642 return -ENOTSUP; 1643 } 1644 bp->vlan = on ? pvid : 0; 1645 1646 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 1647 if (rc) 1648 bp->vlan = vlan; 1649 return rc; 1650 } 1651 1652 static int 1653 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 1654 { 1655 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1656 1657 return bnxt_hwrm_port_led_cfg(bp, true); 1658 } 1659 1660 static int 1661 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 1662 { 1663 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1664 1665 return bnxt_hwrm_port_led_cfg(bp, false); 1666 } 1667 1668 static uint32_t 1669 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1670 { 1671 uint32_t desc = 0, raw_cons = 0, cons; 1672 struct bnxt_cp_ring_info *cpr; 1673 struct bnxt_rx_queue *rxq; 1674 struct rx_pkt_cmpl *rxcmp; 1675 uint16_t cmp_type; 1676 uint8_t cmp = 1; 1677 bool valid; 1678 1679 rxq = dev->data->rx_queues[rx_queue_id]; 1680 cpr = rxq->cp_ring; 1681 valid = cpr->valid; 1682 1683 while (raw_cons < rxq->nb_rx_desc) { 1684 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 1685 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1686 1687 if (!CMPL_VALID(rxcmp, valid)) 1688 goto nothing_to_do; 1689 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid); 1690 cmp_type = CMP_TYPE(rxcmp); 1691 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { 1692 cmp = (rte_le_to_cpu_32( 1693 ((struct rx_tpa_end_cmpl *) 1694 (rxcmp))->agg_bufs_v1) & 1695 RX_TPA_END_CMPL_AGG_BUFS_MASK) >> 1696 RX_TPA_END_CMPL_AGG_BUFS_SFT; 1697 desc++; 1698 } else if (cmp_type == 0x11) { 1699 desc++; 1700 cmp = (rxcmp->agg_bufs_v1 & 1701 RX_PKT_CMPL_AGG_BUFS_MASK) >> 1702 RX_PKT_CMPL_AGG_BUFS_SFT; 1703 } else { 1704 cmp = 1; 1705 } 1706 nothing_to_do: 1707 raw_cons += cmp ? cmp : 2; 1708 } 1709 1710 return desc; 1711 } 1712 1713 static int 1714 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 1715 { 1716 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 1717 struct bnxt_rx_ring_info *rxr; 1718 struct bnxt_cp_ring_info *cpr; 1719 struct bnxt_sw_rx_bd *rx_buf; 1720 struct rx_pkt_cmpl *rxcmp; 1721 uint32_t cons, cp_cons; 1722 1723 if (!rxq) 1724 return -EINVAL; 1725 1726 cpr = rxq->cp_ring; 1727 rxr = rxq->rx_ring; 1728 1729 if (offset >= rxq->nb_rx_desc) 1730 return -EINVAL; 1731 1732 cons = RING_CMP(cpr->cp_ring_struct, offset); 1733 cp_cons = cpr->cp_raw_cons; 1734 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1735 1736 if (cons > cp_cons) { 1737 if (CMPL_VALID(rxcmp, cpr->valid)) 1738 return RTE_ETH_RX_DESC_DONE; 1739 } else { 1740 if (CMPL_VALID(rxcmp, !cpr->valid)) 1741 return RTE_ETH_RX_DESC_DONE; 1742 } 1743 rx_buf = &rxr->rx_buf_ring[cons]; 1744 if (rx_buf->mbuf == NULL) 1745 return RTE_ETH_RX_DESC_UNAVAIL; 1746 1747 1748 return RTE_ETH_RX_DESC_AVAIL; 1749 } 1750 1751 static int 1752 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 1753 { 1754 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 1755 struct bnxt_tx_ring_info *txr; 1756 struct bnxt_cp_ring_info *cpr; 1757 struct bnxt_sw_tx_bd *tx_buf; 1758 struct tx_pkt_cmpl *txcmp; 1759 uint32_t cons, cp_cons; 1760 1761 if (!txq) 1762 return -EINVAL; 1763 1764 cpr = txq->cp_ring; 1765 txr = txq->tx_ring; 1766 1767 if (offset >= txq->nb_tx_desc) 1768 return -EINVAL; 1769 1770 cons = RING_CMP(cpr->cp_ring_struct, offset); 1771 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1772 cp_cons = cpr->cp_raw_cons; 1773 1774 if (cons > cp_cons) { 1775 if (CMPL_VALID(txcmp, cpr->valid)) 1776 return RTE_ETH_TX_DESC_UNAVAIL; 1777 } else { 1778 if (CMPL_VALID(txcmp, !cpr->valid)) 1779 return RTE_ETH_TX_DESC_UNAVAIL; 1780 } 1781 tx_buf = &txr->tx_buf_ring[cons]; 1782 if (tx_buf->mbuf == NULL) 1783 return RTE_ETH_TX_DESC_DONE; 1784 1785 return RTE_ETH_TX_DESC_FULL; 1786 } 1787 1788 static struct bnxt_filter_info * 1789 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 1790 struct rte_eth_ethertype_filter *efilter, 1791 struct bnxt_vnic_info *vnic0, 1792 struct bnxt_vnic_info *vnic, 1793 int *ret) 1794 { 1795 struct bnxt_filter_info *mfilter = NULL; 1796 int match = 0; 1797 *ret = 0; 1798 1799 if (efilter->ether_type == RTE_ETHER_TYPE_IPv4 || 1800 efilter->ether_type == RTE_ETHER_TYPE_IPv6) { 1801 PMD_DRV_LOG(ERR, "invalid ether_type(0x%04x) in" 1802 " ethertype filter.", efilter->ether_type); 1803 *ret = -EINVAL; 1804 goto exit; 1805 } 1806 if (efilter->queue >= bp->rx_nr_rings) { 1807 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 1808 *ret = -EINVAL; 1809 goto exit; 1810 } 1811 1812 vnic0 = &bp->vnic_info[0]; 1813 vnic = &bp->vnic_info[efilter->queue]; 1814 if (vnic == NULL) { 1815 PMD_DRV_LOG(ERR, "Invalid queue %d\n", efilter->queue); 1816 *ret = -EINVAL; 1817 goto exit; 1818 } 1819 1820 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1821 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 1822 if ((!memcmp(efilter->mac_addr.addr_bytes, 1823 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 1824 mfilter->flags == 1825 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 1826 mfilter->ethertype == efilter->ether_type)) { 1827 match = 1; 1828 break; 1829 } 1830 } 1831 } else { 1832 STAILQ_FOREACH(mfilter, &vnic->filter, next) 1833 if ((!memcmp(efilter->mac_addr.addr_bytes, 1834 mfilter->l2_addr, RTE_ETHER_ADDR_LEN) && 1835 mfilter->ethertype == efilter->ether_type && 1836 mfilter->flags == 1837 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 1838 match = 1; 1839 break; 1840 } 1841 } 1842 1843 if (match) 1844 *ret = -EEXIST; 1845 1846 exit: 1847 return mfilter; 1848 } 1849 1850 static int 1851 bnxt_ethertype_filter(struct rte_eth_dev *dev, 1852 enum rte_filter_op filter_op, 1853 void *arg) 1854 { 1855 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1856 struct rte_eth_ethertype_filter *efilter = 1857 (struct rte_eth_ethertype_filter *)arg; 1858 struct bnxt_filter_info *bfilter, *filter1; 1859 struct bnxt_vnic_info *vnic, *vnic0; 1860 int ret; 1861 1862 if (filter_op == RTE_ETH_FILTER_NOP) 1863 return 0; 1864 1865 if (arg == NULL) { 1866 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 1867 filter_op); 1868 return -EINVAL; 1869 } 1870 1871 vnic0 = &bp->vnic_info[0]; 1872 vnic = &bp->vnic_info[efilter->queue]; 1873 1874 switch (filter_op) { 1875 case RTE_ETH_FILTER_ADD: 1876 bnxt_match_and_validate_ether_filter(bp, efilter, 1877 vnic0, vnic, &ret); 1878 if (ret < 0) 1879 return ret; 1880 1881 bfilter = bnxt_get_unused_filter(bp); 1882 if (bfilter == NULL) { 1883 PMD_DRV_LOG(ERR, 1884 "Not enough resources for a new filter.\n"); 1885 return -ENOMEM; 1886 } 1887 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 1888 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 1889 RTE_ETHER_ADDR_LEN); 1890 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 1891 RTE_ETHER_ADDR_LEN); 1892 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 1893 bfilter->ethertype = efilter->ether_type; 1894 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 1895 1896 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 1897 if (filter1 == NULL) { 1898 ret = -1; 1899 goto cleanup; 1900 } 1901 bfilter->enables |= 1902 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 1903 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 1904 1905 bfilter->dst_id = vnic->fw_vnic_id; 1906 1907 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1908 bfilter->flags = 1909 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 1910 } 1911 1912 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 1913 if (ret) 1914 goto cleanup; 1915 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 1916 break; 1917 case RTE_ETH_FILTER_DELETE: 1918 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 1919 vnic0, vnic, &ret); 1920 if (ret == -EEXIST) { 1921 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 1922 1923 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 1924 next); 1925 bnxt_free_filter(bp, filter1); 1926 } else if (ret == 0) { 1927 PMD_DRV_LOG(ERR, "No matching filter found\n"); 1928 } 1929 break; 1930 default: 1931 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 1932 ret = -EINVAL; 1933 goto error; 1934 } 1935 return ret; 1936 cleanup: 1937 bnxt_free_filter(bp, bfilter); 1938 error: 1939 return ret; 1940 } 1941 1942 static inline int 1943 parse_ntuple_filter(struct bnxt *bp, 1944 struct rte_eth_ntuple_filter *nfilter, 1945 struct bnxt_filter_info *bfilter) 1946 { 1947 uint32_t en = 0; 1948 1949 if (nfilter->queue >= bp->rx_nr_rings) { 1950 PMD_DRV_LOG(ERR, "Invalid queue %d\n", nfilter->queue); 1951 return -EINVAL; 1952 } 1953 1954 switch (nfilter->dst_port_mask) { 1955 case UINT16_MAX: 1956 bfilter->dst_port_mask = -1; 1957 bfilter->dst_port = nfilter->dst_port; 1958 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 1959 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 1960 break; 1961 default: 1962 PMD_DRV_LOG(ERR, "invalid dst_port mask."); 1963 return -EINVAL; 1964 } 1965 1966 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 1967 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1968 1969 switch (nfilter->proto_mask) { 1970 case UINT8_MAX: 1971 if (nfilter->proto == 17) /* IPPROTO_UDP */ 1972 bfilter->ip_protocol = 17; 1973 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 1974 bfilter->ip_protocol = 6; 1975 else 1976 return -EINVAL; 1977 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1978 break; 1979 default: 1980 PMD_DRV_LOG(ERR, "invalid protocol mask."); 1981 return -EINVAL; 1982 } 1983 1984 switch (nfilter->dst_ip_mask) { 1985 case UINT32_MAX: 1986 bfilter->dst_ipaddr_mask[0] = -1; 1987 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 1988 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 1989 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 1990 break; 1991 default: 1992 PMD_DRV_LOG(ERR, "invalid dst_ip mask."); 1993 return -EINVAL; 1994 } 1995 1996 switch (nfilter->src_ip_mask) { 1997 case UINT32_MAX: 1998 bfilter->src_ipaddr_mask[0] = -1; 1999 bfilter->src_ipaddr[0] = nfilter->src_ip; 2000 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 2001 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2002 break; 2003 default: 2004 PMD_DRV_LOG(ERR, "invalid src_ip mask."); 2005 return -EINVAL; 2006 } 2007 2008 switch (nfilter->src_port_mask) { 2009 case UINT16_MAX: 2010 bfilter->src_port_mask = -1; 2011 bfilter->src_port = nfilter->src_port; 2012 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 2013 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2014 break; 2015 default: 2016 PMD_DRV_LOG(ERR, "invalid src_port mask."); 2017 return -EINVAL; 2018 } 2019 2020 //TODO Priority 2021 //nfilter->priority = (uint8_t)filter->priority; 2022 2023 bfilter->enables = en; 2024 return 0; 2025 } 2026 2027 static struct bnxt_filter_info* 2028 bnxt_match_ntuple_filter(struct bnxt *bp, 2029 struct bnxt_filter_info *bfilter, 2030 struct bnxt_vnic_info **mvnic) 2031 { 2032 struct bnxt_filter_info *mfilter = NULL; 2033 int i; 2034 2035 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2036 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2037 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 2038 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 2039 bfilter->src_ipaddr_mask[0] == 2040 mfilter->src_ipaddr_mask[0] && 2041 bfilter->src_port == mfilter->src_port && 2042 bfilter->src_port_mask == mfilter->src_port_mask && 2043 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 2044 bfilter->dst_ipaddr_mask[0] == 2045 mfilter->dst_ipaddr_mask[0] && 2046 bfilter->dst_port == mfilter->dst_port && 2047 bfilter->dst_port_mask == mfilter->dst_port_mask && 2048 bfilter->flags == mfilter->flags && 2049 bfilter->enables == mfilter->enables) { 2050 if (mvnic) 2051 *mvnic = vnic; 2052 return mfilter; 2053 } 2054 } 2055 } 2056 return NULL; 2057 } 2058 2059 static int 2060 bnxt_cfg_ntuple_filter(struct bnxt *bp, 2061 struct rte_eth_ntuple_filter *nfilter, 2062 enum rte_filter_op filter_op) 2063 { 2064 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 2065 struct bnxt_vnic_info *vnic, *vnic0, *mvnic; 2066 int ret; 2067 2068 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 2069 PMD_DRV_LOG(ERR, "only 5tuple is supported."); 2070 return -EINVAL; 2071 } 2072 2073 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 2074 PMD_DRV_LOG(ERR, "Ntuple filter: TCP flags not supported\n"); 2075 return -EINVAL; 2076 } 2077 2078 bfilter = bnxt_get_unused_filter(bp); 2079 if (bfilter == NULL) { 2080 PMD_DRV_LOG(ERR, 2081 "Not enough resources for a new filter.\n"); 2082 return -ENOMEM; 2083 } 2084 ret = parse_ntuple_filter(bp, nfilter, bfilter); 2085 if (ret < 0) 2086 goto free_filter; 2087 2088 vnic = &bp->vnic_info[nfilter->queue]; 2089 vnic0 = &bp->vnic_info[0]; 2090 filter1 = STAILQ_FIRST(&vnic0->filter); 2091 if (filter1 == NULL) { 2092 ret = -1; 2093 goto free_filter; 2094 } 2095 2096 bfilter->dst_id = vnic->fw_vnic_id; 2097 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2098 bfilter->enables |= 2099 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2100 bfilter->ethertype = 0x800; 2101 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2102 2103 mfilter = bnxt_match_ntuple_filter(bp, bfilter, &mvnic); 2104 2105 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2106 bfilter->dst_id == mfilter->dst_id) { 2107 PMD_DRV_LOG(ERR, "filter exists.\n"); 2108 ret = -EEXIST; 2109 goto free_filter; 2110 } else if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD && 2111 bfilter->dst_id != mfilter->dst_id) { 2112 mfilter->dst_id = vnic->fw_vnic_id; 2113 ret = bnxt_hwrm_set_ntuple_filter(bp, mfilter->dst_id, mfilter); 2114 STAILQ_REMOVE(&mvnic->filter, mfilter, bnxt_filter_info, next); 2115 STAILQ_INSERT_TAIL(&vnic->filter, mfilter, next); 2116 PMD_DRV_LOG(ERR, "filter with matching pattern exists.\n"); 2117 PMD_DRV_LOG(ERR, " Updated it to the new destination queue\n"); 2118 goto free_filter; 2119 } 2120 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2121 PMD_DRV_LOG(ERR, "filter doesn't exist."); 2122 ret = -ENOENT; 2123 goto free_filter; 2124 } 2125 2126 if (filter_op == RTE_ETH_FILTER_ADD) { 2127 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2128 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2129 if (ret) 2130 goto free_filter; 2131 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2132 } else { 2133 if (mfilter == NULL) { 2134 /* This should not happen. But for Coverity! */ 2135 ret = -ENOENT; 2136 goto free_filter; 2137 } 2138 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2139 2140 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, next); 2141 bnxt_free_filter(bp, mfilter); 2142 mfilter->fw_l2_filter_id = -1; 2143 bnxt_free_filter(bp, bfilter); 2144 bfilter->fw_l2_filter_id = -1; 2145 } 2146 2147 return 0; 2148 free_filter: 2149 bfilter->fw_l2_filter_id = -1; 2150 bnxt_free_filter(bp, bfilter); 2151 return ret; 2152 } 2153 2154 static int 2155 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2156 enum rte_filter_op filter_op, 2157 void *arg) 2158 { 2159 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2160 int ret; 2161 2162 if (filter_op == RTE_ETH_FILTER_NOP) 2163 return 0; 2164 2165 if (arg == NULL) { 2166 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u.", 2167 filter_op); 2168 return -EINVAL; 2169 } 2170 2171 switch (filter_op) { 2172 case RTE_ETH_FILTER_ADD: 2173 ret = bnxt_cfg_ntuple_filter(bp, 2174 (struct rte_eth_ntuple_filter *)arg, 2175 filter_op); 2176 break; 2177 case RTE_ETH_FILTER_DELETE: 2178 ret = bnxt_cfg_ntuple_filter(bp, 2179 (struct rte_eth_ntuple_filter *)arg, 2180 filter_op); 2181 break; 2182 default: 2183 PMD_DRV_LOG(ERR, "unsupported operation %u.", filter_op); 2184 ret = -EINVAL; 2185 break; 2186 } 2187 return ret; 2188 } 2189 2190 static int 2191 bnxt_parse_fdir_filter(struct bnxt *bp, 2192 struct rte_eth_fdir_filter *fdir, 2193 struct bnxt_filter_info *filter) 2194 { 2195 enum rte_fdir_mode fdir_mode = 2196 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2197 struct bnxt_vnic_info *vnic0, *vnic; 2198 struct bnxt_filter_info *filter1; 2199 uint32_t en = 0; 2200 int i; 2201 2202 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2203 return -EINVAL; 2204 2205 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2206 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2207 2208 switch (fdir->input.flow_type) { 2209 case RTE_ETH_FLOW_IPV4: 2210 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2211 /* FALLTHROUGH */ 2212 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2214 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2216 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2217 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2218 filter->ip_addr_type = 2219 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2220 filter->src_ipaddr_mask[0] = 0xffffffff; 2221 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2222 filter->dst_ipaddr_mask[0] = 0xffffffff; 2223 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2224 filter->ethertype = 0x800; 2225 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2226 break; 2227 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2228 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2229 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2230 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2231 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2232 filter->dst_port_mask = 0xffff; 2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2234 filter->src_port_mask = 0xffff; 2235 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2236 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2237 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2238 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2239 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2240 filter->ip_protocol = 6; 2241 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2242 filter->ip_addr_type = 2243 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2244 filter->src_ipaddr_mask[0] = 0xffffffff; 2245 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2246 filter->dst_ipaddr_mask[0] = 0xffffffff; 2247 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2248 filter->ethertype = 0x800; 2249 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2250 break; 2251 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2252 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2253 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2254 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2255 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2256 filter->dst_port_mask = 0xffff; 2257 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2258 filter->src_port_mask = 0xffff; 2259 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2260 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2261 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2262 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2263 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2264 filter->ip_protocol = 17; 2265 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2266 filter->ip_addr_type = 2267 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2268 filter->src_ipaddr_mask[0] = 0xffffffff; 2269 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2270 filter->dst_ipaddr_mask[0] = 0xffffffff; 2271 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2272 filter->ethertype = 0x800; 2273 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2274 break; 2275 case RTE_ETH_FLOW_IPV6: 2276 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2277 /* FALLTHROUGH */ 2278 filter->ip_addr_type = 2279 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2280 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2281 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2282 rte_memcpy(filter->src_ipaddr, 2283 fdir->input.flow.ipv6_flow.src_ip, 16); 2284 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2285 rte_memcpy(filter->dst_ipaddr, 2286 fdir->input.flow.ipv6_flow.dst_ip, 16); 2287 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2288 memset(filter->dst_ipaddr_mask, 0xff, 16); 2289 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2290 memset(filter->src_ipaddr_mask, 0xff, 16); 2291 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2292 filter->ethertype = 0x86dd; 2293 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2294 break; 2295 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2296 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2297 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2298 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2299 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2300 filter->dst_port_mask = 0xffff; 2301 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2302 filter->src_port_mask = 0xffff; 2303 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2304 filter->ip_addr_type = 2305 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2306 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2307 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2308 rte_memcpy(filter->src_ipaddr, 2309 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2310 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2311 rte_memcpy(filter->dst_ipaddr, 2312 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2313 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2314 memset(filter->dst_ipaddr_mask, 0xff, 16); 2315 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2316 memset(filter->src_ipaddr_mask, 0xff, 16); 2317 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2318 filter->ethertype = 0x86dd; 2319 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2320 break; 2321 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2322 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2323 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2324 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2325 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2326 filter->dst_port_mask = 0xffff; 2327 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2328 filter->src_port_mask = 0xffff; 2329 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2330 filter->ip_addr_type = 2331 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2332 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2333 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2334 rte_memcpy(filter->src_ipaddr, 2335 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2336 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2337 rte_memcpy(filter->dst_ipaddr, 2338 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2339 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2340 memset(filter->dst_ipaddr_mask, 0xff, 16); 2341 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2342 memset(filter->src_ipaddr_mask, 0xff, 16); 2343 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2344 filter->ethertype = 0x86dd; 2345 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2346 break; 2347 case RTE_ETH_FLOW_L2_PAYLOAD: 2348 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2349 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2350 break; 2351 case RTE_ETH_FLOW_VXLAN: 2352 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2353 return -EINVAL; 2354 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2355 filter->tunnel_type = 2356 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2357 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2358 break; 2359 case RTE_ETH_FLOW_NVGRE: 2360 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2361 return -EINVAL; 2362 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2363 filter->tunnel_type = 2364 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2365 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2366 break; 2367 case RTE_ETH_FLOW_UNKNOWN: 2368 case RTE_ETH_FLOW_RAW: 2369 case RTE_ETH_FLOW_FRAG_IPV4: 2370 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2371 case RTE_ETH_FLOW_FRAG_IPV6: 2372 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2373 case RTE_ETH_FLOW_IPV6_EX: 2374 case RTE_ETH_FLOW_IPV6_TCP_EX: 2375 case RTE_ETH_FLOW_IPV6_UDP_EX: 2376 case RTE_ETH_FLOW_GENEVE: 2377 /* FALLTHROUGH */ 2378 default: 2379 return -EINVAL; 2380 } 2381 2382 vnic0 = &bp->vnic_info[0]; 2383 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2384 if (vnic == NULL) { 2385 PMD_DRV_LOG(ERR, "Invalid queue %d\n", fdir->action.rx_queue); 2386 return -EINVAL; 2387 } 2388 2389 2390 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2391 rte_memcpy(filter->dst_macaddr, 2392 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2393 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2394 } 2395 2396 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2397 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2398 filter1 = STAILQ_FIRST(&vnic0->filter); 2399 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2400 } else { 2401 filter->dst_id = vnic->fw_vnic_id; 2402 for (i = 0; i < RTE_ETHER_ADDR_LEN; i++) 2403 if (filter->dst_macaddr[i] == 0x00) 2404 filter1 = STAILQ_FIRST(&vnic0->filter); 2405 else 2406 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2407 } 2408 2409 if (filter1 == NULL) 2410 return -EINVAL; 2411 2412 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2413 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2414 2415 filter->enables = en; 2416 2417 return 0; 2418 } 2419 2420 static struct bnxt_filter_info * 2421 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf, 2422 struct bnxt_vnic_info **mvnic) 2423 { 2424 struct bnxt_filter_info *mf = NULL; 2425 int i; 2426 2427 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2428 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2429 2430 STAILQ_FOREACH(mf, &vnic->filter, next) { 2431 if (mf->filter_type == nf->filter_type && 2432 mf->flags == nf->flags && 2433 mf->src_port == nf->src_port && 2434 mf->src_port_mask == nf->src_port_mask && 2435 mf->dst_port == nf->dst_port && 2436 mf->dst_port_mask == nf->dst_port_mask && 2437 mf->ip_protocol == nf->ip_protocol && 2438 mf->ip_addr_type == nf->ip_addr_type && 2439 mf->ethertype == nf->ethertype && 2440 mf->vni == nf->vni && 2441 mf->tunnel_type == nf->tunnel_type && 2442 mf->l2_ovlan == nf->l2_ovlan && 2443 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 2444 mf->l2_ivlan == nf->l2_ivlan && 2445 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 2446 !memcmp(mf->l2_addr, nf->l2_addr, 2447 RTE_ETHER_ADDR_LEN) && 2448 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 2449 RTE_ETHER_ADDR_LEN) && 2450 !memcmp(mf->src_macaddr, nf->src_macaddr, 2451 RTE_ETHER_ADDR_LEN) && 2452 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 2453 RTE_ETHER_ADDR_LEN) && 2454 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 2455 sizeof(nf->src_ipaddr)) && 2456 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 2457 sizeof(nf->src_ipaddr_mask)) && 2458 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 2459 sizeof(nf->dst_ipaddr)) && 2460 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 2461 sizeof(nf->dst_ipaddr_mask))) { 2462 if (mvnic) 2463 *mvnic = vnic; 2464 return mf; 2465 } 2466 } 2467 } 2468 return NULL; 2469 } 2470 2471 static int 2472 bnxt_fdir_filter(struct rte_eth_dev *dev, 2473 enum rte_filter_op filter_op, 2474 void *arg) 2475 { 2476 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2477 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 2478 struct bnxt_filter_info *filter, *match; 2479 struct bnxt_vnic_info *vnic, *mvnic; 2480 int ret = 0, i; 2481 2482 if (filter_op == RTE_ETH_FILTER_NOP) 2483 return 0; 2484 2485 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 2486 return -EINVAL; 2487 2488 switch (filter_op) { 2489 case RTE_ETH_FILTER_ADD: 2490 case RTE_ETH_FILTER_DELETE: 2491 /* FALLTHROUGH */ 2492 filter = bnxt_get_unused_filter(bp); 2493 if (filter == NULL) { 2494 PMD_DRV_LOG(ERR, 2495 "Not enough resources for a new flow.\n"); 2496 return -ENOMEM; 2497 } 2498 2499 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 2500 if (ret != 0) 2501 goto free_filter; 2502 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2503 2504 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2505 vnic = &bp->vnic_info[0]; 2506 else 2507 vnic = &bp->vnic_info[fdir->action.rx_queue]; 2508 2509 match = bnxt_match_fdir(bp, filter, &mvnic); 2510 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2511 if (match->dst_id == vnic->fw_vnic_id) { 2512 PMD_DRV_LOG(ERR, "Flow already exists.\n"); 2513 ret = -EEXIST; 2514 goto free_filter; 2515 } else { 2516 match->dst_id = vnic->fw_vnic_id; 2517 ret = bnxt_hwrm_set_ntuple_filter(bp, 2518 match->dst_id, 2519 match); 2520 STAILQ_REMOVE(&mvnic->filter, match, 2521 bnxt_filter_info, next); 2522 STAILQ_INSERT_TAIL(&vnic->filter, match, next); 2523 PMD_DRV_LOG(ERR, 2524 "Filter with matching pattern exist\n"); 2525 PMD_DRV_LOG(ERR, 2526 "Updated it to new destination q\n"); 2527 goto free_filter; 2528 } 2529 } 2530 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2531 PMD_DRV_LOG(ERR, "Flow does not exist.\n"); 2532 ret = -ENOENT; 2533 goto free_filter; 2534 } 2535 2536 if (filter_op == RTE_ETH_FILTER_ADD) { 2537 ret = bnxt_hwrm_set_ntuple_filter(bp, 2538 filter->dst_id, 2539 filter); 2540 if (ret) 2541 goto free_filter; 2542 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2543 } else { 2544 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 2545 STAILQ_REMOVE(&vnic->filter, match, 2546 bnxt_filter_info, next); 2547 bnxt_free_filter(bp, match); 2548 filter->fw_l2_filter_id = -1; 2549 bnxt_free_filter(bp, filter); 2550 } 2551 break; 2552 case RTE_ETH_FILTER_FLUSH: 2553 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2554 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2555 2556 STAILQ_FOREACH(filter, &vnic->filter, next) { 2557 if (filter->filter_type == 2558 HWRM_CFA_NTUPLE_FILTER) { 2559 ret = 2560 bnxt_hwrm_clear_ntuple_filter(bp, 2561 filter); 2562 STAILQ_REMOVE(&vnic->filter, filter, 2563 bnxt_filter_info, next); 2564 } 2565 } 2566 } 2567 return ret; 2568 case RTE_ETH_FILTER_UPDATE: 2569 case RTE_ETH_FILTER_STATS: 2570 case RTE_ETH_FILTER_INFO: 2571 PMD_DRV_LOG(ERR, "operation %u not implemented", filter_op); 2572 break; 2573 default: 2574 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op); 2575 ret = -EINVAL; 2576 break; 2577 } 2578 return ret; 2579 2580 free_filter: 2581 filter->fw_l2_filter_id = -1; 2582 bnxt_free_filter(bp, filter); 2583 return ret; 2584 } 2585 2586 static int 2587 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 2588 enum rte_filter_type filter_type, 2589 enum rte_filter_op filter_op, void *arg) 2590 { 2591 int ret = 0; 2592 2593 switch (filter_type) { 2594 case RTE_ETH_FILTER_TUNNEL: 2595 PMD_DRV_LOG(ERR, 2596 "filter type: %d: To be implemented\n", filter_type); 2597 break; 2598 case RTE_ETH_FILTER_FDIR: 2599 ret = bnxt_fdir_filter(dev, filter_op, arg); 2600 break; 2601 case RTE_ETH_FILTER_NTUPLE: 2602 ret = bnxt_ntuple_filter(dev, filter_op, arg); 2603 break; 2604 case RTE_ETH_FILTER_ETHERTYPE: 2605 ret = bnxt_ethertype_filter(dev, filter_op, arg); 2606 break; 2607 case RTE_ETH_FILTER_GENERIC: 2608 if (filter_op != RTE_ETH_FILTER_GET) 2609 return -EINVAL; 2610 *(const void **)arg = &bnxt_flow_ops; 2611 break; 2612 default: 2613 PMD_DRV_LOG(ERR, 2614 "Filter type (%d) not supported", filter_type); 2615 ret = -EINVAL; 2616 break; 2617 } 2618 return ret; 2619 } 2620 2621 static const uint32_t * 2622 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 2623 { 2624 static const uint32_t ptypes[] = { 2625 RTE_PTYPE_L2_ETHER_VLAN, 2626 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2627 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2628 RTE_PTYPE_L4_ICMP, 2629 RTE_PTYPE_L4_TCP, 2630 RTE_PTYPE_L4_UDP, 2631 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2632 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2633 RTE_PTYPE_INNER_L4_ICMP, 2634 RTE_PTYPE_INNER_L4_TCP, 2635 RTE_PTYPE_INNER_L4_UDP, 2636 RTE_PTYPE_UNKNOWN 2637 }; 2638 2639 if (dev->rx_pkt_burst == bnxt_recv_pkts) 2640 return ptypes; 2641 return NULL; 2642 } 2643 2644 static int bnxt_map_regs(struct bnxt *bp, uint32_t *reg_arr, int count, 2645 int reg_win) 2646 { 2647 uint32_t reg_base = *reg_arr & 0xfffff000; 2648 uint32_t win_off; 2649 int i; 2650 2651 for (i = 0; i < count; i++) { 2652 if ((reg_arr[i] & 0xfffff000) != reg_base) 2653 return -ERANGE; 2654 } 2655 win_off = BNXT_GRCPF_REG_WINDOW_BASE_OUT + (reg_win - 1) * 4; 2656 rte_write32(reg_base, (uint8_t *)bp->bar0 + win_off); 2657 return 0; 2658 } 2659 2660 static int bnxt_map_ptp_regs(struct bnxt *bp) 2661 { 2662 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2663 uint32_t *reg_arr; 2664 int rc, i; 2665 2666 reg_arr = ptp->rx_regs; 2667 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_RX_REGS, 5); 2668 if (rc) 2669 return rc; 2670 2671 reg_arr = ptp->tx_regs; 2672 rc = bnxt_map_regs(bp, reg_arr, BNXT_PTP_TX_REGS, 6); 2673 if (rc) 2674 return rc; 2675 2676 for (i = 0; i < BNXT_PTP_RX_REGS; i++) 2677 ptp->rx_mapped_regs[i] = 0x5000 + (ptp->rx_regs[i] & 0xfff); 2678 2679 for (i = 0; i < BNXT_PTP_TX_REGS; i++) 2680 ptp->tx_mapped_regs[i] = 0x6000 + (ptp->tx_regs[i] & 0xfff); 2681 2682 return 0; 2683 } 2684 2685 static void bnxt_unmap_ptp_regs(struct bnxt *bp) 2686 { 2687 rte_write32(0, (uint8_t *)bp->bar0 + 2688 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 16); 2689 rte_write32(0, (uint8_t *)bp->bar0 + 2690 BNXT_GRCPF_REG_WINDOW_BASE_OUT + 20); 2691 } 2692 2693 static uint64_t bnxt_cc_read(struct bnxt *bp) 2694 { 2695 uint64_t ns; 2696 2697 ns = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2698 BNXT_GRCPF_REG_SYNC_TIME)); 2699 ns |= (uint64_t)(rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2700 BNXT_GRCPF_REG_SYNC_TIME + 4))) << 32; 2701 return ns; 2702 } 2703 2704 static int bnxt_get_tx_ts(struct bnxt *bp, uint64_t *ts) 2705 { 2706 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2707 uint32_t fifo; 2708 2709 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2710 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2711 if (fifo & BNXT_PTP_TX_FIFO_EMPTY) 2712 return -EAGAIN; 2713 2714 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2715 ptp->tx_mapped_regs[BNXT_PTP_TX_FIFO])); 2716 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2717 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_L])); 2718 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2719 ptp->tx_mapped_regs[BNXT_PTP_TX_TS_H])) << 32; 2720 2721 return 0; 2722 } 2723 2724 static int bnxt_get_rx_ts(struct bnxt *bp, uint64_t *ts) 2725 { 2726 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2727 struct bnxt_pf_info *pf = &bp->pf; 2728 uint16_t port_id; 2729 uint32_t fifo; 2730 2731 if (!ptp) 2732 return -ENODEV; 2733 2734 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2735 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2736 if (!(fifo & BNXT_PTP_RX_FIFO_PENDING)) 2737 return -EAGAIN; 2738 2739 port_id = pf->port_id; 2740 rte_write32(1 << port_id, (uint8_t *)bp->bar0 + 2741 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO_ADV]); 2742 2743 fifo = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2744 ptp->rx_mapped_regs[BNXT_PTP_RX_FIFO])); 2745 if (fifo & BNXT_PTP_RX_FIFO_PENDING) { 2746 /* bnxt_clr_rx_ts(bp); TBD */ 2747 return -EBUSY; 2748 } 2749 2750 *ts = rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2751 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_L])); 2752 *ts |= (uint64_t)rte_le_to_cpu_32(rte_read32((uint8_t *)bp->bar0 + 2753 ptp->rx_mapped_regs[BNXT_PTP_RX_TS_H])) << 32; 2754 2755 return 0; 2756 } 2757 2758 static int 2759 bnxt_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts) 2760 { 2761 uint64_t ns; 2762 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2763 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2764 2765 if (!ptp) 2766 return 0; 2767 2768 ns = rte_timespec_to_ns(ts); 2769 /* Set the timecounters to a new value. */ 2770 ptp->tc.nsec = ns; 2771 2772 return 0; 2773 } 2774 2775 static int 2776 bnxt_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts) 2777 { 2778 uint64_t ns, systime_cycles; 2779 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2780 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2781 2782 if (!ptp) 2783 return 0; 2784 2785 systime_cycles = bnxt_cc_read(bp); 2786 ns = rte_timecounter_update(&ptp->tc, systime_cycles); 2787 *ts = rte_ns_to_timespec(ns); 2788 2789 return 0; 2790 } 2791 static int 2792 bnxt_timesync_enable(struct rte_eth_dev *dev) 2793 { 2794 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2795 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2796 uint32_t shift = 0; 2797 2798 if (!ptp) 2799 return 0; 2800 2801 ptp->rx_filter = 1; 2802 ptp->tx_tstamp_en = 1; 2803 ptp->rxctl = BNXT_PTP_MSG_EVENTS; 2804 2805 if (!bnxt_hwrm_ptp_cfg(bp)) 2806 bnxt_map_ptp_regs(bp); 2807 2808 memset(&ptp->tc, 0, sizeof(struct rte_timecounter)); 2809 memset(&ptp->rx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 2810 memset(&ptp->tx_tstamp_tc, 0, sizeof(struct rte_timecounter)); 2811 2812 ptp->tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2813 ptp->tc.cc_shift = shift; 2814 ptp->tc.nsec_mask = (1ULL << shift) - 1; 2815 2816 ptp->rx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2817 ptp->rx_tstamp_tc.cc_shift = shift; 2818 ptp->rx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 2819 2820 ptp->tx_tstamp_tc.cc_mask = BNXT_CYCLECOUNTER_MASK; 2821 ptp->tx_tstamp_tc.cc_shift = shift; 2822 ptp->tx_tstamp_tc.nsec_mask = (1ULL << shift) - 1; 2823 2824 return 0; 2825 } 2826 2827 static int 2828 bnxt_timesync_disable(struct rte_eth_dev *dev) 2829 { 2830 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2831 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2832 2833 if (!ptp) 2834 return 0; 2835 2836 ptp->rx_filter = 0; 2837 ptp->tx_tstamp_en = 0; 2838 ptp->rxctl = 0; 2839 2840 bnxt_hwrm_ptp_cfg(bp); 2841 2842 bnxt_unmap_ptp_regs(bp); 2843 2844 return 0; 2845 } 2846 2847 static int 2848 bnxt_timesync_read_rx_timestamp(struct rte_eth_dev *dev, 2849 struct timespec *timestamp, 2850 uint32_t flags __rte_unused) 2851 { 2852 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2853 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2854 uint64_t rx_tstamp_cycles = 0; 2855 uint64_t ns; 2856 2857 if (!ptp) 2858 return 0; 2859 2860 bnxt_get_rx_ts(bp, &rx_tstamp_cycles); 2861 ns = rte_timecounter_update(&ptp->rx_tstamp_tc, rx_tstamp_cycles); 2862 *timestamp = rte_ns_to_timespec(ns); 2863 return 0; 2864 } 2865 2866 static int 2867 bnxt_timesync_read_tx_timestamp(struct rte_eth_dev *dev, 2868 struct timespec *timestamp) 2869 { 2870 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2871 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2872 uint64_t tx_tstamp_cycles = 0; 2873 uint64_t ns; 2874 2875 if (!ptp) 2876 return 0; 2877 2878 bnxt_get_tx_ts(bp, &tx_tstamp_cycles); 2879 ns = rte_timecounter_update(&ptp->tx_tstamp_tc, tx_tstamp_cycles); 2880 *timestamp = rte_ns_to_timespec(ns); 2881 2882 return 0; 2883 } 2884 2885 static int 2886 bnxt_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta) 2887 { 2888 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2889 struct bnxt_ptp_cfg *ptp = bp->ptp_cfg; 2890 2891 if (!ptp) 2892 return 0; 2893 2894 ptp->tc.nsec += delta; 2895 2896 return 0; 2897 } 2898 2899 static int 2900 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 2901 { 2902 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2903 int rc; 2904 uint32_t dir_entries; 2905 uint32_t entry_length; 2906 2907 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x\n", 2908 bp->pdev->addr.domain, bp->pdev->addr.bus, 2909 bp->pdev->addr.devid, bp->pdev->addr.function); 2910 2911 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 2912 if (rc != 0) 2913 return rc; 2914 2915 return dir_entries * entry_length; 2916 } 2917 2918 static int 2919 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 2920 struct rte_dev_eeprom_info *in_eeprom) 2921 { 2922 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2923 uint32_t index; 2924 uint32_t offset; 2925 2926 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 2927 "len = %d\n", bp->pdev->addr.domain, 2928 bp->pdev->addr.bus, bp->pdev->addr.devid, 2929 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2930 2931 if (in_eeprom->offset == 0) /* special offset value to get directory */ 2932 return bnxt_get_nvram_directory(bp, in_eeprom->length, 2933 in_eeprom->data); 2934 2935 index = in_eeprom->offset >> 24; 2936 offset = in_eeprom->offset & 0xffffff; 2937 2938 if (index != 0) 2939 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 2940 in_eeprom->length, in_eeprom->data); 2941 2942 return 0; 2943 } 2944 2945 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 2946 { 2947 switch (dir_type) { 2948 case BNX_DIR_TYPE_CHIMP_PATCH: 2949 case BNX_DIR_TYPE_BOOTCODE: 2950 case BNX_DIR_TYPE_BOOTCODE_2: 2951 case BNX_DIR_TYPE_APE_FW: 2952 case BNX_DIR_TYPE_APE_PATCH: 2953 case BNX_DIR_TYPE_KONG_FW: 2954 case BNX_DIR_TYPE_KONG_PATCH: 2955 case BNX_DIR_TYPE_BONO_FW: 2956 case BNX_DIR_TYPE_BONO_PATCH: 2957 /* FALLTHROUGH */ 2958 return true; 2959 } 2960 2961 return false; 2962 } 2963 2964 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 2965 { 2966 switch (dir_type) { 2967 case BNX_DIR_TYPE_AVS: 2968 case BNX_DIR_TYPE_EXP_ROM_MBA: 2969 case BNX_DIR_TYPE_PCIE: 2970 case BNX_DIR_TYPE_TSCF_UCODE: 2971 case BNX_DIR_TYPE_EXT_PHY: 2972 case BNX_DIR_TYPE_CCM: 2973 case BNX_DIR_TYPE_ISCSI_BOOT: 2974 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2975 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2976 /* FALLTHROUGH */ 2977 return true; 2978 } 2979 2980 return false; 2981 } 2982 2983 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 2984 { 2985 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2986 bnxt_dir_type_is_other_exec_format(dir_type); 2987 } 2988 2989 static int 2990 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 2991 struct rte_dev_eeprom_info *in_eeprom) 2992 { 2993 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2994 uint8_t index, dir_op; 2995 uint16_t type, ext, ordinal, attr; 2996 2997 PMD_DRV_LOG(INFO, "%04x:%02x:%02x:%02x in_eeprom->offset = %d " 2998 "len = %d\n", bp->pdev->addr.domain, 2999 bp->pdev->addr.bus, bp->pdev->addr.devid, 3000 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 3001 3002 if (!BNXT_PF(bp)) { 3003 PMD_DRV_LOG(ERR, "NVM write not supported from a VF\n"); 3004 return -EINVAL; 3005 } 3006 3007 type = in_eeprom->magic >> 16; 3008 3009 if (type == 0xffff) { /* special value for directory operations */ 3010 index = in_eeprom->magic & 0xff; 3011 dir_op = in_eeprom->magic >> 8; 3012 if (index == 0) 3013 return -EINVAL; 3014 switch (dir_op) { 3015 case 0x0e: /* erase */ 3016 if (in_eeprom->offset != ~in_eeprom->magic) 3017 return -EINVAL; 3018 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 3019 default: 3020 return -EINVAL; 3021 } 3022 } 3023 3024 /* Create or re-write an NVM item: */ 3025 if (bnxt_dir_type_is_executable(type) == true) 3026 return -EOPNOTSUPP; 3027 ext = in_eeprom->magic & 0xffff; 3028 ordinal = in_eeprom->offset >> 16; 3029 attr = in_eeprom->offset & 0xffff; 3030 3031 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 3032 in_eeprom->data, in_eeprom->length); 3033 return 0; 3034 } 3035 3036 /* 3037 * Initialization 3038 */ 3039 3040 static const struct eth_dev_ops bnxt_dev_ops = { 3041 .dev_infos_get = bnxt_dev_info_get_op, 3042 .dev_close = bnxt_dev_close_op, 3043 .dev_configure = bnxt_dev_configure_op, 3044 .dev_start = bnxt_dev_start_op, 3045 .dev_stop = bnxt_dev_stop_op, 3046 .dev_set_link_up = bnxt_dev_set_link_up_op, 3047 .dev_set_link_down = bnxt_dev_set_link_down_op, 3048 .stats_get = bnxt_stats_get_op, 3049 .stats_reset = bnxt_stats_reset_op, 3050 .rx_queue_setup = bnxt_rx_queue_setup_op, 3051 .rx_queue_release = bnxt_rx_queue_release_op, 3052 .tx_queue_setup = bnxt_tx_queue_setup_op, 3053 .tx_queue_release = bnxt_tx_queue_release_op, 3054 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 3055 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 3056 .reta_update = bnxt_reta_update_op, 3057 .reta_query = bnxt_reta_query_op, 3058 .rss_hash_update = bnxt_rss_hash_update_op, 3059 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 3060 .link_update = bnxt_link_update_op, 3061 .promiscuous_enable = bnxt_promiscuous_enable_op, 3062 .promiscuous_disable = bnxt_promiscuous_disable_op, 3063 .allmulticast_enable = bnxt_allmulticast_enable_op, 3064 .allmulticast_disable = bnxt_allmulticast_disable_op, 3065 .mac_addr_add = bnxt_mac_addr_add_op, 3066 .mac_addr_remove = bnxt_mac_addr_remove_op, 3067 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 3068 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 3069 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 3070 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 3071 .vlan_filter_set = bnxt_vlan_filter_set_op, 3072 .vlan_offload_set = bnxt_vlan_offload_set_op, 3073 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 3074 .mtu_set = bnxt_mtu_set_op, 3075 .mac_addr_set = bnxt_set_default_mac_addr_op, 3076 .xstats_get = bnxt_dev_xstats_get_op, 3077 .xstats_get_names = bnxt_dev_xstats_get_names_op, 3078 .xstats_reset = bnxt_dev_xstats_reset_op, 3079 .fw_version_get = bnxt_fw_version_get, 3080 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 3081 .rxq_info_get = bnxt_rxq_info_get_op, 3082 .txq_info_get = bnxt_txq_info_get_op, 3083 .dev_led_on = bnxt_dev_led_on_op, 3084 .dev_led_off = bnxt_dev_led_off_op, 3085 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 3086 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 3087 .rx_queue_count = bnxt_rx_queue_count_op, 3088 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 3089 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 3090 .rx_queue_start = bnxt_rx_queue_start, 3091 .rx_queue_stop = bnxt_rx_queue_stop, 3092 .tx_queue_start = bnxt_tx_queue_start, 3093 .tx_queue_stop = bnxt_tx_queue_stop, 3094 .filter_ctrl = bnxt_filter_ctrl_op, 3095 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 3096 .get_eeprom_length = bnxt_get_eeprom_length_op, 3097 .get_eeprom = bnxt_get_eeprom_op, 3098 .set_eeprom = bnxt_set_eeprom_op, 3099 .timesync_enable = bnxt_timesync_enable, 3100 .timesync_disable = bnxt_timesync_disable, 3101 .timesync_read_time = bnxt_timesync_read_time, 3102 .timesync_write_time = bnxt_timesync_write_time, 3103 .timesync_adjust_time = bnxt_timesync_adjust_time, 3104 .timesync_read_rx_timestamp = bnxt_timesync_read_rx_timestamp, 3105 .timesync_read_tx_timestamp = bnxt_timesync_read_tx_timestamp, 3106 }; 3107 3108 static bool bnxt_vf_pciid(uint16_t id) 3109 { 3110 if (id == BROADCOM_DEV_ID_57304_VF || 3111 id == BROADCOM_DEV_ID_57406_VF || 3112 id == BROADCOM_DEV_ID_5731X_VF || 3113 id == BROADCOM_DEV_ID_5741X_VF || 3114 id == BROADCOM_DEV_ID_57414_VF || 3115 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3116 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2 || 3117 id == BROADCOM_DEV_ID_58802_VF) 3118 return true; 3119 return false; 3120 } 3121 3122 bool bnxt_stratus_device(struct bnxt *bp) 3123 { 3124 uint16_t id = bp->pdev->id.device_id; 3125 3126 if (id == BROADCOM_DEV_ID_STRATUS_NIC || 3127 id == BROADCOM_DEV_ID_STRATUS_NIC_VF1 || 3128 id == BROADCOM_DEV_ID_STRATUS_NIC_VF2) 3129 return true; 3130 return false; 3131 } 3132 3133 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 3134 { 3135 struct bnxt *bp = eth_dev->data->dev_private; 3136 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3137 int rc; 3138 3139 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 3140 if (!pci_dev->mem_resource[0].addr) { 3141 PMD_DRV_LOG(ERR, 3142 "Cannot find PCI device base address, aborting\n"); 3143 rc = -ENODEV; 3144 goto init_err_disable; 3145 } 3146 3147 bp->eth_dev = eth_dev; 3148 bp->pdev = pci_dev; 3149 3150 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 3151 if (!bp->bar0) { 3152 PMD_DRV_LOG(ERR, "Cannot map device registers, aborting\n"); 3153 rc = -ENOMEM; 3154 goto init_err_release; 3155 } 3156 3157 if (!pci_dev->mem_resource[2].addr) { 3158 PMD_DRV_LOG(ERR, 3159 "Cannot find PCI device BAR 2 address, aborting\n"); 3160 rc = -ENODEV; 3161 goto init_err_release; 3162 } else { 3163 bp->doorbell_base = (void *)pci_dev->mem_resource[2].addr; 3164 } 3165 3166 return 0; 3167 3168 init_err_release: 3169 if (bp->bar0) 3170 bp->bar0 = NULL; 3171 if (bp->doorbell_base) 3172 bp->doorbell_base = NULL; 3173 3174 init_err_disable: 3175 3176 return rc; 3177 } 3178 3179 3180 #define ALLOW_FUNC(x) \ 3181 { \ 3182 typeof(x) arg = (x); \ 3183 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 3184 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 3185 } 3186 static int 3187 bnxt_dev_init(struct rte_eth_dev *eth_dev) 3188 { 3189 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 3190 char mz_name[RTE_MEMZONE_NAMESIZE]; 3191 const struct rte_memzone *mz = NULL; 3192 static int version_printed; 3193 uint32_t total_alloc_len; 3194 rte_iova_t mz_phys_addr; 3195 struct bnxt *bp; 3196 int rc; 3197 3198 if (version_printed++ == 0) 3199 PMD_DRV_LOG(INFO, "%s\n", bnxt_version); 3200 3201 rte_eth_copy_pci_info(eth_dev, pci_dev); 3202 3203 bp = eth_dev->data->dev_private; 3204 3205 bp->dev_stopped = 1; 3206 3207 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3208 goto skip_init; 3209 3210 if (bnxt_vf_pciid(pci_dev->id.device_id)) 3211 bp->flags |= BNXT_FLAG_VF; 3212 3213 rc = bnxt_init_board(eth_dev); 3214 if (rc) { 3215 PMD_DRV_LOG(ERR, 3216 "Board initialization failed rc: %x\n", rc); 3217 goto error; 3218 } 3219 skip_init: 3220 eth_dev->dev_ops = &bnxt_dev_ops; 3221 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 3222 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 3223 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3224 return 0; 3225 3226 if (pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) { 3227 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3228 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 3229 pci_dev->addr.bus, pci_dev->addr.devid, 3230 pci_dev->addr.function, "rx_port_stats"); 3231 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3232 mz = rte_memzone_lookup(mz_name); 3233 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 3234 sizeof(struct rx_port_stats) + 3235 sizeof(struct rx_port_stats_ext) + 3236 512); 3237 if (!mz) { 3238 mz = rte_memzone_reserve(mz_name, total_alloc_len, 3239 SOCKET_ID_ANY, 3240 RTE_MEMZONE_2MB | 3241 RTE_MEMZONE_SIZE_HINT_ONLY | 3242 RTE_MEMZONE_IOVA_CONTIG); 3243 if (mz == NULL) 3244 return -ENOMEM; 3245 } 3246 memset(mz->addr, 0, mz->len); 3247 mz_phys_addr = mz->iova; 3248 if ((unsigned long)mz->addr == mz_phys_addr) { 3249 PMD_DRV_LOG(INFO, 3250 "Memzone physical address same as virtual using rte_mem_virt2iova()\n"); 3251 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3252 if (mz_phys_addr == 0) { 3253 PMD_DRV_LOG(ERR, 3254 "unable to map address to physical memory\n"); 3255 return -ENOMEM; 3256 } 3257 } 3258 3259 bp->rx_mem_zone = (const void *)mz; 3260 bp->hw_rx_port_stats = mz->addr; 3261 bp->hw_rx_port_stats_map = mz_phys_addr; 3262 3263 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 3264 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 3265 pci_dev->addr.bus, pci_dev->addr.devid, 3266 pci_dev->addr.function, "tx_port_stats"); 3267 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 3268 mz = rte_memzone_lookup(mz_name); 3269 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 3270 sizeof(struct tx_port_stats) + 3271 sizeof(struct tx_port_stats_ext) + 3272 512); 3273 if (!mz) { 3274 mz = rte_memzone_reserve(mz_name, 3275 total_alloc_len, 3276 SOCKET_ID_ANY, 3277 RTE_MEMZONE_2MB | 3278 RTE_MEMZONE_SIZE_HINT_ONLY | 3279 RTE_MEMZONE_IOVA_CONTIG); 3280 if (mz == NULL) 3281 return -ENOMEM; 3282 } 3283 memset(mz->addr, 0, mz->len); 3284 mz_phys_addr = mz->iova; 3285 if ((unsigned long)mz->addr == mz_phys_addr) { 3286 PMD_DRV_LOG(WARNING, 3287 "Memzone physical address same as virtual.\n"); 3288 PMD_DRV_LOG(WARNING, 3289 "Using rte_mem_virt2iova()\n"); 3290 mz_phys_addr = rte_mem_virt2iova(mz->addr); 3291 if (mz_phys_addr == 0) { 3292 PMD_DRV_LOG(ERR, 3293 "unable to map address to physical memory\n"); 3294 return -ENOMEM; 3295 } 3296 } 3297 3298 bp->tx_mem_zone = (const void *)mz; 3299 bp->hw_tx_port_stats = mz->addr; 3300 bp->hw_tx_port_stats_map = mz_phys_addr; 3301 3302 bp->flags |= BNXT_FLAG_PORT_STATS; 3303 3304 /* Display extended statistics if FW supports it */ 3305 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_8_4 || 3306 bp->hwrm_spec_code == HWRM_SPEC_CODE_1_9_0) 3307 goto skip_ext_stats; 3308 3309 bp->hw_rx_port_stats_ext = (void *) 3310 (bp->hw_rx_port_stats + sizeof(struct rx_port_stats)); 3311 bp->hw_rx_port_stats_ext_map = bp->hw_rx_port_stats_map + 3312 sizeof(struct rx_port_stats); 3313 bp->flags |= BNXT_FLAG_EXT_RX_PORT_STATS; 3314 3315 3316 if (bp->hwrm_spec_code < HWRM_SPEC_CODE_1_9_2) { 3317 bp->hw_tx_port_stats_ext = (void *) 3318 (bp->hw_tx_port_stats + sizeof(struct tx_port_stats)); 3319 bp->hw_tx_port_stats_ext_map = 3320 bp->hw_tx_port_stats_map + 3321 sizeof(struct tx_port_stats); 3322 bp->flags |= BNXT_FLAG_EXT_TX_PORT_STATS; 3323 } 3324 } 3325 3326 skip_ext_stats: 3327 rc = bnxt_alloc_hwrm_resources(bp); 3328 if (rc) { 3329 PMD_DRV_LOG(ERR, 3330 "hwrm resource allocation failure rc: %x\n", rc); 3331 goto error_free; 3332 } 3333 rc = bnxt_hwrm_ver_get(bp); 3334 if (rc) 3335 goto error_free; 3336 rc = bnxt_hwrm_queue_qportcfg(bp); 3337 if (rc) { 3338 PMD_DRV_LOG(ERR, "hwrm queue qportcfg failed\n"); 3339 goto error_free; 3340 } 3341 3342 rc = bnxt_hwrm_func_qcfg(bp); 3343 if (rc) { 3344 PMD_DRV_LOG(ERR, "hwrm func qcfg failed\n"); 3345 goto error_free; 3346 } 3347 3348 /* Get the MAX capabilities for this function */ 3349 rc = bnxt_hwrm_func_qcaps(bp); 3350 if (rc) { 3351 PMD_DRV_LOG(ERR, "hwrm query capability failure rc: %x\n", rc); 3352 goto error_free; 3353 } 3354 if (bp->max_tx_rings == 0) { 3355 PMD_DRV_LOG(ERR, "No TX rings available!\n"); 3356 rc = -EBUSY; 3357 goto error_free; 3358 } 3359 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 3360 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx, 0); 3361 if (eth_dev->data->mac_addrs == NULL) { 3362 PMD_DRV_LOG(ERR, 3363 "Failed to alloc %u bytes needed to store MAC addr tbl", 3364 RTE_ETHER_ADDR_LEN * bp->max_l2_ctx); 3365 rc = -ENOMEM; 3366 goto error_free; 3367 } 3368 3369 if (bnxt_check_zero_bytes(bp->dflt_mac_addr, RTE_ETHER_ADDR_LEN)) { 3370 PMD_DRV_LOG(ERR, 3371 "Invalid MAC addr %02X:%02X:%02X:%02X:%02X:%02X\n", 3372 bp->dflt_mac_addr[0], bp->dflt_mac_addr[1], 3373 bp->dflt_mac_addr[2], bp->dflt_mac_addr[3], 3374 bp->dflt_mac_addr[4], bp->dflt_mac_addr[5]); 3375 rc = -EINVAL; 3376 goto error_free; 3377 } 3378 /* Copy the permanent MAC from the qcap response address now. */ 3379 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr)); 3380 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, RTE_ETHER_ADDR_LEN); 3381 3382 if (bp->max_ring_grps < bp->rx_cp_nr_rings) { 3383 /* 1 ring is for default completion ring */ 3384 PMD_DRV_LOG(ERR, "Insufficient resource: Ring Group\n"); 3385 rc = -ENOSPC; 3386 goto error_free; 3387 } 3388 3389 bp->grp_info = rte_zmalloc("bnxt_grp_info", 3390 sizeof(*bp->grp_info) * bp->max_ring_grps, 0); 3391 if (!bp->grp_info) { 3392 PMD_DRV_LOG(ERR, 3393 "Failed to alloc %zu bytes to store group info table\n", 3394 sizeof(*bp->grp_info) * bp->max_ring_grps); 3395 rc = -ENOMEM; 3396 goto error_free; 3397 } 3398 3399 /* Forward all requests if firmware is new enough */ 3400 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 3401 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 3402 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 3403 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 3404 } else { 3405 PMD_DRV_LOG(WARNING, 3406 "Firmware too old for VF mailbox functionality\n"); 3407 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 3408 } 3409 3410 /* 3411 * The following are used for driver cleanup. If we disallow these, 3412 * VF drivers can't clean up cleanly. 3413 */ 3414 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 3415 ALLOW_FUNC(HWRM_VNIC_FREE); 3416 ALLOW_FUNC(HWRM_RING_FREE); 3417 ALLOW_FUNC(HWRM_RING_GRP_FREE); 3418 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 3419 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 3420 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 3421 ALLOW_FUNC(HWRM_PORT_PHY_QCFG); 3422 ALLOW_FUNC(HWRM_VNIC_TPA_CFG); 3423 rc = bnxt_hwrm_func_driver_register(bp); 3424 if (rc) { 3425 PMD_DRV_LOG(ERR, 3426 "Failed to register driver"); 3427 rc = -EBUSY; 3428 goto error_free; 3429 } 3430 3431 PMD_DRV_LOG(INFO, 3432 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n", 3433 pci_dev->mem_resource[0].phys_addr, 3434 pci_dev->mem_resource[0].addr); 3435 3436 rc = bnxt_hwrm_func_reset(bp); 3437 if (rc) { 3438 PMD_DRV_LOG(ERR, "hwrm chip reset failure rc: %x\n", rc); 3439 rc = -EIO; 3440 goto error_free; 3441 } 3442 3443 if (BNXT_PF(bp)) { 3444 //if (bp->pf.active_vfs) { 3445 // TODO: Deallocate VF resources? 3446 //} 3447 if (bp->pdev->max_vfs) { 3448 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 3449 if (rc) { 3450 PMD_DRV_LOG(ERR, "Failed to allocate VFs\n"); 3451 goto error_free; 3452 } 3453 } else { 3454 rc = bnxt_hwrm_allocate_pf_only(bp); 3455 if (rc) { 3456 PMD_DRV_LOG(ERR, 3457 "Failed to allocate PF resources\n"); 3458 goto error_free; 3459 } 3460 } 3461 } 3462 3463 bnxt_hwrm_port_led_qcaps(bp); 3464 3465 rc = bnxt_setup_int(bp); 3466 if (rc) 3467 goto error_free; 3468 3469 rc = bnxt_alloc_mem(bp); 3470 if (rc) 3471 goto error_free_int; 3472 3473 rc = bnxt_request_int(bp); 3474 if (rc) 3475 goto error_free_int; 3476 3477 bnxt_enable_int(bp); 3478 bnxt_init_nic(bp); 3479 3480 return 0; 3481 3482 error_free_int: 3483 bnxt_disable_int(bp); 3484 bnxt_hwrm_func_buf_unrgtr(bp); 3485 bnxt_free_int(bp); 3486 bnxt_free_mem(bp); 3487 error_free: 3488 bnxt_dev_uninit(eth_dev); 3489 error: 3490 return rc; 3491 } 3492 3493 static int 3494 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) 3495 { 3496 struct bnxt *bp = eth_dev->data->dev_private; 3497 int rc; 3498 3499 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3500 return -EPERM; 3501 3502 PMD_DRV_LOG(DEBUG, "Calling Device uninit\n"); 3503 bnxt_disable_int(bp); 3504 bnxt_free_int(bp); 3505 bnxt_free_mem(bp); 3506 if (bp->grp_info != NULL) { 3507 rte_free(bp->grp_info); 3508 bp->grp_info = NULL; 3509 } 3510 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 3511 bnxt_free_hwrm_resources(bp); 3512 3513 if (bp->tx_mem_zone) { 3514 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 3515 bp->tx_mem_zone = NULL; 3516 } 3517 3518 if (bp->rx_mem_zone) { 3519 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 3520 bp->rx_mem_zone = NULL; 3521 } 3522 3523 if (bp->dev_stopped == 0) 3524 bnxt_dev_close_op(eth_dev); 3525 if (bp->pf.vf_info) 3526 rte_free(bp->pf.vf_info); 3527 eth_dev->dev_ops = NULL; 3528 eth_dev->rx_pkt_burst = NULL; 3529 eth_dev->tx_pkt_burst = NULL; 3530 3531 return rc; 3532 } 3533 3534 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3535 struct rte_pci_device *pci_dev) 3536 { 3537 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 3538 bnxt_dev_init); 3539 } 3540 3541 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 3542 { 3543 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 3544 return rte_eth_dev_pci_generic_remove(pci_dev, 3545 bnxt_dev_uninit); 3546 else 3547 return rte_eth_dev_pci_generic_remove(pci_dev, NULL); 3548 } 3549 3550 static struct rte_pci_driver bnxt_rte_pmd = { 3551 .id_table = bnxt_pci_id_map, 3552 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 3553 RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_IOVA_AS_VA, 3554 .probe = bnxt_pci_probe, 3555 .remove = bnxt_pci_remove, 3556 }; 3557 3558 static bool 3559 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 3560 { 3561 if (strcmp(dev->device->driver->name, drv->driver.name)) 3562 return false; 3563 3564 return true; 3565 } 3566 3567 bool is_bnxt_supported(struct rte_eth_dev *dev) 3568 { 3569 return is_device_supported(dev, &bnxt_rte_pmd); 3570 } 3571 3572 RTE_INIT(bnxt_init_log) 3573 { 3574 bnxt_logtype_driver = rte_log_register("pmd.net.bnxt.driver"); 3575 if (bnxt_logtype_driver >= 0) 3576 rte_log_set_level(bnxt_logtype_driver, RTE_LOG_NOTICE); 3577 } 3578 3579 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 3580 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 3581 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 3582