1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) Broadcom Limited. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Broadcom Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <inttypes.h> 35 #include <stdbool.h> 36 37 #include <rte_dev.h> 38 #include <rte_ethdev.h> 39 #include <rte_ethdev_pci.h> 40 #include <rte_malloc.h> 41 #include <rte_cycles.h> 42 43 #include "bnxt.h" 44 #include "bnxt_cpr.h" 45 #include "bnxt_filter.h" 46 #include "bnxt_hwrm.h" 47 #include "bnxt_irq.h" 48 #include "bnxt_ring.h" 49 #include "bnxt_rxq.h" 50 #include "bnxt_rxr.h" 51 #include "bnxt_stats.h" 52 #include "bnxt_txq.h" 53 #include "bnxt_txr.h" 54 #include "bnxt_vnic.h" 55 #include "hsi_struct_def_dpdk.h" 56 #include "bnxt_nvm_defs.h" 57 58 #define DRV_MODULE_NAME "bnxt" 59 static const char bnxt_version[] = 60 "Broadcom Cumulus driver " DRV_MODULE_NAME "\n"; 61 62 #define PCI_VENDOR_ID_BROADCOM 0x14E4 63 64 #define BROADCOM_DEV_ID_STRATUS_NIC_VF 0x1609 65 #define BROADCOM_DEV_ID_STRATUS_NIC 0x1614 66 #define BROADCOM_DEV_ID_57414_VF 0x16c1 67 #define BROADCOM_DEV_ID_57301 0x16c8 68 #define BROADCOM_DEV_ID_57302 0x16c9 69 #define BROADCOM_DEV_ID_57304_PF 0x16ca 70 #define BROADCOM_DEV_ID_57304_VF 0x16cb 71 #define BROADCOM_DEV_ID_57417_MF 0x16cc 72 #define BROADCOM_DEV_ID_NS2 0x16cd 73 #define BROADCOM_DEV_ID_57311 0x16ce 74 #define BROADCOM_DEV_ID_57312 0x16cf 75 #define BROADCOM_DEV_ID_57402 0x16d0 76 #define BROADCOM_DEV_ID_57404 0x16d1 77 #define BROADCOM_DEV_ID_57406_PF 0x16d2 78 #define BROADCOM_DEV_ID_57406_VF 0x16d3 79 #define BROADCOM_DEV_ID_57402_MF 0x16d4 80 #define BROADCOM_DEV_ID_57407_RJ45 0x16d5 81 #define BROADCOM_DEV_ID_57412 0x16d6 82 #define BROADCOM_DEV_ID_57414 0x16d7 83 #define BROADCOM_DEV_ID_57416_RJ45 0x16d8 84 #define BROADCOM_DEV_ID_57417_RJ45 0x16d9 85 #define BROADCOM_DEV_ID_5741X_VF 0x16dc 86 #define BROADCOM_DEV_ID_57412_MF 0x16de 87 #define BROADCOM_DEV_ID_57314 0x16df 88 #define BROADCOM_DEV_ID_57317_RJ45 0x16e0 89 #define BROADCOM_DEV_ID_5731X_VF 0x16e1 90 #define BROADCOM_DEV_ID_57417_SFP 0x16e2 91 #define BROADCOM_DEV_ID_57416_SFP 0x16e3 92 #define BROADCOM_DEV_ID_57317_SFP 0x16e4 93 #define BROADCOM_DEV_ID_57404_MF 0x16e7 94 #define BROADCOM_DEV_ID_57406_MF 0x16e8 95 #define BROADCOM_DEV_ID_57407_SFP 0x16e9 96 #define BROADCOM_DEV_ID_57407_MF 0x16ea 97 #define BROADCOM_DEV_ID_57414_MF 0x16ec 98 #define BROADCOM_DEV_ID_57416_MF 0x16ee 99 100 static const struct rte_pci_id bnxt_pci_id_map[] = { 101 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 102 BROADCOM_DEV_ID_STRATUS_NIC_VF) }, 103 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_STRATUS_NIC) }, 104 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_VF) }, 105 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57301) }, 106 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57302) }, 107 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_PF) }, 108 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57304_VF) }, 109 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_NS2) }, 110 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402) }, 111 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404) }, 112 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_PF) }, 113 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_VF) }, 114 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57402_MF) }, 115 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_RJ45) }, 116 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57404_MF) }, 117 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57406_MF) }, 118 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_SFP) }, 119 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57407_MF) }, 120 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5741X_VF) }, 121 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_5731X_VF) }, 122 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57314) }, 123 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_MF) }, 124 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57311) }, 125 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57312) }, 126 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412) }, 127 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414) }, 128 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_RJ45) }, 129 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_RJ45) }, 130 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57412_MF) }, 131 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_RJ45) }, 132 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57417_SFP) }, 133 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_SFP) }, 134 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57317_SFP) }, 135 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57414_MF) }, 136 { RTE_PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, BROADCOM_DEV_ID_57416_MF) }, 137 { .vendor_id = 0, /* sentinel */ }, 138 }; 139 140 #define BNXT_ETH_RSS_SUPPORT ( \ 141 ETH_RSS_IPV4 | \ 142 ETH_RSS_NONFRAG_IPV4_TCP | \ 143 ETH_RSS_NONFRAG_IPV4_UDP | \ 144 ETH_RSS_IPV6 | \ 145 ETH_RSS_NONFRAG_IPV6_TCP | \ 146 ETH_RSS_NONFRAG_IPV6_UDP) 147 148 static void bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask); 149 150 /***********************/ 151 152 /* 153 * High level utility functions 154 */ 155 156 static void bnxt_free_mem(struct bnxt *bp) 157 { 158 bnxt_free_filter_mem(bp); 159 bnxt_free_vnic_attributes(bp); 160 bnxt_free_vnic_mem(bp); 161 162 bnxt_free_stats(bp); 163 bnxt_free_tx_rings(bp); 164 bnxt_free_rx_rings(bp); 165 bnxt_free_def_cp_ring(bp); 166 } 167 168 static int bnxt_alloc_mem(struct bnxt *bp) 169 { 170 int rc; 171 172 /* Default completion ring */ 173 rc = bnxt_init_def_ring_struct(bp, SOCKET_ID_ANY); 174 if (rc) 175 goto alloc_mem_err; 176 177 rc = bnxt_alloc_rings(bp, 0, NULL, NULL, 178 bp->def_cp_ring, "def_cp"); 179 if (rc) 180 goto alloc_mem_err; 181 182 rc = bnxt_alloc_vnic_mem(bp); 183 if (rc) 184 goto alloc_mem_err; 185 186 rc = bnxt_alloc_vnic_attributes(bp); 187 if (rc) 188 goto alloc_mem_err; 189 190 rc = bnxt_alloc_filter_mem(bp); 191 if (rc) 192 goto alloc_mem_err; 193 194 return 0; 195 196 alloc_mem_err: 197 bnxt_free_mem(bp); 198 return rc; 199 } 200 201 static int bnxt_init_chip(struct bnxt *bp) 202 { 203 unsigned int i, rss_idx, fw_idx; 204 struct rte_eth_link new; 205 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(bp->eth_dev); 206 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; 207 uint32_t intr_vector = 0; 208 uint32_t queue_id, base = BNXT_MISC_VEC_ID; 209 uint32_t vec = BNXT_MISC_VEC_ID; 210 int rc; 211 212 /* disable uio/vfio intr/eventfd mapping */ 213 rte_intr_disable(intr_handle); 214 215 if (bp->eth_dev->data->mtu > ETHER_MTU) { 216 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; 217 bp->flags |= BNXT_FLAG_JUMBO; 218 } else { 219 bp->eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; 220 bp->flags &= ~BNXT_FLAG_JUMBO; 221 } 222 223 rc = bnxt_alloc_all_hwrm_stat_ctxs(bp); 224 if (rc) { 225 RTE_LOG(ERR, PMD, "HWRM stat ctx alloc failure rc: %x\n", rc); 226 goto err_out; 227 } 228 229 rc = bnxt_alloc_hwrm_rings(bp); 230 if (rc) { 231 RTE_LOG(ERR, PMD, "HWRM ring alloc failure rc: %x\n", rc); 232 goto err_out; 233 } 234 235 rc = bnxt_alloc_all_hwrm_ring_grps(bp); 236 if (rc) { 237 RTE_LOG(ERR, PMD, "HWRM ring grp alloc failure: %x\n", rc); 238 goto err_out; 239 } 240 241 rc = bnxt_mq_rx_configure(bp); 242 if (rc) { 243 RTE_LOG(ERR, PMD, "MQ mode configure failure rc: %x\n", rc); 244 goto err_out; 245 } 246 247 /* VNIC configuration */ 248 for (i = 0; i < bp->nr_vnics; i++) { 249 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 250 251 rc = bnxt_hwrm_vnic_alloc(bp, vnic); 252 if (rc) { 253 RTE_LOG(ERR, PMD, "HWRM vnic %d alloc failure rc: %x\n", 254 i, rc); 255 goto err_out; 256 } 257 258 rc = bnxt_hwrm_vnic_ctx_alloc(bp, vnic); 259 if (rc) { 260 RTE_LOG(ERR, PMD, 261 "HWRM vnic %d ctx alloc failure rc: %x\n", 262 i, rc); 263 goto err_out; 264 } 265 266 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 267 if (rc) { 268 RTE_LOG(ERR, PMD, "HWRM vnic %d cfg failure rc: %x\n", 269 i, rc); 270 goto err_out; 271 } 272 273 rc = bnxt_set_hwrm_vnic_filters(bp, vnic); 274 if (rc) { 275 RTE_LOG(ERR, PMD, 276 "HWRM vnic %d filter failure rc: %x\n", 277 i, rc); 278 goto err_out; 279 } 280 if (vnic->rss_table && vnic->hash_type) { 281 /* 282 * Fill the RSS hash & redirection table with 283 * ring group ids for all VNICs 284 */ 285 for (rss_idx = 0, fw_idx = 0; 286 rss_idx < HW_HASH_INDEX_SIZE; 287 rss_idx++, fw_idx++) { 288 if (vnic->fw_grp_ids[fw_idx] == 289 INVALID_HW_RING_ID) 290 fw_idx = 0; 291 vnic->rss_table[rss_idx] = 292 vnic->fw_grp_ids[fw_idx]; 293 } 294 rc = bnxt_hwrm_vnic_rss_cfg(bp, vnic); 295 if (rc) { 296 RTE_LOG(ERR, PMD, 297 "HWRM vnic %d set RSS failure rc: %x\n", 298 i, rc); 299 goto err_out; 300 } 301 } 302 303 bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 304 305 if (bp->eth_dev->data->dev_conf.rxmode.enable_lro) 306 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 1); 307 else 308 bnxt_hwrm_vnic_tpa_cfg(bp, vnic, 0); 309 } 310 rc = bnxt_hwrm_cfa_l2_set_rx_mask(bp, &bp->vnic_info[0], 0, NULL); 311 if (rc) { 312 RTE_LOG(ERR, PMD, 313 "HWRM cfa l2 rx mask failure rc: %x\n", rc); 314 goto err_out; 315 } 316 317 /* check and configure queue intr-vector mapping */ 318 if ((rte_intr_cap_multiple(intr_handle) || 319 !RTE_ETH_DEV_SRIOV(bp->eth_dev).active) && 320 bp->eth_dev->data->dev_conf.intr_conf.rxq != 0) { 321 intr_vector = bp->eth_dev->data->nb_rx_queues; 322 RTE_LOG(INFO, PMD, "%s(): intr_vector = %d\n", __func__, 323 intr_vector); 324 if (intr_vector > bp->rx_cp_nr_rings) { 325 RTE_LOG(ERR, PMD, "At most %d intr queues supported", 326 bp->rx_cp_nr_rings); 327 return -ENOTSUP; 328 } 329 if (rte_intr_efd_enable(intr_handle, intr_vector)) 330 return -1; 331 } 332 333 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { 334 intr_handle->intr_vec = 335 rte_zmalloc("intr_vec", 336 bp->eth_dev->data->nb_rx_queues * 337 sizeof(int), 0); 338 if (intr_handle->intr_vec == NULL) { 339 RTE_LOG(ERR, PMD, "Failed to allocate %d rx_queues" 340 " intr_vec", bp->eth_dev->data->nb_rx_queues); 341 return -ENOMEM; 342 } 343 RTE_LOG(DEBUG, PMD, "%s(): intr_handle->intr_vec = %p " 344 "intr_handle->nb_efd = %d intr_handle->max_intr = %d\n", 345 __func__, intr_handle->intr_vec, intr_handle->nb_efd, 346 intr_handle->max_intr); 347 } 348 349 for (queue_id = 0; queue_id < bp->eth_dev->data->nb_rx_queues; 350 queue_id++) { 351 intr_handle->intr_vec[queue_id] = vec; 352 if (vec < base + intr_handle->nb_efd - 1) 353 vec++; 354 } 355 356 /* enable uio/vfio intr/eventfd mapping */ 357 rte_intr_enable(intr_handle); 358 359 rc = bnxt_get_hwrm_link_config(bp, &new); 360 if (rc) { 361 RTE_LOG(ERR, PMD, "HWRM Get link config failure rc: %x\n", rc); 362 goto err_out; 363 } 364 365 if (!bp->link_info.link_up) { 366 rc = bnxt_set_hwrm_link_config(bp, true); 367 if (rc) { 368 RTE_LOG(ERR, PMD, 369 "HWRM link config failure rc: %x\n", rc); 370 goto err_out; 371 } 372 } 373 374 return 0; 375 376 err_out: 377 bnxt_free_all_hwrm_resources(bp); 378 379 return rc; 380 } 381 382 static int bnxt_shutdown_nic(struct bnxt *bp) 383 { 384 bnxt_free_all_hwrm_resources(bp); 385 bnxt_free_all_filters(bp); 386 bnxt_free_all_vnics(bp); 387 return 0; 388 } 389 390 static int bnxt_init_nic(struct bnxt *bp) 391 { 392 int rc; 393 394 bnxt_init_ring_grps(bp); 395 bnxt_init_vnics(bp); 396 bnxt_init_filters(bp); 397 398 rc = bnxt_init_chip(bp); 399 if (rc) 400 return rc; 401 402 return 0; 403 } 404 405 /* 406 * Device configuration and status function 407 */ 408 409 static void bnxt_dev_info_get_op(struct rte_eth_dev *eth_dev, 410 struct rte_eth_dev_info *dev_info) 411 { 412 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 413 uint16_t max_vnics, i, j, vpool, vrxq; 414 unsigned int max_rx_rings; 415 416 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 417 418 /* MAC Specifics */ 419 dev_info->max_mac_addrs = bp->max_l2_ctx; 420 dev_info->max_hash_mac_addrs = 0; 421 422 /* PF/VF specifics */ 423 if (BNXT_PF(bp)) 424 dev_info->max_vfs = bp->pdev->max_vfs; 425 max_rx_rings = RTE_MIN(bp->max_vnics, RTE_MIN(bp->max_l2_ctx, 426 RTE_MIN(bp->max_rsscos_ctx, 427 bp->max_stat_ctx))); 428 /* For the sake of symmetry, max_rx_queues = max_tx_queues */ 429 dev_info->max_rx_queues = max_rx_rings; 430 dev_info->max_tx_queues = max_rx_rings; 431 dev_info->reta_size = bp->max_rsscos_ctx; 432 dev_info->hash_key_size = 40; 433 max_vnics = bp->max_vnics; 434 435 /* Fast path specifics */ 436 dev_info->min_rx_bufsize = 1; 437 dev_info->max_rx_pktlen = BNXT_MAX_MTU + ETHER_HDR_LEN + ETHER_CRC_LEN 438 + VLAN_TAG_SIZE; 439 dev_info->rx_offload_capa = 0; 440 dev_info->tx_offload_capa = DEV_TX_OFFLOAD_VLAN_INSERT | 441 DEV_TX_OFFLOAD_IPV4_CKSUM | 442 DEV_TX_OFFLOAD_TCP_CKSUM | 443 DEV_TX_OFFLOAD_UDP_CKSUM | 444 DEV_TX_OFFLOAD_TCP_TSO | 445 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM | 446 DEV_TX_OFFLOAD_VXLAN_TNL_TSO | 447 DEV_TX_OFFLOAD_GRE_TNL_TSO | 448 DEV_TX_OFFLOAD_IPIP_TNL_TSO | 449 DEV_TX_OFFLOAD_GENEVE_TNL_TSO; 450 451 /* *INDENT-OFF* */ 452 dev_info->default_rxconf = (struct rte_eth_rxconf) { 453 .rx_thresh = { 454 .pthresh = 8, 455 .hthresh = 8, 456 .wthresh = 0, 457 }, 458 .rx_free_thresh = 32, 459 .rx_drop_en = 0, 460 }; 461 462 dev_info->default_txconf = (struct rte_eth_txconf) { 463 .tx_thresh = { 464 .pthresh = 32, 465 .hthresh = 0, 466 .wthresh = 0, 467 }, 468 .tx_free_thresh = 32, 469 .tx_rs_thresh = 32, 470 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS | 471 ETH_TXQ_FLAGS_NOOFFLOADS, 472 }; 473 eth_dev->data->dev_conf.intr_conf.lsc = 1; 474 475 eth_dev->data->dev_conf.intr_conf.rxq = 1; 476 477 /* *INDENT-ON* */ 478 479 /* 480 * TODO: default_rxconf, default_txconf, rx_desc_lim, and tx_desc_lim 481 * need further investigation. 482 */ 483 484 /* VMDq resources */ 485 vpool = 64; /* ETH_64_POOLS */ 486 vrxq = 128; /* ETH_VMDQ_DCB_NUM_QUEUES */ 487 for (i = 0; i < 4; vpool >>= 1, i++) { 488 if (max_vnics > vpool) { 489 for (j = 0; j < 5; vrxq >>= 1, j++) { 490 if (dev_info->max_rx_queues > vrxq) { 491 if (vpool > vrxq) 492 vpool = vrxq; 493 goto found; 494 } 495 } 496 /* Not enough resources to support VMDq */ 497 break; 498 } 499 } 500 /* Not enough resources to support VMDq */ 501 vpool = 0; 502 vrxq = 0; 503 found: 504 dev_info->max_vmdq_pools = vpool; 505 dev_info->vmdq_queue_num = vrxq; 506 507 dev_info->vmdq_pool_base = 0; 508 dev_info->vmdq_queue_base = 0; 509 } 510 511 /* Configure the device based on the configuration provided */ 512 static int bnxt_dev_configure_op(struct rte_eth_dev *eth_dev) 513 { 514 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 515 516 bp->rx_queues = (void *)eth_dev->data->rx_queues; 517 bp->tx_queues = (void *)eth_dev->data->tx_queues; 518 519 /* Inherit new configurations */ 520 bp->rx_nr_rings = eth_dev->data->nb_rx_queues; 521 bp->tx_nr_rings = eth_dev->data->nb_tx_queues; 522 bp->rx_cp_nr_rings = bp->rx_nr_rings; 523 bp->tx_cp_nr_rings = bp->tx_nr_rings; 524 525 if (eth_dev->data->dev_conf.rxmode.jumbo_frame) 526 eth_dev->data->mtu = 527 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 528 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE; 529 return 0; 530 } 531 532 static inline int 533 rte_bnxt_atomic_write_link_status(struct rte_eth_dev *eth_dev, 534 struct rte_eth_link *link) 535 { 536 struct rte_eth_link *dst = ð_dev->data->dev_link; 537 struct rte_eth_link *src = link; 538 539 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst, 540 *(uint64_t *)src) == 0) 541 return 1; 542 543 return 0; 544 } 545 546 static void bnxt_print_link_info(struct rte_eth_dev *eth_dev) 547 { 548 struct rte_eth_link *link = ð_dev->data->dev_link; 549 550 if (link->link_status) 551 RTE_LOG(INFO, PMD, "Port %d Link Up - speed %u Mbps - %s\n", 552 eth_dev->data->port_id, 553 (uint32_t)link->link_speed, 554 (link->link_duplex == ETH_LINK_FULL_DUPLEX) ? 555 ("full-duplex") : ("half-duplex\n")); 556 else 557 RTE_LOG(INFO, PMD, "Port %d Link Down\n", 558 eth_dev->data->port_id); 559 } 560 561 static int bnxt_dev_lsc_intr_setup(struct rte_eth_dev *eth_dev) 562 { 563 bnxt_print_link_info(eth_dev); 564 return 0; 565 } 566 567 static int bnxt_dev_start_op(struct rte_eth_dev *eth_dev) 568 { 569 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 570 int vlan_mask = 0; 571 int rc; 572 573 bp->dev_stopped = 0; 574 575 rc = bnxt_init_nic(bp); 576 if (rc) 577 goto error; 578 579 bnxt_link_update_op(eth_dev, 0); 580 581 if (eth_dev->data->dev_conf.rxmode.hw_vlan_filter) 582 vlan_mask |= ETH_VLAN_FILTER_MASK; 583 if (eth_dev->data->dev_conf.rxmode.hw_vlan_strip) 584 vlan_mask |= ETH_VLAN_STRIP_MASK; 585 bnxt_vlan_offload_set_op(eth_dev, vlan_mask); 586 587 return 0; 588 589 error: 590 bnxt_shutdown_nic(bp); 591 bnxt_free_tx_mbufs(bp); 592 bnxt_free_rx_mbufs(bp); 593 return rc; 594 } 595 596 static int bnxt_dev_set_link_up_op(struct rte_eth_dev *eth_dev) 597 { 598 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 599 600 eth_dev->data->dev_link.link_status = 1; 601 bnxt_set_hwrm_link_config(bp, true); 602 return 0; 603 } 604 605 static int bnxt_dev_set_link_down_op(struct rte_eth_dev *eth_dev) 606 { 607 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 608 609 eth_dev->data->dev_link.link_status = 0; 610 bnxt_set_hwrm_link_config(bp, false); 611 return 0; 612 } 613 614 /* Unload the driver, release resources */ 615 static void bnxt_dev_stop_op(struct rte_eth_dev *eth_dev) 616 { 617 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 618 619 if (bp->eth_dev->data->dev_started) { 620 /* TBD: STOP HW queues DMA */ 621 eth_dev->data->dev_link.link_status = 0; 622 } 623 bnxt_set_hwrm_link_config(bp, false); 624 bnxt_hwrm_port_clr_stats(bp); 625 bnxt_shutdown_nic(bp); 626 bp->dev_stopped = 1; 627 } 628 629 static void bnxt_dev_close_op(struct rte_eth_dev *eth_dev) 630 { 631 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 632 633 if (bp->dev_stopped == 0) 634 bnxt_dev_stop_op(eth_dev); 635 636 bnxt_free_tx_mbufs(bp); 637 bnxt_free_rx_mbufs(bp); 638 bnxt_free_mem(bp); 639 if (eth_dev->data->mac_addrs != NULL) { 640 rte_free(eth_dev->data->mac_addrs); 641 eth_dev->data->mac_addrs = NULL; 642 } 643 if (bp->grp_info != NULL) { 644 rte_free(bp->grp_info); 645 bp->grp_info = NULL; 646 } 647 } 648 649 static void bnxt_mac_addr_remove_op(struct rte_eth_dev *eth_dev, 650 uint32_t index) 651 { 652 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 653 uint64_t pool_mask = eth_dev->data->mac_pool_sel[index]; 654 struct bnxt_vnic_info *vnic; 655 struct bnxt_filter_info *filter, *temp_filter; 656 int i; 657 658 /* 659 * Loop through all VNICs from the specified filter flow pools to 660 * remove the corresponding MAC addr filter 661 */ 662 for (i = 0; i < MAX_FF_POOLS; i++) { 663 if (!(pool_mask & (1ULL << i))) 664 continue; 665 666 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 667 filter = STAILQ_FIRST(&vnic->filter); 668 while (filter) { 669 temp_filter = STAILQ_NEXT(filter, next); 670 if (filter->mac_index == index) { 671 STAILQ_REMOVE(&vnic->filter, filter, 672 bnxt_filter_info, next); 673 bnxt_hwrm_clear_l2_filter(bp, filter); 674 filter->mac_index = INVALID_MAC_INDEX; 675 memset(&filter->l2_addr, 0, 676 ETHER_ADDR_LEN); 677 STAILQ_INSERT_TAIL( 678 &bp->free_filter_list, 679 filter, next); 680 } 681 filter = temp_filter; 682 } 683 } 684 } 685 } 686 687 static int bnxt_mac_addr_add_op(struct rte_eth_dev *eth_dev, 688 struct ether_addr *mac_addr, 689 uint32_t index, uint32_t pool) 690 { 691 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 692 struct bnxt_vnic_info *vnic = STAILQ_FIRST(&bp->ff_pool[pool]); 693 struct bnxt_filter_info *filter; 694 695 if (BNXT_VF(bp)) { 696 RTE_LOG(ERR, PMD, "Cannot add MAC address to a VF interface\n"); 697 return -ENOTSUP; 698 } 699 700 if (!vnic) { 701 RTE_LOG(ERR, PMD, "VNIC not found for pool %d!\n", pool); 702 return -EINVAL; 703 } 704 /* Attach requested MAC address to the new l2_filter */ 705 STAILQ_FOREACH(filter, &vnic->filter, next) { 706 if (filter->mac_index == index) { 707 RTE_LOG(ERR, PMD, 708 "MAC addr already existed for pool %d\n", pool); 709 return -EINVAL; 710 } 711 } 712 filter = bnxt_alloc_filter(bp); 713 if (!filter) { 714 RTE_LOG(ERR, PMD, "L2 filter alloc failed\n"); 715 return -ENODEV; 716 } 717 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 718 filter->mac_index = index; 719 memcpy(filter->l2_addr, mac_addr, ETHER_ADDR_LEN); 720 return bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 721 } 722 723 int bnxt_link_update_op(struct rte_eth_dev *eth_dev, int wait_to_complete) 724 { 725 int rc = 0; 726 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 727 struct rte_eth_link new; 728 unsigned int cnt = BNXT_LINK_WAIT_CNT; 729 730 memset(&new, 0, sizeof(new)); 731 do { 732 /* Retrieve link info from hardware */ 733 rc = bnxt_get_hwrm_link_config(bp, &new); 734 if (rc) { 735 new.link_speed = ETH_LINK_SPEED_100M; 736 new.link_duplex = ETH_LINK_FULL_DUPLEX; 737 RTE_LOG(ERR, PMD, 738 "Failed to retrieve link rc = 0x%x!\n", rc); 739 goto out; 740 } 741 rte_delay_ms(BNXT_LINK_WAIT_INTERVAL); 742 743 if (!wait_to_complete) 744 break; 745 } while (!new.link_status && cnt--); 746 747 out: 748 /* Timed out or success */ 749 if (new.link_status != eth_dev->data->dev_link.link_status || 750 new.link_speed != eth_dev->data->dev_link.link_speed) { 751 rte_bnxt_atomic_write_link_status(eth_dev, &new); 752 bnxt_print_link_info(eth_dev); 753 } 754 755 return rc; 756 } 757 758 static void bnxt_promiscuous_enable_op(struct rte_eth_dev *eth_dev) 759 { 760 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 761 struct bnxt_vnic_info *vnic; 762 763 if (bp->vnic_info == NULL) 764 return; 765 766 vnic = &bp->vnic_info[0]; 767 768 vnic->flags |= BNXT_VNIC_INFO_PROMISC; 769 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 770 } 771 772 static void bnxt_promiscuous_disable_op(struct rte_eth_dev *eth_dev) 773 { 774 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 775 struct bnxt_vnic_info *vnic; 776 777 if (bp->vnic_info == NULL) 778 return; 779 780 vnic = &bp->vnic_info[0]; 781 782 vnic->flags &= ~BNXT_VNIC_INFO_PROMISC; 783 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 784 } 785 786 static void bnxt_allmulticast_enable_op(struct rte_eth_dev *eth_dev) 787 { 788 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 789 struct bnxt_vnic_info *vnic; 790 791 if (bp->vnic_info == NULL) 792 return; 793 794 vnic = &bp->vnic_info[0]; 795 796 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 797 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 798 } 799 800 static void bnxt_allmulticast_disable_op(struct rte_eth_dev *eth_dev) 801 { 802 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 803 struct bnxt_vnic_info *vnic; 804 805 if (bp->vnic_info == NULL) 806 return; 807 808 vnic = &bp->vnic_info[0]; 809 810 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 811 bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 812 } 813 814 static int bnxt_reta_update_op(struct rte_eth_dev *eth_dev, 815 struct rte_eth_rss_reta_entry64 *reta_conf, 816 uint16_t reta_size) 817 { 818 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 819 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 820 struct bnxt_vnic_info *vnic; 821 int i; 822 823 if (!(dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 824 return -EINVAL; 825 826 if (reta_size != HW_HASH_INDEX_SIZE) { 827 RTE_LOG(ERR, PMD, "The configured hash table lookup size " 828 "(%d) must equal the size supported by the hardware " 829 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 830 return -EINVAL; 831 } 832 /* Update the RSS VNIC(s) */ 833 for (i = 0; i < MAX_FF_POOLS; i++) { 834 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 835 memcpy(vnic->rss_table, reta_conf, reta_size); 836 837 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 838 } 839 } 840 return 0; 841 } 842 843 static int bnxt_reta_query_op(struct rte_eth_dev *eth_dev, 844 struct rte_eth_rss_reta_entry64 *reta_conf, 845 uint16_t reta_size) 846 { 847 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 848 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 849 struct rte_intr_handle *intr_handle 850 = &bp->pdev->intr_handle; 851 852 /* Retrieve from the default VNIC */ 853 if (!vnic) 854 return -EINVAL; 855 if (!vnic->rss_table) 856 return -EINVAL; 857 858 if (reta_size != HW_HASH_INDEX_SIZE) { 859 RTE_LOG(ERR, PMD, "The configured hash table lookup size " 860 "(%d) must equal the size supported by the hardware " 861 "(%d)\n", reta_size, HW_HASH_INDEX_SIZE); 862 return -EINVAL; 863 } 864 /* EW - need to revisit here copying from u64 to u16 */ 865 memcpy(reta_conf, vnic->rss_table, reta_size); 866 867 if (rte_intr_allow_others(intr_handle)) { 868 if (eth_dev->data->dev_conf.intr_conf.lsc != 0) 869 bnxt_dev_lsc_intr_setup(eth_dev); 870 } 871 872 return 0; 873 } 874 875 static int bnxt_rss_hash_update_op(struct rte_eth_dev *eth_dev, 876 struct rte_eth_rss_conf *rss_conf) 877 { 878 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 879 struct rte_eth_conf *dev_conf = &bp->eth_dev->data->dev_conf; 880 struct bnxt_vnic_info *vnic; 881 uint16_t hash_type = 0; 882 int i; 883 884 /* 885 * If RSS enablement were different than dev_configure, 886 * then return -EINVAL 887 */ 888 if (dev_conf->rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG) { 889 if (!rss_conf->rss_hf) 890 RTE_LOG(ERR, PMD, "Hash type NONE\n"); 891 } else { 892 if (rss_conf->rss_hf & BNXT_ETH_RSS_SUPPORT) 893 return -EINVAL; 894 } 895 896 bp->flags |= BNXT_FLAG_UPDATE_HASH; 897 memcpy(&bp->rss_conf, rss_conf, sizeof(*rss_conf)); 898 899 if (rss_conf->rss_hf & ETH_RSS_IPV4) 900 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 901 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) 902 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 903 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) 904 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 905 if (rss_conf->rss_hf & ETH_RSS_IPV6) 906 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 907 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) 908 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 909 if (rss_conf->rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) 910 hash_type |= HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 911 912 /* Update the RSS VNIC(s) */ 913 for (i = 0; i < MAX_FF_POOLS; i++) { 914 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 915 vnic->hash_type = hash_type; 916 917 /* 918 * Use the supplied key if the key length is 919 * acceptable and the rss_key is not NULL 920 */ 921 if (rss_conf->rss_key && 922 rss_conf->rss_key_len <= HW_HASH_KEY_SIZE) 923 memcpy(vnic->rss_hash_key, rss_conf->rss_key, 924 rss_conf->rss_key_len); 925 926 bnxt_hwrm_vnic_rss_cfg(bp, vnic); 927 } 928 } 929 return 0; 930 } 931 932 static int bnxt_rss_hash_conf_get_op(struct rte_eth_dev *eth_dev, 933 struct rte_eth_rss_conf *rss_conf) 934 { 935 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 936 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 937 int len; 938 uint32_t hash_types; 939 940 /* RSS configuration is the same for all VNICs */ 941 if (vnic && vnic->rss_hash_key) { 942 if (rss_conf->rss_key) { 943 len = rss_conf->rss_key_len <= HW_HASH_KEY_SIZE ? 944 rss_conf->rss_key_len : HW_HASH_KEY_SIZE; 945 memcpy(rss_conf->rss_key, vnic->rss_hash_key, len); 946 } 947 948 hash_types = vnic->hash_type; 949 rss_conf->rss_hf = 0; 950 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4) { 951 rss_conf->rss_hf |= ETH_RSS_IPV4; 952 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV4; 953 } 954 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4) { 955 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP; 956 hash_types &= 957 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV4; 958 } 959 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4) { 960 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP; 961 hash_types &= 962 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV4; 963 } 964 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6) { 965 rss_conf->rss_hf |= ETH_RSS_IPV6; 966 hash_types &= ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_IPV6; 967 } 968 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6) { 969 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP; 970 hash_types &= 971 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_TCP_IPV6; 972 } 973 if (hash_types & HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6) { 974 rss_conf->rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP; 975 hash_types &= 976 ~HWRM_VNIC_RSS_CFG_INPUT_HASH_TYPE_UDP_IPV6; 977 } 978 if (hash_types) { 979 RTE_LOG(ERR, PMD, 980 "Unknwon RSS config from firmware (%08x), RSS disabled", 981 vnic->hash_type); 982 return -ENOTSUP; 983 } 984 } else { 985 rss_conf->rss_hf = 0; 986 } 987 return 0; 988 } 989 990 static int bnxt_flow_ctrl_get_op(struct rte_eth_dev *dev, 991 struct rte_eth_fc_conf *fc_conf) 992 { 993 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 994 struct rte_eth_link link_info; 995 int rc; 996 997 rc = bnxt_get_hwrm_link_config(bp, &link_info); 998 if (rc) 999 return rc; 1000 1001 memset(fc_conf, 0, sizeof(*fc_conf)); 1002 if (bp->link_info.auto_pause) 1003 fc_conf->autoneg = 1; 1004 switch (bp->link_info.pause) { 1005 case 0: 1006 fc_conf->mode = RTE_FC_NONE; 1007 break; 1008 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX: 1009 fc_conf->mode = RTE_FC_TX_PAUSE; 1010 break; 1011 case HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX: 1012 fc_conf->mode = RTE_FC_RX_PAUSE; 1013 break; 1014 case (HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_TX | 1015 HWRM_PORT_PHY_QCFG_OUTPUT_PAUSE_RX): 1016 fc_conf->mode = RTE_FC_FULL; 1017 break; 1018 } 1019 return 0; 1020 } 1021 1022 static int bnxt_flow_ctrl_set_op(struct rte_eth_dev *dev, 1023 struct rte_eth_fc_conf *fc_conf) 1024 { 1025 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1026 1027 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) { 1028 RTE_LOG(ERR, PMD, "Flow Control Settings cannot be modified\n"); 1029 return -ENOTSUP; 1030 } 1031 1032 switch (fc_conf->mode) { 1033 case RTE_FC_NONE: 1034 bp->link_info.auto_pause = 0; 1035 bp->link_info.force_pause = 0; 1036 break; 1037 case RTE_FC_RX_PAUSE: 1038 if (fc_conf->autoneg) { 1039 bp->link_info.auto_pause = 1040 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1041 bp->link_info.force_pause = 0; 1042 } else { 1043 bp->link_info.auto_pause = 0; 1044 bp->link_info.force_pause = 1045 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1046 } 1047 break; 1048 case RTE_FC_TX_PAUSE: 1049 if (fc_conf->autoneg) { 1050 bp->link_info.auto_pause = 1051 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX; 1052 bp->link_info.force_pause = 0; 1053 } else { 1054 bp->link_info.auto_pause = 0; 1055 bp->link_info.force_pause = 1056 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX; 1057 } 1058 break; 1059 case RTE_FC_FULL: 1060 if (fc_conf->autoneg) { 1061 bp->link_info.auto_pause = 1062 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_TX | 1063 HWRM_PORT_PHY_CFG_INPUT_AUTO_PAUSE_RX; 1064 bp->link_info.force_pause = 0; 1065 } else { 1066 bp->link_info.auto_pause = 0; 1067 bp->link_info.force_pause = 1068 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_TX | 1069 HWRM_PORT_PHY_CFG_INPUT_FORCE_PAUSE_RX; 1070 } 1071 break; 1072 } 1073 return bnxt_set_hwrm_link_config(bp, true); 1074 } 1075 1076 /* Add UDP tunneling port */ 1077 static int 1078 bnxt_udp_tunnel_port_add_op(struct rte_eth_dev *eth_dev, 1079 struct rte_eth_udp_tunnel *udp_tunnel) 1080 { 1081 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1082 uint16_t tunnel_type = 0; 1083 int rc = 0; 1084 1085 switch (udp_tunnel->prot_type) { 1086 case RTE_TUNNEL_TYPE_VXLAN: 1087 if (bp->vxlan_port_cnt) { 1088 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n", 1089 udp_tunnel->udp_port); 1090 if (bp->vxlan_port != udp_tunnel->udp_port) { 1091 RTE_LOG(ERR, PMD, "Only one port allowed\n"); 1092 return -ENOSPC; 1093 } 1094 bp->vxlan_port_cnt++; 1095 return 0; 1096 } 1097 tunnel_type = 1098 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_VXLAN; 1099 bp->vxlan_port_cnt++; 1100 break; 1101 case RTE_TUNNEL_TYPE_GENEVE: 1102 if (bp->geneve_port_cnt) { 1103 RTE_LOG(ERR, PMD, "Tunnel Port %d already programmed\n", 1104 udp_tunnel->udp_port); 1105 if (bp->geneve_port != udp_tunnel->udp_port) { 1106 RTE_LOG(ERR, PMD, "Only one port allowed\n"); 1107 return -ENOSPC; 1108 } 1109 bp->geneve_port_cnt++; 1110 return 0; 1111 } 1112 tunnel_type = 1113 HWRM_TUNNEL_DST_PORT_ALLOC_INPUT_TUNNEL_TYPE_GENEVE; 1114 bp->geneve_port_cnt++; 1115 break; 1116 default: 1117 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n"); 1118 return -ENOTSUP; 1119 } 1120 rc = bnxt_hwrm_tunnel_dst_port_alloc(bp, udp_tunnel->udp_port, 1121 tunnel_type); 1122 return rc; 1123 } 1124 1125 static int 1126 bnxt_udp_tunnel_port_del_op(struct rte_eth_dev *eth_dev, 1127 struct rte_eth_udp_tunnel *udp_tunnel) 1128 { 1129 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1130 uint16_t tunnel_type = 0; 1131 uint16_t port = 0; 1132 int rc = 0; 1133 1134 switch (udp_tunnel->prot_type) { 1135 case RTE_TUNNEL_TYPE_VXLAN: 1136 if (!bp->vxlan_port_cnt) { 1137 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n"); 1138 return -EINVAL; 1139 } 1140 if (bp->vxlan_port != udp_tunnel->udp_port) { 1141 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n", 1142 udp_tunnel->udp_port, bp->vxlan_port); 1143 return -EINVAL; 1144 } 1145 if (--bp->vxlan_port_cnt) 1146 return 0; 1147 1148 tunnel_type = 1149 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN; 1150 port = bp->vxlan_fw_dst_port_id; 1151 break; 1152 case RTE_TUNNEL_TYPE_GENEVE: 1153 if (!bp->geneve_port_cnt) { 1154 RTE_LOG(ERR, PMD, "No Tunnel port configured yet\n"); 1155 return -EINVAL; 1156 } 1157 if (bp->geneve_port != udp_tunnel->udp_port) { 1158 RTE_LOG(ERR, PMD, "Req Port: %d. Configured port: %d\n", 1159 udp_tunnel->udp_port, bp->geneve_port); 1160 return -EINVAL; 1161 } 1162 if (--bp->geneve_port_cnt) 1163 return 0; 1164 1165 tunnel_type = 1166 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE; 1167 port = bp->geneve_fw_dst_port_id; 1168 break; 1169 default: 1170 RTE_LOG(ERR, PMD, "Tunnel type is not supported\n"); 1171 return -ENOTSUP; 1172 } 1173 1174 rc = bnxt_hwrm_tunnel_dst_port_free(bp, port, tunnel_type); 1175 if (!rc) { 1176 if (tunnel_type == 1177 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_VXLAN) 1178 bp->vxlan_port = 0; 1179 if (tunnel_type == 1180 HWRM_TUNNEL_DST_PORT_FREE_INPUT_TUNNEL_TYPE_GENEVE) 1181 bp->geneve_port = 0; 1182 } 1183 return rc; 1184 } 1185 1186 static int bnxt_del_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1187 { 1188 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1189 struct bnxt_vnic_info *vnic; 1190 unsigned int i; 1191 int rc = 0; 1192 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN; 1193 1194 /* Cycle through all VNICs */ 1195 for (i = 0; i < bp->nr_vnics; i++) { 1196 /* 1197 * For each VNIC and each associated filter(s) 1198 * if VLAN exists && VLAN matches vlan_id 1199 * remove the MAC+VLAN filter 1200 * add a new MAC only filter 1201 * else 1202 * VLAN filter doesn't exist, just skip and continue 1203 */ 1204 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 1205 filter = STAILQ_FIRST(&vnic->filter); 1206 while (filter) { 1207 temp_filter = STAILQ_NEXT(filter, next); 1208 1209 if (filter->enables & chk && 1210 filter->l2_ovlan == vlan_id) { 1211 /* Must delete the filter */ 1212 STAILQ_REMOVE(&vnic->filter, filter, 1213 bnxt_filter_info, next); 1214 bnxt_hwrm_clear_l2_filter(bp, filter); 1215 STAILQ_INSERT_TAIL( 1216 &bp->free_filter_list, 1217 filter, next); 1218 1219 /* 1220 * Need to examine to see if the MAC 1221 * filter already existed or not before 1222 * allocating a new one 1223 */ 1224 1225 new_filter = bnxt_alloc_filter(bp); 1226 if (!new_filter) { 1227 RTE_LOG(ERR, PMD, 1228 "MAC/VLAN filter alloc failed\n"); 1229 rc = -ENOMEM; 1230 goto exit; 1231 } 1232 STAILQ_INSERT_TAIL(&vnic->filter, 1233 new_filter, next); 1234 /* Inherit MAC from previous filter */ 1235 new_filter->mac_index = 1236 filter->mac_index; 1237 memcpy(new_filter->l2_addr, 1238 filter->l2_addr, ETHER_ADDR_LEN); 1239 /* MAC only filter */ 1240 rc = bnxt_hwrm_set_l2_filter(bp, 1241 vnic->fw_vnic_id, 1242 new_filter); 1243 if (rc) 1244 goto exit; 1245 RTE_LOG(INFO, PMD, 1246 "Del Vlan filter for %d\n", 1247 vlan_id); 1248 } 1249 filter = temp_filter; 1250 } 1251 } 1252 } 1253 exit: 1254 return rc; 1255 } 1256 1257 static int bnxt_add_vlan_filter(struct bnxt *bp, uint16_t vlan_id) 1258 { 1259 struct bnxt_filter_info *filter, *temp_filter, *new_filter; 1260 struct bnxt_vnic_info *vnic; 1261 unsigned int i; 1262 int rc = 0; 1263 uint32_t en = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN | 1264 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN_MASK; 1265 uint32_t chk = HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_OVLAN; 1266 1267 /* Cycle through all VNICs */ 1268 for (i = 0; i < bp->nr_vnics; i++) { 1269 /* 1270 * For each VNIC and each associated filter(s) 1271 * if VLAN exists: 1272 * if VLAN matches vlan_id 1273 * VLAN filter already exists, just skip and continue 1274 * else 1275 * add a new MAC+VLAN filter 1276 * else 1277 * Remove the old MAC only filter 1278 * Add a new MAC+VLAN filter 1279 */ 1280 STAILQ_FOREACH(vnic, &bp->ff_pool[i], next) { 1281 filter = STAILQ_FIRST(&vnic->filter); 1282 while (filter) { 1283 temp_filter = STAILQ_NEXT(filter, next); 1284 1285 if (filter->enables & chk) { 1286 if (filter->l2_ovlan == vlan_id) 1287 goto cont; 1288 } else { 1289 /* Must delete the MAC filter */ 1290 STAILQ_REMOVE(&vnic->filter, filter, 1291 bnxt_filter_info, next); 1292 bnxt_hwrm_clear_l2_filter(bp, filter); 1293 filter->l2_ovlan = 0; 1294 STAILQ_INSERT_TAIL( 1295 &bp->free_filter_list, 1296 filter, next); 1297 } 1298 new_filter = bnxt_alloc_filter(bp); 1299 if (!new_filter) { 1300 RTE_LOG(ERR, PMD, 1301 "MAC/VLAN filter alloc failed\n"); 1302 rc = -ENOMEM; 1303 goto exit; 1304 } 1305 STAILQ_INSERT_TAIL(&vnic->filter, new_filter, 1306 next); 1307 /* Inherit MAC from the previous filter */ 1308 new_filter->mac_index = filter->mac_index; 1309 memcpy(new_filter->l2_addr, filter->l2_addr, 1310 ETHER_ADDR_LEN); 1311 /* MAC + VLAN ID filter */ 1312 new_filter->l2_ovlan = vlan_id; 1313 new_filter->l2_ovlan_mask = 0xF000; 1314 new_filter->enables |= en; 1315 rc = bnxt_hwrm_set_l2_filter(bp, 1316 vnic->fw_vnic_id, 1317 new_filter); 1318 if (rc) 1319 goto exit; 1320 RTE_LOG(INFO, PMD, 1321 "Added Vlan filter for %d\n", vlan_id); 1322 cont: 1323 filter = temp_filter; 1324 } 1325 } 1326 } 1327 exit: 1328 return rc; 1329 } 1330 1331 static int bnxt_vlan_filter_set_op(struct rte_eth_dev *eth_dev, 1332 uint16_t vlan_id, int on) 1333 { 1334 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1335 1336 /* These operations apply to ALL existing MAC/VLAN filters */ 1337 if (on) 1338 return bnxt_add_vlan_filter(bp, vlan_id); 1339 else 1340 return bnxt_del_vlan_filter(bp, vlan_id); 1341 } 1342 1343 static void 1344 bnxt_vlan_offload_set_op(struct rte_eth_dev *dev, int mask) 1345 { 1346 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1347 unsigned int i; 1348 1349 if (mask & ETH_VLAN_FILTER_MASK) { 1350 if (!dev->data->dev_conf.rxmode.hw_vlan_filter) { 1351 /* Remove any VLAN filters programmed */ 1352 for (i = 0; i < 4095; i++) 1353 bnxt_del_vlan_filter(bp, i); 1354 } 1355 RTE_LOG(INFO, PMD, "VLAN Filtering: %d\n", 1356 dev->data->dev_conf.rxmode.hw_vlan_filter); 1357 } 1358 1359 if (mask & ETH_VLAN_STRIP_MASK) { 1360 /* Enable or disable VLAN stripping */ 1361 for (i = 0; i < bp->nr_vnics; i++) { 1362 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1363 if (dev->data->dev_conf.rxmode.hw_vlan_strip) 1364 vnic->vlan_strip = true; 1365 else 1366 vnic->vlan_strip = false; 1367 bnxt_hwrm_vnic_cfg(bp, vnic); 1368 } 1369 RTE_LOG(INFO, PMD, "VLAN Strip Offload: %d\n", 1370 dev->data->dev_conf.rxmode.hw_vlan_strip); 1371 } 1372 1373 if (mask & ETH_VLAN_EXTEND_MASK) 1374 RTE_LOG(ERR, PMD, "Extend VLAN Not supported\n"); 1375 } 1376 1377 static void 1378 bnxt_set_default_mac_addr_op(struct rte_eth_dev *dev, struct ether_addr *addr) 1379 { 1380 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1381 /* Default Filter is tied to VNIC 0 */ 1382 struct bnxt_vnic_info *vnic = &bp->vnic_info[0]; 1383 struct bnxt_filter_info *filter; 1384 int rc; 1385 1386 if (BNXT_VF(bp)) 1387 return; 1388 1389 memcpy(bp->mac_addr, addr, sizeof(bp->mac_addr)); 1390 memcpy(&dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN); 1391 1392 STAILQ_FOREACH(filter, &vnic->filter, next) { 1393 /* Default Filter is at Index 0 */ 1394 if (filter->mac_index != 0) 1395 continue; 1396 rc = bnxt_hwrm_clear_l2_filter(bp, filter); 1397 if (rc) 1398 break; 1399 memcpy(filter->l2_addr, bp->mac_addr, ETHER_ADDR_LEN); 1400 memset(filter->l2_addr_mask, 0xff, ETHER_ADDR_LEN); 1401 filter->flags |= HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX; 1402 filter->enables |= 1403 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR | 1404 HWRM_CFA_L2_FILTER_ALLOC_INPUT_ENABLES_L2_ADDR_MASK; 1405 rc = bnxt_hwrm_set_l2_filter(bp, vnic->fw_vnic_id, filter); 1406 if (rc) 1407 break; 1408 filter->mac_index = 0; 1409 RTE_LOG(DEBUG, PMD, "Set MAC addr\n"); 1410 } 1411 } 1412 1413 static int 1414 bnxt_dev_set_mc_addr_list_op(struct rte_eth_dev *eth_dev, 1415 struct ether_addr *mc_addr_set, 1416 uint32_t nb_mc_addr) 1417 { 1418 struct bnxt *bp = (struct bnxt *)eth_dev->data->dev_private; 1419 char *mc_addr_list = (char *)mc_addr_set; 1420 struct bnxt_vnic_info *vnic; 1421 uint32_t off = 0, i = 0; 1422 1423 vnic = &bp->vnic_info[0]; 1424 1425 if (nb_mc_addr > BNXT_MAX_MC_ADDRS) { 1426 vnic->flags |= BNXT_VNIC_INFO_ALLMULTI; 1427 goto allmulti; 1428 } 1429 1430 /* TODO Check for Duplicate mcast addresses */ 1431 vnic->flags &= ~BNXT_VNIC_INFO_ALLMULTI; 1432 for (i = 0; i < nb_mc_addr; i++) { 1433 memcpy(vnic->mc_list + off, &mc_addr_list[i], ETHER_ADDR_LEN); 1434 off += ETHER_ADDR_LEN; 1435 } 1436 1437 vnic->mc_addr_cnt = i; 1438 1439 allmulti: 1440 return bnxt_hwrm_cfa_l2_set_rx_mask(bp, vnic, 0, NULL); 1441 } 1442 1443 static int 1444 bnxt_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size) 1445 { 1446 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1447 uint8_t fw_major = (bp->fw_ver >> 24) & 0xff; 1448 uint8_t fw_minor = (bp->fw_ver >> 16) & 0xff; 1449 uint8_t fw_updt = (bp->fw_ver >> 8) & 0xff; 1450 int ret; 1451 1452 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 1453 fw_major, fw_minor, fw_updt); 1454 1455 ret += 1; /* add the size of '\0' */ 1456 if (fw_size < (uint32_t)ret) 1457 return ret; 1458 else 1459 return 0; 1460 } 1461 1462 static void 1463 bnxt_rxq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1464 struct rte_eth_rxq_info *qinfo) 1465 { 1466 struct bnxt_rx_queue *rxq; 1467 1468 rxq = dev->data->rx_queues[queue_id]; 1469 1470 qinfo->mp = rxq->mb_pool; 1471 qinfo->scattered_rx = dev->data->scattered_rx; 1472 qinfo->nb_desc = rxq->nb_rx_desc; 1473 1474 qinfo->conf.rx_free_thresh = rxq->rx_free_thresh; 1475 qinfo->conf.rx_drop_en = 0; 1476 qinfo->conf.rx_deferred_start = 0; 1477 } 1478 1479 static void 1480 bnxt_txq_info_get_op(struct rte_eth_dev *dev, uint16_t queue_id, 1481 struct rte_eth_txq_info *qinfo) 1482 { 1483 struct bnxt_tx_queue *txq; 1484 1485 txq = dev->data->tx_queues[queue_id]; 1486 1487 qinfo->nb_desc = txq->nb_tx_desc; 1488 1489 qinfo->conf.tx_thresh.pthresh = txq->pthresh; 1490 qinfo->conf.tx_thresh.hthresh = txq->hthresh; 1491 qinfo->conf.tx_thresh.wthresh = txq->wthresh; 1492 1493 qinfo->conf.tx_free_thresh = txq->tx_free_thresh; 1494 qinfo->conf.tx_rs_thresh = 0; 1495 qinfo->conf.txq_flags = txq->txq_flags; 1496 qinfo->conf.tx_deferred_start = txq->tx_deferred_start; 1497 } 1498 1499 static int bnxt_mtu_set_op(struct rte_eth_dev *eth_dev, uint16_t new_mtu) 1500 { 1501 struct bnxt *bp = eth_dev->data->dev_private; 1502 struct rte_eth_dev_info dev_info; 1503 uint32_t max_dev_mtu; 1504 uint32_t rc = 0; 1505 uint32_t i; 1506 1507 bnxt_dev_info_get_op(eth_dev, &dev_info); 1508 max_dev_mtu = dev_info.max_rx_pktlen - 1509 ETHER_HDR_LEN - ETHER_CRC_LEN - VLAN_TAG_SIZE * 2; 1510 1511 if (new_mtu < ETHER_MIN_MTU || new_mtu > max_dev_mtu) { 1512 RTE_LOG(ERR, PMD, "MTU requested must be within (%d, %d)\n", 1513 ETHER_MIN_MTU, max_dev_mtu); 1514 return -EINVAL; 1515 } 1516 1517 1518 if (new_mtu > ETHER_MTU) { 1519 bp->flags |= BNXT_FLAG_JUMBO; 1520 eth_dev->data->dev_conf.rxmode.jumbo_frame = 1; 1521 } else { 1522 eth_dev->data->dev_conf.rxmode.jumbo_frame = 0; 1523 bp->flags &= ~BNXT_FLAG_JUMBO; 1524 } 1525 1526 eth_dev->data->dev_conf.rxmode.max_rx_pkt_len = 1527 new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1528 1529 eth_dev->data->mtu = new_mtu; 1530 RTE_LOG(INFO, PMD, "New MTU is %d\n", eth_dev->data->mtu); 1531 1532 for (i = 0; i < bp->nr_vnics; i++) { 1533 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 1534 1535 vnic->mru = bp->eth_dev->data->mtu + ETHER_HDR_LEN + 1536 ETHER_CRC_LEN + VLAN_TAG_SIZE * 2; 1537 rc = bnxt_hwrm_vnic_cfg(bp, vnic); 1538 if (rc) 1539 break; 1540 1541 rc = bnxt_hwrm_vnic_plcmode_cfg(bp, vnic); 1542 if (rc) 1543 return rc; 1544 } 1545 1546 return rc; 1547 } 1548 1549 static int 1550 bnxt_vlan_pvid_set_op(struct rte_eth_dev *dev, uint16_t pvid, int on) 1551 { 1552 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1553 uint16_t vlan = bp->vlan; 1554 int rc; 1555 1556 if (BNXT_NPAR_PF(bp) || BNXT_VF(bp)) { 1557 RTE_LOG(ERR, PMD, 1558 "PVID cannot be modified for this function\n"); 1559 return -ENOTSUP; 1560 } 1561 bp->vlan = on ? pvid : 0; 1562 1563 rc = bnxt_hwrm_set_default_vlan(bp, 0, 0); 1564 if (rc) 1565 bp->vlan = vlan; 1566 return rc; 1567 } 1568 1569 static int 1570 bnxt_dev_led_on_op(struct rte_eth_dev *dev) 1571 { 1572 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1573 1574 return bnxt_hwrm_port_led_cfg(bp, true); 1575 } 1576 1577 static int 1578 bnxt_dev_led_off_op(struct rte_eth_dev *dev) 1579 { 1580 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1581 1582 return bnxt_hwrm_port_led_cfg(bp, false); 1583 } 1584 1585 static uint32_t 1586 bnxt_rx_queue_count_op(struct rte_eth_dev *dev, uint16_t rx_queue_id) 1587 { 1588 uint32_t desc = 0, raw_cons = 0, cons; 1589 struct bnxt_cp_ring_info *cpr; 1590 struct bnxt_rx_queue *rxq; 1591 struct rx_pkt_cmpl *rxcmp; 1592 uint16_t cmp_type; 1593 uint8_t cmp = 1; 1594 bool valid; 1595 1596 rxq = dev->data->rx_queues[rx_queue_id]; 1597 cpr = rxq->cp_ring; 1598 valid = cpr->valid; 1599 1600 while (raw_cons < rxq->nb_rx_desc) { 1601 cons = RING_CMP(cpr->cp_ring_struct, raw_cons); 1602 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1603 1604 if (!CMPL_VALID(rxcmp, valid)) 1605 goto nothing_to_do; 1606 valid = FLIP_VALID(cons, cpr->cp_ring_struct->ring_mask, valid); 1607 cmp_type = CMP_TYPE(rxcmp); 1608 if (cmp_type == RX_TPA_END_CMPL_TYPE_RX_TPA_END) { 1609 cmp = (rte_le_to_cpu_32( 1610 ((struct rx_tpa_end_cmpl *) 1611 (rxcmp))->agg_bufs_v1) & 1612 RX_TPA_END_CMPL_AGG_BUFS_MASK) >> 1613 RX_TPA_END_CMPL_AGG_BUFS_SFT; 1614 desc++; 1615 } else if (cmp_type == 0x11) { 1616 desc++; 1617 cmp = (rxcmp->agg_bufs_v1 & 1618 RX_PKT_CMPL_AGG_BUFS_MASK) >> 1619 RX_PKT_CMPL_AGG_BUFS_SFT; 1620 } else { 1621 cmp = 1; 1622 } 1623 nothing_to_do: 1624 raw_cons += cmp ? cmp : 2; 1625 } 1626 1627 return desc; 1628 } 1629 1630 static int 1631 bnxt_rx_descriptor_status_op(void *rx_queue, uint16_t offset) 1632 { 1633 struct bnxt_rx_queue *rxq = (struct bnxt_rx_queue *)rx_queue; 1634 struct bnxt_rx_ring_info *rxr; 1635 struct bnxt_cp_ring_info *cpr; 1636 struct bnxt_sw_rx_bd *rx_buf; 1637 struct rx_pkt_cmpl *rxcmp; 1638 uint32_t cons, cp_cons; 1639 1640 if (!rxq) 1641 return -EINVAL; 1642 1643 cpr = rxq->cp_ring; 1644 rxr = rxq->rx_ring; 1645 1646 if (offset >= rxq->nb_rx_desc) 1647 return -EINVAL; 1648 1649 cons = RING_CMP(cpr->cp_ring_struct, offset); 1650 cp_cons = cpr->cp_raw_cons; 1651 rxcmp = (struct rx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1652 1653 if (cons > cp_cons) { 1654 if (CMPL_VALID(rxcmp, cpr->valid)) 1655 return RTE_ETH_RX_DESC_DONE; 1656 } else { 1657 if (CMPL_VALID(rxcmp, !cpr->valid)) 1658 return RTE_ETH_RX_DESC_DONE; 1659 } 1660 rx_buf = &rxr->rx_buf_ring[cons]; 1661 if (rx_buf->mbuf == NULL) 1662 return RTE_ETH_RX_DESC_UNAVAIL; 1663 1664 1665 return RTE_ETH_RX_DESC_AVAIL; 1666 } 1667 1668 static int 1669 bnxt_tx_descriptor_status_op(void *tx_queue, uint16_t offset) 1670 { 1671 struct bnxt_tx_queue *txq = (struct bnxt_tx_queue *)tx_queue; 1672 struct bnxt_tx_ring_info *txr; 1673 struct bnxt_cp_ring_info *cpr; 1674 struct bnxt_sw_tx_bd *tx_buf; 1675 struct tx_pkt_cmpl *txcmp; 1676 uint32_t cons, cp_cons; 1677 1678 if (!txq) 1679 return -EINVAL; 1680 1681 cpr = txq->cp_ring; 1682 txr = txq->tx_ring; 1683 1684 if (offset >= txq->nb_tx_desc) 1685 return -EINVAL; 1686 1687 cons = RING_CMP(cpr->cp_ring_struct, offset); 1688 txcmp = (struct tx_pkt_cmpl *)&cpr->cp_desc_ring[cons]; 1689 cp_cons = cpr->cp_raw_cons; 1690 1691 if (cons > cp_cons) { 1692 if (CMPL_VALID(txcmp, cpr->valid)) 1693 return RTE_ETH_TX_DESC_UNAVAIL; 1694 } else { 1695 if (CMPL_VALID(txcmp, !cpr->valid)) 1696 return RTE_ETH_TX_DESC_UNAVAIL; 1697 } 1698 tx_buf = &txr->tx_buf_ring[cons]; 1699 if (tx_buf->mbuf == NULL) 1700 return RTE_ETH_TX_DESC_DONE; 1701 1702 return RTE_ETH_TX_DESC_FULL; 1703 } 1704 1705 static struct bnxt_filter_info * 1706 bnxt_match_and_validate_ether_filter(struct bnxt *bp, 1707 struct rte_eth_ethertype_filter *efilter, 1708 struct bnxt_vnic_info *vnic0, 1709 struct bnxt_vnic_info *vnic, 1710 int *ret) 1711 { 1712 struct bnxt_filter_info *mfilter = NULL; 1713 int match = 0; 1714 *ret = 0; 1715 1716 if (efilter->ether_type != ETHER_TYPE_IPv4 && 1717 efilter->ether_type != ETHER_TYPE_IPv6) { 1718 RTE_LOG(ERR, PMD, "unsupported ether_type(0x%04x) in" 1719 " ethertype filter.", efilter->ether_type); 1720 *ret = -EINVAL; 1721 } 1722 if (efilter->queue >= bp->rx_nr_rings) { 1723 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue); 1724 *ret = -EINVAL; 1725 } 1726 1727 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1728 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); 1729 if (vnic == NULL) { 1730 RTE_LOG(ERR, PMD, "Invalid queue %d\n", efilter->queue); 1731 *ret = -EINVAL; 1732 } 1733 1734 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1735 STAILQ_FOREACH(mfilter, &vnic0->filter, next) { 1736 if ((!memcmp(efilter->mac_addr.addr_bytes, 1737 mfilter->l2_addr, ETHER_ADDR_LEN) && 1738 mfilter->flags == 1739 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP && 1740 mfilter->ethertype == efilter->ether_type)) { 1741 match = 1; 1742 break; 1743 } 1744 } 1745 } else { 1746 STAILQ_FOREACH(mfilter, &vnic->filter, next) 1747 if ((!memcmp(efilter->mac_addr.addr_bytes, 1748 mfilter->l2_addr, ETHER_ADDR_LEN) && 1749 mfilter->ethertype == efilter->ether_type && 1750 mfilter->flags == 1751 HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX)) { 1752 match = 1; 1753 break; 1754 } 1755 } 1756 1757 if (match) 1758 *ret = -EEXIST; 1759 1760 return mfilter; 1761 } 1762 1763 static int 1764 bnxt_ethertype_filter(struct rte_eth_dev *dev, 1765 enum rte_filter_op filter_op, 1766 void *arg) 1767 { 1768 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 1769 struct rte_eth_ethertype_filter *efilter = 1770 (struct rte_eth_ethertype_filter *)arg; 1771 struct bnxt_filter_info *bfilter, *filter1; 1772 struct bnxt_vnic_info *vnic, *vnic0; 1773 int ret; 1774 1775 if (filter_op == RTE_ETH_FILTER_NOP) 1776 return 0; 1777 1778 if (arg == NULL) { 1779 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.", 1780 filter_op); 1781 return -EINVAL; 1782 } 1783 1784 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1785 vnic = STAILQ_FIRST(&bp->ff_pool[efilter->queue]); 1786 1787 switch (filter_op) { 1788 case RTE_ETH_FILTER_ADD: 1789 bnxt_match_and_validate_ether_filter(bp, efilter, 1790 vnic0, vnic, &ret); 1791 if (ret < 0) 1792 return ret; 1793 1794 bfilter = bnxt_get_unused_filter(bp); 1795 if (bfilter == NULL) { 1796 RTE_LOG(ERR, PMD, 1797 "Not enough resources for a new filter.\n"); 1798 return -ENOMEM; 1799 } 1800 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 1801 memcpy(bfilter->l2_addr, efilter->mac_addr.addr_bytes, 1802 ETHER_ADDR_LEN); 1803 memcpy(bfilter->dst_macaddr, efilter->mac_addr.addr_bytes, 1804 ETHER_ADDR_LEN); 1805 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 1806 bfilter->ethertype = efilter->ether_type; 1807 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 1808 1809 filter1 = bnxt_get_l2_filter(bp, bfilter, vnic0); 1810 if (filter1 == NULL) { 1811 ret = -1; 1812 goto cleanup; 1813 } 1814 bfilter->enables |= 1815 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 1816 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 1817 1818 bfilter->dst_id = vnic->fw_vnic_id; 1819 1820 if (efilter->flags & RTE_ETHTYPE_FLAGS_DROP) { 1821 bfilter->flags = 1822 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 1823 } 1824 1825 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 1826 if (ret) 1827 goto cleanup; 1828 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 1829 break; 1830 case RTE_ETH_FILTER_DELETE: 1831 filter1 = bnxt_match_and_validate_ether_filter(bp, efilter, 1832 vnic0, vnic, &ret); 1833 if (ret == -EEXIST) { 1834 ret = bnxt_hwrm_clear_ntuple_filter(bp, filter1); 1835 1836 STAILQ_REMOVE(&vnic->filter, filter1, bnxt_filter_info, 1837 next); 1838 bnxt_free_filter(bp, filter1); 1839 } else if (ret == 0) { 1840 RTE_LOG(ERR, PMD, "No matching filter found\n"); 1841 } 1842 break; 1843 default: 1844 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op); 1845 ret = -EINVAL; 1846 goto error; 1847 } 1848 return ret; 1849 cleanup: 1850 bnxt_free_filter(bp, bfilter); 1851 error: 1852 return ret; 1853 } 1854 1855 static inline int 1856 parse_ntuple_filter(struct bnxt *bp, 1857 struct rte_eth_ntuple_filter *nfilter, 1858 struct bnxt_filter_info *bfilter) 1859 { 1860 uint32_t en = 0; 1861 1862 if (nfilter->queue >= bp->rx_nr_rings) { 1863 RTE_LOG(ERR, PMD, "Invalid queue %d\n", nfilter->queue); 1864 return -EINVAL; 1865 } 1866 1867 switch (nfilter->dst_port_mask) { 1868 case UINT16_MAX: 1869 bfilter->dst_port_mask = -1; 1870 bfilter->dst_port = nfilter->dst_port; 1871 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT | 1872 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 1873 break; 1874 default: 1875 RTE_LOG(ERR, PMD, "invalid dst_port mask."); 1876 return -EINVAL; 1877 } 1878 1879 bfilter->ip_addr_type = NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 1880 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1881 1882 switch (nfilter->proto_mask) { 1883 case UINT8_MAX: 1884 if (nfilter->proto == 17) /* IPPROTO_UDP */ 1885 bfilter->ip_protocol = 17; 1886 else if (nfilter->proto == 6) /* IPPROTO_TCP */ 1887 bfilter->ip_protocol = 6; 1888 else 1889 return -EINVAL; 1890 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 1891 break; 1892 default: 1893 RTE_LOG(ERR, PMD, "invalid protocol mask."); 1894 return -EINVAL; 1895 } 1896 1897 switch (nfilter->dst_ip_mask) { 1898 case UINT32_MAX: 1899 bfilter->dst_ipaddr_mask[0] = -1; 1900 bfilter->dst_ipaddr[0] = nfilter->dst_ip; 1901 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR | 1902 NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 1903 break; 1904 default: 1905 RTE_LOG(ERR, PMD, "invalid dst_ip mask."); 1906 return -EINVAL; 1907 } 1908 1909 switch (nfilter->src_ip_mask) { 1910 case UINT32_MAX: 1911 bfilter->src_ipaddr_mask[0] = -1; 1912 bfilter->src_ipaddr[0] = nfilter->src_ip; 1913 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR | 1914 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 1915 break; 1916 default: 1917 RTE_LOG(ERR, PMD, "invalid src_ip mask."); 1918 return -EINVAL; 1919 } 1920 1921 switch (nfilter->src_port_mask) { 1922 case UINT16_MAX: 1923 bfilter->src_port_mask = -1; 1924 bfilter->src_port = nfilter->src_port; 1925 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT | 1926 NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 1927 break; 1928 default: 1929 RTE_LOG(ERR, PMD, "invalid src_port mask."); 1930 return -EINVAL; 1931 } 1932 1933 //TODO Priority 1934 //nfilter->priority = (uint8_t)filter->priority; 1935 1936 bfilter->enables = en; 1937 return 0; 1938 } 1939 1940 static struct bnxt_filter_info* 1941 bnxt_match_ntuple_filter(struct bnxt_vnic_info *vnic, 1942 struct bnxt_filter_info *bfilter) 1943 { 1944 struct bnxt_filter_info *mfilter = NULL; 1945 1946 STAILQ_FOREACH(mfilter, &vnic->filter, next) { 1947 if (bfilter->src_ipaddr[0] == mfilter->src_ipaddr[0] && 1948 bfilter->src_ipaddr_mask[0] == 1949 mfilter->src_ipaddr_mask[0] && 1950 bfilter->src_port == mfilter->src_port && 1951 bfilter->src_port_mask == mfilter->src_port_mask && 1952 bfilter->dst_ipaddr[0] == mfilter->dst_ipaddr[0] && 1953 bfilter->dst_ipaddr_mask[0] == 1954 mfilter->dst_ipaddr_mask[0] && 1955 bfilter->dst_port == mfilter->dst_port && 1956 bfilter->dst_port_mask == mfilter->dst_port_mask && 1957 bfilter->flags == mfilter->flags && 1958 bfilter->enables == mfilter->enables) 1959 return mfilter; 1960 } 1961 return NULL; 1962 } 1963 1964 static int 1965 bnxt_cfg_ntuple_filter(struct bnxt *bp, 1966 struct rte_eth_ntuple_filter *nfilter, 1967 enum rte_filter_op filter_op) 1968 { 1969 struct bnxt_filter_info *bfilter, *mfilter, *filter1; 1970 struct bnxt_vnic_info *vnic, *vnic0; 1971 int ret; 1972 1973 if (nfilter->flags != RTE_5TUPLE_FLAGS) { 1974 RTE_LOG(ERR, PMD, "only 5tuple is supported."); 1975 return -EINVAL; 1976 } 1977 1978 if (nfilter->flags & RTE_NTUPLE_FLAGS_TCP_FLAG) { 1979 RTE_LOG(ERR, PMD, "Ntuple filter: TCP flags not supported\n"); 1980 return -EINVAL; 1981 } 1982 1983 bfilter = bnxt_get_unused_filter(bp); 1984 if (bfilter == NULL) { 1985 RTE_LOG(ERR, PMD, 1986 "Not enough resources for a new filter.\n"); 1987 return -ENOMEM; 1988 } 1989 ret = parse_ntuple_filter(bp, nfilter, bfilter); 1990 if (ret < 0) 1991 goto free_filter; 1992 1993 vnic = STAILQ_FIRST(&bp->ff_pool[nfilter->queue]); 1994 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 1995 filter1 = STAILQ_FIRST(&vnic0->filter); 1996 if (filter1 == NULL) { 1997 ret = -1; 1998 goto free_filter; 1999 } 2000 2001 bfilter->dst_id = vnic->fw_vnic_id; 2002 bfilter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2003 bfilter->enables |= 2004 HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2005 bfilter->ethertype = 0x800; 2006 bfilter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2007 2008 mfilter = bnxt_match_ntuple_filter(vnic, bfilter); 2009 2010 if (mfilter != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2011 RTE_LOG(ERR, PMD, "filter exists."); 2012 ret = -EEXIST; 2013 goto free_filter; 2014 } 2015 if (mfilter == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2016 RTE_LOG(ERR, PMD, "filter doesn't exist."); 2017 ret = -ENOENT; 2018 goto free_filter; 2019 } 2020 2021 if (filter_op == RTE_ETH_FILTER_ADD) { 2022 bfilter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2023 ret = bnxt_hwrm_set_ntuple_filter(bp, bfilter->dst_id, bfilter); 2024 if (ret) 2025 goto free_filter; 2026 STAILQ_INSERT_TAIL(&vnic->filter, bfilter, next); 2027 } else { 2028 ret = bnxt_hwrm_clear_ntuple_filter(bp, mfilter); 2029 2030 STAILQ_REMOVE(&vnic->filter, mfilter, bnxt_filter_info, 2031 next); 2032 bnxt_free_filter(bp, mfilter); 2033 bfilter->fw_l2_filter_id = -1; 2034 bnxt_free_filter(bp, bfilter); 2035 } 2036 2037 return 0; 2038 free_filter: 2039 bfilter->fw_l2_filter_id = -1; 2040 bnxt_free_filter(bp, bfilter); 2041 return ret; 2042 } 2043 2044 static int 2045 bnxt_ntuple_filter(struct rte_eth_dev *dev, 2046 enum rte_filter_op filter_op, 2047 void *arg) 2048 { 2049 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2050 int ret; 2051 2052 if (filter_op == RTE_ETH_FILTER_NOP) 2053 return 0; 2054 2055 if (arg == NULL) { 2056 RTE_LOG(ERR, PMD, "arg shouldn't be NULL for operation %u.", 2057 filter_op); 2058 return -EINVAL; 2059 } 2060 2061 switch (filter_op) { 2062 case RTE_ETH_FILTER_ADD: 2063 ret = bnxt_cfg_ntuple_filter(bp, 2064 (struct rte_eth_ntuple_filter *)arg, 2065 filter_op); 2066 break; 2067 case RTE_ETH_FILTER_DELETE: 2068 ret = bnxt_cfg_ntuple_filter(bp, 2069 (struct rte_eth_ntuple_filter *)arg, 2070 filter_op); 2071 break; 2072 default: 2073 RTE_LOG(ERR, PMD, "unsupported operation %u.", filter_op); 2074 ret = -EINVAL; 2075 break; 2076 } 2077 return ret; 2078 } 2079 2080 static int 2081 bnxt_parse_fdir_filter(struct bnxt *bp, 2082 struct rte_eth_fdir_filter *fdir, 2083 struct bnxt_filter_info *filter) 2084 { 2085 enum rte_fdir_mode fdir_mode = 2086 bp->eth_dev->data->dev_conf.fdir_conf.mode; 2087 struct bnxt_vnic_info *vnic0, *vnic; 2088 struct bnxt_filter_info *filter1; 2089 uint32_t en = 0; 2090 int i; 2091 2092 if (fdir_mode == RTE_FDIR_MODE_PERFECT_TUNNEL) 2093 return -EINVAL; 2094 2095 filter->l2_ovlan = fdir->input.flow_ext.vlan_tci; 2096 en |= EM_FLOW_ALLOC_INPUT_EN_OVLAN_VID; 2097 2098 switch (fdir->input.flow_type) { 2099 case RTE_ETH_FLOW_IPV4: 2100 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 2101 /* FALLTHROUGH */ 2102 filter->src_ipaddr[0] = fdir->input.flow.ip4_flow.src_ip; 2103 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2104 filter->dst_ipaddr[0] = fdir->input.flow.ip4_flow.dst_ip; 2105 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2106 filter->ip_protocol = fdir->input.flow.ip4_flow.proto; 2107 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2108 filter->ip_addr_type = 2109 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2110 filter->src_ipaddr_mask[0] = 0xffffffff; 2111 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2112 filter->dst_ipaddr_mask[0] = 0xffffffff; 2113 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2114 filter->ethertype = 0x800; 2115 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2116 break; 2117 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 2118 filter->src_port = fdir->input.flow.tcp4_flow.src_port; 2119 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2120 filter->dst_port = fdir->input.flow.tcp4_flow.dst_port; 2121 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2122 filter->dst_port_mask = 0xffff; 2123 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2124 filter->src_port_mask = 0xffff; 2125 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2126 filter->src_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.src_ip; 2127 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2128 filter->dst_ipaddr[0] = fdir->input.flow.tcp4_flow.ip.dst_ip; 2129 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2130 filter->ip_protocol = 6; 2131 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2132 filter->ip_addr_type = 2133 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2134 filter->src_ipaddr_mask[0] = 0xffffffff; 2135 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2136 filter->dst_ipaddr_mask[0] = 0xffffffff; 2137 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2138 filter->ethertype = 0x800; 2139 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2140 break; 2141 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 2142 filter->src_port = fdir->input.flow.udp4_flow.src_port; 2143 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2144 filter->dst_port = fdir->input.flow.udp4_flow.dst_port; 2145 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2146 filter->dst_port_mask = 0xffff; 2147 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2148 filter->src_port_mask = 0xffff; 2149 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2150 filter->src_ipaddr[0] = fdir->input.flow.udp4_flow.ip.src_ip; 2151 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2152 filter->dst_ipaddr[0] = fdir->input.flow.udp4_flow.ip.dst_ip; 2153 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2154 filter->ip_protocol = 17; 2155 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2156 filter->ip_addr_type = 2157 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV4; 2158 filter->src_ipaddr_mask[0] = 0xffffffff; 2159 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2160 filter->dst_ipaddr_mask[0] = 0xffffffff; 2161 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2162 filter->ethertype = 0x800; 2163 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2164 break; 2165 case RTE_ETH_FLOW_IPV6: 2166 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 2167 /* FALLTHROUGH */ 2168 filter->ip_addr_type = 2169 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2170 filter->ip_protocol = fdir->input.flow.ipv6_flow.proto; 2171 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2172 rte_memcpy(filter->src_ipaddr, 2173 fdir->input.flow.ipv6_flow.src_ip, 16); 2174 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2175 rte_memcpy(filter->dst_ipaddr, 2176 fdir->input.flow.ipv6_flow.dst_ip, 16); 2177 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2178 memset(filter->dst_ipaddr_mask, 0xff, 16); 2179 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2180 memset(filter->src_ipaddr_mask, 0xff, 16); 2181 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2182 filter->ethertype = 0x86dd; 2183 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2184 break; 2185 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 2186 filter->src_port = fdir->input.flow.tcp6_flow.src_port; 2187 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2188 filter->dst_port = fdir->input.flow.tcp6_flow.dst_port; 2189 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2190 filter->dst_port_mask = 0xffff; 2191 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2192 filter->src_port_mask = 0xffff; 2193 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2194 filter->ip_addr_type = 2195 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2196 filter->ip_protocol = fdir->input.flow.tcp6_flow.ip.proto; 2197 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2198 rte_memcpy(filter->src_ipaddr, 2199 fdir->input.flow.tcp6_flow.ip.src_ip, 16); 2200 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2201 rte_memcpy(filter->dst_ipaddr, 2202 fdir->input.flow.tcp6_flow.ip.dst_ip, 16); 2203 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2204 memset(filter->dst_ipaddr_mask, 0xff, 16); 2205 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2206 memset(filter->src_ipaddr_mask, 0xff, 16); 2207 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2208 filter->ethertype = 0x86dd; 2209 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2210 break; 2211 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 2212 filter->src_port = fdir->input.flow.udp6_flow.src_port; 2213 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT; 2214 filter->dst_port = fdir->input.flow.udp6_flow.dst_port; 2215 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT; 2216 filter->dst_port_mask = 0xffff; 2217 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_PORT_MASK; 2218 filter->src_port_mask = 0xffff; 2219 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_PORT_MASK; 2220 filter->ip_addr_type = 2221 NTUPLE_FLTR_ALLOC_INPUT_IP_ADDR_TYPE_IPV6; 2222 filter->ip_protocol = fdir->input.flow.udp6_flow.ip.proto; 2223 en |= NTUPLE_FLTR_ALLOC_IN_EN_IP_PROTO; 2224 rte_memcpy(filter->src_ipaddr, 2225 fdir->input.flow.udp6_flow.ip.src_ip, 16); 2226 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR; 2227 rte_memcpy(filter->dst_ipaddr, 2228 fdir->input.flow.udp6_flow.ip.dst_ip, 16); 2229 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR; 2230 memset(filter->dst_ipaddr_mask, 0xff, 16); 2231 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_IPADDR_MASK; 2232 memset(filter->src_ipaddr_mask, 0xff, 16); 2233 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_SRC_IPADDR_MASK; 2234 filter->ethertype = 0x86dd; 2235 filter->enables |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2236 break; 2237 case RTE_ETH_FLOW_L2_PAYLOAD: 2238 filter->ethertype = fdir->input.flow.l2_flow.ether_type; 2239 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_ETHERTYPE; 2240 break; 2241 case RTE_ETH_FLOW_VXLAN: 2242 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2243 return -EINVAL; 2244 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2245 filter->tunnel_type = 2246 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN; 2247 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2248 break; 2249 case RTE_ETH_FLOW_NVGRE: 2250 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2251 return -EINVAL; 2252 filter->vni = fdir->input.flow.tunnel_flow.tunnel_id; 2253 filter->tunnel_type = 2254 CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE; 2255 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_TUNNEL_TYPE; 2256 break; 2257 case RTE_ETH_FLOW_UNKNOWN: 2258 case RTE_ETH_FLOW_RAW: 2259 case RTE_ETH_FLOW_FRAG_IPV4: 2260 case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP: 2261 case RTE_ETH_FLOW_FRAG_IPV6: 2262 case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP: 2263 case RTE_ETH_FLOW_IPV6_EX: 2264 case RTE_ETH_FLOW_IPV6_TCP_EX: 2265 case RTE_ETH_FLOW_IPV6_UDP_EX: 2266 case RTE_ETH_FLOW_GENEVE: 2267 /* FALLTHROUGH */ 2268 default: 2269 return -EINVAL; 2270 } 2271 2272 vnic0 = STAILQ_FIRST(&bp->ff_pool[0]); 2273 vnic = STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); 2274 if (vnic == NULL) { 2275 RTE_LOG(ERR, PMD, "Invalid queue %d\n", fdir->action.rx_queue); 2276 return -EINVAL; 2277 } 2278 2279 2280 if (fdir_mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 2281 rte_memcpy(filter->dst_macaddr, 2282 fdir->input.flow.mac_vlan_flow.mac_addr.addr_bytes, 6); 2283 en |= NTUPLE_FLTR_ALLOC_INPUT_EN_DST_MACADDR; 2284 } 2285 2286 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) { 2287 filter->flags = HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP; 2288 filter1 = STAILQ_FIRST(&vnic0->filter); 2289 //filter1 = bnxt_get_l2_filter(bp, filter, vnic0); 2290 } else { 2291 filter->dst_id = vnic->fw_vnic_id; 2292 for (i = 0; i < ETHER_ADDR_LEN; i++) 2293 if (filter->dst_macaddr[i] == 0x00) 2294 filter1 = STAILQ_FIRST(&vnic0->filter); 2295 else 2296 filter1 = bnxt_get_l2_filter(bp, filter, vnic); 2297 } 2298 2299 if (filter1 == NULL) 2300 return -EINVAL; 2301 2302 en |= HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_ENABLES_L2_FILTER_ID; 2303 filter->fw_l2_filter_id = filter1->fw_l2_filter_id; 2304 2305 filter->enables = en; 2306 2307 return 0; 2308 } 2309 2310 static struct bnxt_filter_info * 2311 bnxt_match_fdir(struct bnxt *bp, struct bnxt_filter_info *nf) 2312 { 2313 struct bnxt_filter_info *mf = NULL; 2314 int i; 2315 2316 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2317 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2318 2319 STAILQ_FOREACH(mf, &vnic->filter, next) { 2320 if (mf->filter_type == nf->filter_type && 2321 mf->flags == nf->flags && 2322 mf->src_port == nf->src_port && 2323 mf->src_port_mask == nf->src_port_mask && 2324 mf->dst_port == nf->dst_port && 2325 mf->dst_port_mask == nf->dst_port_mask && 2326 mf->ip_protocol == nf->ip_protocol && 2327 mf->ip_addr_type == nf->ip_addr_type && 2328 mf->ethertype == nf->ethertype && 2329 mf->vni == nf->vni && 2330 mf->tunnel_type == nf->tunnel_type && 2331 mf->l2_ovlan == nf->l2_ovlan && 2332 mf->l2_ovlan_mask == nf->l2_ovlan_mask && 2333 mf->l2_ivlan == nf->l2_ivlan && 2334 mf->l2_ivlan_mask == nf->l2_ivlan_mask && 2335 !memcmp(mf->l2_addr, nf->l2_addr, ETHER_ADDR_LEN) && 2336 !memcmp(mf->l2_addr_mask, nf->l2_addr_mask, 2337 ETHER_ADDR_LEN) && 2338 !memcmp(mf->src_macaddr, nf->src_macaddr, 2339 ETHER_ADDR_LEN) && 2340 !memcmp(mf->dst_macaddr, nf->dst_macaddr, 2341 ETHER_ADDR_LEN) && 2342 !memcmp(mf->src_ipaddr, nf->src_ipaddr, 2343 sizeof(nf->src_ipaddr)) && 2344 !memcmp(mf->src_ipaddr_mask, nf->src_ipaddr_mask, 2345 sizeof(nf->src_ipaddr_mask)) && 2346 !memcmp(mf->dst_ipaddr, nf->dst_ipaddr, 2347 sizeof(nf->dst_ipaddr)) && 2348 !memcmp(mf->dst_ipaddr_mask, nf->dst_ipaddr_mask, 2349 sizeof(nf->dst_ipaddr_mask))) 2350 return mf; 2351 } 2352 } 2353 return NULL; 2354 } 2355 2356 static int 2357 bnxt_fdir_filter(struct rte_eth_dev *dev, 2358 enum rte_filter_op filter_op, 2359 void *arg) 2360 { 2361 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2362 struct rte_eth_fdir_filter *fdir = (struct rte_eth_fdir_filter *)arg; 2363 struct bnxt_filter_info *filter, *match; 2364 struct bnxt_vnic_info *vnic; 2365 int ret = 0, i; 2366 2367 if (filter_op == RTE_ETH_FILTER_NOP) 2368 return 0; 2369 2370 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH) 2371 return -EINVAL; 2372 2373 switch (filter_op) { 2374 case RTE_ETH_FILTER_ADD: 2375 case RTE_ETH_FILTER_DELETE: 2376 /* FALLTHROUGH */ 2377 filter = bnxt_get_unused_filter(bp); 2378 if (filter == NULL) { 2379 RTE_LOG(ERR, PMD, 2380 "Not enough resources for a new flow.\n"); 2381 return -ENOMEM; 2382 } 2383 2384 ret = bnxt_parse_fdir_filter(bp, fdir, filter); 2385 if (ret != 0) 2386 goto free_filter; 2387 2388 match = bnxt_match_fdir(bp, filter); 2389 if (match != NULL && filter_op == RTE_ETH_FILTER_ADD) { 2390 RTE_LOG(ERR, PMD, "Flow already exists.\n"); 2391 ret = -EEXIST; 2392 goto free_filter; 2393 } 2394 if (match == NULL && filter_op == RTE_ETH_FILTER_DELETE) { 2395 RTE_LOG(ERR, PMD, "Flow does not exist.\n"); 2396 ret = -ENOENT; 2397 goto free_filter; 2398 } 2399 2400 if (fdir->action.behavior == RTE_ETH_FDIR_REJECT) 2401 vnic = STAILQ_FIRST(&bp->ff_pool[0]); 2402 else 2403 vnic = 2404 STAILQ_FIRST(&bp->ff_pool[fdir->action.rx_queue]); 2405 2406 if (filter_op == RTE_ETH_FILTER_ADD) { 2407 filter->filter_type = HWRM_CFA_NTUPLE_FILTER; 2408 ret = bnxt_hwrm_set_ntuple_filter(bp, 2409 filter->dst_id, 2410 filter); 2411 if (ret) 2412 goto free_filter; 2413 STAILQ_INSERT_TAIL(&vnic->filter, filter, next); 2414 } else { 2415 ret = bnxt_hwrm_clear_ntuple_filter(bp, match); 2416 STAILQ_REMOVE(&vnic->filter, match, 2417 bnxt_filter_info, next); 2418 bnxt_free_filter(bp, match); 2419 filter->fw_l2_filter_id = -1; 2420 bnxt_free_filter(bp, filter); 2421 } 2422 break; 2423 case RTE_ETH_FILTER_FLUSH: 2424 for (i = bp->nr_vnics - 1; i >= 0; i--) { 2425 struct bnxt_vnic_info *vnic = &bp->vnic_info[i]; 2426 2427 STAILQ_FOREACH(filter, &vnic->filter, next) { 2428 if (filter->filter_type == 2429 HWRM_CFA_NTUPLE_FILTER) { 2430 ret = 2431 bnxt_hwrm_clear_ntuple_filter(bp, 2432 filter); 2433 STAILQ_REMOVE(&vnic->filter, filter, 2434 bnxt_filter_info, next); 2435 } 2436 } 2437 } 2438 return ret; 2439 case RTE_ETH_FILTER_UPDATE: 2440 case RTE_ETH_FILTER_STATS: 2441 case RTE_ETH_FILTER_INFO: 2442 /* FALLTHROUGH */ 2443 RTE_LOG(ERR, PMD, "operation %u not implemented", filter_op); 2444 break; 2445 default: 2446 RTE_LOG(ERR, PMD, "unknown operation %u", filter_op); 2447 ret = -EINVAL; 2448 break; 2449 } 2450 return ret; 2451 2452 free_filter: 2453 filter->fw_l2_filter_id = -1; 2454 bnxt_free_filter(bp, filter); 2455 return ret; 2456 } 2457 2458 static int 2459 bnxt_filter_ctrl_op(struct rte_eth_dev *dev __rte_unused, 2460 enum rte_filter_type filter_type, 2461 enum rte_filter_op filter_op, void *arg) 2462 { 2463 int ret = 0; 2464 2465 switch (filter_type) { 2466 case RTE_ETH_FILTER_TUNNEL: 2467 RTE_LOG(ERR, PMD, 2468 "filter type: %d: To be implemented\n", filter_type); 2469 break; 2470 case RTE_ETH_FILTER_FDIR: 2471 ret = bnxt_fdir_filter(dev, filter_op, arg); 2472 break; 2473 case RTE_ETH_FILTER_NTUPLE: 2474 ret = bnxt_ntuple_filter(dev, filter_op, arg); 2475 break; 2476 case RTE_ETH_FILTER_ETHERTYPE: 2477 ret = bnxt_ethertype_filter(dev, filter_op, arg); 2478 break; 2479 case RTE_ETH_FILTER_GENERIC: 2480 if (filter_op != RTE_ETH_FILTER_GET) 2481 return -EINVAL; 2482 *(const void **)arg = &bnxt_flow_ops; 2483 break; 2484 default: 2485 RTE_LOG(ERR, PMD, 2486 "Filter type (%d) not supported", filter_type); 2487 ret = -EINVAL; 2488 break; 2489 } 2490 return ret; 2491 } 2492 2493 static const uint32_t * 2494 bnxt_dev_supported_ptypes_get_op(struct rte_eth_dev *dev) 2495 { 2496 static const uint32_t ptypes[] = { 2497 RTE_PTYPE_L2_ETHER_VLAN, 2498 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 2499 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 2500 RTE_PTYPE_L4_ICMP, 2501 RTE_PTYPE_L4_TCP, 2502 RTE_PTYPE_L4_UDP, 2503 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN, 2504 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN, 2505 RTE_PTYPE_INNER_L4_ICMP, 2506 RTE_PTYPE_INNER_L4_TCP, 2507 RTE_PTYPE_INNER_L4_UDP, 2508 RTE_PTYPE_UNKNOWN 2509 }; 2510 2511 if (dev->rx_pkt_burst == bnxt_recv_pkts) 2512 return ptypes; 2513 return NULL; 2514 } 2515 2516 2517 2518 static int 2519 bnxt_get_eeprom_length_op(struct rte_eth_dev *dev) 2520 { 2521 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2522 int rc; 2523 uint32_t dir_entries; 2524 uint32_t entry_length; 2525 2526 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x\n", 2527 __func__, bp->pdev->addr.domain, bp->pdev->addr.bus, 2528 bp->pdev->addr.devid, bp->pdev->addr.function); 2529 2530 rc = bnxt_hwrm_nvm_get_dir_info(bp, &dir_entries, &entry_length); 2531 if (rc != 0) 2532 return rc; 2533 2534 return dir_entries * entry_length; 2535 } 2536 2537 static int 2538 bnxt_get_eeprom_op(struct rte_eth_dev *dev, 2539 struct rte_dev_eeprom_info *in_eeprom) 2540 { 2541 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2542 uint32_t index; 2543 uint32_t offset; 2544 2545 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d " 2546 "len = %d\n", __func__, bp->pdev->addr.domain, 2547 bp->pdev->addr.bus, bp->pdev->addr.devid, 2548 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2549 2550 if (in_eeprom->offset == 0) /* special offset value to get directory */ 2551 return bnxt_get_nvram_directory(bp, in_eeprom->length, 2552 in_eeprom->data); 2553 2554 index = in_eeprom->offset >> 24; 2555 offset = in_eeprom->offset & 0xffffff; 2556 2557 if (index != 0) 2558 return bnxt_hwrm_get_nvram_item(bp, index - 1, offset, 2559 in_eeprom->length, in_eeprom->data); 2560 2561 return 0; 2562 } 2563 2564 static bool bnxt_dir_type_is_ape_bin_format(uint16_t dir_type) 2565 { 2566 switch (dir_type) { 2567 case BNX_DIR_TYPE_CHIMP_PATCH: 2568 case BNX_DIR_TYPE_BOOTCODE: 2569 case BNX_DIR_TYPE_BOOTCODE_2: 2570 case BNX_DIR_TYPE_APE_FW: 2571 case BNX_DIR_TYPE_APE_PATCH: 2572 case BNX_DIR_TYPE_KONG_FW: 2573 case BNX_DIR_TYPE_KONG_PATCH: 2574 case BNX_DIR_TYPE_BONO_FW: 2575 case BNX_DIR_TYPE_BONO_PATCH: 2576 return true; 2577 } 2578 2579 return false; 2580 } 2581 2582 static bool bnxt_dir_type_is_other_exec_format(uint16_t dir_type) 2583 { 2584 switch (dir_type) { 2585 case BNX_DIR_TYPE_AVS: 2586 case BNX_DIR_TYPE_EXP_ROM_MBA: 2587 case BNX_DIR_TYPE_PCIE: 2588 case BNX_DIR_TYPE_TSCF_UCODE: 2589 case BNX_DIR_TYPE_EXT_PHY: 2590 case BNX_DIR_TYPE_CCM: 2591 case BNX_DIR_TYPE_ISCSI_BOOT: 2592 case BNX_DIR_TYPE_ISCSI_BOOT_IPV6: 2593 case BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6: 2594 return true; 2595 } 2596 2597 return false; 2598 } 2599 2600 static bool bnxt_dir_type_is_executable(uint16_t dir_type) 2601 { 2602 return bnxt_dir_type_is_ape_bin_format(dir_type) || 2603 bnxt_dir_type_is_other_exec_format(dir_type); 2604 } 2605 2606 static int 2607 bnxt_set_eeprom_op(struct rte_eth_dev *dev, 2608 struct rte_dev_eeprom_info *in_eeprom) 2609 { 2610 struct bnxt *bp = (struct bnxt *)dev->data->dev_private; 2611 uint8_t index, dir_op; 2612 uint16_t type, ext, ordinal, attr; 2613 2614 RTE_LOG(INFO, PMD, "%s(): %04x:%02x:%02x:%02x in_eeprom->offset = %d " 2615 "len = %d\n", __func__, bp->pdev->addr.domain, 2616 bp->pdev->addr.bus, bp->pdev->addr.devid, 2617 bp->pdev->addr.function, in_eeprom->offset, in_eeprom->length); 2618 2619 if (!BNXT_PF(bp)) { 2620 RTE_LOG(ERR, PMD, "NVM write not supported from a VF\n"); 2621 return -EINVAL; 2622 } 2623 2624 type = in_eeprom->magic >> 16; 2625 2626 if (type == 0xffff) { /* special value for directory operations */ 2627 index = in_eeprom->magic & 0xff; 2628 dir_op = in_eeprom->magic >> 8; 2629 if (index == 0) 2630 return -EINVAL; 2631 switch (dir_op) { 2632 case 0x0e: /* erase */ 2633 if (in_eeprom->offset != ~in_eeprom->magic) 2634 return -EINVAL; 2635 return bnxt_hwrm_erase_nvram_directory(bp, index - 1); 2636 default: 2637 return -EINVAL; 2638 } 2639 } 2640 2641 /* Create or re-write an NVM item: */ 2642 if (bnxt_dir_type_is_executable(type) == true) 2643 return -EOPNOTSUPP; 2644 ext = in_eeprom->magic & 0xffff; 2645 ordinal = in_eeprom->offset >> 16; 2646 attr = in_eeprom->offset & 0xffff; 2647 2648 return bnxt_hwrm_flash_nvram(bp, type, ordinal, ext, attr, 2649 in_eeprom->data, in_eeprom->length); 2650 return 0; 2651 } 2652 2653 /* 2654 * Initialization 2655 */ 2656 2657 static const struct eth_dev_ops bnxt_dev_ops = { 2658 .dev_infos_get = bnxt_dev_info_get_op, 2659 .dev_close = bnxt_dev_close_op, 2660 .dev_configure = bnxt_dev_configure_op, 2661 .dev_start = bnxt_dev_start_op, 2662 .dev_stop = bnxt_dev_stop_op, 2663 .dev_set_link_up = bnxt_dev_set_link_up_op, 2664 .dev_set_link_down = bnxt_dev_set_link_down_op, 2665 .stats_get = bnxt_stats_get_op, 2666 .stats_reset = bnxt_stats_reset_op, 2667 .rx_queue_setup = bnxt_rx_queue_setup_op, 2668 .rx_queue_release = bnxt_rx_queue_release_op, 2669 .tx_queue_setup = bnxt_tx_queue_setup_op, 2670 .tx_queue_release = bnxt_tx_queue_release_op, 2671 .rx_queue_intr_enable = bnxt_rx_queue_intr_enable_op, 2672 .rx_queue_intr_disable = bnxt_rx_queue_intr_disable_op, 2673 .reta_update = bnxt_reta_update_op, 2674 .reta_query = bnxt_reta_query_op, 2675 .rss_hash_update = bnxt_rss_hash_update_op, 2676 .rss_hash_conf_get = bnxt_rss_hash_conf_get_op, 2677 .link_update = bnxt_link_update_op, 2678 .promiscuous_enable = bnxt_promiscuous_enable_op, 2679 .promiscuous_disable = bnxt_promiscuous_disable_op, 2680 .allmulticast_enable = bnxt_allmulticast_enable_op, 2681 .allmulticast_disable = bnxt_allmulticast_disable_op, 2682 .mac_addr_add = bnxt_mac_addr_add_op, 2683 .mac_addr_remove = bnxt_mac_addr_remove_op, 2684 .flow_ctrl_get = bnxt_flow_ctrl_get_op, 2685 .flow_ctrl_set = bnxt_flow_ctrl_set_op, 2686 .udp_tunnel_port_add = bnxt_udp_tunnel_port_add_op, 2687 .udp_tunnel_port_del = bnxt_udp_tunnel_port_del_op, 2688 .vlan_filter_set = bnxt_vlan_filter_set_op, 2689 .vlan_offload_set = bnxt_vlan_offload_set_op, 2690 .vlan_pvid_set = bnxt_vlan_pvid_set_op, 2691 .mtu_set = bnxt_mtu_set_op, 2692 .mac_addr_set = bnxt_set_default_mac_addr_op, 2693 .xstats_get = bnxt_dev_xstats_get_op, 2694 .xstats_get_names = bnxt_dev_xstats_get_names_op, 2695 .xstats_reset = bnxt_dev_xstats_reset_op, 2696 .fw_version_get = bnxt_fw_version_get, 2697 .set_mc_addr_list = bnxt_dev_set_mc_addr_list_op, 2698 .rxq_info_get = bnxt_rxq_info_get_op, 2699 .txq_info_get = bnxt_txq_info_get_op, 2700 .dev_led_on = bnxt_dev_led_on_op, 2701 .dev_led_off = bnxt_dev_led_off_op, 2702 .xstats_get_by_id = bnxt_dev_xstats_get_by_id_op, 2703 .xstats_get_names_by_id = bnxt_dev_xstats_get_names_by_id_op, 2704 .rx_queue_count = bnxt_rx_queue_count_op, 2705 .rx_descriptor_status = bnxt_rx_descriptor_status_op, 2706 .tx_descriptor_status = bnxt_tx_descriptor_status_op, 2707 .filter_ctrl = bnxt_filter_ctrl_op, 2708 .dev_supported_ptypes_get = bnxt_dev_supported_ptypes_get_op, 2709 .get_eeprom_length = bnxt_get_eeprom_length_op, 2710 .get_eeprom = bnxt_get_eeprom_op, 2711 .set_eeprom = bnxt_set_eeprom_op, 2712 }; 2713 2714 static bool bnxt_vf_pciid(uint16_t id) 2715 { 2716 if (id == BROADCOM_DEV_ID_57304_VF || 2717 id == BROADCOM_DEV_ID_57406_VF || 2718 id == BROADCOM_DEV_ID_5731X_VF || 2719 id == BROADCOM_DEV_ID_5741X_VF || 2720 id == BROADCOM_DEV_ID_57414_VF || 2721 id == BROADCOM_DEV_ID_STRATUS_NIC_VF) 2722 return true; 2723 return false; 2724 } 2725 2726 static int bnxt_init_board(struct rte_eth_dev *eth_dev) 2727 { 2728 struct bnxt *bp = eth_dev->data->dev_private; 2729 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2730 int rc; 2731 2732 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 2733 if (!pci_dev->mem_resource[0].addr) { 2734 RTE_LOG(ERR, PMD, 2735 "Cannot find PCI device base address, aborting\n"); 2736 rc = -ENODEV; 2737 goto init_err_disable; 2738 } 2739 2740 bp->eth_dev = eth_dev; 2741 bp->pdev = pci_dev; 2742 2743 bp->bar0 = (void *)pci_dev->mem_resource[0].addr; 2744 if (!bp->bar0) { 2745 RTE_LOG(ERR, PMD, "Cannot map device registers, aborting\n"); 2746 rc = -ENOMEM; 2747 goto init_err_release; 2748 } 2749 return 0; 2750 2751 init_err_release: 2752 if (bp->bar0) 2753 bp->bar0 = NULL; 2754 2755 init_err_disable: 2756 2757 return rc; 2758 } 2759 2760 static int bnxt_dev_uninit(struct rte_eth_dev *eth_dev); 2761 2762 #define ALLOW_FUNC(x) \ 2763 { \ 2764 typeof(x) arg = (x); \ 2765 bp->pf.vf_req_fwd[((arg) >> 5)] &= \ 2766 ~rte_cpu_to_le_32(1 << ((arg) & 0x1f)); \ 2767 } 2768 static int 2769 bnxt_dev_init(struct rte_eth_dev *eth_dev) 2770 { 2771 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev); 2772 char mz_name[RTE_MEMZONE_NAMESIZE]; 2773 const struct rte_memzone *mz = NULL; 2774 static int version_printed; 2775 uint32_t total_alloc_len; 2776 phys_addr_t mz_phys_addr; 2777 struct bnxt *bp; 2778 int rc; 2779 2780 if (version_printed++ == 0) 2781 RTE_LOG(INFO, PMD, "%s\n", bnxt_version); 2782 2783 rte_eth_copy_pci_info(eth_dev, pci_dev); 2784 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE; 2785 2786 bp = eth_dev->data->dev_private; 2787 2788 rte_atomic64_init(&bp->rx_mbuf_alloc_fail); 2789 bp->dev_stopped = 1; 2790 2791 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2792 goto skip_init; 2793 2794 if (bnxt_vf_pciid(pci_dev->id.device_id)) 2795 bp->flags |= BNXT_FLAG_VF; 2796 2797 rc = bnxt_init_board(eth_dev); 2798 if (rc) { 2799 RTE_LOG(ERR, PMD, 2800 "Board initialization failed rc: %x\n", rc); 2801 goto error; 2802 } 2803 skip_init: 2804 eth_dev->dev_ops = &bnxt_dev_ops; 2805 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2806 return 0; 2807 eth_dev->rx_pkt_burst = &bnxt_recv_pkts; 2808 eth_dev->tx_pkt_burst = &bnxt_xmit_pkts; 2809 2810 if (BNXT_PF(bp) && pci_dev->id.device_id != BROADCOM_DEV_ID_NS2) { 2811 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 2812 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 2813 pci_dev->addr.bus, pci_dev->addr.devid, 2814 pci_dev->addr.function, "rx_port_stats"); 2815 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 2816 mz = rte_memzone_lookup(mz_name); 2817 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 2818 sizeof(struct rx_port_stats) + 512); 2819 if (!mz) { 2820 mz = rte_memzone_reserve(mz_name, total_alloc_len, 2821 SOCKET_ID_ANY, 2822 RTE_MEMZONE_2MB | 2823 RTE_MEMZONE_SIZE_HINT_ONLY); 2824 if (mz == NULL) 2825 return -ENOMEM; 2826 } 2827 memset(mz->addr, 0, mz->len); 2828 mz_phys_addr = mz->phys_addr; 2829 if ((unsigned long)mz->addr == mz_phys_addr) { 2830 RTE_LOG(WARNING, PMD, 2831 "Memzone physical address same as virtual.\n"); 2832 RTE_LOG(WARNING, PMD, 2833 "Using rte_mem_virt2phy()\n"); 2834 mz_phys_addr = rte_mem_virt2phy(mz->addr); 2835 if (mz_phys_addr == 0) { 2836 RTE_LOG(ERR, PMD, 2837 "unable to map address to physical memory\n"); 2838 return -ENOMEM; 2839 } 2840 } 2841 2842 bp->rx_mem_zone = (const void *)mz; 2843 bp->hw_rx_port_stats = mz->addr; 2844 bp->hw_rx_port_stats_map = mz_phys_addr; 2845 2846 snprintf(mz_name, RTE_MEMZONE_NAMESIZE, 2847 "bnxt_%04x:%02x:%02x:%02x-%s", pci_dev->addr.domain, 2848 pci_dev->addr.bus, pci_dev->addr.devid, 2849 pci_dev->addr.function, "tx_port_stats"); 2850 mz_name[RTE_MEMZONE_NAMESIZE - 1] = 0; 2851 mz = rte_memzone_lookup(mz_name); 2852 total_alloc_len = RTE_CACHE_LINE_ROUNDUP( 2853 sizeof(struct tx_port_stats) + 512); 2854 if (!mz) { 2855 mz = rte_memzone_reserve(mz_name, total_alloc_len, 2856 SOCKET_ID_ANY, 2857 RTE_MEMZONE_2MB | 2858 RTE_MEMZONE_SIZE_HINT_ONLY); 2859 if (mz == NULL) 2860 return -ENOMEM; 2861 } 2862 memset(mz->addr, 0, mz->len); 2863 mz_phys_addr = mz->phys_addr; 2864 if ((unsigned long)mz->addr == mz_phys_addr) { 2865 RTE_LOG(WARNING, PMD, 2866 "Memzone physical address same as virtual.\n"); 2867 RTE_LOG(WARNING, PMD, 2868 "Using rte_mem_virt2phy()\n"); 2869 mz_phys_addr = rte_mem_virt2phy(mz->addr); 2870 if (mz_phys_addr == 0) { 2871 RTE_LOG(ERR, PMD, 2872 "unable to map address to physical memory\n"); 2873 return -ENOMEM; 2874 } 2875 } 2876 2877 bp->tx_mem_zone = (const void *)mz; 2878 bp->hw_tx_port_stats = mz->addr; 2879 bp->hw_tx_port_stats_map = mz_phys_addr; 2880 2881 bp->flags |= BNXT_FLAG_PORT_STATS; 2882 } 2883 2884 rc = bnxt_alloc_hwrm_resources(bp); 2885 if (rc) { 2886 RTE_LOG(ERR, PMD, 2887 "hwrm resource allocation failure rc: %x\n", rc); 2888 goto error_free; 2889 } 2890 rc = bnxt_hwrm_ver_get(bp); 2891 if (rc) 2892 goto error_free; 2893 bnxt_hwrm_queue_qportcfg(bp); 2894 2895 bnxt_hwrm_func_qcfg(bp); 2896 2897 /* Get the MAX capabilities for this function */ 2898 rc = bnxt_hwrm_func_qcaps(bp); 2899 if (rc) { 2900 RTE_LOG(ERR, PMD, "hwrm query capability failure rc: %x\n", rc); 2901 goto error_free; 2902 } 2903 if (bp->max_tx_rings == 0) { 2904 RTE_LOG(ERR, PMD, "No TX rings available!\n"); 2905 rc = -EBUSY; 2906 goto error_free; 2907 } 2908 eth_dev->data->mac_addrs = rte_zmalloc("bnxt_mac_addr_tbl", 2909 ETHER_ADDR_LEN * bp->max_l2_ctx, 0); 2910 if (eth_dev->data->mac_addrs == NULL) { 2911 RTE_LOG(ERR, PMD, 2912 "Failed to alloc %u bytes needed to store MAC addr tbl", 2913 ETHER_ADDR_LEN * bp->max_l2_ctx); 2914 rc = -ENOMEM; 2915 goto error_free; 2916 } 2917 /* Copy the permanent MAC from the qcap response address now. */ 2918 memcpy(bp->mac_addr, bp->dflt_mac_addr, sizeof(bp->mac_addr)); 2919 memcpy(ð_dev->data->mac_addrs[0], bp->mac_addr, ETHER_ADDR_LEN); 2920 bp->grp_info = rte_zmalloc("bnxt_grp_info", 2921 sizeof(*bp->grp_info) * bp->max_ring_grps, 0); 2922 if (!bp->grp_info) { 2923 RTE_LOG(ERR, PMD, 2924 "Failed to alloc %zu bytes needed to store group info table\n", 2925 sizeof(*bp->grp_info) * bp->max_ring_grps); 2926 rc = -ENOMEM; 2927 goto error_free; 2928 } 2929 2930 /* Forward all requests if firmware is new enough */ 2931 if (((bp->fw_ver >= ((20 << 24) | (6 << 16) | (100 << 8))) && 2932 (bp->fw_ver < ((20 << 24) | (7 << 16)))) || 2933 ((bp->fw_ver >= ((20 << 24) | (8 << 16))))) { 2934 memset(bp->pf.vf_req_fwd, 0xff, sizeof(bp->pf.vf_req_fwd)); 2935 } else { 2936 RTE_LOG(WARNING, PMD, 2937 "Firmware too old for VF mailbox functionality\n"); 2938 memset(bp->pf.vf_req_fwd, 0, sizeof(bp->pf.vf_req_fwd)); 2939 } 2940 2941 /* 2942 * The following are used for driver cleanup. If we disallow these, 2943 * VF drivers can't clean up cleanly. 2944 */ 2945 ALLOW_FUNC(HWRM_FUNC_DRV_UNRGTR); 2946 ALLOW_FUNC(HWRM_VNIC_FREE); 2947 ALLOW_FUNC(HWRM_RING_FREE); 2948 ALLOW_FUNC(HWRM_RING_GRP_FREE); 2949 ALLOW_FUNC(HWRM_VNIC_RSS_COS_LB_CTX_FREE); 2950 ALLOW_FUNC(HWRM_CFA_L2_FILTER_FREE); 2951 ALLOW_FUNC(HWRM_STAT_CTX_FREE); 2952 rc = bnxt_hwrm_func_driver_register(bp); 2953 if (rc) { 2954 RTE_LOG(ERR, PMD, 2955 "Failed to register driver"); 2956 rc = -EBUSY; 2957 goto error_free; 2958 } 2959 2960 RTE_LOG(INFO, PMD, 2961 DRV_MODULE_NAME " found at mem %" PRIx64 ", node addr %pM\n", 2962 pci_dev->mem_resource[0].phys_addr, 2963 pci_dev->mem_resource[0].addr); 2964 2965 rc = bnxt_hwrm_func_reset(bp); 2966 if (rc) { 2967 RTE_LOG(ERR, PMD, "hwrm chip reset failure rc: %x\n", rc); 2968 rc = -1; 2969 goto error_free; 2970 } 2971 2972 if (BNXT_PF(bp)) { 2973 //if (bp->pf.active_vfs) { 2974 // TODO: Deallocate VF resources? 2975 //} 2976 if (bp->pdev->max_vfs) { 2977 rc = bnxt_hwrm_allocate_vfs(bp, bp->pdev->max_vfs); 2978 if (rc) { 2979 RTE_LOG(ERR, PMD, "Failed to allocate VFs\n"); 2980 goto error_free; 2981 } 2982 } else { 2983 rc = bnxt_hwrm_allocate_pf_only(bp); 2984 if (rc) { 2985 RTE_LOG(ERR, PMD, 2986 "Failed to allocate PF resources\n"); 2987 goto error_free; 2988 } 2989 } 2990 } 2991 2992 bnxt_hwrm_port_led_qcaps(bp); 2993 2994 rc = bnxt_setup_int(bp); 2995 if (rc) 2996 goto error_free; 2997 2998 rc = bnxt_alloc_mem(bp); 2999 if (rc) 3000 goto error_free_int; 3001 3002 rc = bnxt_request_int(bp); 3003 if (rc) 3004 goto error_free_int; 3005 3006 rc = bnxt_alloc_def_cp_ring(bp); 3007 if (rc) 3008 goto error_free_int; 3009 3010 bnxt_enable_int(bp); 3011 3012 return 0; 3013 3014 error_free_int: 3015 bnxt_disable_int(bp); 3016 bnxt_free_def_cp_ring(bp); 3017 bnxt_hwrm_func_buf_unrgtr(bp); 3018 bnxt_free_int(bp); 3019 bnxt_free_mem(bp); 3020 error_free: 3021 bnxt_dev_uninit(eth_dev); 3022 error: 3023 return rc; 3024 } 3025 3026 static int 3027 bnxt_dev_uninit(struct rte_eth_dev *eth_dev) { 3028 struct bnxt *bp = eth_dev->data->dev_private; 3029 int rc; 3030 3031 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3032 return -EPERM; 3033 3034 bnxt_disable_int(bp); 3035 bnxt_free_int(bp); 3036 bnxt_free_mem(bp); 3037 if (eth_dev->data->mac_addrs != NULL) { 3038 rte_free(eth_dev->data->mac_addrs); 3039 eth_dev->data->mac_addrs = NULL; 3040 } 3041 if (bp->grp_info != NULL) { 3042 rte_free(bp->grp_info); 3043 bp->grp_info = NULL; 3044 } 3045 rc = bnxt_hwrm_func_driver_unregister(bp, 0); 3046 bnxt_free_hwrm_resources(bp); 3047 rte_memzone_free((const struct rte_memzone *)bp->tx_mem_zone); 3048 rte_memzone_free((const struct rte_memzone *)bp->rx_mem_zone); 3049 if (bp->dev_stopped == 0) 3050 bnxt_dev_close_op(eth_dev); 3051 if (bp->pf.vf_info) 3052 rte_free(bp->pf.vf_info); 3053 eth_dev->dev_ops = NULL; 3054 eth_dev->rx_pkt_burst = NULL; 3055 eth_dev->tx_pkt_burst = NULL; 3056 3057 return rc; 3058 } 3059 3060 static int bnxt_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3061 struct rte_pci_device *pci_dev) 3062 { 3063 return rte_eth_dev_pci_generic_probe(pci_dev, sizeof(struct bnxt), 3064 bnxt_dev_init); 3065 } 3066 3067 static int bnxt_pci_remove(struct rte_pci_device *pci_dev) 3068 { 3069 return rte_eth_dev_pci_generic_remove(pci_dev, bnxt_dev_uninit); 3070 } 3071 3072 static struct rte_pci_driver bnxt_rte_pmd = { 3073 .id_table = bnxt_pci_id_map, 3074 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | 3075 RTE_PCI_DRV_INTR_LSC, 3076 .probe = bnxt_pci_probe, 3077 .remove = bnxt_pci_remove, 3078 }; 3079 3080 static bool 3081 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv) 3082 { 3083 if (strcmp(dev->device->driver->name, drv->driver.name)) 3084 return false; 3085 3086 return true; 3087 } 3088 3089 bool is_bnxt_supported(struct rte_eth_dev *dev) 3090 { 3091 return is_device_supported(dev, &bnxt_rte_pmd); 3092 } 3093 3094 RTE_PMD_REGISTER_PCI(net_bnxt, bnxt_rte_pmd); 3095 RTE_PMD_REGISTER_PCI_TABLE(net_bnxt, bnxt_pci_id_map); 3096 RTE_PMD_REGISTER_KMOD_DEP(net_bnxt, "* igb_uio | uio_pci_generic | vfio-pci"); 3097