1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2007-2013 Broadcom Corporation. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. 9 * Copyright (c) 2015-2018 Cavium Inc. 10 * All rights reserved. 11 * www.cavium.com 12 */ 13 14 #ifndef ECORE_SP_H 15 #define ECORE_SP_H 16 17 #include <rte_bitops.h> 18 #include <rte_byteorder.h> 19 20 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 21 #ifndef __LITTLE_ENDIAN 22 #define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN 23 #endif 24 #undef __BIG_ENDIAN 25 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 26 #ifndef __BIG_ENDIAN 27 #define __BIG_ENDIAN RTE_BIG_ENDIAN 28 #endif 29 #undef __LITTLE_ENDIAN 30 #endif 31 32 #include "ecore_mfw_req.h" 33 #include "ecore_fw_defs.h" 34 #include "ecore_hsi.h" 35 #include "ecore_reg.h" 36 37 struct bnx2x_softc; 38 typedef rte_iova_t ecore_dma_addr_t; /* expected to be 64 bit wide */ 39 typedef volatile int ecore_atomic_t; 40 41 42 #define ETH_ALEN RTE_ETHER_ADDR_LEN /* 6 */ 43 44 #define ECORE_SWCID_SHIFT 17 45 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) 46 47 #define ECORE_MC_HASH_SIZE 8 48 #define ECORE_MC_HASH_OFFSET(sc, i) \ 49 (BAR_TSTRORM_INTMEM + \ 50 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) 51 52 #define ECORE_MAX_MULTICAST 64 53 #define ECORE_MAX_EMUL_MULTI 1 54 55 #define IRO sc->iro_array 56 57 typedef rte_spinlock_t ECORE_MUTEX; 58 #define ECORE_MUTEX_INIT(_mutex) rte_spinlock_init(_mutex) 59 #define ECORE_MUTEX_LOCK(_mutex) rte_spinlock_lock(_mutex) 60 #define ECORE_MUTEX_UNLOCK(_mutex) rte_spinlock_unlock(_mutex) 61 62 typedef rte_spinlock_t ECORE_MUTEX_SPIN; 63 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) rte_spinlock_init(_spin) 64 #define ECORE_SPIN_LOCK_BH(_spin) rte_spinlock_lock(_spin) /* bh = bottom-half */ 65 #define ECORE_SPIN_UNLOCK_BH(_spin) rte_spinlock_unlock(_spin) /* bh = bottom-half */ 66 67 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() 68 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() 69 #define ECORE_SMP_MB() mb() 70 #define ECORE_SMP_RMB() rmb() 71 #define ECORE_SMP_WMB() wmb() 72 #define ECORE_MMIOWB() wmb() 73 74 #define ECORE_SET_BIT_NA(bit, var) (*var |= (1 << bit)) 75 #define ECORE_CLEAR_BIT_NA(bit, var) (*var &= ~(1 << bit)) 76 77 #define ECORE_TEST_BIT(bit, var) rte_bit_relaxed_get32(bit, var) 78 #define ECORE_SET_BIT(bit, var) rte_bit_relaxed_set32(bit, var) 79 #define ECORE_CLEAR_BIT(bit, var) rte_bit_relaxed_clear32(bit, var) 80 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) \ 81 rte_bit_relaxed_test_and_clear32(bit, var) 82 83 #define atomic_load_acq_int (int)* 84 #define atomic_store_rel_int(a, v) (*a = v) 85 #define atomic_cmpset_acq_int(a, o, n) ((*a = (o & (n)) | (n)) ^ o) 86 87 #define atomic_load_acq_long (long)* 88 #define atomic_store_rel_long(a, v) (*a = v) 89 #define atomic_set_acq_long(a, v) (*a |= v) 90 #define atomic_clear_acq_long(a, v) (*a &= ~v) 91 #define atomic_cmpset_acq_long(a, o, n) ((*a = (o & (n)) | (n)) ^ o) 92 #define atomic_subtract_acq_long(a, v) (*a -= v) 93 #define atomic_add_acq_long(a, v) (*a += v) 94 95 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) 96 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) 97 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bnx2x_cmpxchg((volatile int *)a, o, n) 98 99 #define ECORE_RET_PENDING(pending_bit, pending) \ 100 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) 101 102 #define ECORE_SET_FLAG(value, mask, flag) \ 103 do { \ 104 (value) &= ~(mask); \ 105 (value) |= ((flag) << (mask##_SHIFT)); \ 106 } while (0) 107 108 #define ECORE_GET_FLAG(value, mask) \ 109 (((value) &= (mask)) >> (mask##_SHIFT)) 110 111 #define ECORE_MIGHT_SLEEP() 112 113 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) 114 115 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) 116 #define ECORE_MEMCPY(_a, _b, _s) rte_memcpy(_a, _b, _s) 117 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) 118 119 #define ECORE_CPU_TO_LE16(x) htole16(x) 120 #define ECORE_CPU_TO_LE32(x) htole32(x) 121 122 #define ECORE_WAIT(_s, _t) DELAY(1000) 123 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000) 124 125 #define ECORE_LIKELY(x) likely(x) 126 #define ECORE_UNLIKELY(x) unlikely(x) 127 128 #define ECORE_ZALLOC(_size, _flags, _sc) \ 129 rte_zmalloc("", _size, RTE_CACHE_LINE_SIZE) 130 131 #define ECORE_CALLOC(_len, _size, _flags, _sc) \ 132 rte_calloc("", _len, _size, RTE_CACHE_LINE_SIZE) 133 134 #define ECORE_FREE(_s, _buf, _size) \ 135 rte_free(_buf) 136 137 #define SC_ILT(sc) ((sc)->ilt) 138 #define ILOG2(x) bnx2x_ilog2(x) 139 140 #define ECORE_ILT_ZALLOC(x, y, size) \ 141 do { \ 142 x = rte_malloc("", sizeof(struct bnx2x_dma), RTE_CACHE_LINE_SIZE); \ 143 if (x) { \ 144 if (bnx2x_dma_alloc((struct bnx2x_softc *)sc, \ 145 size, (struct bnx2x_dma *)x, \ 146 "ILT", RTE_CACHE_LINE_SIZE) != 0) { \ 147 rte_free(x); \ 148 x = NULL; \ 149 *(y) = 0; \ 150 } else { \ 151 *y = ((struct bnx2x_dma *)x)->paddr; \ 152 } \ 153 } \ 154 } while (0) 155 156 #define ECORE_ILT_FREE(x, y, size) \ 157 do { \ 158 if (x) { \ 159 bnx2x_dma_free((struct bnx2x_dma *)x); \ 160 rte_free(x); \ 161 x = NULL; \ 162 y = 0; \ 163 } \ 164 } while (0) 165 166 #define ECORE_IS_VALID_ETHER_ADDR(_mac) true 167 168 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE 169 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE 170 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE 171 172 #define ECORE_SET_CTX_VALIDATION bnx2x_set_ctx_validation 173 174 #define ECORE_UPDATE_COALESCE_SB_INDEX bnx2x_update_coalesce_sb_index 175 176 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) 177 178 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN 179 180 #define ECORE_PATH_ID SC_PATH 181 #define ECORE_PORT_ID SC_PORT 182 #define ECORE_FUNC_ID SC_FUNC 183 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC 184 185 #define CRCPOLY_LE 0xedb88320 186 uint32_t ecore_calc_crc32(uint32_t crc, uint8_t const *p, 187 uint32_t len, uint32_t magic); 188 189 uint8_t ecore_calc_crc8(uint32_t data, uint8_t crc); 190 191 192 static inline uint32_t 193 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) 194 { 195 return ecore_calc_crc32(seed, mac, len, CRCPOLY_LE); 196 } 197 198 #define ecore_sp_post(_sc, _a, _b, _c, _d) \ 199 bnx2x_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) 200 201 #define ECORE_DBG_BREAK_IF(exp) \ 202 do { \ 203 if (unlikely(exp)) { \ 204 rte_panic("ECORE"); \ 205 } \ 206 } while (0) 207 208 #define ECORE_BUG() \ 209 do { \ 210 rte_panic("BUG (%s:%d)", __FILE__, __LINE__); \ 211 } while(0); 212 213 #define ECORE_BUG_ON(exp) \ 214 do { \ 215 if (likely(exp)) { \ 216 rte_panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ 217 } \ 218 } while (0) 219 220 221 #define ECORE_MSG(sc, m, ...) \ 222 PMD_DRV_LOG(DEBUG, sc, m, ##__VA_ARGS__) 223 224 typedef struct _ecore_list_entry_t 225 { 226 struct _ecore_list_entry_t *next, *prev; 227 } ecore_list_entry_t; 228 229 typedef struct ecore_list_t 230 { 231 ecore_list_entry_t *head, *tail; 232 unsigned long cnt; 233 } ecore_list_t; 234 235 /* initialize the list */ 236 #define ECORE_LIST_INIT(_list) \ 237 do { \ 238 (_list)->head = NULL; \ 239 (_list)->tail = NULL; \ 240 (_list)->cnt = 0; \ 241 } while (0) 242 243 /* return true if the element is the last on the list */ 244 #define ECORE_LIST_IS_LAST(_elem, _list) \ 245 (_elem == (_list)->tail) 246 247 /* return true if the list is empty */ 248 #define ECORE_LIST_IS_EMPTY(_list) \ 249 ((_list)->cnt == 0) 250 251 /* return the first element */ 252 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ 253 (cast *)((_list)->head) 254 255 /* return the next element */ 256 #define ECORE_LIST_NEXT(_elem, _link, cast) \ 257 (cast *)((&((_elem)->_link))->next) 258 259 /* push an element on the head of the list */ 260 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \ 261 do { \ 262 (_elem)->prev = (ecore_list_entry_t *)0; \ 263 (_elem)->next = (_list)->head; \ 264 if ((_list)->tail == (ecore_list_entry_t *)0) { \ 265 (_list)->tail = (_elem); \ 266 } else { \ 267 (_list)->head->prev = (_elem); \ 268 } \ 269 (_list)->head = (_elem); \ 270 (_list)->cnt++; \ 271 } while (0) 272 273 /* push an element on the tail of the list */ 274 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \ 275 do { \ 276 (_elem)->next = (ecore_list_entry_t *)0; \ 277 (_elem)->prev = (_list)->tail; \ 278 if ((_list)->tail) { \ 279 (_list)->tail->next = (_elem); \ 280 } else { \ 281 (_list)->head = (_elem); \ 282 } \ 283 (_list)->tail = (_elem); \ 284 (_list)->cnt++; \ 285 } while (0) 286 287 /* push list1 on the head of list2 and return with list1 as empty */ 288 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ 289 do { \ 290 (_list1)->tail->next = (_list2)->head; \ 291 if ((_list2)->head) { \ 292 (_list2)->head->prev = (_list1)->tail; \ 293 } else { \ 294 (_list2)->tail = (_list1)->tail; \ 295 } \ 296 (_list2)->head = (_list1)->head; \ 297 (_list2)->cnt += (_list1)->cnt; \ 298 (_list1)->head = NULL; \ 299 (_list1)->tail = NULL; \ 300 (_list1)->cnt = 0; \ 301 } while (0) 302 303 /* remove an element from the list */ 304 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ 305 do { \ 306 if ((_list)->head == (_elem)) { \ 307 if ((_list)->head) { \ 308 (_list)->head = (_list)->head->next; \ 309 if ((_list)->head) { \ 310 (_list)->head->prev = (ecore_list_entry_t *)0; \ 311 } else { \ 312 (_list)->tail = (ecore_list_entry_t *)0; \ 313 } \ 314 (_list)->cnt--; \ 315 } \ 316 } else if ((_list)->tail == (_elem)) { \ 317 if ((_list)->tail) { \ 318 (_list)->tail = (_list)->tail->prev; \ 319 if ((_list)->tail) { \ 320 (_list)->tail->next = (ecore_list_entry_t *)0; \ 321 } else { \ 322 (_list)->head = (ecore_list_entry_t *)0; \ 323 } \ 324 (_list)->cnt--; \ 325 } \ 326 } else { \ 327 (_elem)->prev->next = (_elem)->next; \ 328 (_elem)->next->prev = (_elem)->prev; \ 329 (_list)->cnt--; \ 330 } \ 331 } while (0) 332 333 /* walk the list */ 334 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ 335 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ 336 pos; \ 337 pos = ECORE_LIST_NEXT(pos, _link, cast)) 338 339 /* walk the list (safely) */ 340 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ 341 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ 342 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ 343 pos != NULL; \ 344 pos = (cast *)n, \ 345 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) 346 347 348 /* Manipulate a bit vector defined as an array of uint64_t */ 349 350 /* Number of bits in one sge_mask array element */ 351 #define BIT_VEC64_ELEM_SZ 64 352 #define BIT_VEC64_ELEM_SHIFT 6 353 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) 354 355 #define __BIT_VEC64_SET_BIT(el, bit) \ 356 do { \ 357 el = ((el) | ((uint64_t)0x1 << (bit))); \ 358 } while (0) 359 360 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 361 do { \ 362 el = ((el) & (~((uint64_t)0x1 << (bit)))); \ 363 } while (0) 364 365 #define BIT_VEC64_SET_BIT(vec64, idx) \ 366 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 367 (idx) & BIT_VEC64_ELEM_MASK) 368 369 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 370 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 371 (idx) & BIT_VEC64_ELEM_MASK) 372 373 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 374 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 375 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 376 377 /* 378 * Creates a bitmask of all ones in less significant bits. 379 * idx - index of the most significant bit in the created mask 380 */ 381 #define BIT_VEC64_ONES_MASK(idx) \ 382 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 383 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) 384 385 /* fill in a MAC address the way the FW likes it */ 386 static inline void 387 ecore_set_fw_mac_addr(uint16_t *fw_hi, 388 uint16_t *fw_mid, 389 uint16_t *fw_lo, 390 uint8_t *mac) 391 { 392 ((uint8_t *)fw_hi)[0] = mac[1]; 393 ((uint8_t *)fw_hi)[1] = mac[0]; 394 ((uint8_t *)fw_mid)[0] = mac[3]; 395 ((uint8_t *)fw_mid)[1] = mac[2]; 396 ((uint8_t *)fw_lo)[0] = mac[5]; 397 ((uint8_t *)fw_lo)[1] = mac[4]; 398 } 399 400 401 enum ecore_status_t { 402 ECORE_EXISTS = -6, 403 ECORE_IO = -5, 404 ECORE_TIMEOUT = -4, 405 ECORE_INVAL = -3, 406 ECORE_BUSY = -2, 407 ECORE_NOMEM = -1, 408 ECORE_SUCCESS = 0, 409 /* PENDING is not an error and should be positive */ 410 ECORE_PENDING = 1, 411 }; 412 413 enum { 414 SWITCH_UPDATE, 415 AFEX_UPDATE, 416 }; 417 418 struct bnx2x_softc; 419 struct eth_context; 420 421 /* Bits representing general command's configuration */ 422 enum { 423 RAMROD_TX, 424 RAMROD_RX, 425 /* Wait until all pending commands complete */ 426 RAMROD_COMP_WAIT, 427 /* Don't send a ramrod, only update a registry */ 428 RAMROD_DRV_CLR_ONLY, 429 /* Configure HW according to the current object state */ 430 RAMROD_RESTORE, 431 /* Execute the next command now */ 432 RAMROD_EXEC, 433 /* Don't add a new command and continue execution of posponed 434 * commands. If not set a new command will be added to the 435 * pending commands list. 436 */ 437 RAMROD_CONT, 438 /* If there is another pending ramrod, wait until it finishes and 439 * re-try to submit this one. This flag can be set only in sleepable 440 * context, and should not be set from the context that completes the 441 * ramrods as deadlock will occur. 442 */ 443 RAMROD_RETRY, 444 }; 445 446 typedef enum { 447 ECORE_OBJ_TYPE_RX, 448 ECORE_OBJ_TYPE_TX, 449 ECORE_OBJ_TYPE_RX_TX, 450 } ecore_obj_type; 451 452 /* Public slow path states */ 453 enum { 454 ECORE_FILTER_MAC_PENDING, 455 ECORE_FILTER_VLAN_PENDING, 456 ECORE_FILTER_VLAN_MAC_PENDING, 457 ECORE_FILTER_RX_MODE_PENDING, 458 ECORE_FILTER_RX_MODE_SCHED, 459 ECORE_FILTER_ISCSI_ETH_START_SCHED, 460 ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 461 ECORE_FILTER_FCOE_ETH_START_SCHED, 462 ECORE_FILTER_FCOE_ETH_STOP_SCHED, 463 #ifdef ECORE_CHAR_DEV 464 ECORE_FILTER_BYPASS_RX_MODE_PENDING, 465 ECORE_FILTER_BYPASS_MAC_PENDING, 466 ECORE_FILTER_BYPASS_RSS_CONF_PENDING, 467 #endif 468 ECORE_FILTER_MCAST_PENDING, 469 ECORE_FILTER_MCAST_SCHED, 470 ECORE_FILTER_RSS_CONF_PENDING, 471 ECORE_AFEX_FCOE_Q_UPDATE_PENDING, 472 ECORE_AFEX_PENDING_VIFSET_MCP_ACK, 473 ECORE_FILTER_VXLAN_PENDING, 474 ECORE_FILTER_PVLAN_PENDING 475 }; 476 477 struct ecore_raw_obj { 478 uint8_t func_id; 479 480 /* Queue params */ 481 uint8_t cl_id; 482 uint32_t cid; 483 484 /* Ramrod data buffer params */ 485 void *rdata; 486 ecore_dma_addr_t rdata_mapping; 487 488 /* Ramrod state params */ 489 int state; /* "ramrod is pending" state bit */ 490 uint32_t *pstate; /* pointer to state buffer */ 491 492 ecore_obj_type obj_type; 493 494 int (*wait_comp)(struct bnx2x_softc *sc, 495 struct ecore_raw_obj *o); 496 497 bool (*check_pending)(struct ecore_raw_obj *o); 498 void (*clear_pending)(struct ecore_raw_obj *o); 499 void (*set_pending)(struct ecore_raw_obj *o); 500 }; 501 502 /************************* VLAN-MAC commands related parameters ***************/ 503 struct ecore_mac_ramrod_data { 504 uint8_t mac[ETH_ALEN]; 505 uint8_t is_inner_mac; 506 }; 507 508 struct ecore_vlan_ramrod_data { 509 uint16_t vlan; 510 }; 511 512 struct ecore_vlan_mac_ramrod_data { 513 uint8_t mac[ETH_ALEN]; 514 uint8_t is_inner_mac; 515 uint16_t vlan; 516 }; 517 518 struct ecore_vxlan_fltr_ramrod_data { 519 uint8_t innermac[ETH_ALEN]; 520 uint32_t vni; 521 }; 522 523 union ecore_classification_ramrod_data { 524 struct ecore_mac_ramrod_data mac; 525 struct ecore_vlan_ramrod_data vlan; 526 struct ecore_vlan_mac_ramrod_data vlan_mac; 527 struct ecore_vxlan_fltr_ramrod_data vxlan_fltr; 528 }; 529 530 /* VLAN_MAC commands */ 531 enum ecore_vlan_mac_cmd { 532 ECORE_VLAN_MAC_ADD, 533 ECORE_VLAN_MAC_DEL, 534 ECORE_VLAN_MAC_MOVE, 535 }; 536 537 struct ecore_vlan_mac_data { 538 /* Requested command: ECORE_VLAN_MAC_XX */ 539 enum ecore_vlan_mac_cmd cmd; 540 /* used to contain the data related vlan_mac_flags bits from 541 * ramrod parameters. 542 */ 543 uint32_t vlan_mac_flags; 544 545 /* Needed for MOVE command */ 546 struct ecore_vlan_mac_obj *target_obj; 547 548 union ecore_classification_ramrod_data u; 549 }; 550 551 /*************************** Exe Queue obj ************************************/ 552 union ecore_exe_queue_cmd_data { 553 struct ecore_vlan_mac_data vlan_mac; 554 555 struct { 556 /* TODO */ 557 } mcast; 558 }; 559 560 struct ecore_exeq_elem { 561 ecore_list_entry_t link; 562 563 /* Length of this element in the exe_chunk. */ 564 int cmd_len; 565 566 union ecore_exe_queue_cmd_data cmd_data; 567 }; 568 569 union ecore_qable_obj; 570 571 union ecore_exeq_comp_elem { 572 union event_ring_elem *elem; 573 }; 574 575 struct ecore_exe_queue_obj; 576 577 typedef int (*exe_q_validate)(struct bnx2x_softc *sc, 578 union ecore_qable_obj *o, 579 struct ecore_exeq_elem *elem); 580 581 typedef int (*exe_q_remove)(struct bnx2x_softc *sc, 582 union ecore_qable_obj *o, 583 struct ecore_exeq_elem *elem); 584 585 /* Return positive if entry was optimized, 0 - if not, negative 586 * in case of an error. 587 */ 588 typedef int (*exe_q_optimize)(struct bnx2x_softc *sc, 589 union ecore_qable_obj *o, 590 struct ecore_exeq_elem *elem); 591 typedef int (*exe_q_execute)(struct bnx2x_softc *sc, 592 union ecore_qable_obj *o, 593 ecore_list_t *exe_chunk, 594 uint32_t *ramrod_flags); 595 typedef struct ecore_exeq_elem * 596 (*exe_q_get)(struct ecore_exe_queue_obj *o, 597 struct ecore_exeq_elem *elem); 598 599 struct ecore_exe_queue_obj { 600 /* Commands pending for an execution. */ 601 ecore_list_t exe_queue; 602 603 /* Commands pending for an completion. */ 604 ecore_list_t pending_comp; 605 606 ECORE_MUTEX_SPIN lock; 607 608 /* Maximum length of commands' list for one execution */ 609 int exe_chunk_len; 610 611 union ecore_qable_obj *owner; 612 613 /****** Virtual functions ******/ 614 /** 615 * Called before commands execution for commands that are really 616 * going to be executed (after 'optimize'). 617 * 618 * Must run under exe_queue->lock 619 */ 620 exe_q_validate validate; 621 622 /** 623 * Called before removing pending commands, cleaning allocated 624 * resources (e.g., credits from validate) 625 */ 626 exe_q_remove remove; 627 628 /** 629 * This will try to cancel the current pending commands list 630 * considering the new command. 631 * 632 * Returns the number of optimized commands or a negative error code 633 * 634 * Must run under exe_queue->lock 635 */ 636 exe_q_optimize optimize; 637 638 /** 639 * Run the next commands chunk (owner specific). 640 */ 641 exe_q_execute execute; 642 643 /** 644 * Return the exe_queue element containing the specific command 645 * if any. Otherwise return NULL. 646 */ 647 exe_q_get get; 648 }; 649 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 650 /* 651 * Element in the VLAN_MAC registry list having all current configured 652 * rules. 653 */ 654 struct ecore_vlan_mac_registry_elem { 655 ecore_list_entry_t link; 656 657 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 658 * Relevant for 57710 and 57711 only. VLANs and MACs share the 659 * same CAM for these chips. 660 */ 661 int cam_offset; 662 663 /* Needed for DEL and RESTORE flows */ 664 uint32_t vlan_mac_flags; 665 666 union ecore_classification_ramrod_data u; 667 }; 668 669 /* Bits representing VLAN_MAC commands specific flags */ 670 enum { 671 ECORE_UC_LIST_MAC, 672 ECORE_ETH_MAC, 673 ECORE_ISCSI_ETH_MAC, 674 ECORE_NETQ_ETH_MAC, 675 ECORE_VLAN, 676 ECORE_DONT_CONSUME_CAM_CREDIT, 677 ECORE_DONT_CONSUME_CAM_CREDIT_DEST, 678 }; 679 /* When looking for matching filters, some flags are not interesting */ 680 #define ECORE_VLAN_MAC_CMP_MASK (1 << ECORE_UC_LIST_MAC | \ 681 1 << ECORE_ETH_MAC | \ 682 1 << ECORE_ISCSI_ETH_MAC | \ 683 1 << ECORE_NETQ_ETH_MAC | \ 684 1 << ECORE_VLAN) 685 #define ECORE_VLAN_MAC_CMP_FLAGS(flags) \ 686 ((flags) & ECORE_VLAN_MAC_CMP_MASK) 687 688 struct ecore_vlan_mac_ramrod_params { 689 /* Object to run the command from */ 690 struct ecore_vlan_mac_obj *vlan_mac_obj; 691 692 /* General command flags: COMP_WAIT, etc. */ 693 uint32_t ramrod_flags; 694 695 /* Command specific configuration request */ 696 struct ecore_vlan_mac_data user_req; 697 }; 698 699 struct ecore_vlan_mac_obj { 700 struct ecore_raw_obj raw; 701 702 /* Bookkeeping list: will prevent the addition of already existing 703 * entries. 704 */ 705 ecore_list_t head; 706 /* Implement a simple reader/writer lock on the head list. 707 * all these fields should only be accessed under the exe_queue lock 708 */ 709 uint8_t head_reader; /* Num. of readers accessing head list */ 710 bool head_exe_request; /* Pending execution request. */ 711 uint32_t saved_ramrod_flags; /* Ramrods of pending execution */ 712 713 /* Execution queue interface instance */ 714 struct ecore_exe_queue_obj exe_queue; 715 716 /* MACs credit pool */ 717 struct ecore_credit_pool_obj *macs_pool; 718 719 /* VLANs credit pool */ 720 struct ecore_credit_pool_obj *vlans_pool; 721 722 /* RAMROD command to be used */ 723 int ramrod_cmd; 724 725 /* copy first n elements onto preallocated buffer 726 * 727 * @param n number of elements to get 728 * @param buf buffer preallocated by caller into which elements 729 * will be copied. Note elements are 4-byte aligned 730 * so buffer size must be able to accommodate the 731 * aligned elements. 732 * 733 * @return number of copied bytes 734 */ 735 736 int (*get_n_elements)(struct bnx2x_softc *sc, 737 struct ecore_vlan_mac_obj *o, int n, uint8_t *base, 738 uint8_t stride, uint8_t size); 739 740 /** 741 * Checks if ADD-ramrod with the given params may be performed. 742 * 743 * @return zero if the element may be added 744 */ 745 746 int (*check_add)(struct bnx2x_softc *sc, 747 struct ecore_vlan_mac_obj *o, 748 union ecore_classification_ramrod_data *data); 749 750 /** 751 * Checks if DEL-ramrod with the given params may be performed. 752 * 753 * @return true if the element may be deleted 754 */ 755 struct ecore_vlan_mac_registry_elem * 756 (*check_del)(struct bnx2x_softc *sc, 757 struct ecore_vlan_mac_obj *o, 758 union ecore_classification_ramrod_data *data); 759 760 /** 761 * Checks if DEL-ramrod with the given params may be performed. 762 * 763 * @return true if the element may be deleted 764 */ 765 bool (*check_move)(struct bnx2x_softc *sc, 766 struct ecore_vlan_mac_obj *src_o, 767 struct ecore_vlan_mac_obj *dst_o, 768 union ecore_classification_ramrod_data *data); 769 770 /** 771 * Update the relevant credit object(s) (consume/return 772 * correspondingly). 773 */ 774 bool (*get_credit)(struct ecore_vlan_mac_obj *o); 775 bool (*put_credit)(struct ecore_vlan_mac_obj *o); 776 bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); 777 bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); 778 779 /** 780 * Configures one rule in the ramrod data buffer. 781 */ 782 void (*set_one_rule)(struct bnx2x_softc *sc, 783 struct ecore_vlan_mac_obj *o, 784 struct ecore_exeq_elem *elem, int rule_idx, 785 int cam_offset); 786 787 /** 788 * Delete all configured elements having the given 789 * vlan_mac_flags specification. Assumes no pending for 790 * execution commands. Will schedule all all currently 791 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 792 * specification for deletion and will use the given 793 * ramrod_flags for the last DEL operation. 794 * 795 * @param sc 796 * @param o 797 * @param ramrod_flags RAMROD_XX flags 798 * 799 * @return 0 if the last operation has completed successfully 800 * and there are no more elements left, positive value 801 * if there are pending for completion commands, 802 * negative value in case of failure. 803 */ 804 int (*delete_all)(struct bnx2x_softc *sc, 805 struct ecore_vlan_mac_obj *o, 806 uint32_t *vlan_mac_flags, 807 uint32_t *ramrod_flags); 808 809 /** 810 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 811 * configured elements list. 812 * 813 * @param sc 814 * @param p Command parameters (RAMROD_COMP_WAIT bit in 815 * ramrod_flags is only taken into an account) 816 * @param ppos a pointer to the cookie that should be given back in the 817 * next call to make function handle the next element. If 818 * *ppos is set to NULL it will restart the iterator. 819 * If returned *ppos == NULL this means that the last 820 * element has been handled. 821 * 822 * @return int 823 */ 824 int (*restore)(struct bnx2x_softc *sc, 825 struct ecore_vlan_mac_ramrod_params *p, 826 struct ecore_vlan_mac_registry_elem **ppos); 827 828 /** 829 * Should be called on a completion arrival. 830 * 831 * @param sc 832 * @param o 833 * @param cqe Completion element we are handling 834 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 835 * pending commands will be executed. 836 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 837 * may also be set if needed. 838 * 839 * @return 0 if there are neither pending nor waiting for 840 * completion commands. Positive value if there are 841 * pending for execution or for completion commands. 842 * Negative value in case of an error (including an 843 * error in the cqe). 844 */ 845 int (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o, 846 union event_ring_elem *cqe, 847 uint32_t *ramrod_flags); 848 849 /** 850 * Wait for completion of all commands. Don't schedule new ones, 851 * just wait. It assumes that the completion code will schedule 852 * for new commands. 853 */ 854 int (*wait)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o); 855 }; 856 857 enum { 858 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, 859 ECORE_LLH_CAM_ETH_LINE, 860 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 861 }; 862 863 void ecore_set_mac_in_nig(struct bnx2x_softc *sc, 864 bool add, unsigned char *dev_addr, int index); 865 866 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 867 868 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 869 * a ecore_rx_mode_ramrod_params. 870 */ 871 enum { 872 ECORE_RX_MODE_FCOE_ETH, 873 ECORE_RX_MODE_ISCSI_ETH, 874 }; 875 876 enum { 877 ECORE_ACCEPT_UNICAST, 878 ECORE_ACCEPT_MULTICAST, 879 ECORE_ACCEPT_ALL_UNICAST, 880 ECORE_ACCEPT_ALL_MULTICAST, 881 ECORE_ACCEPT_BROADCAST, 882 ECORE_ACCEPT_UNMATCHED, 883 ECORE_ACCEPT_ANY_VLAN 884 }; 885 886 struct ecore_rx_mode_ramrod_params { 887 struct ecore_rx_mode_obj *rx_mode_obj; 888 uint32_t *pstate; 889 int state; 890 uint8_t cl_id; 891 uint32_t cid; 892 uint8_t func_id; 893 uint32_t ramrod_flags; 894 uint32_t rx_mode_flags; 895 896 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 897 * a tstorm_eth_mac_filter_config (e1x). 898 */ 899 void *rdata; 900 ecore_dma_addr_t rdata_mapping; 901 902 /* Rx mode settings */ 903 uint32_t rx_accept_flags; 904 905 /* internal switching settings */ 906 uint32_t tx_accept_flags; 907 }; 908 909 struct ecore_rx_mode_obj { 910 int (*config_rx_mode)(struct bnx2x_softc *sc, 911 struct ecore_rx_mode_ramrod_params *p); 912 913 int (*wait_comp)(struct bnx2x_softc *sc, 914 struct ecore_rx_mode_ramrod_params *p); 915 }; 916 917 /********************** Set multicast group ***********************************/ 918 919 struct ecore_mcast_list_elem { 920 ecore_list_entry_t link; 921 uint8_t *mac; 922 }; 923 924 union ecore_mcast_config_data { 925 uint8_t *mac; 926 uint8_t bin; /* used in a RESTORE/SET flows */ 927 }; 928 929 struct ecore_mcast_ramrod_params { 930 struct ecore_mcast_obj *mcast_obj; 931 932 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 933 uint32_t ramrod_flags; 934 935 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ 936 /** TODO: 937 * - rename it to macs_num. 938 * - Add a new command type for handling pending commands 939 * (remove "zero semantics"). 940 * 941 * Length of mcast_list. If zero and ADD_CONT command - post 942 * pending commands. 943 */ 944 int mcast_list_len; 945 }; 946 947 enum ecore_mcast_cmd { 948 ECORE_MCAST_CMD_ADD, 949 ECORE_MCAST_CMD_CONT, 950 ECORE_MCAST_CMD_DEL, 951 ECORE_MCAST_CMD_RESTORE, 952 953 /* Following this, multicast configuration should equal to approx 954 * the set of MACs provided [i.e., remove all else]. 955 * The two sub-commands are used internally to decide whether a given 956 * bin is to be added or removed 957 */ 958 ECORE_MCAST_CMD_SET, 959 ECORE_MCAST_CMD_SET_ADD, 960 ECORE_MCAST_CMD_SET_DEL, 961 }; 962 963 struct ecore_mcast_obj { 964 struct ecore_raw_obj raw; 965 966 union { 967 struct { 968 #define ECORE_MCAST_BINS_NUM 256 969 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) 970 uint64_t vec[ECORE_MCAST_VEC_SZ]; 971 972 /** Number of BINs to clear. Should be updated 973 * immediately when a command arrives in order to 974 * properly create DEL commands. 975 */ 976 int num_bins_set; 977 } aprox_match; 978 979 struct { 980 ecore_list_t macs; 981 int num_macs_set; 982 } exact_match; 983 } registry; 984 985 /* Pending commands */ 986 ecore_list_t pending_cmds_head; 987 988 /* A state that is set in raw.pstate, when there are pending commands */ 989 int sched_state; 990 991 /* Maximal number of mcast MACs configured in one command */ 992 int max_cmd_len; 993 994 /* Total number of currently pending MACs to configure: both 995 * in the pending commands list and in the current command. 996 */ 997 int total_pending_num; 998 999 uint8_t engine_id; 1000 1001 /** 1002 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) 1003 */ 1004 int (*config_mcast)(struct bnx2x_softc *sc, 1005 struct ecore_mcast_ramrod_params *p, 1006 enum ecore_mcast_cmd cmd); 1007 1008 /** 1009 * Fills the ramrod data during the RESTORE flow. 1010 * 1011 * @param sc 1012 * @param o 1013 * @param start_idx Registry index to start from 1014 * @param rdata_idx Index in the ramrod data to start from 1015 * 1016 * @return -1 if we handled the whole registry or index of the last 1017 * handled registry element. 1018 */ 1019 int (*hdl_restore)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o, 1020 int start_bin, int *rdata_idx); 1021 1022 int (*enqueue_cmd)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o, 1023 struct ecore_mcast_ramrod_params *p, 1024 enum ecore_mcast_cmd cmd); 1025 1026 void (*set_one_rule)(struct bnx2x_softc *sc, 1027 struct ecore_mcast_obj *o, int idx, 1028 union ecore_mcast_config_data *cfg_data, 1029 enum ecore_mcast_cmd cmd); 1030 1031 /** Checks if there are more mcast MACs to be set or a previous 1032 * command is still pending. 1033 */ 1034 bool (*check_pending)(struct ecore_mcast_obj *o); 1035 1036 /** 1037 * Set/Clear/Check SCHEDULED state of the object 1038 */ 1039 void (*set_sched)(struct ecore_mcast_obj *o); 1040 void (*clear_sched)(struct ecore_mcast_obj *o); 1041 bool (*check_sched)(struct ecore_mcast_obj *o); 1042 1043 /* Wait until all pending commands complete */ 1044 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_mcast_obj *o); 1045 1046 /** 1047 * Handle the internal object counters needed for proper 1048 * commands handling. Checks that the provided parameters are 1049 * feasible. 1050 */ 1051 int (*validate)(struct bnx2x_softc *sc, 1052 struct ecore_mcast_ramrod_params *p, 1053 enum ecore_mcast_cmd cmd); 1054 1055 /** 1056 * Restore the values of internal counters in case of a failure. 1057 */ 1058 void (*revert)(struct bnx2x_softc *sc, 1059 struct ecore_mcast_ramrod_params *p, 1060 int old_num_bins, 1061 enum ecore_mcast_cmd cmd); 1062 1063 int (*get_registry_size)(struct ecore_mcast_obj *o); 1064 void (*set_registry_size)(struct ecore_mcast_obj *o, int n); 1065 }; 1066 1067 /*************************** Credit handling **********************************/ 1068 struct ecore_credit_pool_obj { 1069 1070 /* Current amount of credit in the pool */ 1071 ecore_atomic_t credit; 1072 1073 /* Maximum allowed credit. put() will check against it. */ 1074 int pool_sz; 1075 1076 /* Allocate a pool table statically. 1077 * 1078 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 1079 * 1080 * The set bit in the table will mean that the entry is available. 1081 */ 1082 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 1083 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; 1084 1085 /* Base pool offset (initialized differently */ 1086 int base_pool_offset; 1087 1088 /** 1089 * Get the next free pool entry. 1090 * 1091 * @return true if there was a free entry in the pool 1092 */ 1093 bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); 1094 1095 /** 1096 * Return the entry back to the pool. 1097 * 1098 * @return true if entry is legal and has been successfully 1099 * returned to the pool. 1100 */ 1101 bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry); 1102 1103 /** 1104 * Get the requested amount of credit from the pool. 1105 * 1106 * @param cnt Amount of requested credit 1107 * @return true if the operation is successful 1108 */ 1109 bool (*get)(struct ecore_credit_pool_obj *o, int cnt); 1110 1111 /** 1112 * Returns the credit to the pool. 1113 * 1114 * @param cnt Amount of credit to return 1115 * @return true if the operation is successful 1116 */ 1117 bool (*put)(struct ecore_credit_pool_obj *o, int cnt); 1118 1119 /** 1120 * Reads the current amount of credit. 1121 */ 1122 int (*check)(struct ecore_credit_pool_obj *o); 1123 }; 1124 1125 /*************************** RSS configuration ********************************/ 1126 enum { 1127 /* RSS_MODE bits are mutually exclusive */ 1128 ECORE_RSS_MODE_DISABLED, 1129 ECORE_RSS_MODE_REGULAR, 1130 1131 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 1132 1133 ECORE_RSS_IPV4, 1134 ECORE_RSS_IPV4_TCP, 1135 ECORE_RSS_IPV4_UDP, 1136 ECORE_RSS_IPV6, 1137 ECORE_RSS_IPV6_TCP, 1138 ECORE_RSS_IPV6_UDP, 1139 1140 ECORE_RSS_IPV4_VXLAN, 1141 ECORE_RSS_IPV6_VXLAN, 1142 ECORE_RSS_TUNN_INNER_HDRS, 1143 }; 1144 1145 struct ecore_config_rss_params { 1146 struct ecore_rss_config_obj *rss_obj; 1147 1148 /* may have RAMROD_COMP_WAIT set only */ 1149 uint32_t ramrod_flags; 1150 1151 /* ECORE_RSS_X bits */ 1152 uint32_t rss_flags; 1153 1154 /* Number hash bits to take into an account */ 1155 uint8_t rss_result_mask; 1156 1157 /* Indirection table */ 1158 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1159 1160 /* RSS hash values */ 1161 uint32_t rss_key[10]; 1162 1163 /* valid only if ECORE_RSS_UPDATE_TOE is set */ 1164 uint16_t toe_rss_bitmap; 1165 }; 1166 1167 struct ecore_rss_config_obj { 1168 struct ecore_raw_obj raw; 1169 1170 /* RSS engine to use */ 1171 uint8_t engine_id; 1172 1173 /* Last configured indirection table */ 1174 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1175 1176 /* flags for enabling 4-tupple hash on UDP */ 1177 uint8_t udp_rss_v4; 1178 uint8_t udp_rss_v6; 1179 1180 int (*config_rss)(struct bnx2x_softc *sc, 1181 struct ecore_config_rss_params *p); 1182 }; 1183 1184 /*********************** Queue state update ***********************************/ 1185 1186 /* UPDATE command options */ 1187 enum { 1188 ECORE_Q_UPDATE_IN_VLAN_REM, 1189 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, 1190 ECORE_Q_UPDATE_OUT_VLAN_REM, 1191 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, 1192 ECORE_Q_UPDATE_ANTI_SPOOF, 1193 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, 1194 ECORE_Q_UPDATE_ACTIVATE, 1195 ECORE_Q_UPDATE_ACTIVATE_CHNG, 1196 ECORE_Q_UPDATE_DEF_VLAN_EN, 1197 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, 1198 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, 1199 ECORE_Q_UPDATE_SILENT_VLAN_REM, 1200 ECORE_Q_UPDATE_TX_SWITCHING_CHNG, 1201 ECORE_Q_UPDATE_TX_SWITCHING, 1202 ECORE_Q_UPDATE_PTP_PKTS_CHNG, 1203 ECORE_Q_UPDATE_PTP_PKTS, 1204 }; 1205 1206 /* Allowed Queue states */ 1207 enum ecore_q_state { 1208 ECORE_Q_STATE_RESET, 1209 ECORE_Q_STATE_INITIALIZED, 1210 ECORE_Q_STATE_ACTIVE, 1211 ECORE_Q_STATE_MULTI_COS, 1212 ECORE_Q_STATE_MCOS_TERMINATED, 1213 ECORE_Q_STATE_INACTIVE, 1214 ECORE_Q_STATE_STOPPED, 1215 ECORE_Q_STATE_TERMINATED, 1216 ECORE_Q_STATE_FLRED, 1217 ECORE_Q_STATE_MAX, 1218 }; 1219 1220 /* Allowed Queue states */ 1221 enum ecore_q_logical_state { 1222 ECORE_Q_LOGICAL_STATE_ACTIVE, 1223 ECORE_Q_LOGICAL_STATE_STOPPED, 1224 }; 1225 1226 /* Allowed commands */ 1227 enum ecore_queue_cmd { 1228 ECORE_Q_CMD_INIT, 1229 ECORE_Q_CMD_SETUP, 1230 ECORE_Q_CMD_SETUP_TX_ONLY, 1231 ECORE_Q_CMD_DEACTIVATE, 1232 ECORE_Q_CMD_ACTIVATE, 1233 ECORE_Q_CMD_UPDATE, 1234 ECORE_Q_CMD_UPDATE_TPA, 1235 ECORE_Q_CMD_HALT, 1236 ECORE_Q_CMD_CFC_DEL, 1237 ECORE_Q_CMD_TERMINATE, 1238 ECORE_Q_CMD_EMPTY, 1239 ECORE_Q_CMD_MAX, 1240 }; 1241 1242 /* queue SETUP + INIT flags */ 1243 enum { 1244 ECORE_Q_FLG_TPA, 1245 ECORE_Q_FLG_TPA_IPV6, 1246 ECORE_Q_FLG_TPA_GRO, 1247 ECORE_Q_FLG_STATS, 1248 ECORE_Q_FLG_ZERO_STATS, 1249 ECORE_Q_FLG_ACTIVE, 1250 ECORE_Q_FLG_OV, 1251 ECORE_Q_FLG_VLAN, 1252 ECORE_Q_FLG_COS, 1253 ECORE_Q_FLG_HC, 1254 ECORE_Q_FLG_HC_EN, 1255 ECORE_Q_FLG_DHC, 1256 ECORE_Q_FLG_OOO, 1257 ECORE_Q_FLG_FCOE, 1258 ECORE_Q_FLG_LEADING_RSS, 1259 ECORE_Q_FLG_MCAST, 1260 ECORE_Q_FLG_DEF_VLAN, 1261 ECORE_Q_FLG_TX_SWITCH, 1262 ECORE_Q_FLG_TX_SEC, 1263 ECORE_Q_FLG_ANTI_SPOOF, 1264 ECORE_Q_FLG_SILENT_VLAN_REM, 1265 ECORE_Q_FLG_FORCE_DEFAULT_PRI, 1266 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, 1267 ECORE_Q_FLG_PCSUM_ON_PKT, 1268 ECORE_Q_FLG_TUN_INC_INNER_IP_ID, 1269 ECORE_Q_FLG_TPA_VLAN_DIS, 1270 }; 1271 1272 /* Queue type options: queue type may be a combination of below. */ 1273 enum ecore_q_type { 1274 ECORE_Q_TYPE_FWD, 1275 /** TODO: Consider moving both these flags into the init() 1276 * ramrod params. 1277 */ 1278 ECORE_Q_TYPE_HAS_RX, 1279 ECORE_Q_TYPE_HAS_TX, 1280 }; 1281 1282 #define ECORE_PRIMARY_CID_INDEX 0 1283 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ 1284 #define ECORE_MULTI_TX_COS_E2_E3A0 2 1285 #define ECORE_MULTI_TX_COS_E3B0 3 1286 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */ 1287 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) 1288 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends 1289 * timesync-related ramrods must not use this DMAE command ID. 1290 */ 1291 #define FW_DMAE_CMD_ID 6 1292 1293 struct ecore_queue_init_params { 1294 struct { 1295 uint32_t flags; 1296 uint16_t hc_rate; 1297 uint8_t fw_sb_id; 1298 uint8_t sb_cq_index; 1299 } tx; 1300 1301 struct { 1302 uint32_t flags; 1303 uint16_t hc_rate; 1304 uint8_t fw_sb_id; 1305 uint8_t sb_cq_index; 1306 } rx; 1307 1308 /* CID context in the host memory */ 1309 struct eth_context *cxts[ECORE_MULTI_TX_COS]; 1310 1311 /* maximum number of cos supported by hardware */ 1312 uint8_t max_cos; 1313 }; 1314 1315 struct ecore_queue_terminate_params { 1316 /* index within the tx_only cids of this queue object */ 1317 uint8_t cid_index; 1318 }; 1319 1320 struct ecore_queue_cfc_del_params { 1321 /* index within the tx_only cids of this queue object */ 1322 uint8_t cid_index; 1323 }; 1324 1325 struct ecore_queue_update_params { 1326 uint32_t update_flags; /* ECORE_Q_UPDATE_XX bits */ 1327 uint16_t def_vlan; 1328 uint16_t silent_removal_value; 1329 uint16_t silent_removal_mask; 1330 /* index within the tx_only cids of this queue object */ 1331 uint8_t cid_index; 1332 }; 1333 1334 struct ecore_queue_update_tpa_params { 1335 ecore_dma_addr_t sge_map; 1336 uint8_t update_ipv4; 1337 uint8_t update_ipv6; 1338 uint8_t max_tpa_queues; 1339 uint8_t max_sges_pkt; 1340 uint8_t complete_on_both_clients; 1341 uint8_t dont_verify_thr; 1342 uint8_t tpa_mode; 1343 uint8_t _pad; 1344 1345 uint16_t sge_buff_sz; 1346 uint16_t max_agg_sz; 1347 1348 uint16_t sge_pause_thr_low; 1349 uint16_t sge_pause_thr_high; 1350 1351 uint8_t disable_tpa_over_vlan; 1352 }; 1353 1354 struct rxq_pause_params { 1355 uint16_t bd_th_lo; 1356 uint16_t bd_th_hi; 1357 uint16_t rcq_th_lo; 1358 uint16_t rcq_th_hi; 1359 uint16_t sge_th_lo; /* valid if ECORE_Q_FLG_TPA */ 1360 uint16_t sge_th_hi; /* valid if ECORE_Q_FLG_TPA */ 1361 uint16_t pri_map; 1362 }; 1363 1364 /* general */ 1365 struct ecore_general_setup_params { 1366 /* valid if ECORE_Q_FLG_STATS */ 1367 uint8_t stat_id; 1368 1369 uint8_t spcl_id; 1370 uint16_t mtu; 1371 uint8_t cos; 1372 1373 uint8_t fp_hsi; 1374 }; 1375 1376 struct ecore_rxq_setup_params { 1377 /* dma */ 1378 ecore_dma_addr_t dscr_map; 1379 ecore_dma_addr_t sge_map; 1380 ecore_dma_addr_t rcq_map; 1381 ecore_dma_addr_t rcq_np_map; 1382 1383 uint16_t drop_flags; 1384 uint16_t buf_sz; 1385 uint8_t fw_sb_id; 1386 uint8_t cl_qzone_id; 1387 1388 /* valid if ECORE_Q_FLG_TPA */ 1389 uint16_t tpa_agg_sz; 1390 uint16_t sge_buf_sz; 1391 uint8_t max_sges_pkt; 1392 uint8_t max_tpa_queues; 1393 uint8_t rss_engine_id; 1394 1395 /* valid if ECORE_Q_FLG_MCAST */ 1396 uint8_t mcast_engine_id; 1397 1398 uint8_t cache_line_log; 1399 1400 uint8_t sb_cq_index; 1401 1402 /* valid if ECORE_Q_FLG_SILENT_VLAN_REM */ 1403 uint16_t silent_removal_value; 1404 uint16_t silent_removal_mask; 1405 }; 1406 1407 struct ecore_txq_setup_params { 1408 /* dma */ 1409 ecore_dma_addr_t dscr_map; 1410 1411 uint8_t fw_sb_id; 1412 uint8_t sb_cq_index; 1413 uint8_t cos; /* valid if ECORE_Q_FLG_COS */ 1414 uint16_t traffic_type; 1415 /* equals to the leading rss client id, used for TX classification*/ 1416 uint8_t tss_leading_cl_id; 1417 1418 /* valid if ECORE_Q_FLG_DEF_VLAN */ 1419 uint16_t default_vlan; 1420 }; 1421 1422 struct ecore_queue_setup_params { 1423 struct ecore_general_setup_params gen_params; 1424 struct ecore_txq_setup_params txq_params; 1425 struct ecore_rxq_setup_params rxq_params; 1426 struct rxq_pause_params pause_params; 1427 uint32_t flags; 1428 }; 1429 1430 struct ecore_queue_setup_tx_only_params { 1431 struct ecore_general_setup_params gen_params; 1432 struct ecore_txq_setup_params txq_params; 1433 uint32_t flags; 1434 /* index within the tx_only cids of this queue object */ 1435 uint8_t cid_index; 1436 }; 1437 1438 struct ecore_queue_state_params { 1439 struct ecore_queue_sp_obj *q_obj; 1440 1441 /* Current command */ 1442 enum ecore_queue_cmd cmd; 1443 1444 /* may have RAMROD_COMP_WAIT set only */ 1445 uint32_t ramrod_flags; 1446 1447 /* Params according to the current command */ 1448 union { 1449 struct ecore_queue_update_params update; 1450 struct ecore_queue_update_tpa_params update_tpa; 1451 struct ecore_queue_setup_params setup; 1452 struct ecore_queue_init_params init; 1453 struct ecore_queue_setup_tx_only_params tx_only; 1454 struct ecore_queue_terminate_params terminate; 1455 struct ecore_queue_cfc_del_params cfc_del; 1456 } params; 1457 }; 1458 1459 struct ecore_viflist_params { 1460 uint8_t echo_res; 1461 uint8_t func_bit_map_res; 1462 }; 1463 1464 struct ecore_queue_sp_obj { 1465 uint32_t cids[ECORE_MULTI_TX_COS]; 1466 uint8_t cl_id; 1467 uint8_t func_id; 1468 1469 /* number of traffic classes supported by queue. 1470 * The primary connection of the queue supports the first traffic 1471 * class. Any further traffic class is supported by a tx-only 1472 * connection. 1473 * 1474 * Therefore max_cos is also a number of valid entries in the cids 1475 * array. 1476 */ 1477 uint8_t max_cos; 1478 uint8_t num_tx_only, next_tx_only; 1479 1480 enum ecore_q_state state, next_state; 1481 1482 /* bits from enum ecore_q_type */ 1483 uint32_t type; 1484 1485 /* ECORE_Q_CMD_XX bits. This object implements "one 1486 * pending" paradigm but for debug and tracing purposes it's 1487 * more convenient to have different bits for different 1488 * commands. 1489 */ 1490 uint32_t pending; 1491 1492 /* Buffer to use as a ramrod data and its mapping */ 1493 void *rdata; 1494 ecore_dma_addr_t rdata_mapping; 1495 1496 /** 1497 * Performs one state change according to the given parameters. 1498 * 1499 * @return 0 in case of success and negative value otherwise. 1500 */ 1501 int (*send_cmd)(struct bnx2x_softc *sc, 1502 struct ecore_queue_state_params *params); 1503 1504 /** 1505 * Sets the pending bit according to the requested transition. 1506 */ 1507 int (*set_pending)(struct ecore_queue_sp_obj *o, 1508 struct ecore_queue_state_params *params); 1509 1510 /** 1511 * Checks that the requested state transition is legal. 1512 */ 1513 int (*check_transition)(struct bnx2x_softc *sc, 1514 struct ecore_queue_sp_obj *o, 1515 struct ecore_queue_state_params *params); 1516 1517 /** 1518 * Completes the pending command. 1519 */ 1520 int (*complete_cmd)(struct bnx2x_softc *sc, 1521 struct ecore_queue_sp_obj *o, 1522 enum ecore_queue_cmd); 1523 1524 int (*wait_comp)(struct bnx2x_softc *sc, 1525 struct ecore_queue_sp_obj *o, 1526 enum ecore_queue_cmd cmd); 1527 }; 1528 1529 /********************** Function state update *********************************/ 1530 1531 /* UPDATE command options */ 1532 enum { 1533 ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 1534 ECORE_F_UPDATE_TX_SWITCH_SUSPEND, 1535 ECORE_F_UPDATE_SD_VLAN_TAG_CHNG, 1536 ECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG, 1537 ECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG, 1538 ECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG, 1539 ECORE_F_UPDATE_TUNNEL_CFG_CHNG, 1540 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE, 1541 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN, 1542 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE, 1543 ECORE_F_UPDATE_TUNNEL_INNER_RSS, 1544 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN_INNER_VNI, 1545 ECORE_F_UPDATE_VLAN_FILTERING_PVID_CHNG, 1546 }; 1547 1548 /* Allowed Function states */ 1549 enum ecore_func_state { 1550 ECORE_F_STATE_RESET, 1551 ECORE_F_STATE_INITIALIZED, 1552 ECORE_F_STATE_STARTED, 1553 ECORE_F_STATE_TX_STOPPED, 1554 ECORE_F_STATE_MAX, 1555 }; 1556 1557 /* Allowed Function commands */ 1558 enum ecore_func_cmd { 1559 ECORE_F_CMD_HW_INIT, 1560 ECORE_F_CMD_START, 1561 ECORE_F_CMD_STOP, 1562 ECORE_F_CMD_HW_RESET, 1563 ECORE_F_CMD_AFEX_UPDATE, 1564 ECORE_F_CMD_AFEX_VIFLISTS, 1565 ECORE_F_CMD_TX_STOP, 1566 ECORE_F_CMD_TX_START, 1567 ECORE_F_CMD_SWITCH_UPDATE, 1568 ECORE_F_CMD_SET_TIMESYNC, 1569 ECORE_F_CMD_MAX, 1570 }; 1571 1572 struct ecore_func_hw_init_params { 1573 /* A load phase returned by MCP. 1574 * 1575 * May be: 1576 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1577 * FW_MSG_CODE_DRV_LOAD_COMMON 1578 * FW_MSG_CODE_DRV_LOAD_PORT 1579 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1580 */ 1581 uint32_t load_phase; 1582 }; 1583 1584 struct ecore_func_hw_reset_params { 1585 /* A load phase returned by MCP. 1586 * 1587 * May be: 1588 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1589 * FW_MSG_CODE_DRV_LOAD_COMMON 1590 * FW_MSG_CODE_DRV_LOAD_PORT 1591 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1592 */ 1593 uint32_t reset_phase; 1594 }; 1595 1596 struct ecore_func_start_params { 1597 /* Multi Function mode: 1598 * - Single Function 1599 * - Switch Dependent 1600 * - Switch Independent 1601 */ 1602 uint16_t mf_mode; 1603 1604 /* Switch Dependent mode outer VLAN tag */ 1605 uint16_t sd_vlan_tag; 1606 1607 /* Function cos mode */ 1608 uint8_t network_cos_mode; 1609 1610 /* DMAE command id to be used for FW DMAE transactions */ 1611 uint8_t dmae_cmd_id; 1612 1613 /* UDP dest port for VXLAN */ 1614 uint16_t vxlan_dst_port; 1615 1616 /* UDP dest port for Geneve */ 1617 uint16_t geneve_dst_port; 1618 1619 /* Enable inner Rx classifications for L2GRE packets */ 1620 uint8_t inner_clss_l2gre; 1621 1622 /* Enable inner Rx classifications for L2-Geneve packets */ 1623 uint8_t inner_clss_l2geneve; 1624 1625 /* Enable inner Rx classification for vxlan packets */ 1626 uint8_t inner_clss_vxlan; 1627 1628 /* Enable RSS according to inner header */ 1629 uint8_t inner_rss; 1630 1631 /** Allows accepting of packets failing MF classification, possibly 1632 * only matching a given ethertype 1633 */ 1634 uint8_t class_fail; 1635 uint16_t class_fail_ethtype; 1636 1637 /* Override priority of output packets */ 1638 uint8_t sd_vlan_force_pri; 1639 uint8_t sd_vlan_force_pri_val; 1640 1641 /* Replace vlan's ethertype */ 1642 uint16_t sd_vlan_eth_type; 1643 1644 /* Prevent inner vlans from being added by FW */ 1645 uint8_t no_added_tags; 1646 1647 /* Inner-to-Outer vlan priority mapping */ 1648 uint8_t c2s_pri[MAX_VLAN_PRIORITIES]; 1649 uint8_t c2s_pri_default; 1650 uint8_t c2s_pri_valid; 1651 1652 /* TX Vlan filtering configuration */ 1653 uint8_t tx_vlan_filtering_enable; 1654 uint8_t tx_vlan_filtering_use_pvid; 1655 }; 1656 1657 struct ecore_func_switch_update_params { 1658 uint32_t changes; /* ECORE_F_UPDATE_XX bits */ 1659 uint16_t vlan; 1660 uint16_t vlan_eth_type; 1661 uint8_t vlan_force_prio; 1662 uint16_t vxlan_dst_port; 1663 uint16_t geneve_dst_port; 1664 }; 1665 1666 struct ecore_func_afex_update_params { 1667 uint16_t vif_id; 1668 uint16_t afex_default_vlan; 1669 uint8_t allowed_priorities; 1670 }; 1671 1672 struct ecore_func_afex_viflists_params { 1673 uint16_t vif_list_index; 1674 uint8_t func_bit_map; 1675 uint8_t afex_vif_list_command; 1676 uint8_t func_to_clear; 1677 }; 1678 1679 struct ecore_func_tx_start_params { 1680 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1681 uint8_t dcb_enabled; 1682 uint8_t dcb_version; 1683 uint8_t dont_add_pri_0_en; 1684 uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES]; 1685 }; 1686 1687 struct ecore_func_set_timesync_params { 1688 /* Reset, set or keep the current drift value */ 1689 uint8_t drift_adjust_cmd; 1690 /* Dec, inc or keep the current offset */ 1691 uint8_t offset_cmd; 1692 /* Drift value direction */ 1693 uint8_t add_sub_drift_adjust_value; 1694 /* Drift, period and offset values to be used according to the commands 1695 * above. 1696 */ 1697 uint8_t drift_adjust_value; 1698 uint32_t drift_adjust_period; 1699 uint64_t offset_delta; 1700 }; 1701 1702 struct ecore_func_state_params { 1703 struct ecore_func_sp_obj *f_obj; 1704 1705 /* Current command */ 1706 enum ecore_func_cmd cmd; 1707 1708 /* may have RAMROD_COMP_WAIT set only */ 1709 uint32_t ramrod_flags; 1710 1711 /* Params according to the current command */ 1712 union { 1713 struct ecore_func_hw_init_params hw_init; 1714 struct ecore_func_hw_reset_params hw_reset; 1715 struct ecore_func_start_params start; 1716 struct ecore_func_switch_update_params switch_update; 1717 struct ecore_func_afex_update_params afex_update; 1718 struct ecore_func_afex_viflists_params afex_viflists; 1719 struct ecore_func_tx_start_params tx_start; 1720 struct ecore_func_set_timesync_params set_timesync; 1721 } params; 1722 }; 1723 1724 struct ecore_func_sp_drv_ops { 1725 /* Init tool + runtime initialization: 1726 * - Common Chip 1727 * - Common (per Path) 1728 * - Port 1729 * - Function phases 1730 */ 1731 int (*init_hw_cmn_chip)(struct bnx2x_softc *sc); 1732 int (*init_hw_cmn)(struct bnx2x_softc *sc); 1733 int (*init_hw_port)(struct bnx2x_softc *sc); 1734 int (*init_hw_func)(struct bnx2x_softc *sc); 1735 1736 /* Reset Function HW: Common, Port, Function phases. */ 1737 void (*reset_hw_cmn)(struct bnx2x_softc *sc); 1738 void (*reset_hw_port)(struct bnx2x_softc *sc); 1739 void (*reset_hw_func)(struct bnx2x_softc *sc); 1740 1741 /* Init/Free GUNZIP resources */ 1742 int (*gunzip_init)(struct bnx2x_softc *sc); 1743 void (*gunzip_end)(struct bnx2x_softc *sc); 1744 1745 /* Prepare/Release FW resources */ 1746 int (*init_fw)(struct bnx2x_softc *sc); 1747 void (*release_fw)(struct bnx2x_softc *sc); 1748 }; 1749 1750 struct ecore_func_sp_obj { 1751 enum ecore_func_state state, next_state; 1752 1753 /* ECORE_FUNC_CMD_XX bits. This object implements "one 1754 * pending" paradigm but for debug and tracing purposes it's 1755 * more convenient to have different bits for different 1756 * commands. 1757 */ 1758 uint32_t pending; 1759 1760 /* Buffer to use as a ramrod data and its mapping */ 1761 void *rdata; 1762 ecore_dma_addr_t rdata_mapping; 1763 1764 /* Buffer to use as a afex ramrod data and its mapping. 1765 * This can't be same rdata as above because afex ramrod requests 1766 * can arrive to the object in parallel to other ramrod requests. 1767 */ 1768 void *afex_rdata; 1769 ecore_dma_addr_t afex_rdata_mapping; 1770 1771 /* this mutex validates that when pending flag is taken, the next 1772 * ramrod to be sent will be the one set the pending bit 1773 */ 1774 ECORE_MUTEX one_pending_mutex; 1775 1776 /* Driver interface */ 1777 struct ecore_func_sp_drv_ops *drv; 1778 1779 /** 1780 * Performs one state change according to the given parameters. 1781 * 1782 * @return 0 in case of success and negative value otherwise. 1783 */ 1784 int (*send_cmd)(struct bnx2x_softc *sc, 1785 struct ecore_func_state_params *params); 1786 1787 /** 1788 * Checks that the requested state transition is legal. 1789 */ 1790 int (*check_transition)(struct bnx2x_softc *sc, 1791 struct ecore_func_sp_obj *o, 1792 struct ecore_func_state_params *params); 1793 1794 /** 1795 * Completes the pending command. 1796 */ 1797 int (*complete_cmd)(struct bnx2x_softc *sc, 1798 struct ecore_func_sp_obj *o, 1799 enum ecore_func_cmd cmd); 1800 1801 int (*wait_comp)(struct bnx2x_softc *sc, struct ecore_func_sp_obj *o, 1802 enum ecore_func_cmd cmd); 1803 }; 1804 1805 /********************** Interfaces ********************************************/ 1806 /* Queueable objects set */ 1807 union ecore_qable_obj { 1808 struct ecore_vlan_mac_obj vlan_mac; 1809 }; 1810 /************** Function state update *********/ 1811 void ecore_init_func_obj(struct bnx2x_softc *sc, 1812 struct ecore_func_sp_obj *obj, 1813 void *rdata, ecore_dma_addr_t rdata_mapping, 1814 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, 1815 struct ecore_func_sp_drv_ops *drv_iface); 1816 1817 int ecore_func_state_change(struct bnx2x_softc *sc, 1818 struct ecore_func_state_params *params); 1819 1820 enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc, 1821 struct ecore_func_sp_obj *o); 1822 /******************* Queue State **************/ 1823 void ecore_init_queue_obj(struct bnx2x_softc *sc, 1824 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, 1825 uint8_t cid_cnt, uint8_t func_id, void *rdata, 1826 ecore_dma_addr_t rdata_mapping, uint32_t type); 1827 1828 int ecore_queue_state_change(struct bnx2x_softc *sc, 1829 struct ecore_queue_state_params *params); 1830 1831 int ecore_get_q_logical_state(struct bnx2x_softc *sc, 1832 struct ecore_queue_sp_obj *obj); 1833 1834 /********************* VLAN-MAC ****************/ 1835 void ecore_init_mac_obj(struct bnx2x_softc *sc, 1836 struct ecore_vlan_mac_obj *mac_obj, 1837 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1838 ecore_dma_addr_t rdata_mapping, int state, 1839 uint32_t *pstate, ecore_obj_type type, 1840 struct ecore_credit_pool_obj *macs_pool); 1841 1842 void ecore_init_vlan_obj(struct bnx2x_softc *sc, 1843 struct ecore_vlan_mac_obj *vlan_obj, 1844 uint8_t cl_id, uint32_t cid, uint8_t func_id, 1845 void *rdata, 1846 ecore_dma_addr_t rdata_mapping, int state, 1847 uint32_t *pstate, ecore_obj_type type, 1848 struct ecore_credit_pool_obj *vlans_pool); 1849 1850 void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc, 1851 struct ecore_vlan_mac_obj *vlan_mac_obj, 1852 uint8_t cl_id, uint32_t cid, uint8_t func_id, 1853 void *rdata, 1854 ecore_dma_addr_t rdata_mapping, int state, 1855 uint32_t *pstate, ecore_obj_type type, 1856 struct ecore_credit_pool_obj *macs_pool, 1857 struct ecore_credit_pool_obj *vlans_pool); 1858 1859 void ecore_init_vxlan_fltr_obj(struct bnx2x_softc *sc, 1860 struct ecore_vlan_mac_obj *vlan_mac_obj, 1861 uint8_t cl_id, uint32_t cid, uint8_t func_id, 1862 void *rdata, 1863 ecore_dma_addr_t rdata_mapping, int state, 1864 uint32_t *pstate, ecore_obj_type type, 1865 struct ecore_credit_pool_obj *macs_pool, 1866 struct ecore_credit_pool_obj *vlans_pool); 1867 1868 int ecore_vlan_mac_h_read_lock(struct bnx2x_softc *sc, 1869 struct ecore_vlan_mac_obj *o); 1870 void ecore_vlan_mac_h_read_unlock(struct bnx2x_softc *sc, 1871 struct ecore_vlan_mac_obj *o); 1872 int ecore_vlan_mac_h_write_lock(struct bnx2x_softc *sc, 1873 struct ecore_vlan_mac_obj *o); 1874 void ecore_vlan_mac_h_write_unlock(struct bnx2x_softc *sc, 1875 struct ecore_vlan_mac_obj *o); 1876 int ecore_config_vlan_mac(struct bnx2x_softc *sc, 1877 struct ecore_vlan_mac_ramrod_params *p); 1878 1879 int ecore_vlan_mac_move(struct bnx2x_softc *sc, 1880 struct ecore_vlan_mac_ramrod_params *p, 1881 struct ecore_vlan_mac_obj *dest_o); 1882 1883 /********************* RX MODE ****************/ 1884 1885 void ecore_init_rx_mode_obj(struct bnx2x_softc *sc, 1886 struct ecore_rx_mode_obj *o); 1887 1888 /** 1889 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1890 * 1891 * @p: Command parameters 1892 * 1893 * Return: 0 - if operation was successful and there is no pending completions, 1894 * positive number - if there are pending completions, 1895 * negative - if there were errors 1896 */ 1897 int ecore_config_rx_mode(struct bnx2x_softc *sc, 1898 struct ecore_rx_mode_ramrod_params *p); 1899 1900 /****************** MULTICASTS ****************/ 1901 1902 void ecore_init_mcast_obj(struct bnx2x_softc *sc, 1903 struct ecore_mcast_obj *mcast_obj, 1904 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, 1905 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, 1906 int state, uint32_t *pstate, 1907 ecore_obj_type type); 1908 1909 /** 1910 * ecore_config_mcast - Configure multicast MACs list. 1911 * 1912 * @cmd: command to execute: ECORE_MCAST_CMD_X 1913 * 1914 * May configure a new list 1915 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up 1916 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current 1917 * configuration, continue to execute the pending commands 1918 * (ECORE_MCAST_CMD_CONT). 1919 * 1920 * If previous command is still pending or if number of MACs to 1921 * configure is more that maximum number of MACs in one command, 1922 * the current command will be enqueued to the tail of the 1923 * pending commands list. 1924 * 1925 * Return: 0 is operation was successful and there are no pending completions, 1926 * negative if there were errors, positive if there are pending 1927 * completions. 1928 */ 1929 int ecore_config_mcast(struct bnx2x_softc *sc, 1930 struct ecore_mcast_ramrod_params *p, 1931 enum ecore_mcast_cmd cmd); 1932 1933 /****************** CREDIT POOL ****************/ 1934 void ecore_init_mac_credit_pool(struct bnx2x_softc *sc, 1935 struct ecore_credit_pool_obj *p, uint8_t func_id, 1936 uint8_t func_num); 1937 void ecore_init_vlan_credit_pool(struct bnx2x_softc *sc, 1938 struct ecore_credit_pool_obj *p, uint8_t func_id, 1939 uint8_t func_num); 1940 void ecore_init_credit_pool(struct ecore_credit_pool_obj *p, 1941 int base, int credit); 1942 1943 /****************** RSS CONFIGURATION ****************/ 1944 void ecore_init_rss_config_obj(struct bnx2x_softc *sc, 1945 struct ecore_rss_config_obj *rss_obj, 1946 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, 1947 void *rdata, ecore_dma_addr_t rdata_mapping, 1948 int state, uint32_t *pstate, 1949 ecore_obj_type type); 1950 1951 /** 1952 * ecore_config_rss - Updates RSS configuration according to provided parameters 1953 * 1954 * Return: 0 in case of success 1955 */ 1956 int ecore_config_rss(struct bnx2x_softc *sc, 1957 struct ecore_config_rss_params *p); 1958 1959 /** 1960 * ecore_get_rss_ind_table - Return the current ind_table configuration. 1961 * 1962 * @ind_table: buffer to fill with the current indirection 1963 * table content. Should be at least 1964 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1965 */ 1966 void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj, 1967 uint8_t *ind_table); 1968 1969 #define PF_MAC_CREDIT_E2(sc, func_num) \ 1970 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \ 1971 (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT) 1972 1973 #define PF_VLAN_CREDIT_E2(sc, func_num) \ 1974 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \ 1975 (func_num) + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT) 1976 1977 #define ECORE_PF_VLAN_CREDIT_VLAN_FILTERING 256 1978 1979 #endif /* ECORE_SP_H */ 1980