1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright (c) 2007-2013 Broadcom Corporation. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Copyright (c) 2014-2018 Cavium Inc. 9 * All rights reserved. 10 * www.cavium.com 11 */ 12 13 #ifndef ECORE_REG_H 14 #define ECORE_REG_H 15 16 #define ATC_ATC_INT_STS_REG_ADDRESS_ERROR (0x1 << 0) 17 #define ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS (0x1 << 2) 18 #define ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU (0x1 << 5) 19 #define ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT (0x1 << 3) 20 #define ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR (0x1 << 4) 21 #define ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND (0x1 << 1) 22 /* [R 1] ATC initalization done */ 23 #define ATC_REG_ATC_INIT_DONE 0x1100bc 24 /* [RW 6] Interrupt mask register #0 read/write */ 25 #define ATC_REG_ATC_INT_MASK 0x1101c8 26 /* [R 6] Interrupt register #0 read */ 27 #define ATC_REG_ATC_INT_STS 0x1101bc 28 /* [RC 6] Interrupt register #0 read clear */ 29 #define ATC_REG_ATC_INT_STS_CLR 0x1101c0 30 /* [RW 5] Parity mask register #0 read/write */ 31 #define ATC_REG_ATC_PRTY_MASK 0x1101d8 32 /* [R 5] Parity register #0 read */ 33 #define ATC_REG_ATC_PRTY_STS 0x1101cc 34 /* [RC 5] Parity register #0 read clear */ 35 #define ATC_REG_ATC_PRTY_STS_CLR 0x1101d0 36 /* [RW 19] Interrupt mask register #0 read/write */ 37 #define BRB1_REG_BRB1_INT_MASK 0x60128 38 /* [R 19] Interrupt register #0 read */ 39 #define BRB1_REG_BRB1_INT_STS 0x6011c 40 /* [RC 19] Interrupt register #0 read clear */ 41 #define BRB1_REG_BRB1_INT_STS_CLR 0x60120 42 /* [RW 4] Parity mask register #0 read/write */ 43 #define BRB1_REG_BRB1_PRTY_MASK 0x60138 44 /* [R 4] Parity register #0 read */ 45 #define BRB1_REG_BRB1_PRTY_STS 0x6012c 46 /* [RC 4] Parity register #0 read clear */ 47 #define BRB1_REG_BRB1_PRTY_STS_CLR 0x60130 48 /* [RW 11] The number of blocks guarantied for the MAC port. The register is 49 * applicable only when per_class_guaranty_mode is reset. 50 */ 51 #define BRB1_REG_MAC_GUARANTIED_0 0x601e8 52 #define BRB1_REG_MAC_GUARANTIED_1 0x60240 53 /* [R 24] The number of full blocks. */ 54 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090 55 /* [RW 10] Write client 0: De-assert pause threshold. Not Functional */ 56 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078 57 /* [RW 10] Write client 0: Assert pause threshold. Not Functional */ 58 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068 59 /* [R 24] The number of full blocks occpied by port. */ 60 #define BRB1_REG_PORT_NUM_OCC_BLOCKS_0 0x60094 61 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */ 62 #define CCM_REG_CAM_OCCUP 0xd0188 63 /* [RW 11] Interrupt mask register #0 read/write */ 64 #define CCM_REG_CCM_INT_MASK 0xd01e4 65 /* [R 11] Interrupt register #0 read */ 66 #define CCM_REG_CCM_INT_STS 0xd01d8 67 /* [RC 11] Interrupt register #0 read clear */ 68 #define CCM_REG_CCM_INT_STS_CLR 0xd01dc 69 /* [RW 27] Parity mask register #0 read/write */ 70 #define CCM_REG_CCM_PRTY_MASK 0xd01f4 71 /* [R 27] Parity register #0 read */ 72 #define CCM_REG_CCM_PRTY_STS 0xd01e8 73 /* [RC 27] Parity register #0 read clear */ 74 #define CCM_REG_CCM_PRTY_STS_CLR 0xd01ec 75 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 76 * the initial credit value; read returns the current value of the credit 77 * counter. Must be initialized to 1 at start-up. 78 */ 79 #define CCM_REG_CFC_INIT_CRD 0xd0204 80 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes 81 * the initial credit value; read returns the current value of the credit 82 * counter. Must be initialized to 32 at start-up. 83 */ 84 #define CCM_REG_CQM_INIT_CRD 0xd020c 85 /* [RC 1] Set when the message length mismatch (relative to last indication) 86 * at the SDM interface is detected. 87 */ 88 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170 89 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write 90 * writes the initial credit value; read returns the current value of the 91 * credit counter. Must be initialized to 64 at start-up. 92 */ 93 #define CCM_REG_FIC0_INIT_CRD 0xd0210 94 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 95 * writes the initial credit value; read returns the current value of the 96 * credit counter. Must be initialized to 64 at start-up. 97 */ 98 #define CCM_REG_FIC1_INIT_CRD 0xd0214 99 /* [RC 1] Set when the message length mismatch (relative to last indication) 100 * at the pbf interface is detected. 101 */ 102 #define CCM_REG_PBF_LENGTH_MIS 0xd0180 103 /* [RC 1] Set when the message length mismatch (relative to last indication) 104 * at the STORM interface is detected. 105 */ 106 #define CCM_REG_STORM_LENGTH_MIS 0xd016c 107 /* [RC 1] Set when the message length mismatch (relative to last indication) 108 * at the tsem interface is detected. 109 */ 110 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174 111 /* [RC 1] Set when message length mismatch (relative to last indication) at 112 * the usem interface is detected. 113 */ 114 #define CCM_REG_USEM_LENGTH_MIS 0xd017c 115 /* [RC 1] Set when the message length mismatch (relative to last indication) 116 * at the xsem interface is detected. 117 */ 118 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178 119 /* [RW 19] Indirect access to the descriptor table of the XX protection 120 * mechanism. The fields are: [5:0] - message length; [12:6] - message 121 * pointer; 18:13] - next pointer. 122 */ 123 #define CCM_REG_XX_DESCR_TABLE 0xd0300 124 #define CCM_REG_XX_DESCR_TABLE_SIZE 24 125 /* [R 7] Used to read the value of XX protection Free counter. */ 126 #define CCM_REG_XX_FREE 0xd0184 127 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020 128 /* [RW 7] Interrupt mask register #0 read/write */ 129 #define CDU_REG_CDU_INT_MASK 0x10103c 130 /* [R 7] Interrupt register #0 read */ 131 #define CDU_REG_CDU_INT_STS 0x101030 132 /* [RC 7] Interrupt register #0 read clear */ 133 #define CDU_REG_CDU_INT_STS_CLR 0x101034 134 /* [RW 5] Parity mask register #0 read/write */ 135 #define CDU_REG_CDU_PRTY_MASK 0x10104c 136 /* [R 5] Parity register #0 read */ 137 #define CDU_REG_CDU_PRTY_STS 0x101040 138 /* [RC 5] Parity register #0 read clear */ 139 #define CDU_REG_CDU_PRTY_STS_CLR 0x101044 140 /* [RW 32] logging of error data in case of a CDU load error: 141 * {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error; 142 * ype_error; ctual_active; ctual_compressed_context}; 143 */ 144 #define CDU_REG_ERROR_DATA 0x101014 145 /* [RW 13] activity counter ram access */ 146 #define CFC_REG_ACTIVITY_COUNTER 0x104400 147 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256 148 /* [R 1] indication the initializing the activity counter by the hardware 149 * was done. 150 */ 151 #define CFC_REG_AC_INIT_DONE 0x104078 152 /* [R 1] indication the initializing the cams by the hardware was done. */ 153 #define CFC_REG_CAM_INIT_DONE 0x10407c 154 /* [RW 2] Interrupt mask register #0 read/write */ 155 #define CFC_REG_CFC_INT_MASK 0x104108 156 /* [R 2] Interrupt register #0 read */ 157 #define CFC_REG_CFC_INT_STS 0x1040fc 158 /* [RC 2] Interrupt register #0 read clear */ 159 #define CFC_REG_CFC_INT_STS_CLR 0x104100 160 /* [RW 6] Parity mask register #0 read/write */ 161 #define CFC_REG_CFC_PRTY_MASK 0x104118 162 /* [R 6] Parity register #0 read */ 163 #define CFC_REG_CFC_PRTY_STS 0x10410c 164 /* [RC 6] Parity register #0 read clear */ 165 #define CFC_REG_CFC_PRTY_STS_CLR 0x104110 166 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */ 167 #define CFC_REG_CID_CAM 0x104800 168 #define CFC_REG_DEBUG0 0x104050 169 /* [R 16] CFC error vector. when the CFC detects an internal error it will 170 * set one of these bits. the bit description can be found in CFC 171 * specifications 172 */ 173 #define CFC_REG_ERROR_VECTOR 0x10403c 174 /* [WB 97] LCID info ram access = {96-vpf; 5:93-pfid; 2:89-type; 175 * 8:85-action; 4-paddrv; 3:20-paddr; 9:4-rstates; -lsf; :0-lstate} 176 */ 177 #define CFC_REG_INFO_RAM 0x105000 178 #define CFC_REG_INFO_RAM_SIZE 1024 179 #define CFC_REG_INIT_REG 0x10404c 180 /* [RW 22] Link List ram access; data = {prev_pfid; rev_lcid; ext_pfid; 181 * ext_lcid} 182 */ 183 #define CFC_REG_LINK_LIST 0x104c00 184 #define CFC_REG_LINK_LIST_SIZE 256 185 /* [R 1] indication the initializing the link list by the hardware was done. */ 186 #define CFC_REG_LL_INIT_DONE 0x104074 187 /* [R 9] Number of allocated LCIDs which are at empty state */ 188 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020 189 /* [R 9] Number of Arriving LCIDs in Link List Block */ 190 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004 191 #define CFC_REG_NUM_LCIDS_INSIDE_PF 0x104120 192 /* [R 9] Number of Leaving LCIDs in Link List Block */ 193 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018 194 #define CFC_REG_STRONG_ENABLE_PF 0x104128 195 #define CFC_REG_WEAK_ENABLE_PF 0x104124 196 /* [RW 32] Interrupt mask register #0 read/write */ 197 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c 198 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac 199 /* [R 32] Interrupt register #0 read */ 200 #define CSDM_REG_CSDM_INT_STS_0 0xc2290 201 #define CSDM_REG_CSDM_INT_STS_1 0xc22a0 202 /* [RC 32] Interrupt register #0 read clear */ 203 #define CSDM_REG_CSDM_INT_STS_CLR_0 0xc2294 204 #define CSDM_REG_CSDM_INT_STS_CLR_1 0xc22a4 205 /* [RW 11] Parity mask register #0 read/write */ 206 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc 207 /* [R 11] Parity register #0 read */ 208 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0 209 /* [RC 11] Parity register #0 read clear */ 210 #define CSDM_REG_CSDM_PRTY_STS_CLR 0xc22b4 211 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 212 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548 213 /* [R 1] parser fifo empty in sdm_sync block */ 214 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550 215 /* [R 1] parser serial fifo empty in sdm_sync block */ 216 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558 217 /* [RW 32] Interrupt mask register #0 read/write */ 218 #define CSEM_REG_CSEM_INT_MASK_0 0x200110 219 #define CSEM_REG_CSEM_INT_MASK_1 0x200120 220 /* [R 32] Interrupt register #0 read */ 221 #define CSEM_REG_CSEM_INT_STS_0 0x200104 222 #define CSEM_REG_CSEM_INT_STS_1 0x200114 223 /* [RC 32] Interrupt register #0 read clear */ 224 #define CSEM_REG_CSEM_INT_STS_CLR_0 0x200108 225 #define CSEM_REG_CSEM_INT_STS_CLR_1 0x200118 226 /* [RW 32] Parity mask register #0 read/write */ 227 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130 228 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140 229 /* [R 32] Parity register #0 read */ 230 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124 231 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134 232 /* [RC 32] Parity register #0 read clear */ 233 #define CSEM_REG_CSEM_PRTY_STS_CLR_0 0x200128 234 #define CSEM_REG_CSEM_PRTY_STS_CLR_1 0x200138 235 /* [RW 32] This address space contains all registers and memories that are 236 * placed in SEM_FAST block. The SEM_FAST registers are described in 237 * appendix B. In order to access the SEM_FAST registers the base address 238 * CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each 239 * SEM_FAST register offset. 240 */ 241 #define CSEM_REG_FAST_MEMORY 0x220000 242 /* [RW 15] Interrupt table Read and write access to it is not possible in 243 * the middle of the work 244 */ 245 #define CSEM_REG_INT_TABLE 0x200400 246 /* [WB 128] Debug only. Passive buffer memory */ 247 #define CSEM_REG_PASSIVE_BUFFER 0x202000 248 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 249 #define CSEM_REG_PRAM 0x240000 250 /* [R 20] Valid sleeping threads indication have bit per thread */ 251 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c 252 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 253 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0 254 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 255 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. 256 */ 257 #define CSEM_REG_VFPF_ERR_NUM 0x200380 258 /* [RW 2] Interrupt mask register #0 read/write */ 259 #define DBG_REG_DBG_INT_MASK 0xc098 260 /* [R 2] Interrupt register #0 read */ 261 #define DBG_REG_DBG_INT_STS 0xc08c 262 /* [RC 2] Interrupt register #0 read clear */ 263 #define DBG_REG_DBG_INT_STS_CLR 0xc090 264 /* [RW 1] Parity mask register #0 read/write */ 265 #define DBG_REG_DBG_PRTY_MASK 0xc0a8 266 /* [R 1] Parity register #0 read */ 267 #define DBG_REG_DBG_PRTY_STS 0xc09c 268 /* [RC 1] Parity register #0 read clear */ 269 #define DBG_REG_DBG_PRTY_STS_CLR 0xc0a0 270 /* [RW 1] When set the DMAE will process the commands as in E1.5. 1.The 271 * function that is used is always SRC-PCI; 2.VF_Valid = 0; 3.VFID = 0; 272 * 4.Completion function=0; 5.Error handling = 0 273 */ 274 #define DMAE_REG_BACKWARD_COMP_EN 0x10207c 275 /* [RW 32] Commands memory. The address to command X; row Y is to calculated 276 * as 14 * X+Y. 277 */ 278 #define DMAE_REG_CMD_MEM 0x102400 279 #define DMAE_REG_CMD_MEM_SIZE 224 280 /* [RW 2] Interrupt mask register #0 read/write */ 281 #define DMAE_REG_DMAE_INT_MASK 0x102054 282 /* [R 2] Interrupt register #0 read */ 283 #define DMAE_REG_DMAE_INT_STS 0x102048 284 /* [RC 2] Interrupt register #0 read clear */ 285 #define DMAE_REG_DMAE_INT_STS_CLR 0x10204c 286 /* [RW 4] Parity mask register #0 read/write */ 287 #define DMAE_REG_DMAE_PRTY_MASK 0x102064 288 /* [R 4] Parity register #0 read */ 289 #define DMAE_REG_DMAE_PRTY_STS 0x102058 290 /* [RC 4] Parity register #0 read clear */ 291 #define DMAE_REG_DMAE_PRTY_STS_CLR 0x10205c 292 /* [RW 1] Command 0 go. */ 293 #define DMAE_REG_GO_C0 0x102080 294 /* [RW 1] Command 1 go. */ 295 #define DMAE_REG_GO_C1 0x102084 296 /* [RW 1] Command 10 go. */ 297 #define DMAE_REG_GO_C10 0x102088 298 /* [RW 1] Command 11 go. */ 299 #define DMAE_REG_GO_C11 0x10208c 300 /* [RW 1] Command 12 go. */ 301 #define DMAE_REG_GO_C12 0x102090 302 /* [RW 1] Command 13 go. */ 303 #define DMAE_REG_GO_C13 0x102094 304 /* [RW 1] Command 14 go. */ 305 #define DMAE_REG_GO_C14 0x102098 306 /* [RW 1] Command 15 go. */ 307 #define DMAE_REG_GO_C15 0x10209c 308 /* [RW 1] Command 2 go. */ 309 #define DMAE_REG_GO_C2 0x1020a0 310 /* [RW 1] Command 3 go. */ 311 #define DMAE_REG_GO_C3 0x1020a4 312 /* [RW 1] Command 4 go. */ 313 #define DMAE_REG_GO_C4 0x1020a8 314 /* [RW 1] Command 5 go. */ 315 #define DMAE_REG_GO_C5 0x1020ac 316 /* [RW 1] Command 6 go. */ 317 #define DMAE_REG_GO_C6 0x1020b0 318 /* [RW 1] Command 7 go. */ 319 #define DMAE_REG_GO_C7 0x1020b4 320 /* [RW 1] Command 8 go. */ 321 #define DMAE_REG_GO_C8 0x1020b8 322 /* [RW 1] Command 9 go. */ 323 #define DMAE_REG_GO_C9 0x1020bc 324 /* [RW 32] Doorbell address for RBC doorbells (function 0). */ 325 #define DORQ_REG_DB_ADDR0 0x17008c 326 /* [RW 6] Interrupt mask register #0 read/write */ 327 #define DORQ_REG_DORQ_INT_MASK 0x170180 328 /* [R 6] Interrupt register #0 read */ 329 #define DORQ_REG_DORQ_INT_STS 0x170174 330 /* [RC 6] Interrupt register #0 read clear */ 331 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178 332 /* [RW 2] Parity mask register #0 read/write */ 333 #define DORQ_REG_DORQ_PRTY_MASK 0x170190 334 /* [R 2] Parity register #0 read */ 335 #define DORQ_REG_DORQ_PRTY_STS 0x170184 336 /* [RC 2] Parity register #0 read clear */ 337 #define DORQ_REG_DORQ_PRTY_STS_CLR 0x170188 338 /* [R 13] Current value of the DQ FIFO fill level according to following 339 * pointer. The range is 0 - 256 FIFO rows; where each row stands for the 340 * doorbell. 341 */ 342 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4 343 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or 344 * equal to full threshold; reset on full clear. 345 */ 346 #define DORQ_REG_DQ_FULL_ST 0x1700c0 347 #define DORQ_REG_MAX_RVFID_SIZE 0x1701ec 348 #define DORQ_REG_MODE_ACT 0x170008 349 /* [RW 5] The normal mode CID extraction offset. */ 350 #define DORQ_REG_NORM_CID_OFST 0x17002c 351 #define DORQ_REG_PF_USAGE_CNT 0x1701d0 352 /* [R 4] Current value of response A counter credit. Initial credit is 353 * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 354 * register. 355 */ 356 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac 357 /* [R 4] Current value of response B counter credit. Initial credit is 358 * configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd 359 * register. 360 */ 361 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0 362 #define DORQ_REG_VF_NORM_CID_BASE 0x1701a0 363 #define DORQ_REG_VF_NORM_CID_OFST 0x1701f4 364 #define DORQ_REG_VF_NORM_CID_WND_SIZE 0x1701a4 365 #define DORQ_REG_VF_NORM_VF_BASE 0x1701a8 366 /* [RW 10] VF type validation mask value */ 367 #define DORQ_REG_VF_TYPE_MASK_0 0x170218 368 /* [RW 17] VF type validation Min MCID value */ 369 #define DORQ_REG_VF_TYPE_MAX_MCID_0 0x1702d8 370 /* [RW 17] VF type validation Max MCID value */ 371 #define DORQ_REG_VF_TYPE_MIN_MCID_0 0x170298 372 /* [RW 10] VF type validation comp value */ 373 #define DORQ_REG_VF_TYPE_VALUE_0 0x170258 374 #define DORQ_REG_VF_USAGE_CNT 0x170320 375 #define DORQ_REG_VF_USAGE_CT_LIMIT 0x170340 376 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1 << 4) 377 #define HC_CONFIG_0_REG_BLOCK_DISABLE_0 (0x1 << 0) 378 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1 << 3) 379 #define HC_CONFIG_0_REG_MSI_ATTN_EN_0 (0x1 << 7) 380 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1 << 2) 381 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1 << 1) 382 #define HC_CONFIG_1_REG_BLOCK_DISABLE_1 (0x1 << 0) 383 #define HC_REG_AGG_INT_0 0x108050 384 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018 385 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020 386 #define HC_REG_COMMAND_REG 0x108180 387 #define HC_REG_CONFIG_0 0x108000 388 #define HC_REG_CONFIG_1 0x108004 389 /* [RW 7] Interrupt mask register #0 read/write */ 390 #define HC_REG_HC_INT_MASK 0x108090 391 /* [R 7] Interrupt register #0 read */ 392 #define HC_REG_HC_INT_STS 0x108084 393 /* [RC 7] Interrupt register #0 read clear */ 394 #define HC_REG_HC_INT_STS_CLR 0x108088 395 /* [RW 3] Parity mask register #0 read/write */ 396 #define HC_REG_HC_PRTY_MASK 0x1080a0 397 /* [R 3] Parity register #0 read */ 398 #define HC_REG_HC_PRTY_STS 0x108094 399 /* [RC 3] Parity register #0 read clear */ 400 #define HC_REG_HC_PRTY_STS_CLR 0x108098 401 #define HC_REG_INT_MASK 0x108108 402 #define HC_REG_LEADING_EDGE_0 0x108040 403 #define HC_REG_MAIN_MEMORY 0x108800 404 #define HC_REG_MAIN_MEMORY_SIZE 152 405 #define HC_REG_TRAILING_EDGE_0 0x108044 406 #define IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN (0x1 << 1) 407 #define IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE (0x1 << 0) 408 #define IGU_REG_ATTENTION_ACK_BITS 0x130108 409 /* [R 4] Debug: attn_fsm */ 410 #define IGU_REG_ATTN_FSM 0x130054 411 #define IGU_REG_ATTN_MSG_ADDR_H 0x13011c 412 #define IGU_REG_ATTN_MSG_ADDR_L 0x130120 413 /* [R 4] Debug: [3] - attention write done message is pending (0-no pending; 414 * 1-pending). [2:0] = PFID. Pending means attention message was sent; but 415 * write done didn't receive. 416 */ 417 #define IGU_REG_ATTN_WRITE_DONE_PENDING 0x130030 418 #define IGU_REG_BLOCK_CONFIGURATION 0x130000 419 #define IGU_REG_COMMAND_REG_32LSB_DATA 0x130124 420 #define IGU_REG_COMMAND_REG_CTRL 0x13012c 421 /* [WB_R 32] Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit 422 * is clear. The bits in this registers are set and clear via the producer 423 * command. Data valid only in addresses 0-4. all the rest are zero. 424 */ 425 #define IGU_REG_CSTORM_TYPE_0_SB_CLEANUP 0x130200 426 /* [R 5] Debug: ctrl_fsm */ 427 #define IGU_REG_CTRL_FSM 0x130064 428 /* [R 1] data available for error memory. If this bit is clear do not red 429 * from error_handling_memory. 430 */ 431 #define IGU_REG_ERROR_HANDLING_DATA_VALID 0x130130 432 /* [RW 11] Interrupt mask register #0 read/write */ 433 #define IGU_REG_IGU_INT_MASK 0x130098 434 /* [R 11] Interrupt register #0 read */ 435 #define IGU_REG_IGU_INT_STS 0x13008c 436 /* [RC 11] Interrupt register #0 read clear */ 437 #define IGU_REG_IGU_INT_STS_CLR 0x130090 438 /* [RW 11] Parity mask register #0 read/write */ 439 #define IGU_REG_IGU_PRTY_MASK 0x1300a8 440 /* [R 11] Parity register #0 read */ 441 #define IGU_REG_IGU_PRTY_STS 0x13009c 442 /* [RC 11] Parity register #0 read clear */ 443 #define IGU_REG_IGU_PRTY_STS_CLR 0x1300a0 444 /* [R 4] Debug: int_handle_fsm */ 445 #define IGU_REG_INT_HANDLE_FSM 0x130050 446 #define IGU_REG_LEADING_EDGE_LATCH 0x130134 447 /* [RW 14] mapping CAM; relevant for E2 operating mode only. [0] - valid. 448 * [6:1] - vector number; [13:7] - FID (if VF - [13] = 0; [12:7] = VF 449 * number; if PF - [13] = 1; [12:10] = 0; [9:7] = PF number); 450 */ 451 #define IGU_REG_MAPPING_MEMORY 0x131000 452 #define IGU_REG_MAPPING_MEMORY_SIZE 136 453 #define IGU_REG_PBA_STATUS_LSB 0x130138 454 #define IGU_REG_PBA_STATUS_MSB 0x13013c 455 #define IGU_REG_PCI_PF_MSIX_EN 0x130144 456 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK 0x130148 457 #define IGU_REG_PCI_PF_MSI_EN 0x130140 458 /* [WB_R 32] Each bit represent the pending bits status for that SB. 0 = no 459 * pending; 1 = pending. Pendings means interrupt was asserted; and write 460 * done was not received. Data valid only in addresses 0-4. all the rest are 461 * zero. 462 */ 463 #define IGU_REG_PENDING_BITS_STATUS 0x130300 464 #define IGU_REG_PF_CONFIGURATION 0x130154 465 /* [RW 20] producers only. E2 mode: address 0-135 match to the mapping 466 * memory; 136 - PF0 default prod; 137 PF1 default prod; 138 - PF2 default 467 * prod; 139 PF3 default prod; 140 - PF0 - ATTN prod; 141 - PF1 - ATTN prod; 468 * 142 - PF2 - ATTN prod; 143 - PF3 - ATTN prod; 144-147 reserved. E1.5 mode 469 * - In backward compatible mode; for non default SB; each even line in the 470 * memory holds the U producer and each odd line hold the C producer. The 471 * first 128 producer are for NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The 472 * last 20 producers are for the DSB for each PF. each PF has five segments 473 * (the order inside each segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 474 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 144-147 ATTN prods; 475 */ 476 #define IGU_REG_PROD_CONS_MEMORY 0x132000 477 /* [R 3] Debug: pxp_arb_fsm */ 478 #define IGU_REG_PXP_ARB_FSM 0x130068 479 /* [RW 6] Write one for each bit will reset the appropriate memory. When the 480 * memory reset finished the appropriate bit will be clear. Bit 0 - mapping 481 * memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 482 * - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics; 483 */ 484 #define IGU_REG_RESET_MEMORIES 0x130158 485 /* [R 4] Debug: sb_ctrl_fsm */ 486 #define IGU_REG_SB_CTRL_FSM 0x13004c 487 #define IGU_REG_SB_INT_BEFORE_MASK_LSB 0x13015c 488 #define IGU_REG_SB_INT_BEFORE_MASK_MSB 0x130160 489 #define IGU_REG_SB_MASK_LSB 0x130164 490 #define IGU_REG_SB_MASK_MSB 0x130168 491 /* [RW 16] Number of command that were dropped without causing an interrupt 492 * due to: read access for WO BAR address; or write access for RO BAR 493 * address or any access for reserved address or PCI function error is set 494 * and address is not MSIX; PBA or cleanup 495 */ 496 #define IGU_REG_SILENT_DROP 0x13016c 497 /* [RW 10] Number of MSI/MSIX/ATTN messages sent for the function: 0-63 - 498 * number of MSIX messages per VF; 64-67 - number of MSI/MSIX messages per 499 * PF; 68-71 number of ATTN messages per PF 500 */ 501 #define IGU_REG_STATISTIC_NUM_MESSAGE_SENT 0x130800 502 #define IGU_REG_TRAILING_EDGE_LATCH 0x130104 503 #define IGU_REG_VF_CONFIGURATION 0x130170 504 /* [WB_R 32] Each bit represent write done pending bits status for that SB 505 * (MSI/MSIX message was sent and write done was not received yet). 0 = 506 * clear; 1 = set. Data valid only in addresses 0-4. all the rest are zero. 507 */ 508 #define IGU_REG_WRITE_DONE_PENDING 0x130480 509 #define MCP_A_REG_MCPR_SCRATCH 0x3a0000 510 #define MCP_REG_MCPR_ACCESS_LOCK 0x8009c 511 #define MCP_REG_MCPR_CPU_PROGRAM_COUNTER 0x8501c 512 #define MCP_REG_MCPR_GP_INPUTS 0x800c0 513 #define MCP_REG_MCPR_GP_OENABLE 0x800c8 514 #define MCP_REG_MCPR_GP_OUTPUTS 0x800c4 515 #define MCP_REG_MCPR_IMC_COMMAND 0x85900 516 #define MCP_REG_MCPR_IMC_DATAREG0 0x85920 517 #define MCP_REG_MCPR_IMC_SLAVE_CONTROL 0x85904 518 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424 519 #define MCP_REG_MCPR_NVM_ADDR 0x8640c 520 #define MCP_REG_MCPR_NVM_CFG4 0x8642c 521 #define MCP_REG_MCPR_NVM_COMMAND 0x86400 522 #define MCP_REG_MCPR_NVM_READ 0x86410 523 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420 524 #define MCP_REG_MCPR_NVM_WRITE 0x86408 525 #define MCP_REG_MCPR_SCRATCH 0xa0000 526 #define MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK (0x1 << 1) 527 #define MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK (0x1 << 0) 528 /* [R 32] read first 32 bit after inversion of function 0. mapped as 529 * follows: [0] NIG attention for function0; [1] NIG attention for 530 * function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; 531 * [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] 532 * GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE 533 * glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; 534 * [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] 535 * MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB 536 * Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw 537 * interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity 538 * error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw 539 * interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] 540 * PBClient Parity error; [31] PBClient Hw interrupt; 541 */ 542 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c 543 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430 544 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0] 545 * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 546 * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 547 * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 548 * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 549 * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 550 * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 551 * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 552 * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 553 * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 554 * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 555 * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] 556 * PBClient Hw interrupt; 557 */ 558 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434 559 /* [R 32] read second 32 bit after inversion of function 0. mapped as 560 * follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; 561 * [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; 562 * [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] 563 * XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 564 * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 565 * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 566 * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 567 * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 568 * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 569 * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 570 * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; 571 */ 572 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438 573 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c 574 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0] 575 * PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw 576 * interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM 577 * Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw 578 * interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] 579 * DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity 580 * error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux 581 * PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; 582 * [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; 583 * [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt; 584 * [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error; 585 * [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; 586 */ 587 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440 588 /* [R 32] read third 32 bit after inversion of function 0. mapped as 589 * follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity 590 * error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] 591 * PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw 592 * interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity 593 * error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) 594 * Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] 595 * pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] 596 * MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] 597 * SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW 598 * timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 599 * func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General 600 * attn1; 601 */ 602 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444 603 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448 604 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0] 605 * CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP 606 * Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient 607 * Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity 608 * error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw 609 * interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] 610 * MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] 611 * Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW 612 * timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 613 * func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1 614 * func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW 615 * timers attn_4 func1; [30] General attn0; [31] General attn1; 616 */ 617 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c 618 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as 619 * follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 620 * General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 621 * [7] General attn9; [8] General attn10; [9] General attn11; [10] General 622 * attn12; [11] General attn13; [12] General attn14; [13] General attn15; 623 * [14] General attn16; [15] General attn17; [16] General attn18; [17] 624 * General attn19; [18] General attn20; [19] General attn21; [20] Main power 625 * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 626 * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 627 * Latched timeout attention; [27] GRC Latched reserved access attention; 628 * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 629 * Latched ump_tx_parity; [31] MCP Latched scpad_parity; 630 */ 631 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450 632 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454 633 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0] 634 * General attn2; [1] General attn3; [2] General attn4; [3] General attn5; 635 * [4] General attn6; [5] General attn7; [6] General attn8; [7] General 636 * attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11] 637 * General attn13; [12] General attn14; [13] General attn15; [14] General 638 * attn16; [15] General attn17; [16] General attn18; [17] General attn19; 639 * [18] General attn20; [19] General attn21; [20] Main power interrupt; [21] 640 * RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24] 641 * RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout 642 * attention; [27] GRC Latched reserved access attention; [28] MCP Latched 643 * rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched 644 * ump_tx_parity; [31] MCP Latched scpad_parity; 645 */ 646 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458 647 /* [R 32] Read fifth 32 bit after inversion of function 0. Mapped as 648 * follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 649 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 650 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 651 * parity; [31-10] Reserved; 652 */ 653 #define MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 0xa700 654 /* [W 14] write to this register results with the clear of the latched 655 * signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in 656 * d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP 657 * latch; one in d5 clears GRC Latched timeout attention; one in d6 clears 658 * GRC Latched reserved access attention; one in d7 clears Latched 659 * rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears 660 * Latched ump_tx_parity; one in d10 clears Latched scpad_parity (both 661 * ports); one in d11 clears pxpv_misc_mps_attn; one in d12 clears 662 * pxp_misc_exp_rom_attn0; one in d13 clears pxp_misc_exp_rom_attn1; read 663 * from this register return zero 664 */ 665 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c 666 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped 667 * as follows: [0] NIG attention for function0; [1] NIG attention for 668 * function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function 669 * 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 670 * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 671 * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 672 * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 673 * SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X 674 * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 675 * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 676 * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 677 * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 678 * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw 679 * interrupt; 680 */ 681 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c 682 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c 683 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2 0xa08c 684 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped 685 * as follows: [0] NIG attention for function0; [1] NIG attention for 686 * function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function 687 * 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] 688 * GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event 689 * function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP 690 * Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] 691 * SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X 692 * indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; 693 * [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] 694 * SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] 695 * TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] 696 * TSEMI Hw interrupt; [30] PBClient Parity error; [31] PBClient Hw 697 * interrupt; 698 */ 699 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c 700 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c 701 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 0xa12c 702 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped 703 * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 704 * General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 705 * [7] General attn9; [8] General attn10; [9] General attn11; [10] General 706 * attn12; [11] General attn13; [12] General attn14; [13] General attn15; 707 * [14] General attn16; [15] General attn17; [16] General attn18; [17] 708 * General attn19; [18] General attn20; [19] General attn21; [20] Main power 709 * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 710 * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 711 * Latched timeout attention; [27] GRC Latched reserved access attention; 712 * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 713 * Latched ump_tx_parity; [31] MCP Latched scpad_parity; 714 */ 715 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078 716 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped 717 * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 718 * General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 719 * [7] General attn9; [8] General attn10; [9] General attn11; [10] General 720 * attn12; [11] General attn13; [12] General attn14; [13] General attn15; 721 * [14] General attn16; [15] General attn17; [16] General attn18; [17] 722 * General attn19; [18] General attn20; [19] General attn21; [20] Main power 723 * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 724 * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 725 * Latched timeout attention; [27] GRC Latched reserved access attention; 726 * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 727 * Latched ump_tx_parity; [31] MCP Latched scpad_parity; 728 */ 729 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118 730 /* [RW 32] fourth 32b for enabling the output for close the gate nig. Mapped 731 * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 732 * General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 733 * [7] General attn9; [8] General attn10; [9] General attn11; [10] General 734 * attn12; [11] General attn13; [12] General attn14; [13] General attn15; 735 * [14] General attn16; [15] General attn17; [16] General attn18; [17] 736 * General attn19; [18] General attn20; [19] General attn21; [20] Main power 737 * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 738 * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 739 * Latched timeout attention; [27] GRC Latched reserved access attention; 740 * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 741 * Latched ump_tx_parity; [31] MCP Latched scpad_parity; 742 */ 743 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8 744 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198 745 /* [RW 32] fourth 32b for enabling the output for close the gate pxp. Mapped 746 * as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3] 747 * General attn5; [4] General attn6; [5] General attn7; [6] General attn8; 748 * [7] General attn9; [8] General attn10; [9] General attn11; [10] General 749 * attn12; [11] General attn13; [12] General attn14; [13] General attn15; 750 * [14] General attn16; [15] General attn17; [16] General attn18; [17] 751 * General attn19; [18] General attn20; [19] General attn21; [20] Main power 752 * interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN 753 * Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC 754 * Latched timeout attention; [27] GRC Latched reserved access attention; 755 * [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP 756 * Latched ump_tx_parity; [31] MCP Latched scpad_parity; 757 */ 758 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108 759 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8 760 /* [RW 32] fifth 32b for enabling the output for function 0 output0. Mapped 761 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 762 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 763 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 764 * parity; [31-10] Reserved; 765 */ 766 #define MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0 0xa688 767 /* [RW 32] Fifth 32b for enabling the output for function 1 output0. Mapped 768 * as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC 769 * attention [3] PGLUE B RBC parity; [4] ATC attention; [5] ATC parity; [6] 770 * mstat0 attention; [7] mstat0 parity; [8] mstat1 attention; [9] mstat1 771 * parity; [31-10] Reserved; 772 */ 773 #define MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 0xa6b0 774 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu 775 * 128 bit vector 776 */ 777 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000 778 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004 779 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028 780 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c 781 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030 782 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008 783 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c 784 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010 785 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014 786 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018 787 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c 788 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020 789 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024 790 #define MISC_REG_AEU_GENERAL_MASK 0xa61c 791 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0; 792 * [9:8] = reserved. 0 = mask; 1 = unmask 793 */ 794 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060 795 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064 796 /* [RW 1] If set a system kill occurred. Reset on POR reset. */ 797 #define MISC_REG_AEU_SYS_KILL_OCCURRED 0xa610 798 /* [RW 32] Represent the status of the input vector to the AEU when a system 799 * kill occurred. The register is reset in por reset. Mapped as follows: [0] 800 * NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 801 * mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; 802 * [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] 803 * PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event 804 * function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP 805 * Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for 806 * mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] 807 * BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC 808 * Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw 809 * interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI 810 * Parity error; [29] TSEMI Hw interrupt; [30] PBClient Parity error; [31] 811 * PBClient Hw interrupt. Reset on POR reset. 812 */ 813 #define MISC_REG_AEU_SYS_KILL_STATUS_0 0xa600 814 #define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604 815 #define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608 816 #define MISC_REG_AEU_SYS_KILL_STATUS_3 0xa60c 817 /* [R 32] This field indicates the type of the device. '0' - 2 Ports; '1' - 818 * 1 Port. Global register. 819 */ 820 #define MISC_REG_BOND_ID 0xa400 821 /* [R 16] These bits indicate the part number for the chip. Global register. */ 822 #define MISC_REG_CHIP_NUM 0xa408 823 /* [R 4] These bits indicate the base revision of the chip. This value 824 * starts at 0x0 for the A0 tape-out and increments by one for each 825 * all-layer tape-out. Global register. 826 */ 827 #define MISC_REG_CHIP_REV 0xa40c 828 /* [R 14] otp_misc_do[100:0] spare bits collection: 13:11- 829 * otp_misc_do[100:98]; 10:7 - otp_misc_do[87:84]; 6:3 - otp_misc_do[75:72]; 830 * 2:1 - otp_misc_do[51:50]; 0 - otp_misc_do[1]. 831 */ 832 #define MISC_REG_CHIP_TYPE 0xac60 833 #define MISC_REG_CHIP_TYPE_57811_MASK (1 << 1) 834 #define MISC_REG_CPMU_LP_DR_ENABLE 0xa858 835 /* [RW 1] FW EEE LPI Enable. When 1 indicates that EEE LPI mode is enabled 836 * by FW. When 0 indicates that the EEE LPI mode is disabled by FW. Clk 837 * 25MHz. Reset on hard reset. 838 */ 839 #define MISC_REG_CPMU_LP_FW_ENABLE_P0 0xa84c 840 /* [RW 32] EEE LPI Idle Threshold. The threshold value for the idle EEE LPI 841 * counter. Timer tick is 1 us. Clock 25MHz. Reset on hard reset. 842 */ 843 #define MISC_REG_CPMU_LP_IDLE_THR_P0 0xa8a0 844 /* [RW 18] LPI entry events mask. [0] - Vmain SM Mask. When 1 indicates that 845 * the Vmain SM end state is disabled. When 0 indicates that the Vmain SM 846 * end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates that 847 * the FW command that all Queues are empty is disabled. When 0 indicates 848 * that the FW command that all Queues are empty is enabled. [2] - FW Early 849 * Exit Mask / Reserved (Entry mask). When 1 indicates that the FW Early 850 * Exit command is disabled. When 0 indicates that the FW Early Exit command 851 * is enabled. This bit applicable only in the EXIT Events Mask registers. 852 * [3] - PBF Request Mask. When 1 indicates that the PBF Request indication 853 * is disabled. When 0 indicates that the PBF Request indication is enabled. 854 * [4] - Tx Request Mask. When =1 indicates that the Tx other Than PBF 855 * Request indication is disabled. When 0 indicates that the Tx Other Than 856 * PBF Request indication is enabled. [5] - Rx EEE LPI Status Mask. When 1 857 * indicates that the RX EEE LPI Status indication is disabled. When 0 858 * indicates that the RX EEE LPI Status indication is enabled. In the EXIT 859 * Events Masks registers; this bit masks the falling edge detect of the LPI 860 * Status (Rx LPI is on - off). [6] - Tx Pause Mask. When 1 indicates that 861 * the Tx Pause indication is disabled. When 0 indicates that the Tx Pause 862 * indication is enabled. [7] - BRB1 Empty Mask. When 1 indicates that the 863 * BRB1 EMPTY indication is disabled. When 0 indicates that the BRB1 EMPTY 864 * indication is enabled. [8] - QM Idle Mask. When 1 indicates that the QM 865 * IDLE indication is disabled. When 0 indicates that the QM IDLE indication 866 * is enabled. (One bit for both VOQ0 and VOQ1). [9] - QM LB Idle Mask. When 867 * 1 indicates that the QM IDLE indication for LOOPBACK is disabled. When 0 868 * indicates that the QM IDLE indication for LOOPBACK is enabled. [10] - L1 869 * Status Mask. When 1 indicates that the L1 Status indication from the PCIE 870 * CORE is disabled. When 0 indicates that the RX EEE LPI Status indication 871 * from the PCIE CORE is enabled. In the EXIT Events Masks registers; this 872 * bit masks the falling edge detect of the L1 status (L1 is on - off). [11] 873 * - P0 E0 EEE EEE LPI REQ Mask. When =1 indicates that the P0 E0 EEE EEE 874 * LPI REQ indication is disabled. When =0 indicates that the P0 E0 EEE LPI 875 * REQ indication is enabled. [12] - P1 E0 EEE LPI REQ Mask. When =1 876 * indicates that the P0 EEE LPI REQ indication is disabled. When =0 877 * indicates that the P0 EEE LPI REQ indication is enabled. [13] - P0 E1 EEE 878 * LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication is 879 * disabled. When =0 indicates that the P0 EEE LPI REQ indication is 880 * enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE 881 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ 882 * indication is enabled. [15] - L1 REQ Mask. When =1 indicates that the L1 883 * REQ indication is disabled. When =0 indicates that the L1 indication is 884 * enabled. [16] - Rx EEE LPI Status Edge Detect Mask. When =1 indicates 885 * that the RX EEE LPI Status Falling Edge Detect indication is disabled (Rx 886 * EEE LPI is on - off). When =0 indicates that the RX EEE LPI Status 887 * Falling Edge Detec indication is enabled (Rx EEE LPI is on - off). This 888 * bit is applicable only in the EXIT Events Masks registers. [17] - L1 889 * Status Edge Detect Mask. When =1 indicates that the L1 Status Falling 890 * Edge Detect indication from the PCIE CORE is disabled (L1 is on - off). 891 * When =0 indicates that the L1 Status Falling Edge Detect indication from 892 * the PCIE CORE is enabled (L1 is on - off). This bit is applicable only in 893 * the EXIT Events Masks registers. Clock 25MHz. Reset on hard reset. 894 */ 895 #define MISC_REG_CPMU_LP_MASK_ENT_P0 0xa880 896 /* [RW 18] EEE LPI exit events mask. [0] - Vmain SM Mask. When 1 indicates 897 * that the Vmain SM end state is disabled. When 0 indicates that the Vmain 898 * SM end state is enabled. [1] - FW Queues Empty Mask. When 1 indicates 899 * that the FW command that all Queues are empty is disabled. When 0 900 * indicates that the FW command that all Queues are empty is enabled. [2] - 901 * FW Early Exit Mask / Reserved (Entry mask). When 1 indicates that the FW 902 * Early Exit command is disabled. When 0 indicates that the FW Early Exit 903 * command is enabled. This bit applicable only in the EXIT Events Mask 904 * registers. [3] - PBF Request Mask. When 1 indicates that the PBF Request 905 * indication is disabled. When 0 indicates that the PBF Request indication 906 * is enabled. [4] - Tx Request Mask. When =1 indicates that the Tx other 907 * Than PBF Request indication is disabled. When 0 indicates that the Tx 908 * Other Than PBF Request indication is enabled. [5] - Rx EEE LPI Status 909 * Mask. When 1 indicates that the RX EEE LPI Status indication is disabled. 910 * When 0 indicates that the RX LPI Status indication is enabled. In the 911 * EXIT Events Masks registers; this bit masks the falling edge detect of 912 * the EEE LPI Status (Rx EEE LPI is on - off). [6] - Tx Pause Mask. When 1 913 * indicates that the Tx Pause indication is disabled. When 0 indicates that 914 * the Tx Pause indication is enabled. [7] - BRB1 Empty Mask. When 1 915 * indicates that the BRB1 EMPTY indication is disabled. When 0 indicates 916 * that the BRB1 EMPTY indication is enabled. [8] - QM Idle Mask. When 1 917 * indicates that the QM IDLE indication is disabled. When 0 indicates that 918 * the QM IDLE indication is enabled. (One bit for both VOQ0 and VOQ1). [9] 919 * - QM LB Idle Mask. When 1 indicates that the QM IDLE indication for 920 * LOOPBACK is disabled. When 0 indicates that the QM IDLE indication for 921 * LOOPBACK is enabled. [10] - L1 Status Mask. When 1 indicates that the L1 922 * Status indication from the PCIE CORE is disabled. When 0 indicates that 923 * the RX EEE LPI Status indication from the PCIE CORE is enabled. In the 924 * EXIT Events Masks registers; this bit masks the falling edge detect of 925 * the L1 status (L1 is on - off). [11] - P0 E0 EEE EEE LPI REQ Mask. When 926 * =1 indicates that the P0 E0 EEE EEE LPI REQ indication is disabled. When 927 * =0 indicates that the P0 E0 EEE LPI REQ indication is enabled. [12] - P1 928 * E0 EEE LPI REQ Mask. When =1 indicates that the P0 EEE LPI REQ indication 929 * is disabled. When =0 indicates that the P0 EEE LPI REQ indication is 930 * enabled. [13] - P0 E1 EEE LPI REQ Mask. When =1 indicates that the P0 EEE 931 * LPI REQ indication is disabled. When =0 indicates that the P0 EEE LPI REQ 932 * indication is enabled. [14] - P1 E1 EEE LPI REQ Mask. When =1 indicates 933 * that the P0 EEE LPI REQ indication is disabled. When =0 indicates that 934 * the P0 EEE LPI REQ indication is enabled. [15] - L1 REQ Mask. When =1 935 * indicates that the L1 REQ indication is disabled. When =0 indicates that 936 * the L1 indication is enabled. [16] - Rx EEE LPI Status Edge Detect Mask. 937 * When =1 indicates that the RX EEE LPI Status Falling Edge Detect 938 * indication is disabled (Rx EEE LPI is on - off). When =0 indicates that 939 * the RX EEE LPI Status Falling Edge Detec indication is enabled (Rx EEE 940 * LPI is on - off). This bit is applicable only in the EXIT Events Masks 941 * registers. [17] - L1 Status Edge Detect Mask. When =1 indicates that the 942 * L1 Status Falling Edge Detect indication from the PCIE CORE is disabled 943 * (L1 is on - off). When =0 indicates that the L1 Status Falling Edge 944 * Detect indication from the PCIE CORE is enabled (L1 is on - off). This 945 * bit is applicable only in the EXIT Events Masks registers.Clock 25MHz. 946 * Reset on hard reset. 947 */ 948 #define MISC_REG_CPMU_LP_MASK_EXT_P0 0xa888 949 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number 950 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only 951 * register. Reset on hard reset. 952 */ 953 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P0 0xa8b8 954 /* [RW 16] EEE LPI Entry Events Counter. A statistic counter with the number 955 * of counts that the SM entered the EEE LPI state. Clock 25MHz. Read only 956 * register. Reset on hard reset. 957 */ 958 #define MISC_REG_CPMU_LP_SM_ENT_CNT_P1 0xa8bc 959 /* [RW 32] The following driver registers(1...16) represent 16 drivers and 960 * 32 clients. Each client can be controlled by one driver only. One in each 961 * bit represent that this driver control the appropriate client (Ex: bit 5 962 * is set means this driver control client number 5). addr1 = set; addr0 = 963 * clear; read from both addresses will give the same result = status. write 964 * to address 1 will set a request to control all the clients that their 965 * appropriate bit (in the write command) is set. if the client is free (the 966 * appropriate bit in all the other drivers is clear) one will be written to 967 * that driver register; if the client isn't free the bit will remain zero. 968 * if the appropriate bit is set (the driver request to gain control on a 969 * client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW 970 * interrupt will be asserted). write to address 0 will set a request to 971 * free all the clients that their appropriate bit (in the write command) is 972 * set. if the appropriate bit is clear (the driver request to free a client 973 * it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will 974 * be asserted). 975 */ 976 #define MISC_REG_DRIVER_CONTROL_1 0xa510 977 #define MISC_REG_DRIVER_CONTROL_7 0xa3c8 978 /* [R 1] Status of four port mode path swap input pin. */ 979 #define MISC_REG_FOUR_PORT_PATH_SWAP 0xa75c 980 /* [RW 2] 4 port path swap overwrite.[0] - Overwrite control; if it is 0 - 981 * the path_swap output is equal to 4 port mode path swap input pin; if it 982 * is 1 - the path_swap output is equal to bit[1] of this register; [1] - 983 * Overwrite value. If bit[0] of this register is 1 this is the value that 984 * receives the path_swap output. Reset on Hard reset. 985 */ 986 #define MISC_REG_FOUR_PORT_PATH_SWAP_OVWR 0xa738 987 /* [R 1] Status of 4 port mode port swap input pin. */ 988 #define MISC_REG_FOUR_PORT_PORT_SWAP 0xa754 989 /* [RW 2] 4 port port swap overwrite.[0] - Overwrite control; if it is 0 - 990 * the port_swap output is equal to 4 port mode port swap input pin; if it 991 * is 1 - the port_swap output is equal to bit[1] of this register; [1] - 992 * Overwrite value. If bit[0] of this register is 1 this is the value that 993 * receives the port_swap output. Reset on Hard reset. 994 */ 995 #define MISC_REG_FOUR_PORT_PORT_SWAP_OVWR 0xa734 996 /* [RW 32] Debug only: spare RW register reset by core reset. Global 997 * register. Reset on core reset. 998 */ 999 #define MISC_REG_GENERIC_CR_0 0xa460 1000 #define MISC_REG_GENERIC_CR_1 0xa464 1001 /* [RW 32] Debug only: spare RW register reset by por reset. Global 1002 * register. Reset on POR reset. 1003 */ 1004 #define MISC_REG_GENERIC_POR_1 0xa474 1005 /* [RW 32] Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to 1006 * use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO 1007 * can not be configured as an output. Each output has its output enable in 1008 * the MCP register space; but this bit needs to be set to make use of that. 1009 * Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When 1010 * set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. 1011 * When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change 1012 * the i/o to an output and will drive the TimeSync output. Bit[31:7]: 1013 * spare. Global register. Reset by hard reset. 1014 */ 1015 #define MISC_REG_GEN_PURP_HWG 0xa9a0 1016 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of 1017 * these bits is written as a '1'; the corresponding GPIO bit will turn off 1018 * it's drivers and become an input. This is the reset state of all GPIO 1019 * pins. The read value of these bits will be a '1' if that last command 1020 * (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff). 1021 * [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written 1022 * as a '1'; the corresponding GPIO bit will drive low. The read value of 1023 * these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for 1024 * this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0; 1025 * SET When any of these bits is written as a '1'; the corresponding GPIO 1026 * bit will drive high (if it has that capability). The read value of these 1027 * bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this 1028 * bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0; 1029 * RO; These bits indicate the read value of each of the eight GPIO pins. 1030 * This is the result value of the pin; not the drive value. Writing these 1031 * bits will have not effect. Global register. 1032 */ 1033 #define MISC_REG_GPIO 0xa490 1034 /* [RW 8] These bits enable the GPIO_INTs to signals event to the 1035 * IGU/MCP.according to the following map: [0] p0_gpio_0; [1] p0_gpio_1; [2] 1036 * p0_gpio_2; [3] p0_gpio_3; [4] p1_gpio_0; [5] p1_gpio_1; [6] p1_gpio_2; 1037 * [7] p1_gpio_3; Global register. 1038 */ 1039 #define MISC_REG_GPIO_EVENT_EN 0xa2bc 1040 /* [RW 32] GPIO INT. [31-28] OLD_CLR port1; [27-24] OLD_CLR port0; Writing a 1041 * '1' to these bit clears the corresponding bit in the #OLD_VALUE register. 1042 * This will acknowledge an interrupt on the falling edge of corresponding 1043 * GPIO input (reset value 0). [23-16] OLD_SET [23-16] port1; OLD_SET port0; 1044 * Writing a '1' to these bit sets the corresponding bit in the #OLD_VALUE 1045 * register. This will acknowledge an interrupt on the rising edge of 1046 * corresponding GPIO input (reset value 0). [15-12] OLD_VALUE [11-8] port1; 1047 * OLD_VALUE port0; RO; These bits indicate the old value of the GPIO input 1048 * value. When the ~INT_STATE bit is set; this bit indicates the OLD value 1049 * of the pin such that if ~INT_STATE is set and this bit is '0'; then the 1050 * interrupt is due to a low to high edge. If ~INT_STATE is set and this bit 1051 * is '1'; then the interrupt is due to a high to low edge (reset value 0). 1052 * [7-4] INT_STATE port1; [3-0] INT_STATE RO port0; These bits indicate the 1053 * current GPIO interrupt state for each GPIO pin. This bit is cleared when 1054 * the appropriate #OLD_SET or #OLD_CLR command bit is written. This bit is 1055 * set when the GPIO input does not match the current value in #OLD_VALUE 1056 * (reset value 0). Global register. 1057 */ 1058 #define MISC_REG_GPIO_INT 0xa494 1059 /* [R 28] this field hold the last information that caused reserved 1060 * attention. bits [19:0] - address; [22:20] function; [23] reserved; 1061 * [27:24] the master that caused the attention - according to the following 1062 * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1063 * dbu; 8 = dmae 1064 */ 1065 #define MISC_REG_GRC_RSV_ATTN 0xa3c0 1066 /* [R 28] this field hold the last information that caused timeout 1067 * attention. bits [19:0] - address; [22:20] function; [23] reserved; 1068 * [27:24] the master that caused the attention - according to the following 1069 * encodeing:1 = pxp; 2 = mcp; 3 = usdm; 4 = tsdm; 5 = xsdm; 6 = csdm; 7 = 1070 * dbu; 8 = dmae 1071 */ 1072 #define MISC_REG_GRC_TIMEOUT_ATTN 0xa3c4 1073 /* [R 10] Holds the last FID that caused timeout attention. Need to be used 1074 * in conjunction with ~misc_registers_timeout_attn; where 3 bits of 1075 * function (3 lsb) are also represented. Bit[2:0] - PFID; bit[3] - VFID 1076 * valid; bit[9:4] - VFID. Global register. 1077 */ 1078 #define MISC_REG_GRC_TIMEOUT_ATTN_FULL_FID 0xa714 1079 /* [RW 1] LCPLL power down. Global register. Active High. Reset on POR 1080 * reset. 1081 */ 1082 #define MISC_REG_LCPLL_E40_PWRDWN 0xaa74 1083 /* [RW 1] LCPLL VCO reset. Global register. Active Low Reset on POR reset. */ 1084 #define MISC_REG_LCPLL_E40_RESETB_ANA 0xaa78 1085 /* [RW 1] LCPLL post-divider reset. Global register. Active Low Reset on POR 1086 * reset. 1087 */ 1088 #define MISC_REG_LCPLL_E40_RESETB_DIG 0xaa7c 1089 /* [RW 8] Interrupt mask register #0 read/write */ 1090 #define MISC_REG_MISC_INT_MASK 0xa388 1091 /* [R 8] Interrupt register #0 read */ 1092 #define MISC_REG_MISC_INT_STS 0xa37c 1093 /* [RC 8] Interrupt register #0 read clear */ 1094 #define MISC_REG_MISC_INT_STS_CLR 0xa380 1095 /* [RW 1] Parity mask register #0 read/write */ 1096 #define MISC_REG_MISC_PRTY_MASK 0xa398 1097 /* [R 1] Parity register #0 read */ 1098 #define MISC_REG_MISC_PRTY_STS 0xa38c 1099 /* [RC 1] Parity register #0 read clear */ 1100 #define MISC_REG_MISC_PRTY_STS_CLR 0xa390 1101 /* [R 1] If set indicate that the pcie_rst_b was asserted without perst 1102 * assertion. Global register. 1103 */ 1104 #define MISC_REG_PCIE_HOT_RESET 0xa618 1105 /* [R 1] Status of 4 port mode enable input pin. */ 1106 #define MISC_REG_PORT4MODE_EN 0xa750 1107 /* [RW 2] 4 port mode enable overwrite.[0] - Overwrite control; if it is 0 - 1108 * the port4mode_en output is equal to 4 port mode input pin; if it is 1 - 1109 * the port4mode_en output is equal to bit[1] of this register; [1] - 1110 * Overwrite value. If bit[0] of this register is 1 this is the value that 1111 * receives the port4mode_en output. Reset on Hard reset. 1112 */ 1113 #define MISC_REG_PORT4MODE_EN_OVWR 0xa720 1114 /* [RW 32] reset reg#1; rite/read one = the specific block is out of reset; 1115 * write/read zero = the specific block is in reset; addr 0-wr- the write 1116 * value will be written to the register; addr 1-set - one will be written 1117 * to all the bits that have the value of one in the data written (bits that 1118 * have the value of zero will not be change) ; addr 2-clear - zero will be 1119 * written to all the bits that have the value of one in the data written 1120 * (bits that have the value of zero will not be change); addr 3-ignore; 1121 * read ignore from all addr except addr 00; inside order of the bits is: 1122 * [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] 1123 * rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10] 1124 * rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15] 1125 * rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20] 1126 * rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25] 1127 * rst_cfc; [26] rst_pxp_hst; [27] rst_pxpv (global register); [28] 1128 * rst_rbcp; [29] rst_hc; [30] rst_dmae; [31] rst_semi_rtc; 1129 */ 1130 #define MISC_REG_RESET_REG_1 0xa580 1131 #define MISC_REG_RESET_REG_2 0xa590 1132 /* [RW 22] 22 bit GRC address where the scratch-pad of the MCP that is 1133 * shared with the driver resides 1134 */ 1135 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4 1136 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1'; 1137 * the corresponding SPIO bit will turn off it's drivers and become an 1138 * input. This is the reset state of all SPIO pins. The read value of these 1139 * bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this 1140 * bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits 1141 * is written as a '1'; the corresponding SPIO bit will drive low. The read 1142 * value of these bits will be a '1' if that last command (#SET; #CLR; or 1143 * #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of 1144 * these bits is written as a '1'; the corresponding SPIO bit will drive 1145 * high (if it has that capability). The read value of these bits will be a 1146 * '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET. 1147 * (reset value 0). [7-0] VALUE RO; These bits indicate the read value of 1148 * each of the eight SPIO pins. This is the result value of the pin; not the 1149 * drive value. Writing these bits will have not effect. Each 8 bits field 1150 * is divided as follows: [0] VAUX Enable; when pulsed low; enables supply 1151 * from VAUX. (This is an output pin only; the FLOAT field is not applicable 1152 * for this pin); [1] VAUX Disable; when pulsed low; disables supply form 1153 * VAUX. (This is an output pin only; FLOAT field is not applicable for this 1154 * pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to 1155 * select VAUX supply. (This is an output pin only; it is not controlled by 1156 * the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT 1157 * field is not applicable for this pin; only the VALUE fields is relevant - 1158 * it reflects the output value); [3] port swap [4] spio_4; [5] spio_5; [6] 1159 * Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP 1160 * device ID select; read by UMP firmware. Global register. 1161 */ 1162 #define MISC_REG_SPIO 0xa4fc 1163 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC. 1164 * according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5; 1165 * [7:6] reserved. Global register. 1166 */ 1167 #define MISC_REG_SPIO_EVENT_EN 0xa2b8 1168 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the 1169 * corresponding bit in the #OLD_VALUE register. This will acknowledge an 1170 * interrupt on the falling edge of corresponding SPIO input (reset value 1171 * 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit 1172 * in the #OLD_VALUE register. This will acknowledge an interrupt on the 1173 * rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE 1174 * RO; These bits indicate the old value of the SPIO input value. When the 1175 * ~INT_STATE bit is set; this bit indicates the OLD value of the pin such 1176 * that if ~INT_STATE is set and this bit is '0'; then the interrupt is due 1177 * to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the 1178 * interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE 1179 * RO; These bits indicate the current SPIO interrupt state for each SPIO 1180 * pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR 1181 * command bit is written. This bit is set when the SPIO input does not 1182 * match the current value in #OLD_VALUE (reset value 0). Global register. 1183 */ 1184 #define MISC_REG_SPIO_INT 0xa500 1185 /* [R 1] Status of two port mode path swap input pin. */ 1186 #define MISC_REG_TWO_PORT_PATH_SWAP 0xa758 1187 /* [RW 2] 2 port swap overwrite.[0] - Overwrite control; if it is 0 - the 1188 * path_swap output is equal to 2 port mode path swap input pin; if it is 1 1189 * - the path_swap output is equal to bit[1] of this register; [1] - 1190 * Overwrite value. If bit[0] of this register is 1 this is the value that 1191 * receives the path_swap output. Reset on Hard reset. 1192 */ 1193 #define MISC_REG_TWO_PORT_PATH_SWAP_OVWR 0xa72c 1194 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are 1195 * loaded; 0-prepare; -unprepare. Global register. Reset on hard reset. 1196 */ 1197 #define MISC_REG_UNPREPARED 0xa424 1198 /* [RW 5] MDIO PHY Address. The WC uses this address to determine whether or 1199 * not it is the recipient of the message on the MDIO interface. The value 1200 * is compared to the value on ctrl_md_devad. Drives output 1201 * misc_xgxs0_phy_addr. Global register. 1202 */ 1203 #define MISC_REG_WC0_CTRL_PHY_ADDR 0xa9cc 1204 /* [RW 10] reset reg#3; rite/read one = the specific block is out of reset; 1205 * write/read zero = the specific block is in reset; addr 0-wr- the write 1206 * value will be written to the register; addr 1-set - one will be written 1207 * to all the bits that have the value of one in the data written (bits that 1208 * have the value of zero will not be change) ; addr 2-clear - zero will be 1209 * written to all the bits that have the value of one in the data written 1210 * (bits that have the value of zero will not be change); addr 3-ignore; 1211 * read ignore from all addr except addr 00. [0]: rstb_hw: Active low reset 1212 * which when asserted drives entire WC into the reset state. All flops 1213 * which within WC are driven into an initial state; as well as the analog 1214 * core. Output clocks txck_out; rxck0_10g; and clk_25 will be driven to 0 1215 * upon its assertion. [1]: iddq. Enables iddq testing where the supply 1216 * current (Idd) is measured in the quiescent state. [2]: pwrdwn: Active 1217 * high control which forces the analog core of the WC into power-down mode; 1218 * and forces digital logic of the WC into reset. Output clock (refclk) 1219 * remains active. [3]: pwrdwn_sd: Power down signal detect. [4]: 1220 * txd10g_fifo_rstb: Transmit 10Gbps FIFO reset; active low. Used to reset 1221 * the transmit FIFO used in xlgmii operation. [8:5]: txd1g_fifo_rstb: 1222 * Transmit 1Gbps FIFO reset; active low. Used to reset the per-lane 1223 * transmit FIFOs used in the mii/gmii operation. [9]: 1224 * txd10g_fifo_rstb_dxgxs1: Transmit 10Gbps DXGXS FIFO reset; active low. 1225 * Used to reset the transmit FIFO used in the DXGXS logic in xlgmii 1226 * operation. Global register. 1227 */ 1228 #define MISC_REG_WC0_RESET 0xac30 1229 /* [RW 2] XMAC Core port mode. Indicates the number of ports on the system 1230 * side. This should be less than or equal to phy_port_mode; if some of the 1231 * ports are not used. This enables reduction of frequency on the core side. 1232 * This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - 1233 * Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap 1234 * input for the XMAC_MP core; and should be changed only while reset is 1235 * held low. Reset on Hard reset. 1236 */ 1237 #define MISC_REG_XMAC_CORE_PORT_MODE 0xa964 1238 /* [RW 2] XMAC PHY port mode. Indicates the number of ports on the Warp 1239 * Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 1240 * 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the 1241 * XMAC_MP core; and should be changed only while reset is held low. Reset 1242 * on Hard reset. 1243 */ 1244 #define MISC_REG_XMAC_PHY_PORT_MODE 0xa960 1245 /* [RW 1] Interrupt mask register #0 read/write */ 1246 #define MSTAT_REG_MSTAT_INT_MASK 0x7fc 1247 /* [R 1] Interrupt register #0 read */ 1248 #define MSTAT_REG_MSTAT_INT_STS 0x7f0 1249 /* [RC 1] Interrupt register #0 read clear */ 1250 #define MSTAT_REG_MSTAT_INT_STS_CLR 0x7f4 1251 /* [RW 32] 1 [47] Packet Size = 64 Write to this register write bits 31:0. 1252 * Reads from this register will clear bits 31:0. 1253 */ 1254 #define MSTAT_REG_RX_STAT_GR64_LO 0x200 1255 /* [RW 32] 1 [00] Tx Good Packet Count Write to this register write bits 1256 * 31:0. Reads from this register will clear bits 31:0. 1257 */ 1258 #define MSTAT_REG_TX_STAT_GTXPOK_LO 0 1259 #define NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN (0x1 << 0) 1260 #define NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN (0x1 << 0) 1261 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1 << 0) 1262 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1 << 9) 1263 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1 << 15) 1264 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf << 18) 1265 /* [R 1] Input enable for RX_BMAC0 IF */ 1266 #define NIG_REG_BMAC0_IN_EN 0x100ac 1267 /* [R 1] output enable for TX_BMAC0 IF */ 1268 #define NIG_REG_BMAC0_OUT_EN 0x100e0 1269 /* [R 1] output enable for TX BMAC pause port 0 IF */ 1270 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110 1271 /* [R 1] output enable for RX_BMAC0_REGS IF */ 1272 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8 1273 /* [RW 1] output enable for RX BRB1 port0 IF */ 1274 #define NIG_REG_BRB0_OUT_EN 0x100f8 1275 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */ 1276 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4 1277 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */ 1278 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8 1279 /* [WB_W 90] Debug packet to LP from RBC; Data spelling:[63:0] data; 64] 1280 * error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush; 1281 * 72:73]-vnic_num; 89:74]-sideband_info 1282 */ 1283 #define NIG_REG_DEBUG_PACKET_LB 0x10800 1284 /* [R 1] FIFO empty in DEBUG_FIFO in NIG_TX_DBG */ 1285 #define NIG_REG_EGRESS_DEBUG_FIFO_EMPTY 0x10418 1286 /* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT0 */ 1287 #define NIG_REG_EGRESS_DELAY0_EMPTY 0x10420 1288 /* [R 1] FIFO empty in DELAY_PBF_FIFO in NIG_RX_PORT1 */ 1289 #define NIG_REG_EGRESS_DELAY1_EMPTY 0x10428 1290 /* [R 1] PBF FIFO empty flag. */ 1291 #define NIG_REG_EGRESS_DELAY2_EMPTY 0x1862c 1292 /* [R 1] PBF FIFO empty flag. */ 1293 #define NIG_REG_EGRESS_DELAY3_EMPTY 0x18630 1294 /* [R 1] PBF FIFO empty flag. */ 1295 #define NIG_REG_EGRESS_DELAY4_EMPTY 0x18634 1296 /* [R 1] PBF FIFO empty flag. */ 1297 #define NIG_REG_EGRESS_DELAY5_EMPTY 0x18638 1298 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all 1299 * packets from PBFare not forwarded to the MAC and just deleted from FIFO. 1300 * First packet may be deleted from the middle. And last packet will be 1301 * always deleted till the end. 1302 */ 1303 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060 1304 /* [R 1] Output enable to EMAC0 */ 1305 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120 1306 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs 1307 * to emac for port0; other way to bmac for port0 1308 */ 1309 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058 1310 /* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT0 */ 1311 #define NIG_REG_EGRESS_MNG0_FIFO_EMPTY 0x10460 1312 /* [R 1] FIFO empty in MNG_FIFO in NIG_TX_PORT1 */ 1313 #define NIG_REG_EGRESS_MNG1_FIFO_EMPTY 0x10474 1314 /* [RW 1] Input enable for TX UMP management packet port0 IF */ 1315 #define NIG_REG_EGRESS_UMP0_IN_EN 0x100d4 1316 /* [R 1] Input enable for RX_EMAC0 IF */ 1317 #define NIG_REG_EMAC0_IN_EN 0x100a4 1318 /* [R 1] output enable for TX EMAC pause port 0 IF */ 1319 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118 1320 /* [R 1] status from emac0. This bit is set when MDINT from either the 1321 * EXT_MDINT pin or from the Copper PHY is driven low. This condition must 1322 * be cleared in the attached PHY device that is driving the MINT pin. 1323 */ 1324 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494 1325 /* [R 48] This address space contains BMAC0 registers. The BMAC registers 1326 * are described in appendix A. In order to access the BMAC0 registers; the 1327 * base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be 1328 * added to each BMAC register offset 1329 */ 1330 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00 1331 /* [R 48] This address space contains BMAC1 registers. The BMAC registers 1332 * are described in appendix A. In order to access the BMAC0 registers; the 1333 * base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be 1334 * added to each BMAC register offset 1335 */ 1336 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000 1337 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */ 1338 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0 1339 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data 1340 * packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] 1341 */ 1342 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4 1343 /* [R 1] FIFO empty in EOP descriptor FIFO of port 0 in NIG_RX_EOP */ 1344 #define NIG_REG_INGRESS_EOP_PORT0_EMPTY 0x104ec 1345 /* [R 1] FIFO empty in EOP descriptor FIFO of port 1 in NIG_RX_EOP */ 1346 #define NIG_REG_INGRESS_EOP_PORT1_EMPTY 0x104f8 1347 /* [R 1] FIFO empty in PBF_DELAY_lb_FIFO in NIG_RX_lb */ 1348 #define NIG_REG_INGRESS_LB_PBF_DELAY_EMPTY 0x10508 1349 /* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */ 1350 #define NIG_REG_INGRESS_RMP0_DSCR_EMPTY 0x10530 1351 /* [R 1] FIFO empty in dscr_fifo in NIG_RX_RMP block */ 1352 #define NIG_REG_INGRESS_RMP1_DSCR_EMPTY 0x10538 1353 /* [RW 27] 0 - must be active for Everest A0; 1- for Everest B0 when latch 1354 * logic for interrupts must be used. Enable per bit of interrupt of 1355 * ~latch_status.latch_status 1356 */ 1357 #define NIG_REG_LATCH_BC_0 0x16210 1358 /* [RW 27] Latch for each interrupt from Unicore.b[0] 1359 * status_emac0_misc_mi_int; b[1] status_emac0_misc_mi_complete; 1360 * b[2]status_emac0_misc_cfg_change; b[3]status_emac0_misc_link_status; 1361 * b[4]status_emac0_misc_link_change; b[5]status_emac0_misc_attn; 1362 * b[6]status_serdes0_mac_crs; b[7]status_serdes0_autoneg_complete; 1363 * b[8]status_serdes0_fiber_rxact; b[9]status_serdes0_link_status; 1364 * b[10]status_serdes0_mr_page_rx; b[11]status_serdes0_cl73_an_complete; 1365 * b[12]status_serdes0_cl73_mr_page_rx; b[13]status_serdes0_rx_sigdet; 1366 * b[14]status_xgxs0_remotemdioreq; b[15]status_xgxs0_link10g; 1367 * b[16]status_xgxs0_autoneg_complete; b[17]status_xgxs0_fiber_rxact; 1368 * b[21:18]status_xgxs0_link_status; b[22]status_xgxs0_mr_page_rx; 1369 * b[23]status_xgxs0_cl73_an_complete; b[24]status_xgxs0_cl73_mr_page_rx; 1370 * b[25]status_xgxs0_rx_sigdet; b[26]status_xgxs0_mac_crs 1371 */ 1372 #define NIG_REG_LATCH_STATUS_0 0x18000 1373 /* [RW 1] led 10g for port 0 */ 1374 #define NIG_REG_LED_10G_P0 0x10320 1375 /* [RW 1] Port0: This bit is set to enable the use of the 1376 * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field 1377 * defined below. If this bit is cleared; then the blink rate will be about 1378 * 8Hz. 1379 */ 1380 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318 1381 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for 1382 * Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field 1383 * is reset to 0x080; giving a default blink period of approximately 8Hz. 1384 */ 1385 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310 1386 /* [RW 1] Port0: If set along with the 1387 * s_led_control_override_traffic_p0.led_control_override_traffic_p0 1388 * bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED 1389 * bit; the Traffic LED will blink with the blink rate specified in 1390 * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1391 * ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1392 * fields. 1393 */ 1394 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308 1395 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The 1396 * Traffic LED will then be controlled via bit ~nig_registers_ 1397 * led_control_traffic_p0.led_control_traffic_p0 and bit 1398 * ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 1399 */ 1400 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8 1401 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit; 1402 * turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also 1403 * set; the LED will blink with blink rate specified in 1404 * ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and 1405 * ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0 1406 * fields. 1407 */ 1408 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300 1409 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3; 1410 * 9-11PHY7; 12 MAC4; 13-15 PHY10; 1411 */ 1412 #define NIG_REG_LED_MODE_P0 0x102f0 1413 /* [RW 3] for port0 enable for llfc ppp and pause. b0 - brb1 enable; b1- 1414 * tsdm enable; b2- usdm enable 1415 */ 1416 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_0 0x16070 1417 #define NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 0x16074 1418 /* [RW 1] SAFC enable for port0. This register may get 1 only when 1419 * ~ppp_enable.ppp_enable = 0 and pause_enable.pause_enable =0 for the same 1420 * port 1421 */ 1422 #define NIG_REG_LLFC_ENABLE_0 0x16208 1423 #define NIG_REG_LLFC_ENABLE_1 0x1620c 1424 /* [RW 16] classes are high-priority for port0 */ 1425 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0 0x16058 1426 #define NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 0x1605c 1427 /* [RW 16] classes are low-priority for port0 */ 1428 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0 0x16060 1429 #define NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 0x16064 1430 /* [RW 1] Output enable of message to LLFC BMAC IF for port0 */ 1431 #define NIG_REG_LLFC_OUT_EN_0 0x160c8 1432 #define NIG_REG_LLFC_OUT_EN_1 0x160cc 1433 #define NIG_REG_LLH0_ACPI_PAT_0_CRC 0x1015c 1434 #define NIG_REG_LLH0_ACPI_PAT_6_LEN 0x10154 1435 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244 1436 #define NIG_REG_LLH0_BRB1_DRV_MASK_MF 0x16048 1437 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1438 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c 1439 /* [RW 2] Determine the classification participants. 0: no classification.1: 1440 * classification upon VLAN id. 2: classification upon MAC address. 3: 1441 * classification upon both VLAN id & MAC addr. 1442 */ 1443 #define NIG_REG_LLH0_CLS_TYPE 0x16080 1444 #define NIG_REG_LLH0_DEST_IP_0_1 0x101dc 1445 #define NIG_REG_LLH0_DEST_MAC_0_0 0x101c0 1446 /* [RW 16] destination TCP address 1. The LLH will look for this address in 1447 * all incoming packets. 1448 */ 1449 #define NIG_REG_LLH0_DEST_TCP_0 0x10220 1450 /* [RW 16] destination UDP address 1 The LLH will look for this address in 1451 * all incoming packets. 1452 */ 1453 #define NIG_REG_LLH0_DEST_UDP_0 0x10214 1454 /* [R 1] FIFO empty in LLH port0 */ 1455 #define NIG_REG_LLH0_FIFO_EMPTY 0x10548 1456 #define NIG_REG_LLH0_FUNC_EN 0x160fc 1457 #define NIG_REG_LLH0_FUNC_MEM 0x16180 1458 #define NIG_REG_LLH0_FUNC_MEM_ENABLE 0x16140 1459 #define NIG_REG_LLH0_FUNC_VLAN_ID 0x16100 1460 /* [RW 1] Determine the IP version to look for in 1461 * ~nig_registers_llh0_dest_ip_0.llh0_dest_ip_0. 0 - IPv6; 1-IPv4 1462 */ 1463 #define NIG_REG_LLH0_IPV4_IPV6_0 0x10208 1464 /* [RW 1] t bit for llh0 */ 1465 #define NIG_REG_LLH0_T_BIT 0x10074 1466 /* [RW 12] VLAN ID 1. In case of VLAN packet the LLH will look for this ID. */ 1467 #define NIG_REG_LLH0_VLAN_ID_0 0x1022c 1468 #define NIG_REG_LLH0_XCM_MASK 0x10130 1469 #define NIG_REG_LLH1_BRB1_DRV_MASK_MF 0x1604c 1470 /* [RW 1] send to BRB1 if no match on any of RMP rules. */ 1471 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc 1472 /* [RW 2] Determine the classification participants. 0: no classification.1: 1473 * classification upon VLAN id. 2: classification upon MAC address. 3: 1474 * classification upon both VLAN id & MAC addr. 1475 */ 1476 #define NIG_REG_LLH1_CLS_TYPE 0x16084 1477 /* [R 1] FIFO empty in LLH port1 */ 1478 #define NIG_REG_LLH1_FIFO_EMPTY 0x10558 1479 #define NIG_REG_LLH1_FUNC_EN 0x16104 1480 #define NIG_REG_LLH1_FUNC_MEM 0x161c0 1481 #define NIG_REG_LLH1_FUNC_MEM_ENABLE 0x16160 1482 #define NIG_REG_LLH1_FUNC_MEM_SIZE 16 1483 /* [RW 1] When this bit is set; the LLH will classify the packet before 1484 * sending it to the BRB or calculating WoL on it. This bit controls port 1 1485 * only. The legacy llh_multi_function_mode bit controls port 0. 1486 */ 1487 #define NIG_REG_LLH1_MF_MODE 0x18614 1488 #define NIG_REG_LLH1_XCM_MASK 0x10134 1489 /* [RW 1] When this bit is set; the LLH will expect all packets to be with 1490 * outer VLAN. This is not applicable to E2. 1491 */ 1492 #define NIG_REG_LLH_E1HOV_MODE 0x160d8 1493 /* [RW 16] Outer VLAN type identifier for multi-function mode. In non 1494 * multi-function mode; it will hold the inner VLAN type. Typically 0x8100. 1495 */ 1496 #define NIG_REG_LLH_E1HOV_TYPE_1 0x16028 1497 /* [RW 1] When this bit is set; the LLH will classify the packet before 1498 * sending it to the BRB or calculating WoL on it. This bit is applicable to 1499 * both ports 0 and 1 for E2. This bit only controls port 0 in E3. 1500 */ 1501 #define NIG_REG_LLH_MF_MODE 0x16024 1502 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330 1503 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334 1504 /* [R 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */ 1505 #define NIG_REG_NIG_EMAC0_EN 0x1003c 1506 /* [R 1] Output signal from NIG to TX_EMAC0. When set indicates to the EMAC0 1507 * to strip the CRC from the ingress packets. 1508 */ 1509 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044 1510 /* [RW 32] Interrupt mask register #0 read/write */ 1511 #define NIG_REG_NIG_INT_MASK_0 0x103bc 1512 #define NIG_REG_NIG_INT_MASK_1 0x103cc 1513 /* [R 32] Interrupt register #0 read */ 1514 #define NIG_REG_NIG_INT_STS_0 0x103b0 1515 #define NIG_REG_NIG_INT_STS_1 0x103c0 1516 /* [RC 32] Interrupt register #0 read clear */ 1517 #define NIG_REG_NIG_INT_STS_CLR_0 0x103b4 1518 #define NIG_REG_NIG_INT_STS_CLR_1 0x103c4 1519 /* [R 32] Legacy E1 and E1H location for parity error mask register. */ 1520 #define NIG_REG_NIG_PRTY_MASK 0x103dc 1521 /* [RW 32] Parity mask register #0 read/write */ 1522 #define NIG_REG_NIG_PRTY_MASK_0 0x183c8 1523 #define NIG_REG_NIG_PRTY_MASK_1 0x183d8 1524 /* [R 32] Legacy E1 and E1H location for parity error status register. */ 1525 #define NIG_REG_NIG_PRTY_STS 0x103d0 1526 /* [R 32] Parity register #0 read */ 1527 #define NIG_REG_NIG_PRTY_STS_0 0x183bc 1528 #define NIG_REG_NIG_PRTY_STS_1 0x183cc 1529 /* [R 32] Legacy E1 and E1H location for parity error status clear register. */ 1530 #define NIG_REG_NIG_PRTY_STS_CLR 0x103d4 1531 /* [RC 32] Parity register #0 read clear */ 1532 #define NIG_REG_NIG_PRTY_STS_CLR_0 0x183c0 1533 #define NIG_REG_NIG_PRTY_STS_CLR_1 0x183d0 1534 /* [R 1] Indication that HBUF descriptor FIFO is empty. */ 1535 #define NIG_REG_P0_HBUF_DSCR_EMPTY 0x18318 1536 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 1537 * Ethernet header. 1538 */ 1539 #define NIG_REG_P0_HDRS_AFTER_BASIC 0x18038 1540 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 1541 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 1542 * disabled when this bit is set. 1543 */ 1544 #define NIG_REG_P0_HWPFC_ENABLE 0x18078 1545 #define NIG_REG_P0_LLH_FUNC_MEM2 0x18480 1546 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for 1547 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16 1548 * indicates the validity of the data in the buffer. Writing a 1 to bit 16 1549 * will clear the buffer. 1550 */ 1551 #define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID 0x1875c 1552 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1553 * the host. This location returns the lower 32 bits of timestamp value. 1554 */ 1555 #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB 0x18754 1556 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1557 * the host. This location returns the upper 32 bits of timestamp value. 1558 */ 1559 #define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB 0x18758 1560 /* [RW 11] Mask register for the various parameters used in determining PTP 1561 * packet presence. Set each bit to 1 to mask out the particular parameter. 1562 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 1563 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 1564 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 1565 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 1566 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 1567 * MAC DA 2. The reset default is set to mask out all parameters. 1568 */ 1569 #define NIG_REG_P0_LLH_PTP_PARAM_MASK 0x187a0 1570 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 1571 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1572 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1573 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 1574 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 1575 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1576 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 1577 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4 1578 * packets only and require that the packet is IPv4 for the rules to match. 1579 * Note that rules 4-7 are for IPv6 packets only and require that the packet 1580 * is IPv6 for the rules to match. 1581 */ 1582 #define NIG_REG_P0_LLH_PTP_RULE_MASK 0x187a4 1583 /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */ 1584 #define NIG_REG_P0_LLH_PTP_TO_HOST 0x187ac 1585 /* [RW 1] Input enable for RX MAC interface. */ 1586 #define NIG_REG_P0_MAC_IN_EN 0x185ac 1587 /* [RW 1] Output enable for TX MAC interface */ 1588 #define NIG_REG_P0_MAC_OUT_EN 0x185b0 1589 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 1590 #define NIG_REG_P0_MAC_PAUSE_OUT_EN 0x185b4 1591 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 1592 * future expansion) each priority is to be mapped to. Bits 3:0 specify the 1593 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 1594 * priority field is extracted from the outer-most VLAN in receive packet. 1595 * Only COS 0 and COS 1 are supported in E2. 1596 */ 1597 #define NIG_REG_P0_PKT_PRIORITY_TO_COS 0x18054 1598 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits 1599 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables 1600 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2 1601 * frame format in timesync event detection on RX side. Bit 3 enables 1602 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event 1603 * detection on TX side. Bit 5 enables V2 frame format in timesync event 1604 * detection on TX side. Note that for HW to detect PTP packet and extract 1605 * data from the packet, at least one of the version bits of that traffic 1606 * direction has to be enabled. 1607 */ 1608 #define NIG_REG_P0_PTP_EN 0x18788 1609 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 1610 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 1611 * than one bit may be set; allowing multiple priorities to be mapped to one 1612 * COS. 1613 */ 1614 #define NIG_REG_P0_RX_COS0_PRIORITY_MASK 0x18058 1615 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 1616 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 1617 * than one bit may be set; allowing multiple priorities to be mapped to one 1618 * COS. 1619 */ 1620 #define NIG_REG_P0_RX_COS1_PRIORITY_MASK 0x1805c 1621 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 1622 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 1623 * than one bit may be set; allowing multiple priorities to be mapped to one 1624 * COS. 1625 */ 1626 #define NIG_REG_P0_RX_COS2_PRIORITY_MASK 0x186b0 1627 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 3. A 1628 * priority is mapped to COS 3 when the corresponding mask bit is 1. More 1629 * than one bit may be set; allowing multiple priorities to be mapped to one 1630 * COS. 1631 */ 1632 #define NIG_REG_P0_RX_COS3_PRIORITY_MASK 0x186b4 1633 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 4. A 1634 * priority is mapped to COS 4 when the corresponding mask bit is 1. More 1635 * than one bit may be set; allowing multiple priorities to be mapped to one 1636 * COS. 1637 */ 1638 #define NIG_REG_P0_RX_COS4_PRIORITY_MASK 0x186b8 1639 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 5. A 1640 * priority is mapped to COS 5 when the corresponding mask bit is 1. More 1641 * than one bit may be set; allowing multiple priorities to be mapped to one 1642 * COS. 1643 */ 1644 #define NIG_REG_P0_RX_COS5_PRIORITY_MASK 0x186bc 1645 /* [R 1] RX FIFO for receiving data from MAC is empty. */ 1646 #define NIG_REG_P0_RX_MACFIFO_EMPTY 0x18570 1647 /* [R 1] TLLH FIFO is empty. */ 1648 #define NIG_REG_P0_TLLH_FIFO_EMPTY 0x18308 1649 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for 1650 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 1651 * indicates the validity of the data in the buffer. Bit 17 indicates that 1652 * the sequence ID is valid and it is waiting for the TX timestamp value. 1653 * Bit 18 indicates whether the timestamp is from a SW request (value of 1) 1654 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. 1655 */ 1656 #define NIG_REG_P0_TLLH_PTP_BUF_SEQID 0x187e0 1657 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1658 * MCP. This location returns the lower 32 bits of timestamp value. 1659 */ 1660 #define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB 0x187d8 1661 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1662 * MCP. This location returns the upper 32 bits of timestamp value. 1663 */ 1664 #define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB 0x187dc 1665 /* [RW 11] Mask register for the various parameters used in determining PTP 1666 * packet presence. Set each bit to 1 to mask out the particular parameter. 1667 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 1668 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 1669 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 1670 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 1671 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 1672 * MAC DA 2. The reset default is set to mask out all parameters. 1673 */ 1674 #define NIG_REG_P0_TLLH_PTP_PARAM_MASK 0x187f0 1675 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 1676 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1677 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1678 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 1679 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 1680 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1681 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 1682 * default is to mask out all of the rules. 1683 */ 1684 #define NIG_REG_P0_TLLH_PTP_RULE_MASK 0x187f4 1685 /* [R 15] Specify which of the credit registers the client is to be mapped 1686 * to. Bits[2:0] are for client 0; bits [14:12] are for client 4. For 1687 * clients that are not subject to WFQ credit blocking - their 1688 * specifications here are not used. 1689 */ 1690 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP 0x180f0 1691 /* [RW 32] Specify which of the credit registers the client is to be mapped 1692 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 1693 * for client 0; bits [35:32] are for client 8. For clients that are not 1694 * subject to WFQ credit blocking - their specifications here are not used. 1695 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 1696 * input clients to ETS arbiter. The reset default is set for management and 1697 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 1698 * use credit registers 0-5 respectively (0x543210876). Note that credit 1699 * registers can not be shared between clients. 1700 */ 1701 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x18688 1702 /* [RW 4] Specify which of the credit registers the client is to be mapped 1703 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 1704 * for client 0; bits [35:32] are for client 8. For clients that are not 1705 * subject to WFQ credit blocking - their specifications here are not used. 1706 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 1707 * input clients to ETS arbiter. The reset default is set for management and 1708 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 1709 * use credit registers 0-5 respectively (0x543210876). Note that credit 1710 * registers can not be shared between clients. 1711 */ 1712 #define NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x1868c 1713 /* [RW 9] Specify whether the client competes directly in the strict 1714 * priority arbiter. The bits are mapped according to client ID (client IDs 1715 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 1716 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 1717 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 1718 * Default value is set to enable strict priorities for all clients. 1719 */ 1720 #define NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT 0x180e8 1721 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 1722 * bits are mapped according to client ID (client IDs are defined in 1723 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 1724 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 1725 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 1726 * 0 for not using WFQ credit blocking. 1727 */ 1728 #define NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x180ec 1729 /* [RW 32] Specify the upper bound that credit register 0 is allowed to 1730 * reach. 1731 */ 1732 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0 0x1810c 1733 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1 0x18110 1734 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2 0x18114 1735 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3 0x18118 1736 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4 0x1811c 1737 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5 0x186a0 1738 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6 0x186a4 1739 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7 0x186a8 1740 #define NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8 0x186ac 1741 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 1742 * when it is time to increment. 1743 */ 1744 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0 0x180f8 1745 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1 0x180fc 1746 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2 0x18100 1747 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3 0x18104 1748 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4 0x18108 1749 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5 0x18690 1750 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6 0x18694 1751 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7 0x18698 1752 #define NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8 0x1869c 1753 /* [RW 12] Specify the number of strict priority arbitration slots between 1754 * two round-robin arbitration slots to avoid starvation. A value of 0 means 1755 * no strict priority cycles - the strict priority with anti-starvation 1756 * arbiter becomes a round-robin arbiter. 1757 */ 1758 #define NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS 0x180f4 1759 /* [R 15] Specify the client number to be assigned to each priority of the 1760 * strict priority arbiter. Priority 0 is the highest priority. Bits [2:0] 1761 * are for priority 0 client; bits [14:12] are for priority 4 client. The 1762 * clients are assigned the following IDs: 0-management; 1-debug traffic 1763 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 1764 * traffic. The reset value[14:0] is set to 0x4688 (15'b100_011_010_001_000) 1765 * for management at priority 0; debug traffic at priorities 1 and 2; COS0 1766 * traffic at priority 3; and COS1 traffic at priority 4. 1767 */ 1768 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT 0x180e4 1769 /* [RW 32] Specify the client number to be assigned to each priority of the 1770 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 1771 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 1772 * client; bits [35-32] are for priority 8 client. The clients are assigned 1773 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 1774 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 1775 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 1776 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 1777 * accommodate the 9 input clients to ETS arbiter. 1778 */ 1779 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB 0x18680 1780 /* [RW 4] Specify the client number to be assigned to each priority of the 1781 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 1782 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 1783 * client; bits [35-32] are for priority 8 client. The clients are assigned 1784 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 1785 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 1786 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 1787 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 1788 * accommodate the 9 input clients to ETS arbiter. 1789 */ 1790 #define NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB 0x18684 1791 /* [R 1] TX FIFO for transmitting data to MAC is empty. */ 1792 #define NIG_REG_P0_TX_MACFIFO_EMPTY 0x18578 1793 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP 1794 * packets to BRB LB interface to forward the packet to the host. All 1795 * packets from MCP are forwarded to the network when this bit is cleared - 1796 * regardless of the configured destination in tx_mng_destination register. 1797 * When MCP-to-host paths for both ports 0 and 1 are disabled - the arbiter 1798 * for BRB LB interface is bypassed and PBF LB traffic is always selected to 1799 * send to BRB LB. 1800 */ 1801 #define NIG_REG_P0_TX_MNG_HOST_ENABLE 0x182f4 1802 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 1803 * forwarded to the host. 1804 */ 1805 #define NIG_REG_P0_TX_MNG_HOST_FIFO_EMPTY 0x182a8 1806 /* [R 1] Indication that HBUF descriptor FIFO is empty. */ 1807 #define NIG_REG_P1_HBUF_DSCR_EMPTY 0x18348 1808 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 1809 * Ethernet header. 1810 */ 1811 #define NIG_REG_P1_HDRS_AFTER_BASIC 0x1818c 1812 /* [RW 1] HW PFC enable bit. Set this bit to enable the PFC functionality in 1813 * the NIG. Other flow control modes such as PAUSE and SAFC/LLFC should be 1814 * disabled when this bit is set. 1815 */ 1816 #define NIG_REG_P1_HWPFC_ENABLE 0x181d0 1817 #define NIG_REG_P1_LLH_FUNC_MEM2 0x184c0 1818 /* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for 1819 * the host. Bits [15:0] return the sequence ID of the packet. Bit 16 1820 * indicates the validity of the data in the buffer. Writing a 1 to bit 16 1821 * will clear the buffer. 1822 */ 1823 #define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID 0x18774 1824 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1825 * the host. This location returns the lower 32 bits of timestamp value. 1826 */ 1827 #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB 0x1876c 1828 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1829 * the host. This location returns the upper 32 bits of timestamp value. 1830 */ 1831 #define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB 0x18770 1832 /* [RW 11] Mask register for the various parameters used in determining PTP 1833 * packet presence. Set each bit to 1 to mask out the particular parameter. 1834 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 1835 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 1836 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 1837 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 1838 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 1839 * MAC DA 2. The reset default is set to mask out all parameters. 1840 */ 1841 #define NIG_REG_P1_LLH_PTP_PARAM_MASK 0x187c8 1842 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 1843 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1844 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1845 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 1846 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 1847 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1848 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 1849 * default is to mask out all of the rules. Note that rules 0-3 are for IPv4 1850 * packets only and require that the packet is IPv4 for the rules to match. 1851 * Note that rules 4-7 are for IPv6 packets only and require that the packet 1852 * is IPv6 for the rules to match. 1853 */ 1854 #define NIG_REG_P1_LLH_PTP_RULE_MASK 0x187cc 1855 /* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */ 1856 #define NIG_REG_P1_LLH_PTP_TO_HOST 0x187d4 1857 /* [RW 1] Input enable for RX MAC interface. */ 1858 #define NIG_REG_P1_MAC_IN_EN 0x185c0 1859 /* [RW 1] Output enable for TX MAC interface */ 1860 #define NIG_REG_P1_MAC_OUT_EN 0x185c4 1861 /* [RW 1] Output enable for TX PAUSE signal to the MAC. */ 1862 #define NIG_REG_P1_MAC_PAUSE_OUT_EN 0x185c8 1863 /* [RW 32] Eight 4-bit configurations for specifying which COS (0-15 for 1864 * future expansion) each priority is to be mapped to. Bits 3:0 specify the 1865 * COS for priority 0. Bits 31:28 specify the COS for priority 7. The 3-bit 1866 * priority field is extracted from the outer-most VLAN in receive packet. 1867 * Only COS 0 and COS 1 are supported in E2. 1868 */ 1869 #define NIG_REG_P1_PKT_PRIORITY_TO_COS 0x181a8 1870 /* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits 1871 * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables 1872 * V1 frame format in timesync event detection on RX side. Bit 2 enables V2 1873 * frame format in timesync event detection on RX side. Bit 3 enables 1874 * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event 1875 * detection on TX side. Bit 5 enables V2 frame format in timesync event 1876 * detection on TX side. Note that for HW to detect PTP packet and extract 1877 * data from the packet, at least one of the version bits of that traffic 1878 * direction has to be enabled. 1879 */ 1880 #define NIG_REG_P1_PTP_EN 0x187b0 1881 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A 1882 * priority is mapped to COS 0 when the corresponding mask bit is 1. More 1883 * than one bit may be set; allowing multiple priorities to be mapped to one 1884 * COS. 1885 */ 1886 #define NIG_REG_P1_RX_COS0_PRIORITY_MASK 0x181ac 1887 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 1. A 1888 * priority is mapped to COS 1 when the corresponding mask bit is 1. More 1889 * than one bit may be set; allowing multiple priorities to be mapped to one 1890 * COS. 1891 */ 1892 #define NIG_REG_P1_RX_COS1_PRIORITY_MASK 0x181b0 1893 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 2. A 1894 * priority is mapped to COS 2 when the corresponding mask bit is 1. More 1895 * than one bit may be set; allowing multiple priorities to be mapped to one 1896 * COS. 1897 */ 1898 #define NIG_REG_P1_RX_COS2_PRIORITY_MASK 0x186f8 1899 /* [R 1] RX FIFO for receiving data from MAC is empty. */ 1900 #define NIG_REG_P1_RX_MACFIFO_EMPTY 0x1858c 1901 /* [R 1] TLLH FIFO is empty. */ 1902 #define NIG_REG_P1_TLLH_FIFO_EMPTY 0x18338 1903 /* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for 1904 * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16 1905 * indicates the validity of the data in the buffer. Bit 17 indicates that 1906 * the sequence ID is valid and it is waiting for the TX timestamp value. 1907 * Bit 18 indicates whether the timestamp is from a SW request (value of 1) 1908 * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer. 1909 */ 1910 #define NIG_REG_P1_TLLH_PTP_BUF_SEQID 0x187ec 1911 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1912 * MCP. This location returns the lower 32 bits of timestamp value. 1913 */ 1914 #define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB 0x187e4 1915 /* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for 1916 * MCP. This location returns the upper 32 bits of timestamp value. 1917 */ 1918 #define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB 0x187e8 1919 /* [RW 11] Mask register for the various parameters used in determining PTP 1920 * packet presence. Set each bit to 1 to mask out the particular parameter. 1921 * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of 1922 * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP 1923 * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC 1924 * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of 1925 * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable 1926 * MAC DA 2. The reset default is set to mask out all parameters. 1927 */ 1928 #define NIG_REG_P1_TLLH_PTP_PARAM_MASK 0x187f8 1929 /* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set 1930 * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} . 1931 * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP 1932 * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; 1933 * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC 1934 * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype 1935 * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset 1936 * default is to mask out all of the rules. 1937 */ 1938 #define NIG_REG_P1_TLLH_PTP_RULE_MASK 0x187fc 1939 /* [RW 32] Specify which of the credit registers the client is to be mapped 1940 * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are 1941 * for client 0; bits [35:32] are for client 8. For clients that are not 1942 * subject to WFQ credit blocking - their specifications here are not used. 1943 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 1944 * input clients to ETS arbiter. The reset default is set for management and 1945 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 1946 * use credit registers 0-5 respectively (0x543210876). Note that credit 1947 * registers can not be shared between clients. Note also that there are 1948 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 1949 * credit registers 0-5 are valid. This register should be configured 1950 * appropriately before enabling WFQ. 1951 */ 1952 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB 0x186e8 1953 /* [RW 4] Specify which of the credit registers the client is to be mapped 1954 * to. This register specifies bits 35:32 of the 36-bit value. Bits[3:0] are 1955 * for client 0; bits [35:32] are for client 8. For clients that are not 1956 * subject to WFQ credit blocking - their specifications here are not used. 1957 * This is a new register (with 2_) added in E3 B0 to accommodate the 9 1958 * input clients to ETS arbiter. The reset default is set for management and 1959 * debug to use credit registers 6, 7, and 8, respectively, and COSes 0-5 to 1960 * use credit registers 0-5 respectively (0x543210876). Note that credit 1961 * registers can not be shared between clients. Note also that there are 1962 * only COS0-2 in port 1- there is a total of 6 clients in port 1. Only 1963 * credit registers 0-5 are valid. This register should be configured 1964 * appropriately before enabling WFQ. 1965 */ 1966 #define NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB 0x186ec 1967 /* [RW 9] Specify whether the client competes directly in the strict 1968 * priority arbiter. The bits are mapped according to client ID (client IDs 1969 * are defined in tx_arb_priority_client2): 0-management; 1-debug traffic 1970 * from this port; 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 1971 * traffic; 5-COS2 traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. 1972 * Default value is set to enable strict priorities for all clients. 1973 */ 1974 #define NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT 0x18234 1975 /* [RW 9] Specify whether the client is subject to WFQ credit blocking. The 1976 * bits are mapped according to client ID (client IDs are defined in 1977 * tx_arb_priority_client2): 0-management; 1-debug traffic from this port; 1978 * 2-debug traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 1979 * traffic; 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. Default value is 1980 * 0 for not using WFQ credit blocking. 1981 */ 1982 #define NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ 0x18238 1983 /* [RW 32] Specify the upper bound that credit register 0 is allowed to 1984 * reach. 1985 */ 1986 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 0x18258 1987 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 0x1825c 1988 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 0x18260 1989 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 0x18264 1990 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 0x18268 1991 #define NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 0x186f4 1992 /* [RW 32] Specify the weight (in bytes) to be added to credit register 0 1993 * when it is time to increment. 1994 */ 1995 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 0x18244 1996 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 0x18248 1997 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 0x1824c 1998 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 0x18250 1999 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 0x18254 2000 #define NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 0x186f0 2001 /* [RW 12] Specify the number of strict priority arbitration slots between 2002 * two round-robin arbitration slots to avoid starvation. A value of 0 means 2003 * no strict priority cycles - the strict priority with anti-starvation 2004 * arbiter becomes a round-robin arbiter. 2005 */ 2006 #define NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS 0x18240 2007 /* [RW 32] Specify the client number to be assigned to each priority of the 2008 * strict priority arbiter. This register specifies bits 31:0 of the 36-bit 2009 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2010 * client; bits [35-32] are for priority 8 client. The clients are assigned 2011 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2012 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2013 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2014 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2015 * accommodate the 9 input clients to ETS arbiter. Note that this register 2016 * is the same as the one for port 0, except that port 1 only has COS 0-2 2017 * traffic. There is no traffic for COS 3-5 of port 1. 2018 */ 2019 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB 0x186e0 2020 /* [RW 4] Specify the client number to be assigned to each priority of the 2021 * strict priority arbiter. This register specifies bits 35:32 of the 36-bit 2022 * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0 2023 * client; bits [35-32] are for priority 8 client. The clients are assigned 2024 * the following IDs: 0-management; 1-debug traffic from this port; 2-debug 2025 * traffic from other port; 3-COS0 traffic; 4-COS1 traffic; 5-COS2 traffic; 2026 * 6-COS3 traffic; 7-COS4 traffic; 8-COS5 traffic. The reset value[35:0] is 2027 * set to 0x345678021. This is a new register (with 2_) added in E3 B0 to 2028 * accommodate the 9 input clients to ETS arbiter. Note that this register 2029 * is the same as the one for port 0, except that port 1 only has COS 0-2 2030 * traffic. There is no traffic for COS 3-5 of port 1. 2031 */ 2032 #define NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB 0x186e4 2033 /* [R 1] TX FIFO for transmitting data to MAC is empty. */ 2034 #define NIG_REG_P1_TX_MACFIFO_EMPTY 0x18594 2035 /* [RW 1] MCP-to-host path enable. Set this bit to enable the routing of MCP 2036 * packets to BRB LB interface to forward the packet to the host. All 2037 * packets from MCP are forwarded to the network when this bit is cleared - 2038 * regardless of the configured destination in tx_mng_destination register. 2039 */ 2040 #define NIG_REG_P1_TX_MNG_HOST_ENABLE 0x182f8 2041 /* [R 1] FIFO empty status of the MCP TX FIFO used for storing MCP packets 2042 * forwarded to the host. 2043 */ 2044 #define NIG_REG_P1_TX_MNG_HOST_FIFO_EMPTY 0x182b8 2045 /* [RW 1] Pause enable for port0. This register may get 1 only when 2046 * ~safc_enable.safc_enable = 0 and ppp_enable.ppp_enable =0 for the same 2047 * port 2048 */ 2049 #define NIG_REG_PAUSE_ENABLE_0 0x160c0 2050 #define NIG_REG_PAUSE_ENABLE_1 0x160c4 2051 /* [RW 1] Value of this register will be transmitted to port swap when 2052 * ~nig_registers_strap_override.strap_override =1 2053 */ 2054 #define NIG_REG_PORT_SWAP 0x10394 2055 /* [RW 1] PPP enable for port0. This register may get 1 only when 2056 * ~safc_enable.safc_enable = 0 and pause_enable.pause_enable =0 for the 2057 * same port 2058 */ 2059 #define NIG_REG_PPP_ENABLE_0 0x160b0 2060 #define NIG_REG_PPP_ENABLE_1 0x160b4 2061 /* [RW 1] Input enable for RX parser request IF */ 2062 #define NIG_REG_PRS_REQ_IN_EN 0x100b8 2063 /* [R 5] control to serdes - CL45 DEVAD */ 2064 #define NIG_REG_SERDES0_CTRL_MD_DEVAD 0x10370 2065 /* [R 1] control to serdes; 0 - clause 45; 1 - clause 22 */ 2066 #define NIG_REG_SERDES0_CTRL_MD_ST 0x1036c 2067 /* [R 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */ 2068 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374 2069 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */ 2070 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578 2071 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2072 * for port 0 COS0 2073 */ 2074 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0 2075 /* [R 32] Rx statistics : In user packets truncated due to BRB backpressure 2076 * for port 0 COS0 2077 */ 2078 #define NIG_REG_STAT0_BRB_TRUNCATE 0x105f8 2079 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2080 * between 1024 and 1522 bytes for port0 2081 */ 2082 #define NIG_REG_STAT0_EGRESS_MAC_PKT0 0x10750 2083 /* [WB_R 36] Tx statistics : Number of packets from emac0 or bmac0 that 2084 * between 1523 bytes and above for port0 2085 */ 2086 #define NIG_REG_STAT0_EGRESS_MAC_PKT1 0x10760 2087 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure 2088 * for port 1 COS0 2089 */ 2090 #define NIG_REG_STAT1_BRB_DISCARD 0x10628 2091 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2092 * between 1024 and 1522 bytes for port1 2093 */ 2094 #define NIG_REG_STAT1_EGRESS_MAC_PKT0 0x107a0 2095 /* [WB_R 36] Tx statistics : Number of packets from emac1 or bmac1 that 2096 * between 1523 bytes and above for port1 2097 */ 2098 #define NIG_REG_STAT1_EGRESS_MAC_PKT1 0x107b0 2099 /* [WB_R 64] Rx statistics : User octets received for LP */ 2100 #define NIG_REG_STAT2_BRB_OCTET 0x107e0 2101 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328 2102 /* [RW 1] port swap mux selection. If this register equal to 0 then port 2103 * swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then 2104 * ort swap is equal to ~nig_registers_port_swap.port_swap 2105 */ 2106 #define NIG_REG_STRAP_OVERRIDE 0x10398 2107 /* [WB 64] Addresses for TimeSync related registers in the timesync 2108 * generator sub-module. 2109 */ 2110 #define NIG_REG_TIMESYNC_GEN_REG 0x18800 2111 /* [RW 1] output enable for RX_XCM0 IF */ 2112 #define NIG_REG_XCM0_OUT_EN 0x100f0 2113 /* [RW 1] output enable for RX_XCM1 IF */ 2114 #define NIG_REG_XCM1_OUT_EN 0x100f4 2115 /* [R 1] control to xgxs - remote PHY in-band MDIO */ 2116 #define NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST 0x10348 2117 /* [R 5] control to xgxs - CL45 DEVAD */ 2118 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c 2119 /* [R 1] control to xgxs; 0 - clause 45; 1 - clause 22 */ 2120 #define NIG_REG_XGXS0_CTRL_MD_ST 0x10338 2121 /* [R 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */ 2122 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340 2123 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */ 2124 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680 2125 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */ 2126 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684 2127 /* [R 2] selection for XGXS lane of port 0 in NIG_MUX block */ 2128 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8 2129 /* [R 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */ 2130 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0 2131 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT (0x1 << 0) 2132 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1 << 9) 2133 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1 << 15) 2134 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf << 18) 2135 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18 2136 /* [RW 1] Interrupt mask register #0 read/write */ 2137 #define NIG_TSGEN_REG_NIG_TSGEN_INT_MASK 0xcc 2138 /* [R 1] Interrupt register #0 read */ 2139 #define NIG_TSGEN_REG_NIG_TSGEN_INT_STS 0xc0 2140 /* [RC 1] Interrupt register #0 read clear */ 2141 #define NIG_TSGEN_REG_NIG_TSGEN_INT_STS_CLR 0xc4 2142 /* [R 31] Removed for E3 B0 -The upper bound of the weight of COS0 in the 2143 * ETS command arbiter. 2144 */ 2145 #define PBF_REG_COS0_UPPER_BOUND 0x15c05c 2146 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2147 * of port 0. 2148 */ 2149 #define PBF_REG_COS0_UPPER_BOUND_P0 0x15c2cc 2150 /* [RW 31] The upper bound of the weight of COS0 in the ETS command arbiter 2151 * of port 1. 2152 */ 2153 #define PBF_REG_COS0_UPPER_BOUND_P1 0x15c2e4 2154 /* [R 31] Removed for E3 B0 - The weight of COS0 in the ETS command arbiter. */ 2155 #define PBF_REG_COS0_WEIGHT 0x15c054 2156 /* [RW 31] The weight of COS0 in port 0 ETS command arbiter. */ 2157 #define PBF_REG_COS0_WEIGHT_P0 0x15c2a8 2158 /* [RW 31] The weight of COS0 in port 1 ETS command arbiter. */ 2159 #define PBF_REG_COS0_WEIGHT_P1 0x15c2c0 2160 /* [R 31] Removed for E3 B0 -The upper bound of the weight of COS1 in the 2161 * ETS command arbiter. 2162 */ 2163 #define PBF_REG_COS1_UPPER_BOUND 0x15c060 2164 /* [R 31] Removed for E3 B0 - The weight of COS1 in the ETS command arbiter. */ 2165 #define PBF_REG_COS1_WEIGHT 0x15c058 2166 /* [RW 31] The weight of COS1 in port 0 ETS command arbiter. */ 2167 #define PBF_REG_COS1_WEIGHT_P0 0x15c2ac 2168 /* [RW 31] The weight of COS1 in port 1 ETS command arbiter. */ 2169 #define PBF_REG_COS1_WEIGHT_P1 0x15c2c4 2170 /* [RW 31] The weight of COS2 in port 0 ETS command arbiter. */ 2171 #define PBF_REG_COS2_WEIGHT_P0 0x15c2b0 2172 /* [RW 31] The weight of COS2 in port 1 ETS command arbiter. */ 2173 #define PBF_REG_COS2_WEIGHT_P1 0x15c2c8 2174 /* [RW 31] The weight of COS3 in port 0 ETS command arbiter. */ 2175 #define PBF_REG_COS3_WEIGHT_P0 0x15c2b4 2176 /* [RW 31] The weight of COS4 in port 0 ETS command arbiter. */ 2177 #define PBF_REG_COS4_WEIGHT_P0 0x15c2b8 2178 /* [RW 31] The weight of COS5 in port 0 ETS command arbiter. */ 2179 #define PBF_REG_COS5_WEIGHT_P0 0x15c2bc 2180 /* [R 11] Current credit for the LB queue in the tx port buffers in 16 byte 2181 * lines. 2182 */ 2183 #define PBF_REG_CREDIT_LB_Q 0x140338 2184 /* [R 11] Current credit for queue 0 in the tx port buffers in 16 byte 2185 * lines. 2186 */ 2187 #define PBF_REG_CREDIT_Q0 0x14033c 2188 /* [R 11] Current credit for queue 1 in the tx port buffers in 16 byte 2189 * lines. 2190 */ 2191 #define PBF_REG_CREDIT_Q1 0x140340 2192 /* [R 11] Current credit for queue 2 in the tx port buffers in 16 byte 2193 * lines. 2194 */ 2195 #define PBF_REG_CREDIT_Q2 0x140344 2196 /* [R 11] Current credit for queue 3 in the tx port buffers in 16 byte 2197 * lines. 2198 */ 2199 #define PBF_REG_CREDIT_Q3 0x140348 2200 /* [R 11] Current credit for queue 4 in the tx port buffers in 16 byte 2201 * lines. 2202 */ 2203 #define PBF_REG_CREDIT_Q4 0x14034c 2204 /* [R 11] Current credit for queue 5 in the tx port buffers in 16 byte 2205 * lines. 2206 */ 2207 #define PBF_REG_CREDIT_Q5 0x140350 2208 /* [R 1] Removed for E3 B0 - Disable processing further tasks from port 0 2209 * (after ending the current task in process). 2210 */ 2211 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c 2212 /* [R 1] Removed for E3 B0 - Disable processing further tasks from port 1 2213 * (after ending the current task in process). 2214 */ 2215 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060 2216 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2217 * current task in process). 2218 */ 2219 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q0 0x15c1bc 2220 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2221 * current task in process). 2222 */ 2223 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q1 0x15c1c0 2224 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2225 * current task in process). 2226 */ 2227 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q2 0x15c1c4 2228 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2229 * current task in process). 2230 */ 2231 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q3 0x15c1c8 2232 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2233 * current task in process). 2234 */ 2235 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q4 0x15c1cc 2236 /* [RW 1] Disable processing further tasks from port 0 (after ending the 2237 * current task in process). 2238 */ 2239 #define PBF_REG_DISABLE_NEW_TASK_PROC_Q5 0x15c1d0 2240 #define PBF_REG_DISABLE_PF 0x1402e8 2241 #define PBF_REG_DISABLE_VF 0x1402ec 2242 /* [RW 18] For port 0: For each client that is subject to WFQ (the 2243 * corresponding bit is 1); indicates to which of the credit registers this 2244 * client is mapped. For clients which are not credit blocked; their mapping 2245 * is dont care. 2246 */ 2247 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0 0x15c288 2248 /* [RW 9] For port 1: For each client that is subject to WFQ (the 2249 * corresponding bit is 1); indicates to which of the credit registers this 2250 * client is mapped. For clients which are not credit blocked; their mapping 2251 * is dont care. 2252 */ 2253 #define PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1 0x15c28c 2254 /* [RW 6] For port 0: Bit per client to indicate if the client competes in 2255 * the strict priority arbiter directly (corresponding bit = 1); or first 2256 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2257 * lowest priority in the strict-priority arbiter. 2258 */ 2259 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 0x15c278 2260 /* [RW 3] For port 1: Bit per client to indicate if the client competes in 2261 * the strict priority arbiter directly (corresponding bit = 1); or first 2262 * goes to the RR arbiter (corresponding bit = 0); and then competes in the 2263 * lowest priority in the strict-priority arbiter. 2264 */ 2265 #define PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 0x15c27c 2266 /* [RW 6] For port 0: Bit per client to indicate if the client is subject to 2267 * WFQ credit blocking (corresponding bit = 1). 2268 */ 2269 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 0x15c280 2270 /* [RW 3] For port 0: Bit per client to indicate if the client is subject to 2271 * WFQ credit blocking (corresponding bit = 1). 2272 */ 2273 #define PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 0x15c284 2274 /* [RW 16] For port 0: The number of strict priority arbitration slots 2275 * between 2 RR arbitration slots. A value of 0 means no strict priority 2276 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2277 * arbiter. 2278 */ 2279 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 0x15c2a0 2280 /* [RW 16] For port 1: The number of strict priority arbitration slots 2281 * between 2 RR arbitration slots. A value of 0 means no strict priority 2282 * cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR 2283 * arbiter. 2284 */ 2285 #define PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 0x15c2a4 2286 /* [RW 18] For port 0: Indicates which client is connected to each priority 2287 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2288 * priority 5 is the lowest; to which the RR output is connected to (this is 2289 * not configurable). 2290 */ 2291 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 0x15c270 2292 /* [RW 9] For port 1: Indicates which client is connected to each priority 2293 * in the strict-priority arbiter. Priority 0 is the highest priority, and 2294 * priority 5 is the lowest; to which the RR output is connected to (this is 2295 * not configurable). 2296 */ 2297 #define PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 0x15c274 2298 /* [R 1] Removed for E3 B0 - Indicates that ETS is performed between the 2299 * COSes in the command arbiter. If reset strict priority w/ anti-starvation 2300 * will be performed w/o WFQ. 2301 */ 2302 #define PBF_REG_ETS_ENABLED 0x15c050 2303 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2304 * Ethernet header. 2305 */ 2306 #define PBF_REG_HDRS_AFTER_BASIC 0x15c0a8 2307 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2308 #define PBF_REG_HDRS_AFTER_TAG_0 0x15c0b8 2309 /* [R 1] Removed for E3 B0 - Indicates which COS is conncted to the highest 2310 * priority in the command arbiter. 2311 */ 2312 #define PBF_REG_HIGH_PRIORITY_COS_NUM 0x15c04c 2313 /* [RW 11] Initial credit for the LB queue in the tx port buffers in 16 byte 2314 * lines. 2315 */ 2316 #define PBF_REG_INIT_CRD_LB_Q 0x15c248 2317 /* [RW 11] Initial credit for queue 0 in the tx port buffers in 16 byte 2318 * lines. 2319 */ 2320 #define PBF_REG_INIT_CRD_Q0 0x15c230 2321 /* [RW 11] Initial credit for queue 1 in the tx port buffers in 16 byte 2322 * lines. 2323 */ 2324 #define PBF_REG_INIT_CRD_Q1 0x15c234 2325 /* [RW 11] Initial credit for queue 2 in the tx port buffers in 16 byte 2326 * lines. 2327 */ 2328 #define PBF_REG_INIT_CRD_Q2 0x15c238 2329 /* [RW 11] Initial credit for queue 3 in the tx port buffers in 16 byte 2330 * lines. 2331 */ 2332 #define PBF_REG_INIT_CRD_Q3 0x15c23c 2333 /* [RW 11] Initial credit for queue 4 in the tx port buffers in 16 byte 2334 * lines. 2335 */ 2336 #define PBF_REG_INIT_CRD_Q4 0x15c240 2337 /* [RW 11] Initial credit for queue 5 in the tx port buffers in 16 byte 2338 * lines. 2339 */ 2340 #define PBF_REG_INIT_CRD_Q5 0x15c244 2341 /* [R 1] Removed for E3 B0 - Init bit for port 0. When set the initial 2342 * credit of port 0 is copied to the credit register. Should be set and then 2343 * reset after the configuration of the port has ended. 2344 */ 2345 #define PBF_REG_INIT_P0 0x140004 2346 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2347 * the LB queue. Reset upon init. 2348 */ 2349 #define PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q 0x140354 2350 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2351 * queue 0. Reset upon init. 2352 */ 2353 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 0x140358 2354 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2355 * queue 1. Reset upon init. 2356 */ 2357 #define PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 0x14035c 2358 /* [RW 1] Enable for mac interface 0. */ 2359 #define PBF_REG_MAC_IF0_ENABLE 0x140030 2360 /* [RW 6] Bit-map indicating which headers must appear in the packet */ 2361 #define PBF_REG_MUST_HAVE_HDRS 0x15c0c4 2362 /* [R 16] Removed for E3 B0 - The number of strict priority arbitration 2363 * slots between 2 RR arbitration slots. A value of 0 means no strict 2364 * priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a 2365 * RR arbiter. 2366 */ 2367 #define PBF_REG_NUM_STRICT_ARB_SLOTS 0x15c064 2368 /* [R 11] Removed for E3 B0 - Port 0 threshold used by arbiter in 16 byte 2369 * lines used when pause not suppoterd. 2370 */ 2371 #define PBF_REG_P0_ARB_THRSH 0x1400e4 2372 /* [R 11] Removed for E3 B0 - Current credit for port 0 in the tx port 2373 * buffers in 16 byte lines. 2374 */ 2375 #define PBF_REG_P0_CREDIT 0x140200 2376 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2377 * buffers in 16 byte lines. 2378 */ 2379 #define PBF_REG_P0_INIT_CRD 0x1400d0 2380 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2381 * port 0. Reset upon init. 2382 */ 2383 #define PBF_REG_P0_INTERNAL_CRD_FREED_CNT 0x140308 2384 /* [R 1] Removed for E3 B0 - Indication that pause is enabled for port 0. */ 2385 #define PBF_REG_P0_PAUSE_ENABLE 0x140014 2386 /* [R 8] Removed for E3 B0 - Number of tasks in port 0 task queue. */ 2387 #define PBF_REG_P0_TASK_CNT 0x140204 2388 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2389 * freed from the task queue of port 0. Reset upon init. 2390 */ 2391 #define PBF_REG_P0_TQ_LINES_FREED_CNT 0x1402f0 2392 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 0. */ 2393 #define PBF_REG_P0_TQ_OCCUPANCY 0x1402fc 2394 /* [R 11] Removed for E3 B0 - Current credit for port 1 in the tx port 2395 * buffers in 16 byte lines. 2396 */ 2397 #define PBF_REG_P1_CREDIT 0x140208 2398 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2399 * buffers in 16 byte lines. 2400 */ 2401 #define PBF_REG_P1_INIT_CRD 0x1400d4 2402 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2403 * port 1. Reset upon init. 2404 */ 2405 #define PBF_REG_P1_INTERNAL_CRD_FREED_CNT 0x14030c 2406 /* [R 8] Removed for E3 B0 - Number of tasks in port 1 task queue. */ 2407 #define PBF_REG_P1_TASK_CNT 0x14020c 2408 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2409 * freed from the task queue of port 1. Reset upon init. 2410 */ 2411 #define PBF_REG_P1_TQ_LINES_FREED_CNT 0x1402f4 2412 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 1. */ 2413 #define PBF_REG_P1_TQ_OCCUPANCY 0x140300 2414 /* [R 11] Removed for E3 B0 - Current credit for port 4 in the tx port 2415 * buffers in 16 byte lines. 2416 */ 2417 #define PBF_REG_P4_CREDIT 0x140210 2418 /* [R 11] Removed for E3 B0 - Initial credit for port 0 in the tx port 2419 * buffers in 16 byte lines. 2420 */ 2421 #define PBF_REG_P4_INIT_CRD 0x1400e0 2422 /* [R 32] Cyclic counter for the amount credits in 16 bytes lines added for 2423 * port 4. Reset upon init. 2424 */ 2425 #define PBF_REG_P4_INTERNAL_CRD_FREED_CNT 0x140310 2426 /* [R 8] Removed for E3 B0 - Number of tasks in port 4 task queue. */ 2427 #define PBF_REG_P4_TASK_CNT 0x140214 2428 /* [R 32] Removed for E3 B0 - Cyclic counter for number of 8 byte lines 2429 * freed from the task queue of port 4. Reset upon init. 2430 */ 2431 #define PBF_REG_P4_TQ_LINES_FREED_CNT 0x1402f8 2432 /* [R 12] Number of 8 bytes lines occupied in the task queue of port 4. */ 2433 #define PBF_REG_P4_TQ_OCCUPANCY 0x140304 2434 /* [RW 7] Interrupt mask register #0 read/write */ 2435 #define PBF_REG_PBF_INT_MASK 0x1401d4 2436 /* [R 7] Interrupt register #0 read */ 2437 #define PBF_REG_PBF_INT_STS 0x1401c8 2438 /* [RC 7] Interrupt register #0 read clear */ 2439 #define PBF_REG_PBF_INT_STS_CLR 0x1401cc 2440 /* [RW 28] Parity mask register #0 read/write */ 2441 #define PBF_REG_PBF_PRTY_MASK 0x1401e4 2442 /* [R 28] Parity register #0 read */ 2443 #define PBF_REG_PBF_PRTY_STS 0x1401d8 2444 /* [RC 28] Parity register #0 read clear */ 2445 #define PBF_REG_PBF_PRTY_STS_CLR 0x1401dc 2446 /* [RW 16] The Ethernet type value for L2 tag 0 */ 2447 #define PBF_REG_TAG_ETHERTYPE_0 0x15c090 2448 /* [RW 4] The length of the info field for L2 tag 0. The length is between 2449 * 2B and 14B; in 2B granularity 2450 */ 2451 #define PBF_REG_TAG_LEN_0 0x15c09c 2452 /* [R 8] Number of tasks in queue 0 task queue. */ 2453 #define PBF_REG_TASK_CNT_LB_Q 0x140370 2454 /* [R 8] Number of tasks in queue 0 task queue. */ 2455 #define PBF_REG_TASK_CNT_Q0 0x140374 2456 /* [R 8] Number of tasks in queue 0 task queue. */ 2457 #define PBF_REG_TASK_CNT_Q1 0x140378 2458 /* [R 8] Number of tasks in queue 0 task queue. */ 2459 #define PBF_REG_TASK_CNT_Q2 0x14037c 2460 /* [R 8] Number of tasks in queue 0 task queue. */ 2461 #define PBF_REG_TASK_CNT_Q3 0x140380 2462 /* [R 8] Number of tasks in queue 0 task queue. */ 2463 #define PBF_REG_TASK_CNT_Q4 0x140384 2464 /* [R 8] Number of tasks in queue 0 task queue. */ 2465 #define PBF_REG_TASK_CNT_Q5 0x140388 2466 /* [R 32] Cyclic counter for number of 8 byte lines freed from the LB task 2467 * queue. Reset upon init. 2468 */ 2469 #define PBF_REG_TQ_LINES_FREED_CNT_LB_Q 0x14038c 2470 /* [R 32] Cyclic counter for number of 8 byte lines freed from the task 2471 * queue 0. Reset upon init. 2472 */ 2473 #define PBF_REG_TQ_LINES_FREED_CNT_Q0 0x140390 2474 /* [R 32] Cyclic counter for number of 8 byte lines freed from task queue 1. 2475 * Reset upon init. 2476 */ 2477 #define PBF_REG_TQ_LINES_FREED_CNT_Q1 0x140394 2478 /* [R 13] Number of 8 bytes lines occupied in the task queue of the LB 2479 * queue. 2480 */ 2481 #define PBF_REG_TQ_OCCUPANCY_LB_Q 0x1403a8 2482 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 0. */ 2483 #define PBF_REG_TQ_OCCUPANCY_Q0 0x1403ac 2484 /* [R 13] Number of 8 bytes lines occupied in the task queue of queue 1. */ 2485 #define PBF_REG_TQ_OCCUPANCY_Q1 0x1403b0 2486 /* [RW 16] One of 8 values that should be compared to type in Ethernet 2487 * parsing. If there is a match; the field after Ethernet is the first VLAN. 2488 * Reset value is 0x8100 which is the standard VLAN type. Note that when 2489 * checking second VLAN; type is compared only to 0x8100. 2490 */ 2491 #define PBF_REG_VLAN_TYPE_0 0x15c06c 2492 /* [RW 2] Interrupt mask register #0 read/write */ 2493 #define PB_REG_PB_INT_MASK 0x28 2494 /* [R 2] Interrupt register #0 read */ 2495 #define PB_REG_PB_INT_STS 0x1c 2496 /* [RC 2] Interrupt register #0 read clear */ 2497 #define PB_REG_PB_INT_STS_CLR 0x20 2498 /* [RW 4] Parity mask register #0 read/write */ 2499 #define PB_REG_PB_PRTY_MASK 0x38 2500 /* [R 4] Parity register #0 read */ 2501 #define PB_REG_PB_PRTY_STS 0x2c 2502 /* [RC 4] Parity register #0 read clear */ 2503 #define PB_REG_PB_PRTY_STS_CLR 0x30 2504 #define PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR (0x1 << 0) 2505 #define PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW (0x1 << 8) 2506 #define PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR (0x1 << 1) 2507 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN (0x1 << 6) 2508 #define PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN (0x1 << 7) 2509 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN (0x1 << 4) 2510 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN (0x1 << 3) 2511 #define PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN (0x1 << 5) 2512 #define PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN (0x1 << 2) 2513 /* [R 8] Config space A attention dirty bits. Each bit indicates that the 2514 * corresponding PF generates config space A attention. Set by PXP. Reset by 2515 * MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits 2516 * from both paths. 2517 */ 2518 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST 0x9010 2519 /* [R 8] Config space B attention dirty bits. Each bit indicates that the 2520 * corresponding PF generates config space B attention. Set by PXP. Reset by 2521 * MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits 2522 * from both paths. 2523 */ 2524 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST 0x9014 2525 /* [R 8] FLR request attention dirty bits for PFs 0 to 7. Each bit indicates 2526 * that the FLR register of the corresponding PF was set. Set by PXP. Reset 2527 * by MCP writing 1 to flr_request_pf_7_0_clr. Note: register contains bits 2528 * from both paths. 2529 */ 2530 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0 0x9028 2531 /* [W 8] FLR request attention dirty bits clear for PFs 0 to 7. MCP writes 1 2532 * to a bit in this register in order to clear the corresponding bit in 2533 * flr_request_pf_7_0 register. Note: register contains bits from both 2534 * paths. 2535 */ 2536 #define PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR 0x9418 2537 /* [R 32] FLR request attention dirty bits for VFs 96 to 127. Each bit 2538 * indicates that the FLR register of the corresponding VF was set. Set by 2539 * PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr. 2540 */ 2541 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96 0x9024 2542 /* [R 32] FLR request attention dirty bits for VFs 0 to 31. Each bit 2543 * indicates that the FLR register of the corresponding VF was set. Set by 2544 * PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr. 2545 */ 2546 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0 0x9018 2547 /* [R 32] FLR request attention dirty bits for VFs 32 to 63. Each bit 2548 * indicates that the FLR register of the corresponding VF was set. Set by 2549 * PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr. 2550 */ 2551 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32 0x901c 2552 /* [R 32] FLR request attention dirty bits for VFs 64 to 95. Each bit 2553 * indicates that the FLR register of the corresponding VF was set. Set by 2554 * PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr. 2555 */ 2556 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64 0x9020 2557 /* [R 8] Each bit indicates an incorrect behavior in user RX interface. Bit 2558 * 0 - Target memory read arrived with a correctable error. Bit 1 - Target 2559 * memory read arrived with an uncorrectable error. Bit 2 - Configuration RW 2560 * arrived with a correctable error. Bit 3 - Configuration RW arrived with 2561 * an uncorrectable error. Bit 4 - Completion with Configuration Request 2562 * Retry Status. Bit 5 - Expansion ROM access received with a write request. 2563 * Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and 2564 * pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; 2565 * and pcie_rx_last not asserted. 2566 */ 2567 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS 0x9068 2568 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER 0x942c 2569 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ 0x9430 2570 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE 0x9438 2571 /* [W 7] Writing 1 to each bit in this register clears a corresponding error 2572 * details register and enables logging new error details. Bit 0 - clears 2573 * INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears 2574 * TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS 2575 * TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32 2576 * TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL; Bit 3 - 2577 * clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears 2578 * VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6 2579 * - clears TCPL_IN_TWO_RCBS_DETAILS. 2580 */ 2581 #define PGLUE_B_REG_LATCHED_ERRORS_CLR 0x943c 2582 /* [RW 11] Interrupt mask register #0 read/write */ 2583 #define PGLUE_B_REG_PGLUE_B_INT_MASK 0x92a4 2584 /* [R 11] Interrupt register #0 read */ 2585 #define PGLUE_B_REG_PGLUE_B_INT_STS 0x9298 2586 /* [RC 11] Interrupt register #0 read clear */ 2587 #define PGLUE_B_REG_PGLUE_B_INT_STS_CLR 0x929c 2588 /* [RW 2] Parity mask register #0 read/write */ 2589 #define PGLUE_B_REG_PGLUE_B_PRTY_MASK 0x92b4 2590 /* [R 2] Parity register #0 read */ 2591 #define PGLUE_B_REG_PGLUE_B_PRTY_STS 0x92a8 2592 /* [RC 2] Parity register #0 read clear */ 2593 #define PGLUE_B_REG_PGLUE_B_PRTY_STS_CLR 0x92ac 2594 /* [R 13] Details of first request received with error. [2:0] - PFID. [3] - 2595 * VF_VALID. [9:4] - VFID. [11:10] - Error Code - 0 - Indicates Completion 2596 * Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - 2597 * completer abort. 3 - Illegal value for this field. [12] valid - indicates 2598 * if there was a completion error since the last time this register was 2599 * cleared. 2600 */ 2601 #define PGLUE_B_REG_RX_ERR_DETAILS 0x9080 2602 /* [R 18] Details of first ATS Translation Completion request received with 2603 * error. [2:0] - PFID. [3] - VF_VALID. [9:4] - VFID. [11:10] - Error Code - 2604 * 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - 2605 * unsupported request. 2 - completer abort. 3 - Illegal value for this 2606 * field. [16:12] - ATC OTB EntryID. [17] valid - indicates if there was a 2607 * completion error since the last time this register was cleared. 2608 */ 2609 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS 0x9084 2610 /* [W 8] Debug only - Shadow BME bits clear for PFs 0 to 7. MCP writes 1 to 2611 * a bit in this register in order to clear the corresponding bit in 2612 * shadow_bme_pf_7_0 register. MCP should never use this unless a 2613 * work-around is needed. Note: register contains bits from both paths. 2614 */ 2615 #define PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR 0x9458 2616 /* [R 8] SR IOV disabled attention dirty bits. Each bit indicates that the 2617 * VF enable register of the corresponding PF is written to 0 and was 2618 * previously 1. Set by PXP. Reset by MCP writing 1 to 2619 * sr_iov_disabled_request_clr. Note: register contains bits from both 2620 * paths. 2621 */ 2622 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x9030 2623 /* [R 32] Indicates the status of tags 32-63. 0 - tags is used - read 2624 * completion did not return yet. 1 - tag is unused. Same functionality as 2625 * pxp2_registers_pgl_exp_rom_data2 for tags 0-31. 2626 */ 2627 #define PGLUE_B_REG_TAGS_63_32 0x9244 2628 /* [R 32] Address [31:0] of first read request not submitted due to error */ 2629 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0 0x9098 2630 /* [R 32] Address [63:32] of first read request not submitted due to error */ 2631 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32 0x909c 2632 /* [R 31] Details of first read request not submitted due to error. [4:0] 2633 * VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. 2634 * [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] - 2635 * VFID. 2636 */ 2637 #define PGLUE_B_REG_TX_ERR_RD_DETAILS 0x90a0 2638 /* [R 26] Details of first read request not submitted due to error. [15:0] 2639 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2640 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2641 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2642 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2643 * indicates if there was a request not submitted due to error since the 2644 * last time this register was cleared. 2645 */ 2646 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2 0x90a4 2647 /* [R 32] Address [31:0] of first write request not submitted due to error */ 2648 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0 0x9088 2649 /* [R 32] Address [63:32] of first write request not submitted due to error */ 2650 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32 0x908c 2651 /* [R 31] Details of first write request not submitted due to error. [4:0] 2652 * VQID. [20:8] - Length in bytes. [23:21] - PFID. [24] - VF_VALID. [30:25] 2653 * - VFID. 2654 */ 2655 #define PGLUE_B_REG_TX_ERR_WR_DETAILS 0x9090 2656 /* [R 26] Details of first write request not submitted due to error. [15:0] 2657 * Request ID. [19:16] client ID. [20] - last SR. [24:21] - Error type - 2658 * [21] - Indicates was_error was set; [22] - Indicates BME was cleared; 2659 * [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent 2660 * PF FLR_request or IOV_disable_request dirty bit is set. [25] valid - 2661 * indicates if there was a request not submitted due to error since the 2662 * last time this register was cleared. 2663 */ 2664 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2 0x9094 2665 /* [R 26] Details of first target VF request accessing VF GRC space that 2666 * failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. 2667 * [21:16] VFID. [24:22] - PFID. [25] valid - indicates if there was a 2668 * request accessing VF GRC space that failed permission check since the 2669 * last time this register was cleared. Permission checks are: function 2670 * permission; R/W permission; address range permission. 2671 */ 2672 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS 0x9234 2673 /* [R 31] Details of first target VF request with length violation (too many 2674 * DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). 2675 * [14:13] BAR. [20:15] VFID. [23:21] - PFID. [29:24] - Length in DWs. [30] 2676 * valid - indicates if there was a request with length violation since the 2677 * last time this register was cleared. Length violations: length of more 2678 * than 2DWs; length of 2DWs and address not QW aligned; window is GRC and 2679 * length is more than 1 DW. 2680 */ 2681 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS 0x9230 2682 /* [R 8] Was_error indication dirty bits for PFs 0 to 7. Each bit indicates 2683 * that there was a completion with uncorrectable error for the 2684 * corresponding PF. Set by PXP. Reset by MCP writing 1 to 2685 * was_error_pf_7_0_clr. 2686 */ 2687 #define PGLUE_B_REG_WAS_ERROR_PF_7_0 0x907c 2688 /* [W 8] Was_error indication dirty bits clear for PFs 0 to 7. MCP writes 1 2689 * to a bit in this register in order to clear the corresponding bit in 2690 * flr_request_pf_7_0 register. 2691 */ 2692 #define PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR 0x9470 2693 /* [R 32] Was_error indication dirty bits for VFs 96 to 127. Each bit 2694 * indicates that there was a completion with uncorrectable error for the 2695 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2696 * was_error_vf_127_96_clr. 2697 */ 2698 #define PGLUE_B_REG_WAS_ERROR_VF_127_96 0x9078 2699 /* [W 32] Was_error indication dirty bits clear for VFs 96 to 127. MCP 2700 * writes 1 to a bit in this register in order to clear the corresponding 2701 * bit in was_error_vf_127_96 register. 2702 */ 2703 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR 0x9474 2704 /* [R 32] Was_error indication dirty bits for VFs 0 to 31. Each bit 2705 * indicates that there was a completion with uncorrectable error for the 2706 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2707 * was_error_vf_31_0_clr. 2708 */ 2709 #define PGLUE_B_REG_WAS_ERROR_VF_31_0 0x906c 2710 /* [W 32] Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 2711 * 1 to a bit in this register in order to clear the corresponding bit in 2712 * was_error_vf_31_0 register. 2713 */ 2714 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR 0x9478 2715 /* [R 32] Was_error indication dirty bits for VFs 32 to 63. Each bit 2716 * indicates that there was a completion with uncorrectable error for the 2717 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2718 * was_error_vf_63_32_clr. 2719 */ 2720 #define PGLUE_B_REG_WAS_ERROR_VF_63_32 0x9070 2721 /* [W 32] Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 2722 * 1 to a bit in this register in order to clear the corresponding bit in 2723 * was_error_vf_63_32 register. 2724 */ 2725 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR 0x947c 2726 /* [R 32] Was_error indication dirty bits for VFs 64 to 95. Each bit 2727 * indicates that there was a completion with uncorrectable error for the 2728 * corresponding VF. Set by PXP. Reset by MCP writing 1 to 2729 * was_error_vf_95_64_clr. 2730 */ 2731 #define PGLUE_B_REG_WAS_ERROR_VF_95_64 0x9074 2732 /* [W 32] Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 2733 * 1 to a bit in this register in order to clear the corresponding bit in 2734 * was_error_vf_95_64 register. 2735 */ 2736 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR 0x9480 2737 #define PRS_REG_A_PRSU_20 0x40134 2738 /* [R 8] debug only: CFC load request current credit. Transaction based. */ 2739 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164 2740 /* [R 8] debug only: CFC search request current credit. Transaction based. */ 2741 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168 2742 /* [RW 6] The initial credit for the search message to the CFC interface. 2743 * Credit is transaction based. 2744 */ 2745 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c 2746 /* [RW 24] CID for port 0 if no match */ 2747 #define PRS_REG_CID_PORT_0 0x400fc 2748 /* [RW 1] Indicates if in outer vlan mode. 0=non-outer-vlan mode; 1 = outer 2749 * vlan mode. 2750 */ 2751 #define PRS_REG_E1HOV_MODE 0x401c8 2752 /* [R 6] Bit-map indicating which L2 hdrs may appear after the basic 2753 * Ethernet header. 2754 */ 2755 #define PRS_REG_HDRS_AFTER_BASIC 0x40238 2756 /* [RW 6] Bit-map indicating which L2 hdrs may appear after the basic 2757 * Ethernet header for port 0 packets. 2758 */ 2759 #define PRS_REG_HDRS_AFTER_BASIC_PORT_0 0x40270 2760 #define PRS_REG_HDRS_AFTER_BASIC_PORT_1 0x40290 2761 /* [R 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 */ 2762 #define PRS_REG_HDRS_AFTER_TAG_0 0x40248 2763 /* [RW 6] Bit-map indicating which L2 hdrs may appear after L2 tag 0 for 2764 * port 0 packets 2765 */ 2766 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_0 0x40280 2767 #define PRS_REG_HDRS_AFTER_TAG_0_PORT_1 0x402a0 2768 /* [R 6] Bit-map indicating which headers must appear in the packet */ 2769 #define PRS_REG_MUST_HAVE_HDRS 0x40254 2770 /* [RW 6] Bit-map indicating which headers must appear in the packet for 2771 * port 0 packets 2772 */ 2773 #define PRS_REG_MUST_HAVE_HDRS_PORT_0 0x4028c 2774 #define PRS_REG_MUST_HAVE_HDRS_PORT_1 0x402ac 2775 #define PRS_REG_NIC_MODE 0x40138 2776 /* [ST 24] The number of input packets */ 2777 #define PRS_REG_NUM_OF_PACKETS 0x40124 2778 /* [R 2] debug only: Number of pending requests for CAC on port 0. */ 2779 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174 2780 /* [R 2] debug only: Number of pending requests for header parsing. */ 2781 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170 2782 /* [RW 1] Interrupt mask register #0 read/write */ 2783 #define PRS_REG_PRS_INT_MASK 0x40194 2784 /* [R 1] Interrupt register #0 read */ 2785 #define PRS_REG_PRS_INT_STS 0x40188 2786 /* [RC 1] Interrupt register #0 read clear */ 2787 #define PRS_REG_PRS_INT_STS_CLR 0x4018c 2788 /* [RW 8] Parity mask register #0 read/write */ 2789 #define PRS_REG_PRS_PRTY_MASK 0x401a4 2790 /* [R 8] Parity register #0 read */ 2791 #define PRS_REG_PRS_PRTY_STS 0x40198 2792 /* [RC 8] Parity register #0 read clear */ 2793 #define PRS_REG_PRS_PRTY_STS_CLR 0x4019c 2794 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this 2795 * serail number was released by SDM but cannot be used because a previous 2796 * serial number was not released. 2797 */ 2798 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154 2799 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this 2800 * serail number was released by SDM but cannot be used because a previous 2801 * serial number was not released. 2802 */ 2803 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158 2804 /* [R 4] debug only: SRC current credit. Transaction based. */ 2805 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c 2806 /* [RW 16] The Ethernet type value for L2 tag 0 */ 2807 #define PRS_REG_TAG_ETHERTYPE_0 0x401d4 2808 /* [RW 4] The length of the info field for L2 tag 0. The length is between 2809 * 2B and 14B; in 2B granularity 2810 */ 2811 #define PRS_REG_TAG_LEN_0 0x4022c 2812 /* [R 8] debug only: TCM current credit. Cycle based. */ 2813 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160 2814 /* [R 8] debug only: TSDM current credit. Transaction based. */ 2815 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c 2816 /* [RW 16] One of 8 values that should be compared to type in Ethernet 2817 * parsing. If there is a match; the field after Ethernet is the first VLAN. 2818 * Reset value is 0x8100 which is the standard VLAN type. Note that when 2819 * checking second VLAN; type is compared only to 0x8100. 2820 */ 2821 #define PRS_REG_VLAN_TYPE_0 0x401a8 2822 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT (0x1 << 19) 2823 #define PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF (0x1 << 20) 2824 #define PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN (0x1 << 22) 2825 #define PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED (0x1 << 23) 2826 #define PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED (0x1 << 24) 2827 #define PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR (0x1 << 7) 2828 #define PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR (0x1 << 7) 2829 /* [R 7] Debug only: Number of used entries in the data FIFO */ 2830 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c 2831 /* [R 7] Debug only: Number of used entries in the header FIFO */ 2832 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478 2833 #define PXP2_REG_PGL_ADDR_88_F0 0x120534 2834 /* [R 32] GRC address for configuration access to PCIE config address 0x88. 2835 * any write to this PCIE address will cause a GRC write access to the 2836 * address that's in t this register 2837 */ 2838 #define PXP2_REG_PGL_ADDR_88_F1 0x120544 2839 #define PXP2_REG_PGL_ADDR_8C_F0 0x120538 2840 /* [R 32] GRC address for configuration access to PCIE config address 0x8c. 2841 * any write to this PCIE address will cause a GRC write access to the 2842 * address that's in t this register 2843 */ 2844 #define PXP2_REG_PGL_ADDR_8C_F1 0x120548 2845 #define PXP2_REG_PGL_ADDR_90_F0 0x12053c 2846 /* [R 32] GRC address for configuration access to PCIE config address 0x90. 2847 * any write to this PCIE address will cause a GRC write access to the 2848 * address that's in t this register 2849 */ 2850 #define PXP2_REG_PGL_ADDR_90_F1 0x12054c 2851 #define PXP2_REG_PGL_ADDR_94_F0 0x120540 2852 /* [R 32] GRC address for configuration access to PCIE config address 0x94. 2853 * any write to this PCIE address will cause a GRC write access to the 2854 * address that's in t this register 2855 */ 2856 #define PXP2_REG_PGL_ADDR_94_F1 0x120550 2857 /* [RW 32] third dword data of expansion rom request. this register is 2858 * special. reading from it provides a vector outstanding read requests. if 2859 * a bit is zero it means that a read request on the corresponding tag did 2860 * not finish yet (not all completions have arrived for it) 2861 */ 2862 #define PXP2_REG_PGL_EXP_ROM2 0x120808 2863 /* [RW 16] this field allows one function to pretend being another function 2864 * when accessing any BAR mapped resource within the device. the value of 2865 * the field is the number of the function that will be accessed 2866 * effectively. after software write to this bit it must read it in order to 2867 * know that the new value is updated. Bits [15] - force. Bits [14] - path 2868 * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits 2869 * [2:0] - PFID. 2870 */ 2871 #define PXP2_REG_PGL_PRETEND_FUNC_F0 0x120674 2872 /* [RW 16] this field allows one function to pretend being another function 2873 * when accessing any BAR mapped resource within the device. the value of 2874 * the field is the number of the function that will be accessed 2875 * effectively. after software write to this bit it must read it in order to 2876 * know that the new value is updated. Bits [15] - force. Bits [14] - path 2877 * ID. Bits [13:10] - Reserved. Bits [9:4] - VFID. Bits [3] - VF valid. Bits 2878 * [2:0] - PFID. 2879 */ 2880 #define PXP2_REG_PGL_PRETEND_FUNC_F1 0x120678 2881 /* [R 1] this bit indicates that a read request was blocked because of 2882 * bus_master_en was deasserted 2883 */ 2884 #define PXP2_REG_PGL_READ_BLOCKED 0x120568 2885 #define PXP2_REG_PGL_TAGS_LIMIT 0x1205a8 2886 /* [R 21] debug only */ 2887 #define PXP2_REG_PGL_TXW_CDTS 0x12052c 2888 /* [R 1] this bit indicates that a write request was blocked because of 2889 * bus_master_en was deasserted 2890 */ 2891 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564 2892 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0 2893 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4 2894 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8 2895 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4 2896 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228 2897 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8 2898 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4 2899 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8 2900 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc 2901 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0 2902 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c 2903 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0 2904 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4 2905 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8 2906 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4 2907 #define PXP2_REG_PSWRQ_BW_L28 0x120318 2908 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8 2909 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4 2910 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8 2911 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc 2912 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0 2913 #define PXP2_REG_PSWRQ_BW_RD 0x120324 2914 #define PXP2_REG_PSWRQ_BW_UB1 0x120238 2915 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c 2916 #define PXP2_REG_PSWRQ_BW_UB11 0x120260 2917 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c 2918 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0 2919 #define PXP2_REG_PSWRQ_BW_UB3 0x120240 2920 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c 2921 #define PXP2_REG_PSWRQ_BW_UB7 0x120250 2922 #define PXP2_REG_PSWRQ_BW_UB8 0x120254 2923 #define PXP2_REG_PSWRQ_BW_UB9 0x120258 2924 #define PXP2_REG_PSWRQ_BW_WR 0x120328 2925 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000 2926 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038 2927 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054 2928 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c 2929 #define PXP2_REG_PSWRQ_TSDM0_L2P 0x1200e0 2930 /* [RW 32] Interrupt mask register #0 read/write */ 2931 #define PXP2_REG_PXP2_INT_MASK_0 0x120578 2932 #define PXP2_REG_PXP2_INT_MASK_1 0x120614 2933 /* [R 32] Interrupt register #0 read */ 2934 #define PXP2_REG_PXP2_INT_STS_0 0x12056c 2935 #define PXP2_REG_PXP2_INT_STS_1 0x120608 2936 /* [RC 32] Interrupt register #0 read clear */ 2937 #define PXP2_REG_PXP2_INT_STS_CLR_0 0x120570 2938 #define PXP2_REG_PXP2_INT_STS_CLR_1 0x12060c 2939 /* [RW 32] Parity mask register #0 read/write */ 2940 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588 2941 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598 2942 /* [R 32] Parity register #0 read */ 2943 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c 2944 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c 2945 /* [RC 32] Parity register #0 read clear */ 2946 #define PXP2_REG_PXP2_PRTY_STS_CLR_0 0x120580 2947 #define PXP2_REG_PXP2_PRTY_STS_CLR_1 0x120590 2948 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives 2949 * indication about backpressure) 2950 */ 2951 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424 2952 /* [R 8] Debug only: The blocks counter - number of unused block ids */ 2953 #define PXP2_REG_RD_BLK_CNT 0x120418 2954 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer. 2955 * Must be bigger than 6. Normally should not be changed. 2956 */ 2957 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c 2958 /* [RW 2] CDU byte swapping mode configuration for master read requests */ 2959 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404 2960 /* [R 29] Details of first request with error on receive side: [15:0] - Echo 2961 * ID. [28:16] - sub-request length plus start_offset_2_0 minus 1. 2962 */ 2963 #define PXP2_REG_RD_CPL_ERR_DETAILS 0x120778 2964 /* [R 10] Details of first request with error on receive side: [4:0] - VQ 2965 * ID. [8:5] - client ID. [9] - valid - indicates if there was a completion 2966 * error since the last time this register was read. 2967 */ 2968 #define PXP2_REG_RD_CPL_ERR_DETAILS2 0x12077c 2969 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */ 2970 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374 2971 /* [R 1] PSWRD internal memories initialization is done */ 2972 #define PXP2_REG_RD_INIT_DONE 0x120370 2973 /* [R 1] Debug only: Indication if delivery ports are idle */ 2974 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c 2975 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420 2976 /* [RW 2] QM byte swapping mode configuration for master read requests */ 2977 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8 2978 /* [RW 2] SRC byte swapping mode configuration for master read requests */ 2979 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400 2980 /* [R 7] Debug only: The SR counter - number of unused sub request ids */ 2981 #define PXP2_REG_RD_SR_CNT 0x120414 2982 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must 2983 * be bigger than 1. Normally should not be changed. 2984 */ 2985 #define PXP2_REG_RD_SR_NUM_CFG 0x120408 2986 /* [RW 1] Signals the PSWRD block to start initializing internal memories */ 2987 #define PXP2_REG_RD_START_INIT 0x12036c 2988 /* [RW 2] TM byte swapping mode configuration for master read requests */ 2989 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc 2990 /* [RW 10] Bandwidth addition to VQ0 write requests */ 2991 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc 2992 /* [RW 10] Bandwidth addition to VQ12 read requests */ 2993 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec 2994 /* [RW 10] Bandwidth addition to VQ13 read requests */ 2995 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0 2996 /* [RW 10] Bandwidth addition to VQ14 read requests */ 2997 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4 2998 /* [RW 10] Bandwidth addition to VQ15 read requests */ 2999 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8 3000 /* [RW 10] Bandwidth addition to VQ16 read requests */ 3001 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc 3002 /* [RW 10] Bandwidth addition to VQ17 read requests */ 3003 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200 3004 /* [RW 10] Bandwidth addition to VQ18 read requests */ 3005 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204 3006 /* [RW 10] Bandwidth addition to VQ19 read requests */ 3007 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208 3008 /* [RW 10] Bandwidth addition to VQ20 read requests */ 3009 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c 3010 /* [RW 10] Bandwidth addition to VQ22 read requests */ 3011 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210 3012 /* [RW 10] Bandwidth addition to VQ23 read requests */ 3013 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214 3014 /* [RW 10] Bandwidth addition to VQ24 read requests */ 3015 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218 3016 /* [RW 10] Bandwidth addition to VQ25 read requests */ 3017 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c 3018 /* [RW 10] Bandwidth addition to VQ26 read requests */ 3019 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220 3020 /* [RW 10] Bandwidth addition to VQ27 read requests */ 3021 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224 3022 /* [RW 10] Bandwidth addition to VQ4 read requests */ 3023 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc 3024 /* [RW 10] Bandwidth addition to VQ5 read requests */ 3025 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0 3026 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */ 3027 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac 3028 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */ 3029 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc 3030 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */ 3031 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0 3032 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */ 3033 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4 3034 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */ 3035 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8 3036 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */ 3037 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec 3038 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */ 3039 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0 3040 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */ 3041 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4 3042 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */ 3043 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8 3044 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */ 3045 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc 3046 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */ 3047 #define PXP2_REG_RQ_BW_RD_L22 0x120300 3048 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */ 3049 #define PXP2_REG_RQ_BW_RD_L23 0x120304 3050 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */ 3051 #define PXP2_REG_RQ_BW_RD_L24 0x120308 3052 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */ 3053 #define PXP2_REG_RQ_BW_RD_L25 0x12030c 3054 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */ 3055 #define PXP2_REG_RQ_BW_RD_L26 0x120310 3056 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */ 3057 #define PXP2_REG_RQ_BW_RD_L27 0x120314 3058 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */ 3059 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc 3060 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */ 3061 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0 3062 /* [RW 7] Bandwidth upper bound for VQ0 read requests */ 3063 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234 3064 /* [RW 7] Bandwidth upper bound for VQ12 read requests */ 3065 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264 3066 /* [RW 7] Bandwidth upper bound for VQ13 read requests */ 3067 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268 3068 /* [RW 7] Bandwidth upper bound for VQ14 read requests */ 3069 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c 3070 /* [RW 7] Bandwidth upper bound for VQ15 read requests */ 3071 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270 3072 /* [RW 7] Bandwidth upper bound for VQ16 read requests */ 3073 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274 3074 /* [RW 7] Bandwidth upper bound for VQ17 read requests */ 3075 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278 3076 /* [RW 7] Bandwidth upper bound for VQ18 read requests */ 3077 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c 3078 /* [RW 7] Bandwidth upper bound for VQ19 read requests */ 3079 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280 3080 /* [RW 7] Bandwidth upper bound for VQ20 read requests */ 3081 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284 3082 /* [RW 7] Bandwidth upper bound for VQ22 read requests */ 3083 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288 3084 /* [RW 7] Bandwidth upper bound for VQ23 read requests */ 3085 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c 3086 /* [RW 7] Bandwidth upper bound for VQ24 read requests */ 3087 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290 3088 /* [RW 7] Bandwidth upper bound for VQ25 read requests */ 3089 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294 3090 /* [RW 7] Bandwidth upper bound for VQ26 read requests */ 3091 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298 3092 /* [RW 7] Bandwidth upper bound for VQ27 read requests */ 3093 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c 3094 /* [RW 7] Bandwidth upper bound for VQ4 read requests */ 3095 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244 3096 /* [RW 7] Bandwidth upper bound for VQ5 read requests */ 3097 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248 3098 /* [RW 10] Bandwidth addition to VQ29 write requests */ 3099 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c 3100 /* [RW 10] Bandwidth addition to VQ30 write requests */ 3101 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230 3102 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */ 3103 #define PXP2_REG_RQ_BW_WR_L29 0x12031c 3104 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */ 3105 #define PXP2_REG_RQ_BW_WR_L30 0x120320 3106 /* [RW 7] Bandwidth upper bound for VQ29 */ 3107 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4 3108 /* [RW 7] Bandwidth upper bound for VQ30 */ 3109 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8 3110 /* [RW 18] external first_mem_addr field in L2P table for CDU module port 0 */ 3111 #define PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR 0x120008 3112 /* [RW 2] Endian mode for cdu */ 3113 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0 3114 #define PXP2_REG_RQ_CDU_FIRST_ILT 0x12061c 3115 #define PXP2_REG_RQ_CDU_LAST_ILT 0x120620 3116 /* [RW 4] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k; 3117 * -128k; -256k; -512k; -1M; -2M; 0-4M 3118 */ 3119 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018 3120 /* [R 1] 1' indicates that the requester has finished its internal 3121 * configuration 3122 */ 3123 #define PXP2_REG_RQ_CFG_DONE 0x1201b4 3124 /* [RW 2] Endian mode for debug */ 3125 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4 3126 /* [RW 1] When '1'; requests will enter input buffers but wont get out 3127 * towards the glue 3128 */ 3129 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330 3130 /* [RW 4] Determines alignment of write SRs when a request is split into 3131 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3132 * aligned. 4 - 512B aligned. 3133 */ 3134 #define PXP2_REG_RQ_DRAM_ALIGN 0x1205b0 3135 /* [RW 4] Determines alignment of read SRs when a request is split into 3136 * several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B 3137 * aligned. 4 - 512B aligned. 3138 */ 3139 #define PXP2_REG_RQ_DRAM_ALIGN_RD 0x12092c 3140 /* [RW 1] when set the new alignment method (E2) will be applied; when reset 3141 * the original alignment method (E1 E1H) will be applied 3142 */ 3143 #define PXP2_REG_RQ_DRAM_ALIGN_SEL 0x120930 3144 /* [R 32] Status signals in pswrq_garb module */ 3145 #define PXP2_REG_RQ_GARB 0x120748 3146 /* [RW 2] Endian mode for hc */ 3147 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8 3148 /* [WB 53] Onchip address table */ 3149 #define PXP2_REG_RQ_ONCHIP_AT 0x122000 3150 /* [WB 53] Onchip address table - B0 */ 3151 #define PXP2_REG_RQ_ONCHIP_AT_B0 0x128000 3152 /* [RW 13] Pending read limiter threshold; in Dwords */ 3153 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c 3154 /* [RW 2] Endian mode for qm */ 3155 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194 3156 #define PXP2_REG_RQ_QM_FIRST_ILT 0x120634 3157 #define PXP2_REG_RQ_QM_LAST_ILT 0x120638 3158 /* [RW 4] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k; 3159 * -128k; -256k; -512k; -1M; -2M; 0-4M 3160 */ 3161 #define PXP2_REG_RQ_QM_P_SIZE 0x120050 3162 /* [RW 1] 1' indicates that the RBC has finished configuring the PSWRQ */ 3163 #define PXP2_REG_RQ_RBC_DONE 0x1201b0 3164 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B; 3165 * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K 3166 */ 3167 #define PXP2_REG_RQ_RD_MBS0 0x120160 3168 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B; 3169 * 001:256B; 010: 512B; 11:1K:100:2K; 01:4K 3170 */ 3171 #define PXP2_REG_RQ_RD_MBS1 0x120168 3172 /* [RW 2] Endian mode for src */ 3173 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c 3174 #define PXP2_REG_RQ_SRC_FIRST_ILT 0x12063c 3175 #define PXP2_REG_RQ_SRC_LAST_ILT 0x120640 3176 /* [RW 4] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k; 3177 * -128k; -256k; -512k; -1M; -2M; 0-4M 3178 */ 3179 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c 3180 /* [RW 2] Endian mode for tm */ 3181 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198 3182 #define PXP2_REG_RQ_TM_FIRST_ILT 0x120644 3183 #define PXP2_REG_RQ_TM_LAST_ILT 0x120648 3184 /* [RW 4] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k; 3185 * -128k; -256k; -512k; -1M; -2M; 0-4M 3186 */ 3187 #define PXP2_REG_RQ_TM_P_SIZE 0x120034 3188 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */ 3189 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c 3190 /* [RW 18] external first_mem_addr field in L2P table for USDM module port 0 */ 3191 #define PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR 0x120094 3192 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */ 3193 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810 3194 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */ 3195 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818 3196 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */ 3197 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820 3198 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */ 3199 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828 3200 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */ 3201 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830 3202 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */ 3203 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838 3204 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */ 3205 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840 3206 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */ 3207 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848 3208 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */ 3209 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850 3210 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */ 3211 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858 3212 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */ 3213 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860 3214 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */ 3215 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868 3216 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */ 3217 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870 3218 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */ 3219 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878 3220 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */ 3221 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880 3222 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */ 3223 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888 3224 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */ 3225 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890 3226 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */ 3227 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898 3228 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */ 3229 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0 3230 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */ 3231 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8 3232 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */ 3233 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0 3234 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */ 3235 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8 3236 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */ 3237 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0 3238 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */ 3239 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8 3240 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */ 3241 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0 3242 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */ 3243 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8 3244 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */ 3245 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0 3246 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */ 3247 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8 3248 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */ 3249 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0 3250 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */ 3251 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8 3252 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */ 3253 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900 3254 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */ 3255 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908 3256 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B; 3257 * 001:256B; 010: 512B; 3258 */ 3259 #define PXP2_REG_RQ_WR_MBS0 0x12015c 3260 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B; 3261 * 001:256B; 010: 512B; 3262 */ 3263 #define PXP2_REG_RQ_WR_MBS1 0x120164 3264 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3265 * buffer reaches this number has_payload will be asserted. 1024B is not a 3266 * real MPS; it is a way of indicating that the client needs to wait for EOP 3267 * before asserting has_payload. Register should be initialized according to 3268 * has_payload value. 3269 */ 3270 #define PXP2_REG_WR_CDU_MPS 0x1205f0 3271 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3272 * buffer reaches this number has_payload will be asserted. 1024B is not a 3273 * real MPS; it is a way of indicating that the client needs to wait for EOP 3274 * before asserting has_payload. Register should be initialized according to 3275 * has_payload value. 3276 */ 3277 #define PXP2_REG_WR_CSDM_MPS 0x1205d0 3278 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3279 * buffer reaches this number has_payload will be asserted. 1024B is not a 3280 * real MPS; it is a way of indicating that the client needs to wait for EOP 3281 * before asserting has_payload. Register should be initialized according to 3282 * has_payload value. 3283 */ 3284 #define PXP2_REG_WR_DBG_MPS 0x1205e8 3285 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3286 * buffer reaches this number has_payload will be asserted. 1024B is not a 3287 * real MPS; it is a way of indicating that the client needs to wait for EOP 3288 * before asserting has_payload. Register should be initialized according to 3289 * has_payload value. 3290 */ 3291 #define PXP2_REG_WR_DMAE_MPS 0x1205ec 3292 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3293 * buffer reaches this number has_payload will be asserted. 1024B is not a 3294 * real MPS; it is a way of indicating that the client needs to wait for EOP 3295 * before asserting has_payload. Register should be initialized according to 3296 * has_payload value. 3297 */ 3298 #define PXP2_REG_WR_HC_MPS 0x1205c8 3299 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3300 * buffer reaches this number has_payload will be asserted. 1024B is not a 3301 * real MPS; it is a way of indicating that the client needs to wait for EOP 3302 * before asserting has_payload. Register should be initialized according to 3303 * has_payload value. 3304 */ 3305 #define PXP2_REG_WR_QM_MPS 0x1205dc 3306 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3307 * buffer reaches this number has_payload will be asserted. 1024B is not a 3308 * real MPS; it is a way of indicating that the client needs to wait for EOP 3309 * before asserting has_payload. Register should be initialized according to 3310 * has_payload value. 3311 */ 3312 #define PXP2_REG_WR_SRC_MPS 0x1205e4 3313 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3314 * buffer reaches this number has_payload will be asserted. 1024B is not a 3315 * real MPS; it is a way of indicating that the client needs to wait for EOP 3316 * before asserting has_payload. Register should be initialized according to 3317 * has_payload value. 3318 */ 3319 #define PXP2_REG_WR_TM_MPS 0x1205e0 3320 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3321 * buffer reaches this number has_payload will be asserted. 1024B is not a 3322 * real MPS; it is a way of indicating that the client needs to wait for EOP 3323 * before asserting has_payload. Register should be initialized according to 3324 * has_payload value. 3325 */ 3326 #define PXP2_REG_WR_TSDM_MPS 0x1205d4 3327 /* [RW 9] a. When pxp2.wr_th_mode_usdmdp = 0 (E1.5-65 mode) should be 3328 * initialized to (MPS/32); b. When pxp2.wr_th_mode_usdmdp = 1 (E1.5-90; 3329 * enhanced mode) and pxp2.wr_usdmdp_outst_req is different than default (3) 3330 * should be initialized to (pxp2.wr_usdmdp_outst_req x MPS/32); when 3331 * pxp2.wr_usdmdp_outst_req is 3 the reset value is the correct 3332 * configuration 3333 */ 3334 #define PXP2_REG_WR_USDMDP_TH 0x120348 3335 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3336 * buffer reaches this number has_payload will be asserted. 1024B is not a 3337 * real MPS; it is a way of indicating that the client needs to wait for EOP 3338 * before asserting has_payload. Register should be initialized according to 3339 * has_payload value. 3340 */ 3341 #define PXP2_REG_WR_USDM_MPS 0x1205cc 3342 /* [RW 2] 0 - 128B; - 256B; - 512B; - 1024B; when the payload in the 3343 * buffer reaches this number has_payload will be asserted. 1024B is not a 3344 * real MPS; it is a way of indicating that the client needs to wait for EOP 3345 * before asserting has_payload. Register should be initialized according to 3346 * has_payload value. 3347 */ 3348 #define PXP2_REG_WR_XSDM_MPS 0x1205d8 3349 /* [R 1] debug only: Indication if PSWHST arbiter is idle */ 3350 #define PXP_REG_HST_ARB_IS_IDLE 0x103004 3351 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means 3352 * this client is waiting for the arbiter. 3353 */ 3354 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008 3355 /* [RW 1] When 1; doorbells are discarded and not passed to doorbell queue 3356 * block. Should be used for close the gates. 3357 */ 3358 #define PXP_REG_HST_DISCARD_DOORBELLS 0x1030a4 3359 /* [R 1] debug only: '1' means this PSWHST is discarding doorbells. This bit 3360 * should update according to 'hst_discard_doorbells' register when the state 3361 * machine is idle 3362 */ 3363 #define PXP_REG_HST_DISCARD_DOORBELLS_STATUS 0x1030a0 3364 /* [RW 1] When 1; new internal writes arriving to the block are discarded. 3365 * Should be used for close the gates. 3366 */ 3367 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES 0x1030a8 3368 /* [R 6] debug only: A bit mask for all PSWHST internal write clients. '1' 3369 * means this PSWHST is discarding inputs from this client. Each bit should 3370 * update according to 'hst_discard_internal_writes' register when the state 3371 * machine is idle. 3372 */ 3373 #define PXP_REG_HST_DISCARD_INTERNAL_WRITES_STATUS 0x10309c 3374 /* [R 1] 1 - An incorrect access is logged. The valid bit is reset when the 3375 * relevant interrupt register is read (PXP_REG_INT_STS_CLR_1) 3376 */ 3377 #define PXP_REG_HST_INCORRECT_ACCESS_VALID 0x1030cc 3378 /* [R 1] 1- permission violation data is logged. The valid bit is reset when 3379 * the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1) 3380 */ 3381 #define PXP_REG_HST_PER_VIOLATION_VALID 0x1030e0 3382 /* [R 15] The FID of the first access to a disabled VF; the format is 3383 * [14:12] - pfid; [11:6] - vfid; [5] - vf_valid; [4:1] - client (0 USDM; 1 3384 * CSDM; 2 XSDM; 3 TSDM; 4 HC; 5 GRC; 6 DQ; 7 RESERVED SPACE; 8 ATC); [0] - 3385 * w_nr(0-read req; 1- write req). The data is written only when the valid 3386 * bit is reset. and it is stays stable until it is reset by the read from 3387 * interrupt_clr register 3388 */ 3389 #define PXP_REG_HST_VF_DISABLED_ERROR_DATA 0x1030b8 3390 /* [R 1] 1 - An error request is logged and wasn't handled yet. The valid 3391 * bit is reset when the relevant interrupt register is read 3392 * (PXP_REG_INT_STS_CLR_1) 3393 */ 3394 #define PXP_REG_HST_VF_DISABLED_ERROR_VALID 0x1030bc 3395 /* [RW 7] Indirect access to the permission table. The fields are : {Valid; 3396 * VFID[5:0]} 3397 */ 3398 #define PXP_REG_HST_ZONE_PERMISSION_TABLE 0x103400 3399 /* [RW 32] Interrupt mask register #0 read/write */ 3400 #define PXP_REG_PXP_INT_MASK_0 0x103074 3401 #define PXP_REG_PXP_INT_MASK_1 0x103084 3402 /* [R 32] Interrupt register #0 read */ 3403 #define PXP_REG_PXP_INT_STS_0 0x103068 3404 #define PXP_REG_PXP_INT_STS_1 0x103078 3405 /* [RC 32] Interrupt register #0 read clear */ 3406 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c 3407 #define PXP_REG_PXP_INT_STS_CLR_1 0x10307c 3408 /* [RW 27] Parity mask register #0 read/write */ 3409 #define PXP_REG_PXP_PRTY_MASK 0x103094 3410 /* [R 27] Parity register #0 read */ 3411 #define PXP_REG_PXP_PRTY_STS 0x103088 3412 /* [RC 27] Parity register #0 read clear */ 3413 #define PXP_REG_PXP_PRTY_STS_CLR 0x10308c 3414 /* [RW 32] The base logical address (in bytes) of each physical queue. The 3415 * index I represents the physical queue number. The 12 lsbs are ignore and 3416 * considered zero so practically there are only 20 bits in this register; 3417 * queues 63-0 3418 */ 3419 #define QM_REG_BASEADDR 0x168900 3420 /* [R 32] NOT USED */ 3421 #define QM_REG_BASEADDR_EXT_A 0x16e100 3422 /* [R 18] The credit value for byte credit 0. The value is 2s complement 3423 * value (i.e. msb is used for the sign). 3424 */ 3425 #define QM_REG_BYTECRD0 0x16e6fc 3426 /* [R 18] The credit value for byte credit 1. The value is 2s complement 3427 * value (i.e. msb is used for the sign). 3428 */ 3429 #define QM_REG_BYTECRD1 0x16e700 3430 /* [R 18] The credit value for byte credit 2. The value is 2s complement 3431 * value (i.e. msb is used for the sign). 3432 */ 3433 #define QM_REG_BYTECRD2 0x16e704 3434 /* [R 18] The credit value for byte credit 3. The value is 2s complement 3435 * value (i.e. msb is used for the sign). 3436 */ 3437 #define QM_REG_BYTECRD3 0x16e7ac 3438 /* [R 18] The credit value for byte credit 4. The value is 2s complement 3439 * value (i.e. msb is used for the sign). 3440 */ 3441 #define QM_REG_BYTECRD4 0x16e7b0 3442 /* [R 18] The credit value for byte credit 5. The value is 2s complement 3443 * value (i.e. msb is used for the sign). 3444 */ 3445 #define QM_REG_BYTECRD5 0x16e7b4 3446 /* [R 18] The credit value for byte credit 6. The value is 2s complement 3447 * value (i.e. msb is used for the sign). 3448 */ 3449 #define QM_REG_BYTECRD6 0x16e7b8 3450 /* [R 32] NOT USED - removed for E3 B0 */ 3451 #define QM_REG_BYTECRDCMDQ_0 0x16e6e8 3452 /* [RC 32] byte credit update error register; b2-b0: byte credit id (pbf 3453 * error); b3 - reserved (zero filled); b6-b4: byte credit id (storm 3454 * increment error); b7 - reserved (zero filled); b10-b8: byte credit id 3455 * (storm decrement error); b11 - reserved (zero filled); b12: pbf error 3456 * valid; b13: storm increment error valid; b14: storm decrement error 3457 * valid; b15: reserved; b22-b16: byte credit warning (warning = decremented 3458 * below zero). mask bit per voq counter; b31-b23: reserved; NOTE: VOQ id-s 3459 * represent HW 3460 */ 3461 #define QM_REG_BYTECRDERRREG 0x16e708 3462 /* [RW 17] The initial byte credit value for all counters */ 3463 #define QM_REG_BYTECRDINITVAL 0x168238 3464 /* [RW 20] The number of connections divided by 16 which dictates the size 3465 * of each queue which belongs to even function number. 3466 */ 3467 #define QM_REG_CONNNUM_0 0x168020 3468 /* [R 6] Keep the fill level of the fifo from write client 4 */ 3469 #define QM_REG_CQM_WRC_FIFOLVL 0x168018 3470 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3471 * FW (virtual) VOQ0 3472 */ 3473 #define QM_REG_FWVOQ0TOHWVOQ 0x16e7bc 3474 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3475 * FW (virtual) VOQ1 3476 */ 3477 #define QM_REG_FWVOQ1TOHWVOQ 0x16e7c0 3478 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3479 * FW (virtual) VOQ2 3480 */ 3481 #define QM_REG_FWVOQ2TOHWVOQ 0x16e7c4 3482 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3483 * FW (virtual) VOQ3 3484 */ 3485 #define QM_REG_FWVOQ3TOHWVOQ 0x16e7c8 3486 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3487 * FW (virtual) VOQ4 3488 */ 3489 #define QM_REG_FWVOQ4TOHWVOQ 0x16e7cc 3490 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3491 * FW (virtual) VOQ5 3492 */ 3493 #define QM_REG_FWVOQ5TOHWVOQ 0x16e7d0 3494 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3495 * FW (virtual) VOQ6 3496 */ 3497 #define QM_REG_FWVOQ6TOHWVOQ 0x16e7d4 3498 /* [RW 3] Describes the HW (real) VOQ id (id-s 0-6 used for HW TX VOQ-s) of 3499 * FW (virtual) VOQ7 3500 */ 3501 #define QM_REG_FWVOQ7TOHWVOQ 0x16e7d8 3502 /* [RC 1] A flag to indicate that overflow error occurred in one of the 3503 * queues. 3504 */ 3505 #define QM_REG_OVFERROR 0x16805c 3506 /* [RC 6] the Q were the qverflow occurs */ 3507 #define QM_REG_OVFQNUM 0x168058 3508 /* [R 16] Pause state for physical queues 15-0 */ 3509 #define QM_REG_PAUSESTATE0 0x168410 3510 /* [R 16] Pause state for physical queues 31-16 */ 3511 #define QM_REG_PAUSESTATE1 0x168414 3512 /* [R 16] Pause state for physical queues 47-32 */ 3513 #define QM_REG_PAUSESTATE2 0x16e684 3514 /* [R 16] Pause state for physical queues 63-48 */ 3515 #define QM_REG_PAUSESTATE3 0x16e688 3516 /* [R 16] NOT USED */ 3517 #define QM_REG_PAUSESTATE4 0x16e68c 3518 /* [R 16] NOT USED */ 3519 #define QM_REG_PAUSESTATE5 0x16e690 3520 /* [R 16] NOT USED */ 3521 #define QM_REG_PAUSESTATE6 0x16e694 3522 /* [R 16] NOT USED */ 3523 #define QM_REG_PAUSESTATE7 0x16e698 3524 #define QM_REG_PF_EN 0x16e70c 3525 /* [R 24] The number of tasks stored in the QM for the PF. only even 3526 * functions are valid in E2 (odd I registers will be hard wired to 0) 3527 */ 3528 #define QM_REG_PF_USG_CNT_0 0x16e040 3529 /* [R 16] NOT USED */ 3530 #define QM_REG_PORT0BYTECRD 0x168300 3531 /* [R 16] NOT USED */ 3532 #define QM_REG_PORT1BYTECRD 0x168304 3533 /* [WB 54] Pointer Table Memory for queues 63-0; The mapping is as follow: 3534 * ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read 3535 * bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; 3536 */ 3537 #define QM_REG_PTRTBL 0x168a00 3538 /* [R 54] NOT USED */ 3539 #define QM_REG_PTRTBL_EXT_A 0x16e200 3540 /* [RW 14] Interrupt mask register #0 read/write */ 3541 #define QM_REG_QM_INT_MASK 0x168444 3542 /* [R 14] Interrupt register #0 read */ 3543 #define QM_REG_QM_INT_STS 0x168438 3544 /* [RC 14] Interrupt register #0 read clear */ 3545 #define QM_REG_QM_INT_STS_CLR 0x16843c 3546 /* [RW 12] Parity mask register #0 read/write */ 3547 #define QM_REG_QM_PRTY_MASK 0x168454 3548 /* [R 12] Parity register #0 read */ 3549 #define QM_REG_QM_PRTY_STS 0x168448 3550 /* [RC 12] Parity register #0 read clear */ 3551 #define QM_REG_QM_PRTY_STS_CLR 0x16844c 3552 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */ 3553 #define QM_REG_QSTATUS_HIGH 0x16802c 3554 /* [R 32] NOT USED */ 3555 #define QM_REG_QSTATUS_HIGH_EXT_A 0x16e408 3556 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */ 3557 #define QM_REG_QSTATUS_LOW 0x168028 3558 /* [R 32] NOT USED */ 3559 #define QM_REG_QSTATUS_LOW_EXT_A 0x16e404 3560 /* [R 24] The number of tasks queued for each queue; queues 63-0 */ 3561 #define QM_REG_QTASKCTR_0 0x168308 3562 /* [R 24] NOT USED */ 3563 #define QM_REG_QTASKCTR_EXT_A_0 0x16e584 3564 /* [RW 4] Queue tied to VOQ */ 3565 #define QM_REG_QVOQIDX_0 0x1680f4 3566 /* [RW 1] Initialization bit command */ 3567 #define QM_REG_SOFT_RESET 0x168428 3568 /* [R 6] Keep the fill level of the fifo from write client 3 */ 3569 #define QM_REG_TQM_WRC_FIFOLVL 0x168010 3570 /* [R 6] Keep the fill level of the fifo from write client 2 */ 3571 #define QM_REG_UQM_WRC_FIFOLVL 0x168008 3572 /* [RC 32] VOQ credit update error register; b3-b0: voq id (pbf error); 3573 * b7-b4: voq id (storm increment error); b11-b8: voq id (storm decrement 3574 * error); b12: pbf error valid; b13: storm increment error valid; b14: 3575 * storm decrement error valid; b15: reserved; b27-b16: voq warning 3576 * (warning = decremented below zero). mask bit per voq counter; b31-b28: 3577 * reserved; NOTE: VOQ id-s represent HW VOQ id 3578 */ 3579 #define QM_REG_VOQCRDERRREG 0x168408 3580 /* [R 17] The credit value for each VOQ. The value is 2s complement value 3581 * (i.e. msb is used for the sign). 3582 */ 3583 #define QM_REG_VOQCREDIT_0 0x1682d0 3584 #define QM_REG_VOQCREDIT_1 0x1682d4 3585 #define QM_REG_VOQCREDIT_2 0x1682d8 3586 #define QM_REG_VOQCREDIT_3 0x1682dc 3587 #define QM_REG_VOQCREDIT_4 0x1682e0 3588 #define QM_REG_VOQCREDIT_5 0x1682e4 3589 #define QM_REG_VOQCREDIT_6 0x1682e8 3590 /* [RW 16] The init and maximum credit for each VoQ */ 3591 #define QM_REG_VOQINITCREDIT_0 0x168060 3592 #define QM_REG_VOQINITCREDIT_1 0x168064 3593 #define QM_REG_VOQINITCREDIT_2 0x168068 3594 #define QM_REG_VOQINITCREDIT_3 0x16806c 3595 #define QM_REG_VOQINITCREDIT_4 0x168070 3596 #define QM_REG_VOQINITCREDIT_5 0x168074 3597 #define QM_REG_VOQINITCREDIT_6 0x168078 3598 /* [RW 32] The physical queue number associated with each VOQ; queues 31-0 */ 3599 #define QM_REG_VOQQMASK_0_LSB 0x168240 3600 /* [R 6] Keep the fill level of the fifo from write client 1 */ 3601 #define QM_REG_XQM_WRC_FIFOLVL 0x168000 3602 /* [W 1] reset to parity interrupt */ 3603 #define SEM_FAST_REG_PARITY_RST 0x18840 3604 /* [RW 1] Interrupt mask register #0 read/write */ 3605 #define SEM_FAST_REG_SEM_FAST_INT_MASK 0x1fff0 3606 /* [R 1] Interrupt register #0 read */ 3607 #define SEM_FAST_REG_SEM_FAST_INT_STS 0x1fffc 3608 /* [RC 1] Interrupt register #0 read clear */ 3609 #define SEM_FAST_REG_SEM_FAST_INT_STS_CLR 0x1fff8 3610 /* [RW 1] Parity mask register #0 read/write */ 3611 #define SEM_FAST_REG_SEM_FAST_PRTY_MASK 0x1ffe0 3612 /* [R 1] Parity register #0 read */ 3613 #define SEM_FAST_REG_SEM_FAST_PRTY_STS 0x1ffec 3614 /* [RC 1] Parity register #0 read clear */ 3615 #define SEM_FAST_REG_SEM_FAST_PRTY_STS_CLR 0x1ffe8 3616 #define SRC_REG_COUNTFREE0 0x40500 3617 #define SRC_REG_FIRSTFREE0 0x40510 3618 #define SRC_REG_KEYRSS0_0 0x40408 3619 #define SRC_REG_KEYRSS0_7 0x40424 3620 #define SRC_REG_KEYSEARCH_0 0x40458 3621 #define SRC_REG_KEYSEARCH_1 0x4045c 3622 #define SRC_REG_KEYSEARCH_2 0x40460 3623 #define SRC_REG_KEYSEARCH_3 0x40464 3624 #define SRC_REG_KEYSEARCH_4 0x40468 3625 #define SRC_REG_KEYSEARCH_5 0x4046c 3626 #define SRC_REG_KEYSEARCH_6 0x40470 3627 #define SRC_REG_KEYSEARCH_7 0x40474 3628 #define SRC_REG_KEYSEARCH_8 0x40478 3629 #define SRC_REG_KEYSEARCH_9 0x4047c 3630 #define SRC_REG_LASTFREE0 0x40530 3631 #define SRC_REG_NUMBER_HASH_BITS0 0x40400 3632 /* [RW 1] Reset internal state machines. */ 3633 #define SRC_REG_SOFT_RST 0x4049c 3634 /* [RW 3] Interrupt mask register #0 read/write */ 3635 #define SRC_REG_SRC_INT_MASK 0x404b8 3636 /* [R 3] Interrupt register #0 read */ 3637 #define SRC_REG_SRC_INT_STS 0x404ac 3638 /* [RC 3] Interrupt register #0 read clear */ 3639 #define SRC_REG_SRC_INT_STS_CLR 0x404b0 3640 /* [RW 3] Parity mask register #0 read/write */ 3641 #define SRC_REG_SRC_PRTY_MASK 0x404c8 3642 /* [R 3] Parity register #0 read */ 3643 #define SRC_REG_SRC_PRTY_STS 0x404bc 3644 /* [RC 3] Parity register #0 read clear */ 3645 #define SRC_REG_SRC_PRTY_STS_CLR 0x404c0 3646 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */ 3647 #define TCM_REG_CAM_OCCUP 0x5017c 3648 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 3649 * the initial credit value; read returns the current value of the credit 3650 * counter. Must be initialized to 1 at start-up. 3651 */ 3652 #define TCM_REG_CFC_INIT_CRD 0x50204 3653 /* [RC 1] Message length mismatch (relative to last indication) at the In#9 3654 * interface. 3655 */ 3656 #define TCM_REG_CSEM_LENGTH_MIS 0x50174 3657 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 3658 * writes the initial credit value; read returns the current value of the 3659 * credit counter. Must be initialized to 64 at start-up. 3660 */ 3661 #define TCM_REG_FIC0_INIT_CRD 0x5020c 3662 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 3663 * writes the initial credit value; read returns the current value of the 3664 * credit counter. Must be initialized to 64 at start-up. 3665 */ 3666 #define TCM_REG_FIC1_INIT_CRD 0x50210 3667 /* [RC 1] Message length mismatch (relative to last indication) at the In#7 3668 * interface. 3669 */ 3670 #define TCM_REG_PBF_LENGTH_MIS 0x5016c 3671 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded; 3672 * acknowledge output is deasserted; all other signals are treated as usual; 3673 * if 1 - normal activity. 3674 */ 3675 #define TCM_REG_PRS_IFEN 0x50020 3676 /* [RC 1] Message length mismatch (relative to last indication) at the In#6 3677 * interface. 3678 */ 3679 #define TCM_REG_PRS_LENGTH_MIS 0x50168 3680 /* [RC 1] Message length mismatch (relative to last indication) at the STORM 3681 * interface. 3682 */ 3683 #define TCM_REG_STORM_LENGTH_MIS 0x50160 3684 /* [RW 11] Interrupt mask register #0 read/write */ 3685 #define TCM_REG_TCM_INT_MASK 0x501dc 3686 /* [R 11] Interrupt register #0 read */ 3687 #define TCM_REG_TCM_INT_STS 0x501d0 3688 /* [RC 11] Interrupt register #0 read clear */ 3689 #define TCM_REG_TCM_INT_STS_CLR 0x501d4 3690 /* [RW 27] Parity mask register #0 read/write */ 3691 #define TCM_REG_TCM_PRTY_MASK 0x501ec 3692 /* [R 27] Parity register #0 read */ 3693 #define TCM_REG_TCM_PRTY_STS 0x501e0 3694 /* [RC 27] Parity register #0 read clear */ 3695 #define TCM_REG_TCM_PRTY_STS_CLR 0x501e4 3696 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 3697 * the initial credit value; read returns the current value of the credit 3698 * counter. Must be initialized to 32 at start-up. 3699 */ 3700 #define TCM_REG_TQM_INIT_CRD 0x5021c 3701 /* [RC 1] Message length mismatch (relative to last indication) at the SDM 3702 * interface. 3703 */ 3704 #define TCM_REG_TSDM_LENGTH_MIS 0x50164 3705 /* [RC 1] Message length mismatch (relative to last indication) at the In#8 3706 * interface. 3707 */ 3708 #define TCM_REG_USEM_LENGTH_MIS 0x50170 3709 /* [RW 21] Indirect access to the descriptor table of the XX protection 3710 * mechanism. The fields are: [5:0] - length of the message; 15:6] - message 3711 * pointer; 20:16] - next pointer. 3712 */ 3713 #define TCM_REG_XX_DESCR_TABLE 0x50280 3714 #define TCM_REG_XX_DESCR_TABLE_SIZE 29 3715 /* [R 6] Use to read the value of XX protection Free counter. */ 3716 #define TCM_REG_XX_FREE 0x50178 3717 #define TM_REG_EN_LINEAR0_TIMER 0x164014 3718 /* [RW 18] Linear0 Max active cid (in banks of 32 entries). */ 3719 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048 3720 /* [ST 16] Linear0 Number of scans counter. */ 3721 #define TM_REG_LIN0_NUM_SCANS 0x1640a0 3722 #define TM_REG_LIN0_SCAN_ON 0x1640d0 3723 /* [RW 24] Linear0 array scan timeout. */ 3724 #define TM_REG_LIN0_SCAN_TIME 0x16403c 3725 #define TM_REG_LIN0_VNIC_UC 0x164128 3726 /* [RW 1] Interrupt mask register #0 read/write */ 3727 #define TM_REG_TM_INT_MASK 0x1640fc 3728 /* [R 1] Interrupt register #0 read */ 3729 #define TM_REG_TM_INT_STS 0x1640f0 3730 /* [RC 1] Interrupt register #0 read clear */ 3731 #define TM_REG_TM_INT_STS_CLR 0x1640f4 3732 /* [RW 7] Parity mask register #0 read/write */ 3733 #define TM_REG_TM_PRTY_MASK 0x16410c 3734 /* [R 7] Parity register #0 read */ 3735 #define TM_REG_TM_PRTY_STS 0x164100 3736 /* [RC 7] Parity register #0 read clear */ 3737 #define TM_REG_TM_PRTY_STS_CLR 0x164104 3738 #define TSDM_REG_ENABLE_IN1 0x42238 3739 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 3740 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548 3741 /* [R 1] parser fifo empty in sdm_sync block */ 3742 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550 3743 /* [R 1] parser serial fifo empty in sdm_sync block */ 3744 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558 3745 /* [RW 32] Interrupt mask register #0 read/write */ 3746 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c 3747 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac 3748 /* [R 32] Interrupt register #0 read */ 3749 #define TSDM_REG_TSDM_INT_STS_0 0x42290 3750 #define TSDM_REG_TSDM_INT_STS_1 0x422a0 3751 /* [RC 32] Interrupt register #0 read clear */ 3752 #define TSDM_REG_TSDM_INT_STS_CLR_0 0x42294 3753 #define TSDM_REG_TSDM_INT_STS_CLR_1 0x422a4 3754 /* [RW 11] Parity mask register #0 read/write */ 3755 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc 3756 /* [R 11] Parity register #0 read */ 3757 #define TSDM_REG_TSDM_PRTY_STS 0x422b0 3758 /* [RC 11] Parity register #0 read clear */ 3759 #define TSDM_REG_TSDM_PRTY_STS_CLR 0x422b4 3760 /* [RW 32] This address space contains all registers and memories that are 3761 * placed in SEM_FAST block. The SEM_FAST registers are described in 3762 * appendix B. In order to access the SEM_FAST registers the base address 3763 * TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each 3764 * SEM_FAST register offset. 3765 */ 3766 #define TSEM_REG_FAST_MEMORY 0x1a0000 3767 /* [RW 15] Interrupt table Read and write access to it is not possible in 3768 * the middle of the work 3769 */ 3770 #define TSEM_REG_INT_TABLE 0x180400 3771 /* [WB 128] Debug only. Passive buffer memory */ 3772 #define TSEM_REG_PASSIVE_BUFFER 0x181000 3773 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 3774 #define TSEM_REG_PRAM 0x1c0000 3775 /* [R 20] Valid sleeping threads indication have bit per thread */ 3776 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c 3777 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 3778 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0 3779 /* [RW 32] Interrupt mask register #0 read/write */ 3780 #define TSEM_REG_TSEM_INT_MASK_0 0x180100 3781 #define TSEM_REG_TSEM_INT_MASK_1 0x180110 3782 /* [R 32] Interrupt register #0 read */ 3783 #define TSEM_REG_TSEM_INT_STS_0 0x1800f4 3784 #define TSEM_REG_TSEM_INT_STS_1 0x180104 3785 /* [RC 32] Interrupt register #0 read clear */ 3786 #define TSEM_REG_TSEM_INT_STS_CLR_0 0x1800f8 3787 #define TSEM_REG_TSEM_INT_STS_CLR_1 0x180108 3788 /* [RW 32] Parity mask register #0 read/write */ 3789 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120 3790 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130 3791 /* [R 32] Parity register #0 read */ 3792 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114 3793 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124 3794 /* [RC 32] Parity register #0 read clear */ 3795 #define TSEM_REG_TSEM_PRTY_STS_CLR_0 0x180118 3796 #define TSEM_REG_TSEM_PRTY_STS_CLR_1 0x180128 3797 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 3798 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. 3799 */ 3800 #define TSEM_REG_VFPF_ERR_NUM 0x180380 3801 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 3802 #define UCM_REG_CAM_OCCUP 0xe0170 3803 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 3804 * the initial credit value; read returns the current value of the credit 3805 * counter. Must be initialized to 1 at start-up. 3806 */ 3807 #define UCM_REG_CFC_INIT_CRD 0xe0204 3808 /* [RC 1] Set when the message length mismatch (relative to last indication) 3809 * at the csem interface is detected. 3810 */ 3811 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160 3812 /* [RC 1] Set when the message length mismatch (relative to last indication) 3813 * at the dorq interface is detected. 3814 */ 3815 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168 3816 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 3817 * writes the initial credit value; read returns the current value of the 3818 * credit counter. Must be initialized to 64 at start-up. 3819 */ 3820 #define UCM_REG_FIC0_INIT_CRD 0xe020c 3821 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 3822 * writes the initial credit value; read returns the current value of the 3823 * credit counter. Must be initialized to 64 at start-up. 3824 */ 3825 #define UCM_REG_FIC1_INIT_CRD 0xe0210 3826 /* [RC 1] Set when the message length mismatch (relative to last indication) 3827 * at the STORM interface is detected. 3828 */ 3829 #define UCM_REG_STORM_LENGTH_MIS 0xe0154 3830 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 3831 * writes the initial credit value; read returns the current value of the 3832 * credit counter. Must be initialized to 4 at start-up. 3833 */ 3834 #define UCM_REG_TM_INIT_CRD 0xe021c 3835 /* [RC 1] Set when the message length mismatch (relative to last indication) 3836 * at the tsem interface is detected. 3837 */ 3838 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c 3839 /* [RW 11] Interrupt mask register #0 read/write */ 3840 #define UCM_REG_UCM_INT_MASK 0xe01d4 3841 /* [R 11] Interrupt register #0 read */ 3842 #define UCM_REG_UCM_INT_STS 0xe01c8 3843 /* [RC 11] Interrupt register #0 read clear */ 3844 #define UCM_REG_UCM_INT_STS_CLR 0xe01cc 3845 /* [RW 27] Parity mask register #0 read/write */ 3846 #define UCM_REG_UCM_PRTY_MASK 0xe01e4 3847 /* [R 27] Parity register #0 read */ 3848 #define UCM_REG_UCM_PRTY_STS 0xe01d8 3849 /* [RC 27] Parity register #0 read clear */ 3850 #define UCM_REG_UCM_PRTY_STS_CLR 0xe01dc 3851 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 3852 * the initial credit value; read returns the current value of the credit 3853 * counter. Must be initialized to 32 at start-up. 3854 */ 3855 #define UCM_REG_UQM_INIT_CRD 0xe0220 3856 /* [RC 1] Set when the message length mismatch (relative to last indication) 3857 * at the SDM interface is detected. 3858 */ 3859 #define UCM_REG_USDM_LENGTH_MIS 0xe0158 3860 /* [RC 1] Set when the message length mismatch (relative to last indication) 3861 * at the xsem interface isdetected. 3862 */ 3863 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164 3864 /* [RW 20] Indirect access to the descriptor table of the XX protection 3865 * mechanism. The fields are:[5:0] - message length; 14:6] - message 3866 * pointer; 19:15] - next pointer. 3867 */ 3868 #define UCM_REG_XX_DESCR_TABLE 0xe0280 3869 #define UCM_REG_XX_DESCR_TABLE_SIZE 27 3870 /* [R 6] Use to read the XX protection Free counter. */ 3871 #define UCM_REG_XX_FREE 0xe016c 3872 #define UMAC_COMMAND_CONFIG_REG_HD_ENA (0x1 << 10) 3873 #define UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE (0x1 << 28) 3874 #define UMAC_COMMAND_CONFIG_REG_LOOP_ENA (0x1 << 15) 3875 #define UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK (0x1 << 24) 3876 #define UMAC_COMMAND_CONFIG_REG_PAD_EN (0x1 << 5) 3877 #define UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE (0x1 << 8) 3878 #define UMAC_COMMAND_CONFIG_REG_PROMIS_EN (0x1 << 4) 3879 #define UMAC_COMMAND_CONFIG_REG_RX_ENA (0x1 << 1) 3880 #define UMAC_COMMAND_CONFIG_REG_SW_RESET (0x1 << 13) 3881 #define UMAC_COMMAND_CONFIG_REG_TX_ENA (0x1 << 0) 3882 #define UMAC_REG_COMMAND_CONFIG 0x8 3883 /* [RW 16] This is the duration for which MAC must wait to go back to ACTIVE 3884 * state from LPI state when it receives packet for transmission. The 3885 * decrement unit is 1 micro-second. 3886 */ 3887 #define UMAC_REG_EEE_WAKE_TIMER 0x6c 3888 /* [RW 32] Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers 3889 * to bit 17 of the MAC address etc. 3890 */ 3891 #define UMAC_REG_MAC_ADDR0 0xc 3892 /* [RW 16] Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 3893 * refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved. 3894 */ 3895 #define UMAC_REG_MAC_ADDR1 0x10 3896 /* [RW 14] Defines a 14-Bit maximum frame length used by the MAC receive 3897 * logic to check frames. 3898 */ 3899 #define UMAC_REG_MAXFR 0x14 3900 #define UMAC_REG_UMAC_EEE_CTRL 0x64 3901 #define UMAC_UMAC_EEE_CTRL_REG_EEE_EN (0x1 << 3) 3902 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 3903 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550 3904 /* [R 1] parser fifo empty in sdm_sync block */ 3905 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558 3906 /* [R 1] parser serial fifo empty in sdm_sync block */ 3907 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560 3908 /* [RW 32] Interrupt mask register #0 read/write */ 3909 #define USDM_REG_USDM_INT_MASK_0 0xc42a0 3910 #define USDM_REG_USDM_INT_MASK_1 0xc42b0 3911 /* [R 32] Interrupt register #0 read */ 3912 #define USDM_REG_USDM_INT_STS_0 0xc4294 3913 #define USDM_REG_USDM_INT_STS_1 0xc42a4 3914 /* [RC 32] Interrupt register #0 read clear */ 3915 #define USDM_REG_USDM_INT_STS_CLR_0 0xc4298 3916 #define USDM_REG_USDM_INT_STS_CLR_1 0xc42a8 3917 /* [RW 11] Parity mask register #0 read/write */ 3918 #define USDM_REG_USDM_PRTY_MASK 0xc42c0 3919 /* [R 11] Parity register #0 read */ 3920 #define USDM_REG_USDM_PRTY_STS 0xc42b4 3921 /* [RC 11] Parity register #0 read clear */ 3922 #define USDM_REG_USDM_PRTY_STS_CLR 0xc42b8 3923 /* [RW 32] This address space contains all registers and memories that are 3924 * placed in SEM_FAST block. The SEM_FAST registers are described in 3925 * appendix B. In order to access the SEM_FAST registers the base address 3926 * USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each 3927 * SEM_FAST register offset. 3928 */ 3929 #define USEM_REG_FAST_MEMORY 0x320000 3930 /* [RW 15] Interrupt table Read and write access to it is not possible in 3931 * the middle of the work 3932 */ 3933 #define USEM_REG_INT_TABLE 0x300400 3934 /* [WB 128] Debug only. Passive buffer memory */ 3935 #define USEM_REG_PASSIVE_BUFFER 0x302000 3936 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 3937 #define USEM_REG_PRAM 0x340000 3938 /* [R 20] Valid sleeping threads indication have bit per thread */ 3939 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c 3940 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 3941 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0 3942 /* [RW 32] Interrupt mask register #0 read/write */ 3943 #define USEM_REG_USEM_INT_MASK_0 0x300110 3944 #define USEM_REG_USEM_INT_MASK_1 0x300120 3945 /* [R 32] Interrupt register #0 read */ 3946 #define USEM_REG_USEM_INT_STS_0 0x300104 3947 #define USEM_REG_USEM_INT_STS_1 0x300114 3948 /* [RC 32] Interrupt register #0 read clear */ 3949 #define USEM_REG_USEM_INT_STS_CLR_0 0x300108 3950 #define USEM_REG_USEM_INT_STS_CLR_1 0x300118 3951 /* [RW 32] Parity mask register #0 read/write */ 3952 #define USEM_REG_USEM_PRTY_MASK_0 0x300130 3953 #define USEM_REG_USEM_PRTY_MASK_1 0x300140 3954 /* [R 32] Parity register #0 read */ 3955 #define USEM_REG_USEM_PRTY_STS_0 0x300124 3956 #define USEM_REG_USEM_PRTY_STS_1 0x300134 3957 /* [RC 32] Parity register #0 read clear */ 3958 #define USEM_REG_USEM_PRTY_STS_CLR_0 0x300128 3959 #define USEM_REG_USEM_PRTY_STS_CLR_1 0x300138 3960 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 3961 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. 3962 */ 3963 #define USEM_REG_VFPF_ERR_NUM 0x300380 3964 #define VFC_MEMORIES_RST_REG_CAM_RST (0x1 << 0) 3965 #define VFC_MEMORIES_RST_REG_RAM_RST (0x1 << 1) 3966 #define VFC_REG_MEMORIES_RST 0x1943c 3967 /* [RW 1] Interrupt mask register #0 read/write */ 3968 #define VFC_REG_VFC_INT_MASK 0x194f0 3969 /* [R 1] Interrupt register #0 read */ 3970 #define VFC_REG_VFC_INT_STS 0x194fc 3971 /* [RC 1] Interrupt register #0 read clear */ 3972 #define VFC_REG_VFC_INT_STS_CLR 0x194f8 3973 /* [RW 1] Parity mask register #0 read/write */ 3974 #define VFC_REG_VFC_PRTY_MASK 0x194e0 3975 /* [R 1] Parity register #0 read */ 3976 #define VFC_REG_VFC_PRTY_STS 0x194ec 3977 /* [RC 1] Parity register #0 read clear */ 3978 #define VFC_REG_VFC_PRTY_STS_CLR 0x194e8 3979 /* [R 5] Used to read the XX protection CAM occupancy counter. */ 3980 #define XCM_REG_CAM_OCCUP 0x20244 3981 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes 3982 * the initial credit value; read returns the current value of the credit 3983 * counter. Must be initialized to 1 at start-up. 3984 */ 3985 #define XCM_REG_CFC_INIT_CRD 0x20404 3986 /* [RC 1] Set at message length mismatch (relative to last indication) at 3987 * the csem interface. 3988 */ 3989 #define XCM_REG_CSEM_LENGTH_MIS 0x20228 3990 /* [RC 1] Set at message length mismatch (relative to last indication) at 3991 * the dorq interface. 3992 */ 3993 #define XCM_REG_DORQ_LENGTH_MIS 0x20230 3994 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write 3995 * writes the initial credit value; read returns the current value of the 3996 * credit counter. Must be initialized to 64 at start-up. 3997 */ 3998 #define XCM_REG_FIC0_INIT_CRD 0x2040c 3999 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write 4000 * writes the initial credit value; read returns the current value of the 4001 * credit counter. Must be initialized to 64 at start-up. 4002 */ 4003 #define XCM_REG_FIC1_INIT_CRD 0x20410 4004 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118 4005 /* [RC 1] Set at message length mismatch (relative to last indication) at 4006 * the nig0 interface. 4007 */ 4008 #define XCM_REG_NIG0_LENGTH_MIS 0x20238 4009 /* [RC 1] Set at message length mismatch (relative to last indication) at 4010 * the nig1 interface. 4011 */ 4012 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c 4013 /* [RC 1] Set at message length mismatch (relative to last indication) at 4014 * the pbf interface. 4015 */ 4016 #define XCM_REG_PBF_LENGTH_MIS 0x20234 4017 /* [RC 1] Set at message length mismatch (relative to last indication) at 4018 * the STORM interface. 4019 */ 4020 #define XCM_REG_STORM_LENGTH_MIS 0x2021c 4021 /* [RW 4] Timers output initial credit. Max credit available - 15.Write 4022 * writes the initial credit value; read returns the current value of the 4023 * credit counter. Must be initialized to 4 at start-up. 4024 */ 4025 #define XCM_REG_TM_INIT_CRD 0x2041c 4026 /* [RC 1] Set at message length mismatch (relative to last indication) at 4027 * the tsem interface. 4028 */ 4029 #define XCM_REG_TSEM_LENGTH_MIS 0x20224 4030 /* [RC 1] Message length mismatch (relative to last indication) at the usem 4031 * interface. 4032 */ 4033 #define XCM_REG_USEM_LENGTH_MIS 0x2022c 4034 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4 4035 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4 4036 /* [RW 14] Interrupt mask register #0 read/write */ 4037 #define XCM_REG_XCM_INT_MASK 0x202b4 4038 /* [R 14] Interrupt register #0 read */ 4039 #define XCM_REG_XCM_INT_STS 0x202a8 4040 /* [RC 14] Interrupt register #0 read clear */ 4041 #define XCM_REG_XCM_INT_STS_CLR 0x202ac 4042 /* [RW 30] Parity mask register #0 read/write */ 4043 #define XCM_REG_XCM_PRTY_MASK 0x202c4 4044 /* [R 30] Parity register #0 read */ 4045 #define XCM_REG_XCM_PRTY_STS 0x202b8 4046 /* [RC 30] Parity register #0 read clear */ 4047 #define XCM_REG_XCM_PRTY_STS_CLR 0x202bc 4048 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes 4049 * the initial credit value; read returns the current value of the credit 4050 * counter. Must be initialized to 32 at start-up. 4051 */ 4052 #define XCM_REG_XQM_INIT_CRD 0x20420 4053 /* [RC 1] Set at message length mismatch (relative to last indication) at 4054 * the SDM interface. 4055 */ 4056 #define XCM_REG_XSDM_LENGTH_MIS 0x20220 4057 /* [RW 17] Indirect access to the descriptor table of the XX protection 4058 * mechanism. The fields are: [5:0] - message length; 11:6] - message 4059 * pointer; 16:12] - next pointer. 4060 */ 4061 #define XCM_REG_XX_DESCR_TABLE 0x20480 4062 #define XCM_REG_XX_DESCR_TABLE_SIZE 32 4063 /* [R 6] Used to read the XX protection Free counter. */ 4064 #define XCM_REG_XX_FREE 0x20240 4065 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS (0x1 << 0) 4066 #define XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS (0x1 << 1) 4067 #define XMAC_CTRL_REG_LINE_LOCAL_LPBK (0x1 << 2) 4068 #define XMAC_CTRL_REG_RX_EN (0x1 << 1) 4069 #define XMAC_CTRL_REG_SOFT_RESET (0x1 << 6) 4070 #define XMAC_CTRL_REG_TX_EN (0x1 << 0) 4071 #define XMAC_CTRL_REG_XLGMII_ALIGN_ENB (0x1 << 7) 4072 #define XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN (0x1 << 18) 4073 #define XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN (0x1 << 17) 4074 #define XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON (0x1 << 1) 4075 #define XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN (0x1 << 0) 4076 #define XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN (0x1 << 3) 4077 #define XMAC_PFC_CTRL_HI_REG_RX_PFC_EN (0x1 << 4) 4078 #define XMAC_PFC_CTRL_HI_REG_TX_PFC_EN (0x1 << 5) 4079 #define XMAC_REG_CLEAR_RX_LSS_STATUS 0x60 4080 #define XMAC_REG_CTRL 0 4081 /* [RW 16] Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 4082 * packets transmitted by the MAC 4083 */ 4084 #define XMAC_REG_CTRL_SA_HI 0x2c 4085 /* [RW 32] Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC 4086 * packets transmitted by the MAC 4087 */ 4088 #define XMAC_REG_CTRL_SA_LO 0x28 4089 #define XMAC_REG_EEE_CTRL 0xd8 4090 #define XMAC_REG_EEE_TIMERS_HI 0xe4 4091 #define XMAC_REG_PAUSE_CTRL 0x68 4092 #define XMAC_REG_PFC_CTRL 0x70 4093 #define XMAC_REG_PFC_CTRL_HI 0x74 4094 #define XMAC_REG_RX_LSS_CTRL 0x50 4095 #define XMAC_REG_RX_LSS_STATUS 0x58 4096 /* [RW 14] Maximum packet size in receive direction; exclusive of preamble & 4097 * CRC in strip mode 4098 */ 4099 #define XMAC_REG_RX_MAX_SIZE 0x40 4100 #define XMAC_REG_TX_CTRL 0x20 4101 #define XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE (0x1 << 0) 4102 #define XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE (0x1 << 1) 4103 /* [W 17] Generate an operation after completion; bit-16 is 4104 * AggVectIdx_valid; bits 15:8 are AggVectIdx; bits 7:5 are the TRIG and 4105 * bits 4:0 are the T124Param[4:0] 4106 */ 4107 #define XSDM_REG_OPERATION_GEN 0x1664c4 4108 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */ 4109 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548 4110 /* [R 1] parser fifo empty in sdm_sync block */ 4111 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550 4112 /* [R 1] parser serial fifo empty in sdm_sync block */ 4113 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558 4114 /* [RW 32] Interrupt mask register #0 read/write */ 4115 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c 4116 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac 4117 /* [R 32] Interrupt register #0 read */ 4118 #define XSDM_REG_XSDM_INT_STS_0 0x166290 4119 #define XSDM_REG_XSDM_INT_STS_1 0x1662a0 4120 /* [RC 32] Interrupt register #0 read clear */ 4121 #define XSDM_REG_XSDM_INT_STS_CLR_0 0x166294 4122 #define XSDM_REG_XSDM_INT_STS_CLR_1 0x1662a4 4123 /* [RW 11] Parity mask register #0 read/write */ 4124 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc 4125 /* [R 11] Parity register #0 read */ 4126 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0 4127 /* [RC 11] Parity register #0 read clear */ 4128 #define XSDM_REG_XSDM_PRTY_STS_CLR 0x1662b4 4129 /* [RW 32] This address space contains all registers and memories that are 4130 * placed in SEM_FAST block. The SEM_FAST registers are described in 4131 * appendix B. In order to access the SEM_FAST registers the base address 4132 * XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each 4133 * SEM_FAST register offset. 4134 */ 4135 #define XSEM_REG_FAST_MEMORY 0x2a0000 4136 /* [RW 15] Interrupt table Read and write access to it is not possible in 4137 * the middle of the work 4138 */ 4139 #define XSEM_REG_INT_TABLE 0x280400 4140 /* [WB 128] Debug only. Passive buffer memory */ 4141 #define XSEM_REG_PASSIVE_BUFFER 0x282000 4142 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */ 4143 #define XSEM_REG_PRAM 0x2c0000 4144 /* [R 20] Valid sleeping threads indication have bit per thread */ 4145 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c 4146 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */ 4147 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0 4148 /* [W 7] VF or PF ID for reset error bit. Values 0-63 reset error bit for 64 4149 * VF; values 64-67 reset error for 4 PF; values 68-127 are not valid. 4150 */ 4151 #define XSEM_REG_VFPF_ERR_NUM 0x280380 4152 /* [RW 32] Interrupt mask register #0 read/write */ 4153 #define XSEM_REG_XSEM_INT_MASK_0 0x280110 4154 #define XSEM_REG_XSEM_INT_MASK_1 0x280120 4155 /* [R 32] Interrupt register #0 read */ 4156 #define XSEM_REG_XSEM_INT_STS_0 0x280104 4157 #define XSEM_REG_XSEM_INT_STS_1 0x280114 4158 /* [RC 32] Interrupt register #0 read clear */ 4159 #define XSEM_REG_XSEM_INT_STS_CLR_0 0x280108 4160 #define XSEM_REG_XSEM_INT_STS_CLR_1 0x280118 4161 /* [RW 32] Parity mask register #0 read/write */ 4162 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130 4163 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140 4164 /* [R 32] Parity register #0 read */ 4165 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124 4166 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134 4167 /* [RC 32] Parity register #0 read clear */ 4168 #define XSEM_REG_XSEM_PRTY_STS_CLR_0 0x280128 4169 #define XSEM_REG_XSEM_PRTY_STS_CLR_1 0x280138 4170 #define MCPR_ACCESS_LOCK_LOCK (1L << 31) 4171 #define MCPR_IMC_COMMAND_ENABLE (1L << 31) 4172 #define MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT 16 4173 #define MCPR_IMC_COMMAND_OPERATION_BITSHIFT 28 4174 #define MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT 8 4175 #define MCPR_NVM_ACCESS_ENABLE_EN (1L << 0) 4176 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L << 1) 4177 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL << 0) 4178 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L << 0) 4179 #define MCPR_NVM_COMMAND_DOIT (1L << 4) 4180 #define MCPR_NVM_COMMAND_DONE (1L << 3) 4181 #define MCPR_NVM_COMMAND_FIRST (1L << 7) 4182 #define MCPR_NVM_COMMAND_LAST (1L << 8) 4183 #define MCPR_NVM_COMMAND_WR (1L << 5) 4184 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L << 9) 4185 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L << 5) 4186 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L << 1) 4187 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00 << 3) 4188 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01 << 3) 4189 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05 << 3) 4190 #define BIGMAC_REGISTER_RX_CONTROL (0x21 << 3) 4191 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46 << 3) 4192 #define BIGMAC_REGISTER_RX_LSS_STATUS (0x43 << 3) 4193 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23 << 3) 4194 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26 << 3) 4195 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42 << 3) 4196 #define BIGMAC_REGISTER_TX_CONTROL (0x07 << 3) 4197 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09 << 3) 4198 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A << 3) 4199 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08 << 3) 4200 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20 << 3) 4201 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C << 3) 4202 #define BIGMAC2_REGISTER_BMAC_CONTROL (0x00 << 3) 4203 #define BIGMAC2_REGISTER_BMAC_XGXS_CONTROL (0x01 << 3) 4204 #define BIGMAC2_REGISTER_CNT_MAX_SIZE (0x05 << 3) 4205 #define BIGMAC2_REGISTER_PFC_CONTROL (0x06 << 3) 4206 #define BIGMAC2_REGISTER_RX_CONTROL (0x3A << 3) 4207 #define BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS (0x62 << 3) 4208 #define BIGMAC2_REGISTER_RX_LSS_STAT (0x3E << 3) 4209 #define BIGMAC2_REGISTER_RX_MAX_SIZE (0x3C << 3) 4210 #define BIGMAC2_REGISTER_RX_STAT_GR64 (0x40 << 3) 4211 #define BIGMAC2_REGISTER_RX_STAT_GRIPJ (0x5f << 3) 4212 #define BIGMAC2_REGISTER_TX_CONTROL (0x1C << 3) 4213 #define BIGMAC2_REGISTER_TX_MAX_SIZE (0x1E << 3) 4214 #define BIGMAC2_REGISTER_TX_PAUSE_CONTROL (0x20 << 3) 4215 #define BIGMAC2_REGISTER_TX_SOURCE_ADDR (0x1D << 3) 4216 #define BIGMAC2_REGISTER_TX_STAT_GTBYT (0x39 << 3) 4217 #define BIGMAC2_REGISTER_TX_STAT_GTPOK (0x22 << 3) 4218 #define EMAC_LED_1000MB_OVERRIDE (1L << 1) 4219 #define EMAC_LED_100MB_OVERRIDE (1L << 2) 4220 #define EMAC_LED_10MB_OVERRIDE (1L << 3) 4221 #define EMAC_LED_OVERRIDE (1L << 0) 4222 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L << 26) 4223 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L << 26) 4224 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L << 26) 4225 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L << 26) 4226 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L << 26) 4227 #define EMAC_MDIO_COMM_DATA (0xffffL << 0) 4228 #define EMAC_MDIO_COMM_START_BUSY (1L << 29) 4229 #define EMAC_MDIO_MODE_AUTO_POLL (1L << 4) 4230 #define EMAC_MDIO_MODE_CLAUSE_45 (1L << 31) 4231 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3ffL << 16) 4232 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16 4233 #define EMAC_MDIO_STATUS_10MB (1L << 1) 4234 #define EMAC_MODE_25G_MODE (1L << 5) 4235 #define EMAC_MODE_HALF_DUPLEX (1L << 1) 4236 #define EMAC_MODE_PORT_GMII (2L << 2) 4237 #define EMAC_MODE_PORT_MII (1L << 2) 4238 #define EMAC_MODE_PORT_MII_10M (3L << 2) 4239 #define EMAC_MODE_RESET (1L << 0) 4240 #define EMAC_REG_EMAC_LED 0xc 4241 #define EMAC_REG_EMAC_MAC_MATCH 0x10 4242 #define EMAC_REG_EMAC_MDIO_COMM 0xac 4243 #define EMAC_REG_EMAC_MDIO_MODE 0xb4 4244 #define EMAC_REG_EMAC_MDIO_STATUS 0xb0 4245 #define EMAC_REG_EMAC_MODE 0x0 4246 #define EMAC_REG_EMAC_RX_MODE 0xc8 4247 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c 4248 #define EMAC_REG_EMAC_RX_STAT_AC 0x180 4249 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4 4250 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23 4251 #define EMAC_REG_EMAC_TX_MODE 0xbc 4252 #define EMAC_REG_EMAC_TX_STAT_AC 0x280 4253 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22 4254 #define EMAC_REG_RX_PFC_MODE 0x320 4255 #define EMAC_REG_RX_PFC_MODE_PRIORITIES (1L << 2) 4256 #define EMAC_REG_RX_PFC_MODE_RX_EN (1L << 1) 4257 #define EMAC_REG_RX_PFC_MODE_TX_EN (1L << 0) 4258 #define EMAC_REG_RX_PFC_PARAM 0x324 4259 #define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT 0 4260 #define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT 16 4261 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD 0x328 4262 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT (0xffff << 0) 4263 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT 0x330 4264 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT (0xffff << 0) 4265 #define EMAC_REG_RX_PFC_STATS_XON_RCVD 0x32c 4266 #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT (0xffff << 0) 4267 #define EMAC_REG_RX_PFC_STATS_XON_SENT 0x334 4268 #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT (0xffff << 0) 4269 #define EMAC_RX_MODE_FLOW_EN (1L << 2) 4270 #define EMAC_RX_MODE_KEEP_MAC_CONTROL (1L << 3) 4271 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L << 10) 4272 #define EMAC_RX_MODE_PROMISCUOUS (1L << 8) 4273 #define EMAC_RX_MODE_RESET (1L << 0) 4274 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L << 31) 4275 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L << 3) 4276 #define EMAC_TX_MODE_FLOW_EN (1L << 4) 4277 #define EMAC_TX_MODE_RESET (1L << 0) 4278 #define MISC_REGISTERS_GPIO_0 0 4279 #define MISC_REGISTERS_GPIO_1 1 4280 #define MISC_REGISTERS_GPIO_2 2 4281 #define MISC_REGISTERS_GPIO_3 3 4282 #define MISC_REGISTERS_GPIO_CLR_POS 16 4283 #define MISC_REGISTERS_GPIO_FLOAT (0xffL << 24) 4284 #define MISC_REGISTERS_GPIO_FLOAT_POS 24 4285 #define MISC_REGISTERS_GPIO_HIGH 1 4286 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2 4287 #define MISC_REGISTERS_GPIO_INT_CLR_POS 24 4288 #define MISC_REGISTERS_GPIO_INT_OUTPUT_CLR 0 4289 #define MISC_REGISTERS_GPIO_INT_OUTPUT_SET 1 4290 #define MISC_REGISTERS_GPIO_INT_SET_POS 16 4291 #define MISC_REGISTERS_GPIO_LOW 0 4292 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1 4293 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0 4294 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4 4295 #define MISC_REGISTERS_GPIO_SET_POS 8 4296 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588 4297 #define MISC_REGISTERS_RESET_REG_1_RST_BRB1 (0x1 << 0) 4298 #define MISC_REGISTERS_RESET_REG_1_RST_DORQ (0x1 << 19) 4299 #define MISC_REGISTERS_RESET_REG_1_RST_HC (0x1 << 29) 4300 #define MISC_REGISTERS_RESET_REG_1_RST_PXP (0x1 << 26) 4301 #define MISC_REGISTERS_RESET_REG_1_RST_PXPV (0x1 << 27) 4302 #define MISC_REGISTERS_RESET_REG_1_RST_QM (0x1 << 17) 4303 #define MISC_REGISTERS_RESET_REG_1_SET 0x584 4304 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598 4305 #define MISC_REGISTERS_RESET_REG_2_MSTAT0 (0x1 << 24) 4306 #define MISC_REGISTERS_RESET_REG_2_MSTAT1 (0x1 << 25) 4307 #define MISC_REGISTERS_RESET_REG_2_PGLC (0x1 << 19) 4308 #define MISC_REGISTERS_RESET_REG_2_RST_ATC (0x1 << 17) 4309 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1 << 0) 4310 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC1 (0x1 << 1) 4311 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0 (0x1 << 2) 4312 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1 << 14) 4313 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1 (0x1 << 3) 4314 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE (0x1 << 15) 4315 #define MISC_REGISTERS_RESET_REG_2_RST_GRC (0x1 << 4) 4316 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B (0x1 << 6) 4317 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE (0x1 << 8) 4318 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU (0x1 << 7) 4319 #define MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE (0x1 << 5) 4320 #define MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE (0x1 << 11) 4321 #define MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO (0x1 << 13) 4322 #define MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR (0x1 << 16) 4323 #define MISC_REGISTERS_RESET_REG_2_RST_RBCN (0x1 << 9) 4324 #define MISC_REGISTERS_RESET_REG_2_SET 0x594 4325 #define MISC_REGISTERS_RESET_REG_2_UMAC0 (0x1 << 20) 4326 #define MISC_REGISTERS_RESET_REG_2_UMAC1 (0x1 << 21) 4327 #define MISC_REGISTERS_RESET_REG_2_XMAC (0x1 << 22) 4328 #define MISC_REGISTERS_RESET_REG_2_XMAC_SOFT (0x1 << 23) 4329 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8 4330 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1 << 1) 4331 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1 << 2) 4332 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1 << 3) 4333 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1 << 0) 4334 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1 << 5) 4335 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1 << 6) 4336 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1 << 7) 4337 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1 << 4) 4338 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1 << 8) 4339 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4 4340 #define MISC_SPIO_CLR_POS 16 4341 #define MISC_SPIO_FLOAT (0xffL << 24) 4342 #define MISC_SPIO_FLOAT_POS 24 4343 #define MISC_SPIO_INPUT_HI_Z 2 4344 #define MISC_SPIO_INT_OLD_SET_POS 16 4345 #define MISC_SPIO_OUTPUT_HIGH 1 4346 #define MISC_SPIO_OUTPUT_LOW 0 4347 #define MISC_SPIO_SET_POS 8 4348 #define MISC_SPIO_SPIO4 0x10 4349 #define MISC_SPIO_SPIO5 0x20 4350 #define HW_LOCK_MAX_RESOURCE_VALUE 31 4351 #define HW_LOCK_RESOURCE_DCBX_ADMIN_MIB 13 4352 #define HW_LOCK_RESOURCE_DRV_FLAGS 10 4353 #define HW_LOCK_RESOURCE_GPIO 1 4354 #define HW_LOCK_RESOURCE_MDIO 0 4355 #define HW_LOCK_RESOURCE_NVRAM 12 4356 #define HW_LOCK_RESOURCE_PORT0_ATT_MASK 3 4357 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_0 8 4358 #define HW_LOCK_RESOURCE_RECOVERY_LEADER_1 9 4359 #define HW_LOCK_RESOURCE_RECOVERY_REG 11 4360 #define HW_LOCK_RESOURCE_RESET 5 4361 #define HW_LOCK_RESOURCE_SPIO 2 4362 #define AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT (0x1 << 4) 4363 #define AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR (0x1 << 5) 4364 #define AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT (0x1 << 19) 4365 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (0x1 << 18) 4366 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (0x1 << 31) 4367 #define AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR (0x1 << 30) 4368 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (0x1 << 9) 4369 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (0x1 << 8) 4370 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (0x1 << 7) 4371 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (0x1 << 6) 4372 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (0x1 << 29) 4373 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (0x1 << 28) 4374 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (0x1 << 1) 4375 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (0x1 << 0) 4376 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (0x1 << 18) 4377 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (0x1 << 11) 4378 #define AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR (0x1 << 10) 4379 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (0x1 << 13) 4380 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (0x1 << 12) 4381 #define AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 (0x1 << 2) 4382 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (0x1 << 12) 4383 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY (0x1 << 28) 4384 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY (0x1 << 31) 4385 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY (0x1 << 29) 4386 #define AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY (0x1 << 30) 4387 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (0x1 << 15) 4388 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (0x1 << 14) 4389 #define AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR (0x1 << 14) 4390 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (0x1 << 20) 4391 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT (0x1 << 31) 4392 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (0x1 << 30) 4393 #define AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR (0x1 << 0) 4394 #define AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT (0x1 << 2) 4395 #define AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR (0x1 << 3) 4396 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (0x1 << 5) 4397 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (0x1 << 4) 4398 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (0x1 << 3) 4399 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (0x1 << 2) 4400 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (0x1 << 3) 4401 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (0x1 << 2) 4402 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (0x1 << 22) 4403 #define AEU_INPUTS_ATTN_BITS_SPIO5 (0x1 << 15) 4404 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (0x1 << 27) 4405 #define AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR (0x1 << 26) 4406 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (0x1 << 5) 4407 #define AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR (0x1 << 4) 4408 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (0x1 << 25) 4409 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (0x1 << 24) 4410 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (0x1 << 29) 4411 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (0x1 << 28) 4412 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (0x1 << 23) 4413 #define AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR (0x1 << 22) 4414 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (0x1 << 27) 4415 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (0x1 << 26) 4416 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (0x1 << 21) 4417 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (0x1 << 20) 4418 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (0x1 << 25) 4419 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (0x1 << 24) 4420 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (0x1 << 16) 4421 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (0x1 << 9) 4422 #define AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR (0x1 << 8) 4423 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (0x1 << 7) 4424 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (0x1 << 6) 4425 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (0x1 << 11) 4426 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (0x1 << 10) 4427 #define RESERVED_GENERAL_ATTENTION_BIT_0 0 4428 4429 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x7ffe0 4430 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000 4431 4432 #define RESERVED_GENERAL_ATTENTION_BIT_6 6 4433 #define RESERVED_GENERAL_ATTENTION_BIT_7 7 4434 #define RESERVED_GENERAL_ATTENTION_BIT_8 8 4435 #define RESERVED_GENERAL_ATTENTION_BIT_9 9 4436 #define RESERVED_GENERAL_ATTENTION_BIT_10 10 4437 #define RESERVED_GENERAL_ATTENTION_BIT_11 11 4438 #define RESERVED_GENERAL_ATTENTION_BIT_12 12 4439 #define RESERVED_GENERAL_ATTENTION_BIT_13 13 4440 #define RESERVED_GENERAL_ATTENTION_BIT_14 14 4441 #define RESERVED_GENERAL_ATTENTION_BIT_15 15 4442 #define RESERVED_GENERAL_ATTENTION_BIT_16 16 4443 #define RESERVED_GENERAL_ATTENTION_BIT_17 17 4444 #define RESERVED_GENERAL_ATTENTION_BIT_18 18 4445 #define RESERVED_GENERAL_ATTENTION_BIT_19 19 4446 #define RESERVED_GENERAL_ATTENTION_BIT_20 20 4447 #define RESERVED_GENERAL_ATTENTION_BIT_21 21 4448 4449 /* storm asserts attention bits */ 4450 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7 4451 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8 4452 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9 4453 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10 4454 4455 /* mcp error attention bit */ 4456 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11 4457 4458 /*E1H NIG status sync attention mapped to group 4-7*/ 4459 #define LINK_SYNC_ATTENTION_BIT_FUNC_0 RESERVED_GENERAL_ATTENTION_BIT_12 4460 #define LINK_SYNC_ATTENTION_BIT_FUNC_1 RESERVED_GENERAL_ATTENTION_BIT_13 4461 #define LINK_SYNC_ATTENTION_BIT_FUNC_2 RESERVED_GENERAL_ATTENTION_BIT_14 4462 #define LINK_SYNC_ATTENTION_BIT_FUNC_3 RESERVED_GENERAL_ATTENTION_BIT_15 4463 #define LINK_SYNC_ATTENTION_BIT_FUNC_4 RESERVED_GENERAL_ATTENTION_BIT_16 4464 #define LINK_SYNC_ATTENTION_BIT_FUNC_5 RESERVED_GENERAL_ATTENTION_BIT_17 4465 #define LINK_SYNC_ATTENTION_BIT_FUNC_6 RESERVED_GENERAL_ATTENTION_BIT_18 4466 #define LINK_SYNC_ATTENTION_BIT_FUNC_7 RESERVED_GENERAL_ATTENTION_BIT_19 4467 4468 /* Used For Error Recovery: changing this will require more \ 4469 changes in code that assume 4470 * error recovery uses general attn bit20 ! 4471 */ 4472 #define ERROR_RECOVERY_ATTENTION_BIT \ 4473 RESERVED_GENERAL_ATTENTION_BIT_20 4474 #define RESERVED_ATTENTION_BIT \ 4475 RESERVED_GENERAL_ATTENTION_BIT_21 4476 4477 #define LATCHED_ATTN_RBCR 23 4478 #define LATCHED_ATTN_RBCT 24 4479 #define LATCHED_ATTN_RBCN 25 4480 #define LATCHED_ATTN_RBCU 26 4481 #define LATCHED_ATTN_RBCP 27 4482 #define LATCHED_ATTN_TIMEOUT_GRC 28 4483 #define LATCHED_ATTN_RSVD_GRC 29 4484 #define LATCHED_ATTN_ROM_PARITY_MCP 30 4485 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31 4486 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32 4487 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33 4488 4489 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32) 4490 #define GENERAL_ATTEN_OFFSET(atten_name) (1UL << ((94 + atten_name) % 32)) 4491 /* 4492 * This file defines GRC base address for every block. 4493 * This file is included by chipsim, asm microcode and cpp microcode. 4494 * These values are used in Design.xml on regBase attribute 4495 * Use the base with the generated offsets of specific registers. 4496 */ 4497 4498 #define GRCBASE_PXPCS 0x000000 4499 #define GRCBASE_PCICONFIG 0x002000 4500 #define GRCBASE_PCIREG 0x002400 4501 #define GRCBASE_EMAC0 0x008000 4502 #define GRCBASE_EMAC1 0x008400 4503 #define GRCBASE_DBU 0x008800 4504 #define GRCBASE_PGLUE_B 0x009000 4505 #define GRCBASE_MISC 0x00A000 4506 #define GRCBASE_DBG 0x00C000 4507 #define GRCBASE_NIG 0x010000 4508 #define GRCBASE_XCM 0x020000 4509 #define GRCBASE_PRS 0x040000 4510 #define GRCBASE_SRCH 0x040400 4511 #define GRCBASE_TSDM 0x042000 4512 #define GRCBASE_TCM 0x050000 4513 #define GRCBASE_BRB1 0x060000 4514 #define GRCBASE_MCP 0x080000 4515 #define GRCBASE_UPB 0x0C1000 4516 #define GRCBASE_CSDM 0x0C2000 4517 #define GRCBASE_USDM 0x0C4000 4518 #define GRCBASE_CCM 0x0D0000 4519 #define GRCBASE_UCM 0x0E0000 4520 #define GRCBASE_CDU 0x101000 4521 #define GRCBASE_DMAE 0x102000 4522 #define GRCBASE_PXP 0x103000 4523 #define GRCBASE_CFC 0x104000 4524 #define GRCBASE_HC 0x108000 4525 #define GRCBASE_ATC 0x110000 4526 #define GRCBASE_PXP2 0x120000 4527 #define GRCBASE_IGU 0x130000 4528 #define GRCBASE_PBF 0x140000 4529 #define GRCBASE_UMAC0 0x160000 4530 #define GRCBASE_UMAC1 0x160400 4531 #define GRCBASE_XPB 0x161000 4532 #define GRCBASE_MSTAT0 0x162000 4533 #define GRCBASE_MSTAT1 0x162800 4534 #define GRCBASE_XMAC0 0x163000 4535 #define GRCBASE_XMAC1 0x163800 4536 #define GRCBASE_TIMERS 0x164000 4537 #define GRCBASE_XSDM 0x166000 4538 #define GRCBASE_QM 0x168000 4539 #define GRCBASE_QM_4PORT 0x168000 4540 #define GRCBASE_DQ 0x170000 4541 #define GRCBASE_TSEM 0x180000 4542 #define GRCBASE_CSEM 0x200000 4543 #define GRCBASE_XSEM 0x280000 4544 #define GRCBASE_XSEM_4PORT 0x280000 4545 #define GRCBASE_USEM 0x300000 4546 #define GRCBASE_MCP_A 0x380000 4547 #define GRCBASE_MISC_AEU GRCBASE_MISC 4548 #define GRCBASE_Tstorm GRCBASE_TSEM 4549 #define GRCBASE_Cstorm GRCBASE_CSEM 4550 #define GRCBASE_Xstorm GRCBASE_XSEM 4551 #define GRCBASE_Ustorm GRCBASE_USEM 4552 4553 4554 /* offset of configuration space in the pci core register */ 4555 #define PCICFG_OFFSET 0x2000 4556 #define PCICFG_VENDOR_ID_OFFSET 0x00 4557 #define PCICFG_DEVICE_ID_OFFSET 0x02 4558 #define PCICFG_COMMAND_OFFSET 0x04 4559 #define PCICFG_COMMAND_IO_SPACE (1<<0) 4560 #define PCICFG_COMMAND_MEM_SPACE (1<<1) 4561 #define PCICFG_COMMAND_BUS_MASTER (1<<2) 4562 #define PCICFG_COMMAND_SPECIAL_CYCLES (1<<3) 4563 #define PCICFG_COMMAND_MWI_CYCLES (1<<4) 4564 #define PCICFG_COMMAND_VGA_SNOOP (1<<5) 4565 #define PCICFG_COMMAND_PERR_ENA (1<<6) 4566 #define PCICFG_COMMAND_STEPPING (1<<7) 4567 #define PCICFG_COMMAND_SERR_ENA (1<<8) 4568 #define PCICFG_COMMAND_FAST_B2B (1<<9) 4569 #define PCICFG_COMMAND_INT_DISABLE (1<<10) 4570 #define PCICFG_COMMAND_RESERVED (0x1f<<11) 4571 #define PCICFG_STATUS_OFFSET 0x06 4572 #define PCICFG_REVISION_ID_OFFSET 0x08 4573 #define PCICFG_REVESION_ID_MASK 0xff 4574 #define PCICFG_REVESION_ID_ERROR_VAL 0xff 4575 #define PCICFG_CACHE_LINE_SIZE 0x0c 4576 #define PCICFG_LATENCY_TIMER 0x0d 4577 #define PCICFG_HEADER_TYPE 0x0e 4578 #define PCICFG_HEADER_TYPE_NORMAL 0 4579 #define PCICFG_HEADER_TYPE_BRIDGE 1 4580 #define PCICFG_HEADER_TYPE_CARDBUS 2 4581 #define PCICFG_BAR_1_LOW 0x10 4582 #define PCICFG_BAR_1_HIGH 0x14 4583 #define PCICFG_BAR_2_LOW 0x18 4584 #define PCICFG_BAR_2_HIGH 0x1c 4585 #define PCICFG_BAR_3_LOW 0x20 4586 #define PCICFG_BAR_3_HIGH 0x24 4587 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c 4588 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e 4589 #define PCICFG_INT_LINE 0x3c 4590 #define PCICFG_INT_PIN 0x3d 4591 #define PCICFG_PM_CAPABILITY 0x48 4592 #define PCICFG_PM_CAPABILITY_VERSION (0x3<<16) 4593 #define PCICFG_PM_CAPABILITY_CLOCK (1<<19) 4594 #define PCICFG_PM_CAPABILITY_RESERVED (1<<20) 4595 #define PCICFG_PM_CAPABILITY_DSI (1<<21) 4596 #define PCICFG_PM_CAPABILITY_AUX_CURRENT (0x7<<22) 4597 #define PCICFG_PM_CAPABILITY_D1_SUPPORT (1<<25) 4598 #define PCICFG_PM_CAPABILITY_D2_SUPPORT (1<<26) 4599 #define PCICFG_PM_CAPABILITY_PME_IN_D0 (1<<27) 4600 #define PCICFG_PM_CAPABILITY_PME_IN_D1 (1<<28) 4601 #define PCICFG_PM_CAPABILITY_PME_IN_D2 (1<<29) 4602 #define PCICFG_PM_CAPABILITY_PME_IN_D3_HOT (1<<30) 4603 #define PCICFG_PM_CAPABILITY_PME_IN_D3_COLD (1<<31) 4604 #define PCICFG_PM_CSR_OFFSET 0x4c 4605 #define PCICFG_PM_CSR_STATE (0x3<<0) 4606 #define PCICFG_PM_CSR_PME_ENABLE (1<<8) 4607 #define PCICFG_PM_CSR_PME_STATUS (1<<15) 4608 #define PCICFG_VPD_FLAG_ADDR_OFFSET 0x50 4609 #define PCICFG_VPD_DATA_OFFSET 0x54 4610 #define PCICFG_MSI_CAP_ID_OFFSET 0x58 4611 #define PCICFG_MSI_CONTROL_ENABLE (0x1<<16) 4612 #define PCICFG_MSI_CONTROL_MCAP (0x7<<17) 4613 #define PCICFG_MSI_CONTROL_MENA (0x7<<20) 4614 #define PCICFG_MSI_CONTROL_64_BIT_ADDR_CAP (0x1<<23) 4615 #define PCICFG_MSI_CONTROL_MSI_PVMASK_CAPABLE (0x1<<24) 4616 #define PCICFG_MSI_ADDR_LOW_OFFSET 0x5c 4617 #define PCICFG_MSI_ADDR_HIGH_OFFSET 0x60 4618 #define PCICFG_MSI_DATA_OFFSET 0x64 4619 #define PCICFG_GRC_ADDRESS 0x78 4620 #define PCICFG_GRC_DATA 0x80 4621 #define PCICFG_ME_REGISTER 0x98 4622 #define PCICFG_MSIX_CAP_ID_OFFSET 0xa0 4623 #define PCICFG_MSIX_CONTROL_TABLE_SIZE (0x7ff<<16) 4624 #define PCICFG_MSIX_CONTROL_RESERVED (0x7<<27) 4625 #define PCICFG_MSIX_CONTROL_FUNC_MASK (0x1<<30) 4626 #define PCICFG_MSIX_CONTROL_MSIX_ENABLE (0x1<<31) 4627 4628 #define PCICFG_DEVICE_CONTROL 0xb4 4629 #define PCICFG_DEVICE_CONTROL_NP_TRANSACTION_PEND (1<<21) 4630 #define PCICFG_DEVICE_STATUS 0xb6 4631 #define PCICFG_DEVICE_STATUS_CORR_ERR_DET (1<<0) 4632 #define PCICFG_DEVICE_STATUS_NON_FATAL_ERR_DET (1<<1) 4633 #define PCICFG_DEVICE_STATUS_FATAL_ERR_DET (1<<2) 4634 #define PCICFG_DEVICE_STATUS_UNSUP_REQ_DET (1<<3) 4635 #define PCICFG_DEVICE_STATUS_AUX_PWR_DET (1<<4) 4636 #define PCICFG_DEVICE_STATUS_NO_PEND (1<<5) 4637 #define PCICFG_LINK_CONTROL 0xbc 4638 4639 4640 /* config_2 offset */ 4641 #define GRC_CONFIG_2_SIZE_REG 0x408 4642 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) 4643 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0) 4644 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) 4645 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0) 4646 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0) 4647 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0) 4648 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) 4649 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) 4650 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) 4651 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) 4652 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) 4653 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) 4654 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) 4655 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0) 4656 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0) 4657 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0) 4658 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) 4659 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4) 4660 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) 4661 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6) 4662 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7) 4663 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) 4664 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8) 4665 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8) 4666 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8) 4667 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8) 4668 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8) 4669 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8) 4670 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8) 4671 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8) 4672 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8) 4673 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8) 4674 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8) 4675 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8) 4676 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8) 4677 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8) 4678 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8) 4679 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8) 4680 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16) 4681 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17) 4682 4683 /* config_3 offset */ 4684 #define GRC_CONFIG_3_SIZE_REG 0x40c 4685 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) 4686 #define PCI_CONFIG_3_FORCE_PME (1L<<24) 4687 #define PCI_CONFIG_3_PME_STATUS (1L<<25) 4688 #define PCI_CONFIG_3_PME_ENABLE (1L<<26) 4689 #define PCI_CONFIG_3_PM_STATE (0x3L<<27) 4690 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30) 4691 #define PCI_CONFIG_3_PCI_POWER (1L<<31) 4692 4693 #define GRC_REG_DEVICE_CONTROL 0x4d8 4694 #define PCIE_SRIOV_DISABLE_IN_PROGRESS \ 4695 (1 << 29) /*When VF Enable is cleared(after it was previously set), 4696 this register will read a value of 1, indicating that all the 4697 VFs that belong to this PF should be flushed. 4698 Software should clear this bit within 1 second of VF Enable 4699 being set by writing a 1 to it, so that VFs are visible to the system again. 4700 WC */ 4701 #define PCIE_FLR_IN_PROGRESS \ 4702 (1 << 27) /*When FLR is initiated, this register will read a \ 4703 value of 1 indicating that the 4704 Function is in FLR state. Func can be brought out of FLR state either by 4705 writing 1 to this register (at least 50 ms after FLR was initiated), 4706 or it can also be cleared automatically after 55 ms if auto_clear bit 4707 in private reg space is set. This bit also exists in VF register space 4708 WC */ 4709 4710 #define GRC_BAR2_CONFIG 0x4e0 4711 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0) 4712 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0) 4713 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0) 4714 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0) 4715 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0) 4716 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0) 4717 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0) 4718 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0) 4719 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0) 4720 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0) 4721 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0) 4722 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0) 4723 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0) 4724 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0) 4725 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0) 4726 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0) 4727 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0) 4728 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4) 4729 4730 #define GRC_BAR3_CONFIG 0x4f4 4731 #define PCI_CONFIG_2_BAR3_SIZE (0xfL<<0) 4732 #define PCI_CONFIG_2_BAR3_SIZE_DISABLED (0L<<0) 4733 #define PCI_CONFIG_2_BAR3_SIZE_64K (1L<<0) 4734 #define PCI_CONFIG_2_BAR3_SIZE_128K (2L<<0) 4735 #define PCI_CONFIG_2_BAR3_SIZE_256K (3L<<0) 4736 #define PCI_CONFIG_2_BAR3_SIZE_512K (4L<<0) 4737 #define PCI_CONFIG_2_BAR3_SIZE_1M (5L<<0) 4738 #define PCI_CONFIG_2_BAR3_SIZE_2M (6L<<0) 4739 #define PCI_CONFIG_2_BAR3_SIZE_4M (7L<<0) 4740 #define PCI_CONFIG_2_BAR3_SIZE_8M (8L<<0) 4741 #define PCI_CONFIG_2_BAR3_SIZE_16M (9L<<0) 4742 #define PCI_CONFIG_2_BAR3_SIZE_32M (10L<<0) 4743 #define PCI_CONFIG_2_BAR3_SIZE_64M (11L<<0) 4744 #define PCI_CONFIG_2_BAR3_SIZE_128M (12L<<0) 4745 #define PCI_CONFIG_2_BAR3_SIZE_256M (13L<<0) 4746 #define PCI_CONFIG_2_BAR3_SIZE_512M (14L<<0) 4747 #define PCI_CONFIG_2_BAR3_SIZE_1G (15L<<0) 4748 #define PCI_CONFIG_2_BAR3_64ENA (1L<<4) 4749 4750 #define PCI_PM_DATA_A 0x410 4751 #define PCI_PM_DATA_B 0x414 4752 #define PCI_ID_VAL1 0x434 4753 #define PCI_ID_VAL2 0x438 4754 #define PCI_ID_VAL3 0x43c 4755 #define PCI_ID_VAL3_REVISION_ID_ERROR (0xffL<<24) 4756 4757 4758 #define GRC_CONFIG_REG_VF_BAR_REG_1 0x608 4759 #define GRC_CONFIG_REG_VF_BAR_REG_BAR0_SIZE 0xf 4760 4761 #define GRC_CONFIG_REG_VF_MSIX_CONTROL 0x61C 4762 #define GRC_CR_VF_MSIX_CTRL_VF_MSIX_TBL_SIZE_MASK \ 4763 0x3F /*This field resides in VF only and does not exist in PF. 4764 This register controls the read value of the MSIX_CONTROL[10:0] register 4765 in the VF configuration space. A value of "00000000011" indicates 4766 a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ 4767 define in version.v */ 4768 4769 #define GRC_CONFIG_REG_PF_INIT_VF 0x624 4770 #define GRC_CR_PF_INIT_VF_PF_FIRST_VF_NUM_MASK \ 4771 0xf /*First VF_NUM for PF is encoded in this register. 4772 The number of VFs assigned to a PF is assumed to be a multiple of 8. 4773 Software should program these bits based on Total Number of VFs \ 4774 programmed for each PF. 4775 Since registers from 0x000-0x7ff are spilt across functions, each PF will have 4776 the same location for the same 4 bits*/ 4777 4778 #define PXPCS_TL_CONTROL_5 0x814 4779 #define PXPCS_TL_CONTROL_5_UNKNOWNTYPE_ERR_ATTN (1 << 29) /*WC*/ 4780 #define PXPCS_TL_CONTROL_5_BOUNDARY4K_ERR_ATTN (1 << 28) /*WC*/ 4781 #define PXPCS_TL_CONTROL_5_MRRS_ERR_ATTN (1 << 27) /*WC*/ 4782 #define PXPCS_TL_CONTROL_5_MPS_ERR_ATTN (1 << 26) /*WC*/ 4783 #define PXPCS_TL_CONTROL_5_TTX_BRIDGE_FORWARD_ERR (1 << 25) /*WC*/ 4784 #define PXPCS_TL_CONTROL_5_TTX_TXINTF_OVERFLOW (1 << 24) /*WC*/ 4785 #define PXPCS_TL_CONTROL_5_PHY_ERR_ATTN (1 << 23) /*RO*/ 4786 #define PXPCS_TL_CONTROL_5_DL_ERR_ATTN (1 << 22) /*RO*/ 4787 #define PXPCS_TL_CONTROL_5_TTX_ERR_NP_TAG_IN_USE (1 << 21) /*WC*/ 4788 #define PXPCS_TL_CONTROL_5_TRX_ERR_UNEXP_RTAG (1 << 20) /*WC*/ 4789 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT1 (1 << 19) /*WC*/ 4790 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 (1 << 18) /*WC*/ 4791 #define PXPCS_TL_CONTROL_5_ERR_ECRC1 (1 << 17) /*WC*/ 4792 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP1 (1 << 16) /*WC*/ 4793 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW1 (1 << 15) /*WC*/ 4794 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL1 (1 << 14) /*WC*/ 4795 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT1 (1 << 13) /*WC*/ 4796 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT1 (1 << 12) /*WC*/ 4797 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL1 (1 << 11) /*WC*/ 4798 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP1 (1 << 10) /*WC*/ 4799 #define PXPCS_TL_CONTROL_5_PRI_SIG_TARGET_ABORT (1 << 9) /*WC*/ 4800 #define PXPCS_TL_CONTROL_5_ERR_UNSPPORT (1 << 8) /*WC*/ 4801 #define PXPCS_TL_CONTROL_5_ERR_ECRC (1 << 7) /*WC*/ 4802 #define PXPCS_TL_CONTROL_5_ERR_MALF_TLP (1 << 6) /*WC*/ 4803 #define PXPCS_TL_CONTROL_5_ERR_RX_OFLOW (1 << 5) /*WC*/ 4804 #define PXPCS_TL_CONTROL_5_ERR_UNEXP_CPL (1 << 4) /*WC*/ 4805 #define PXPCS_TL_CONTROL_5_ERR_MASTER_ABRT (1 << 3) /*WC*/ 4806 #define PXPCS_TL_CONTROL_5_ERR_CPL_TIMEOUT (1 << 2) /*WC*/ 4807 #define PXPCS_TL_CONTROL_5_ERR_FC_PRTL (1 << 1) /*WC*/ 4808 #define PXPCS_TL_CONTROL_5_ERR_PSND_TLP (1 << 0) /*WC*/ 4809 4810 4811 #define PXPCS_TL_FUNC345_STAT 0x854 4812 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4 (1 << 29) /* WC */ 4813 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 \ 4814 (1 << 28) /* Unsupported Request Error Status in function4, if \ 4815 set, generate pcie_err_attn output when this error is seen. WC */ 4816 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC4 \ 4817 (1 << 27) /* ECRC Error TLP Status Status in function 4, if set, \ 4818 generate pcie_err_attn output when this error is seen.. WC */ 4819 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP4 \ 4820 (1 << 26) /* Malformed TLP Status Status in function 4, if set, \ 4821 generate pcie_err_attn output when this error is seen.. WC */ 4822 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW4 \ 4823 (1 << 25) /* Receiver Overflow Status Status in function 4, if \ 4824 set, generate pcie_err_attn output when this error is seen.. WC \ 4825 */ 4826 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL4 \ 4827 (1 << 24) /* Unexpected Completion Status Status in function 4, \ 4828 if set, generate pcie_err_attn output when this error is seen. WC \ 4829 */ 4830 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT4 \ 4831 (1 << 23) /* Receive UR Statusin function 4. If set, generate \ 4832 pcie_err_attn output when this error is seen. WC */ 4833 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4 \ 4834 (1 << 22) /* Completer Timeout Status Status in function 4, if \ 4835 set, generate pcie_err_attn output when this error is seen. WC */ 4836 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL4 \ 4837 (1 << 21) /* Flow Control Protocol Error Status Status in \ 4838 function 4, if set, generate pcie_err_attn output when this error \ 4839 is seen. WC */ 4840 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP4 \ 4841 (1 << 20) /* Poisoned Error Status Status in function 4, if set, \ 4842 generate pcie_err_attn output when this error is seen.. WC */ 4843 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3 (1 << 19) /* WC */ 4844 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 \ 4845 (1 << 18) /* Unsupported Request Error Status in function3, if \ 4846 set, generate pcie_err_attn output when this error is seen. WC */ 4847 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC3 \ 4848 (1 << 17) /* ECRC Error TLP Status Status in function 3, if set, \ 4849 generate pcie_err_attn output when this error is seen.. WC */ 4850 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP3 \ 4851 (1 << 16) /* Malformed TLP Status Status in function 3, if set, \ 4852 generate pcie_err_attn output when this error is seen.. WC */ 4853 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW3 \ 4854 (1 << 15) /* Receiver Overflow Status Status in function 3, if \ 4855 set, generate pcie_err_attn output when this error is seen.. WC \ 4856 */ 4857 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL3 \ 4858 (1 << 14) /* Unexpected Completion Status Status in function 3, \ 4859 if set, generate pcie_err_attn output when this error is seen. WC \ 4860 */ 4861 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT3 \ 4862 (1 << 13) /* Receive UR Statusin function 3. If set, generate \ 4863 pcie_err_attn output when this error is seen. WC */ 4864 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3 \ 4865 (1 << 12) /* Completer Timeout Status Status in function 3, if \ 4866 set, generate pcie_err_attn output when this error is seen. WC */ 4867 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL3 \ 4868 (1 << 11) /* Flow Control Protocol Error Status Status in \ 4869 function 3, if set, generate pcie_err_attn output when this error \ 4870 is seen. WC */ 4871 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP3 \ 4872 (1 << 10) /* Poisoned Error Status Status in function 3, if set, \ 4873 generate pcie_err_attn output when this error is seen.. WC */ 4874 #define PXPCS_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2 (1 << 9) /* WC */ 4875 #define PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2 \ 4876 (1 << 8) /* Unsupported Request Error Status for Function 2, if \ 4877 set, generate pcie_err_attn output when this error is seen. WC */ 4878 #define PXPCS_TL_FUNC345_STAT_ERR_ECRC2 \ 4879 (1 << 7) /* ECRC Error TLP Status Status for Function 2, if set, \ 4880 generate pcie_err_attn output when this error is seen.. WC */ 4881 #define PXPCS_TL_FUNC345_STAT_ERR_MALF_TLP2 \ 4882 (1 << 6) /* Malformed TLP Status Status for Function 2, if set, \ 4883 generate pcie_err_attn output when this error is seen.. WC */ 4884 #define PXPCS_TL_FUNC345_STAT_ERR_RX_OFLOW2 \ 4885 (1 << 5) /* Receiver Overflow Status Status for Function 2, if \ 4886 set, generate pcie_err_attn output when this error is seen.. WC \ 4887 */ 4888 #define PXPCS_TL_FUNC345_STAT_ERR_UNEXP_CPL2 \ 4889 (1 << 4) /* Unexpected Completion Status Status for Function 2, \ 4890 if set, generate pcie_err_attn output when this error is seen. WC \ 4891 */ 4892 #define PXPCS_TL_FUNC345_STAT_ERR_MASTER_ABRT2 \ 4893 (1 << 3) /* Receive UR Statusfor Function 2. If set, generate \ 4894 pcie_err_attn output when this error is seen. WC */ 4895 #define PXPCS_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2 \ 4896 (1 << 2) /* Completer Timeout Status Status for Function 2, if \ 4897 set, generate pcie_err_attn output when this error is seen. WC */ 4898 #define PXPCS_TL_FUNC345_STAT_ERR_FC_PRTL2 \ 4899 (1 << 1) /* Flow Control Protocol Error Status Status for \ 4900 Function 2, if set, generate pcie_err_attn output when this error \ 4901 is seen. WC */ 4902 #define PXPCS_TL_FUNC345_STAT_ERR_PSND_TLP2 \ 4903 (1 << 0) /* Poisoned Error Status Status for Function 2, if set, \ 4904 generate pcie_err_attn output when this error is seen.. WC */ 4905 4906 4907 #define PXPCS_TL_FUNC678_STAT 0x85C 4908 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7 (1 << 29) /* WC */ 4909 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 \ 4910 (1 << 28) /* Unsupported Request Error Status in function7, if \ 4911 set, generate pcie_err_attn output when this error is seen. WC */ 4912 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC7 \ 4913 (1 << 27) /* ECRC Error TLP Status Status in function 7, if set, \ 4914 generate pcie_err_attn output when this error is seen.. WC */ 4915 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP7 \ 4916 (1 << 26) /* Malformed TLP Status Status in function 7, if set, \ 4917 generate pcie_err_attn output when this error is seen.. WC */ 4918 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW7 \ 4919 (1 << 25) /* Receiver Overflow Status Status in function 7, if \ 4920 set, generate pcie_err_attn output when this error is seen.. WC \ 4921 */ 4922 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL7 \ 4923 (1 << 24) /* Unexpected Completion Status Status in function 7, \ 4924 if set, generate pcie_err_attn output when this error is seen. WC \ 4925 */ 4926 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT7 \ 4927 (1 << 23) /* Receive UR Statusin function 7. If set, generate \ 4928 pcie_err_attn output when this error is seen. WC */ 4929 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7 \ 4930 (1 << 22) /* Completer Timeout Status Status in function 7, if \ 4931 set, generate pcie_err_attn output when this error is seen. WC */ 4932 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL7 \ 4933 (1 << 21) /* Flow Control Protocol Error Status Status in \ 4934 function 7, if set, generate pcie_err_attn output when this error \ 4935 is seen. WC */ 4936 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP7 \ 4937 (1 << 20) /* Poisoned Error Status Status in function 7, if set, \ 4938 generate pcie_err_attn output when this error is seen.. WC */ 4939 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6 (1 << 19) /* WC */ 4940 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 \ 4941 (1 << 18) /* Unsupported Request Error Status in function6, if \ 4942 set, generate pcie_err_attn output when this error is seen. WC */ 4943 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC6 \ 4944 (1 << 17) /* ECRC Error TLP Status Status in function 6, if set, \ 4945 generate pcie_err_attn output when this error is seen.. WC */ 4946 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP6 \ 4947 (1 << 16) /* Malformed TLP Status Status in function 6, if set, \ 4948 generate pcie_err_attn output when this error is seen.. WC */ 4949 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW6 \ 4950 (1 << 15) /* Receiver Overflow Status Status in function 6, if \ 4951 set, generate pcie_err_attn output when this error is seen.. WC \ 4952 */ 4953 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL6 \ 4954 (1 << 14) /* Unexpected Completion Status Status in function 6, \ 4955 if set, generate pcie_err_attn output when this error is seen. WC \ 4956 */ 4957 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT6 \ 4958 (1 << 13) /* Receive UR Statusin function 6. If set, generate \ 4959 pcie_err_attn output when this error is seen. WC */ 4960 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6 \ 4961 (1 << 12) /* Completer Timeout Status Status in function 6, if \ 4962 set, generate pcie_err_attn output when this error is seen. WC */ 4963 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL6 \ 4964 (1 << 11) /* Flow Control Protocol Error Status Status in \ 4965 function 6, if set, generate pcie_err_attn output when this error \ 4966 is seen. WC */ 4967 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP6 \ 4968 (1 << 10) /* Poisoned Error Status Status in function 6, if set, \ 4969 generate pcie_err_attn output when this error is seen.. WC */ 4970 #define PXPCS_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5 (1 << 9) /* WC */ 4971 #define PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5 \ 4972 (1 << 8) /* Unsupported Request Error Status for Function 5, if \ 4973 set, generate pcie_err_attn output when this error is seen. WC */ 4974 #define PXPCS_TL_FUNC678_STAT_ERR_ECRC5 \ 4975 (1 << 7) /* ECRC Error TLP Status Status for Function 5, if set, \ 4976 generate pcie_err_attn output when this error is seen.. WC */ 4977 #define PXPCS_TL_FUNC678_STAT_ERR_MALF_TLP5 \ 4978 (1 << 6) /* Malformed TLP Status Status for Function 5, if set, \ 4979 generate pcie_err_attn output when this error is seen.. WC */ 4980 #define PXPCS_TL_FUNC678_STAT_ERR_RX_OFLOW5 \ 4981 (1 << 5) /* Receiver Overflow Status Status for Function 5, if \ 4982 set, generate pcie_err_attn output when this error is seen.. WC \ 4983 */ 4984 #define PXPCS_TL_FUNC678_STAT_ERR_UNEXP_CPL5 \ 4985 (1 << 4) /* Unexpected Completion Status Status for Function 5, \ 4986 if set, generate pcie_err_attn output when this error is seen. WC \ 4987 */ 4988 #define PXPCS_TL_FUNC678_STAT_ERR_MASTER_ABRT5 \ 4989 (1 << 3) /* Receive UR Statusfor Function 5. If set, generate \ 4990 pcie_err_attn output when this error is seen. WC */ 4991 #define PXPCS_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5 \ 4992 (1 << 2) /* Completer Timeout Status Status for Function 5, if \ 4993 set, generate pcie_err_attn output when this error is seen. WC */ 4994 #define PXPCS_TL_FUNC678_STAT_ERR_FC_PRTL5 \ 4995 (1 << 1) /* Flow Control Protocol Error Status Status for \ 4996 Function 5, if set, generate pcie_err_attn output when this error \ 4997 is seen. WC */ 4998 #define PXPCS_TL_FUNC678_STAT_ERR_PSND_TLP5 \ 4999 (1 << 0) /* Poisoned Error Status Status for Function 5, if set, \ 5000 generate pcie_err_attn output when this error is seen.. WC */ 5001 5002 5003 #define BAR_USTRORM_INTMEM 0x400000 5004 #define BAR_CSTRORM_INTMEM 0x410000 5005 #define BAR_XSTRORM_INTMEM 0x420000 5006 #define BAR_TSTRORM_INTMEM 0x430000 5007 5008 /* for accessing the IGU in case of status block ACK */ 5009 #define BAR_IGU_INTMEM 0x440000 5010 5011 #define BAR_DOORBELL_OFFSET 0x800000 5012 5013 #define BAR_ME_REGISTER 0x450000 5014 #define ME_REG_PF_NUM_SHIFT 0 5015 #define ME_REG_PF_NUM \ 5016 (7L<<ME_REG_PF_NUM_SHIFT) /* Relative PF Num */ 5017 #define ME_REG_VF_VALID (1<<8) 5018 #define ME_REG_VF_NUM_SHIFT 9 5019 #define ME_REG_VF_NUM_MASK (0x3f<<ME_REG_VF_NUM_SHIFT) 5020 #define VF_ID(x) 0 /* TODO: remove def */ 5021 #define ME_REG_VF_ERR (0x1<<3) 5022 #define ME_REG_ABS_PF_NUM_SHIFT 16 5023 #define ME_REG_ABS_PF_NUM \ 5024 (7L<<ME_REG_ABS_PF_NUM_SHIFT) /* Absolute PF Num */ 5025 5026 5027 #define PXP_VF_ADRR_NUM_QUEUES 136 5028 #define PXP_ADDR_QUEUE_SIZE 32 5029 #define PXP_ADDR_REG_SIZE 512 5030 5031 5032 #define PXP_VF_ADDR_IGU_START 0 5033 #define PXP_VF_ADDR_IGU_SIZE (0x3000) 5034 #define PXP_VF_ADDR_IGU_END \ 5035 ((PXP_VF_ADDR_IGU_START) + (PXP_VF_ADDR_IGU_SIZE) - 1) 5036 5037 #define PXP_VF_ADDR_USDM_QUEUES_START 0x3000 5038 #define PXP_VF_ADDR_USDM_QUEUES_SIZE \ 5039 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 5040 #define PXP_VF_ADDR_USDM_QUEUES_END \ 5041 ((PXP_VF_ADDR_USDM_QUEUES_START) + (PXP_VF_ADDR_USDM_QUEUES_SIZE) - 1) 5042 5043 #define PXP_VF_ADDR_CSDM_QUEUES_START 0x4100 5044 #define PXP_VF_ADDR_CSDM_QUEUES_SIZE \ 5045 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 5046 #define PXP_VF_ADDR_CSDM_QUEUES_END \ 5047 ((PXP_VF_ADDR_CSDM_QUEUES_START) + (PXP_VF_ADDR_CSDM_QUEUES_SIZE) - 1) 5048 5049 #define PXP_VF_ADDR_XSDM_QUEUES_START 0x5200 5050 #define PXP_VF_ADDR_XSDM_QUEUES_SIZE \ 5051 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 5052 #define PXP_VF_ADDR_XSDM_QUEUES_END \ 5053 ((PXP_VF_ADDR_XSDM_QUEUES_START) + (PXP_VF_ADDR_XSDM_QUEUES_SIZE) - 1) 5054 5055 #define PXP_VF_ADDR_TSDM_QUEUES_START 0x6300 5056 #define PXP_VF_ADDR_TSDM_QUEUES_SIZE \ 5057 (PXP_VF_ADRR_NUM_QUEUES * PXP_ADDR_QUEUE_SIZE) 5058 #define PXP_VF_ADDR_TSDM_QUEUES_END \ 5059 ((PXP_VF_ADDR_TSDM_QUEUES_START) + (PXP_VF_ADDR_TSDM_QUEUES_SIZE) - 1) 5060 5061 #define PXP_VF_ADDR_USDM_GLOBAL_START 0x7400 5062 #define PXP_VF_ADDR_USDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 5063 #define PXP_VF_ADDR_USDM_GLOBAL_END \ 5064 ((PXP_VF_ADDR_USDM_GLOBAL_START) + (PXP_VF_ADDR_USDM_GLOBAL_SIZE) - 1) 5065 5066 #define PXP_VF_ADDR_CSDM_GLOBAL_START 0x7600 5067 #define PXP_VF_ADDR_CSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 5068 #define PXP_VF_ADDR_CSDM_GLOBAL_END \ 5069 ((PXP_VF_ADDR_CSDM_GLOBAL_START) + (PXP_VF_ADDR_CSDM_GLOBAL_SIZE) - 1) 5070 5071 #define PXP_VF_ADDR_XSDM_GLOBAL_START 0x7800 5072 #define PXP_VF_ADDR_XSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 5073 #define PXP_VF_ADDR_XSDM_GLOBAL_END \ 5074 ((PXP_VF_ADDR_XSDM_GLOBAL_START) + (PXP_VF_ADDR_XSDM_GLOBAL_SIZE) - 1) 5075 5076 #define PXP_VF_ADDR_TSDM_GLOBAL_START 0x7a00 5077 #define PXP_VF_ADDR_TSDM_GLOBAL_SIZE (PXP_ADDR_REG_SIZE) 5078 #define PXP_VF_ADDR_TSDM_GLOBAL_END \ 5079 ((PXP_VF_ADDR_TSDM_GLOBAL_START) + (PXP_VF_ADDR_TSDM_GLOBAL_SIZE) - 1) 5080 5081 #define PXP_VF_ADDR_DB_START 0x7c00 5082 #define PXP_VF_ADDR_DB_SIZE (0x200) 5083 #define PXP_VF_ADDR_DB_END \ 5084 ((PXP_VF_ADDR_DB_START) + (PXP_VF_ADDR_DB_SIZE) - 1) 5085 5086 #define PXP_VF_ADDR_GRC_START 0x7e00 5087 #define PXP_VF_ADDR_GRC_SIZE (0x200) 5088 #define PXP_VF_ADDR_GRC_END \ 5089 ((PXP_VF_ADDR_GRC_START) + (PXP_VF_ADDR_GRC_SIZE) - 1) 5090 5091 #define PXP_VF_ADDR_DORQ_START (0x0) 5092 #define PXP_VF_ADDR_DORQ_SIZE (0xffffffff) 5093 #define PXP_VF_ADDR_DORQ_END (0xffffffff) 5094 5095 #define PXP_BAR_GRC 0 5096 #define PXP_BAR_TSDM 0 5097 #define PXP_BAR_USDM 0 5098 #define PXP_BAR_XSDM 0 5099 #define PXP_BAR_CSDM 0 5100 #define PXP_BAR_IGU 0 5101 #define PXP_BAR_DQ 1 5102 5103 #define PXP_VF_BAR_IGU 0 5104 #define PXP_VF_BAR_USDM_QUEUES 0 5105 #define PXP_VF_BAR_TSDM_QUEUES 0 5106 #define PXP_VF_BAR_XSDM_QUEUES 0 5107 #define PXP_VF_BAR_CSDM_QUEUES 0 5108 #define PXP_VF_BAR_USDM_GLOBAL 0 5109 #define PXP_VF_BAR_TSDM_GLOBAL 0 5110 #define PXP_VF_BAR_XSDM_GLOBAL 0 5111 #define PXP_VF_BAR_CSDM_GLOBAL 0 5112 #define PXP_VF_BAR_DB 0 5113 #define PXP_VF_BAR_GRC 0 5114 #define PXP_VF_BAR_DORQ 1 5115 5116 /* PCI CAPABILITIES*/ 5117 5118 #define PCI_CAP_PCIE 0x10 /*PCIe capability ID*/ 5119 5120 #define PCIE_DEV_CAPS 0x04 5121 5122 #define PCIE_DEV_CTRL 0x08 5123 #define PCIE_DEV_CTRL_FLR 0x8000; 5124 5125 #define PCIE_DEV_STATUS 0x0A 5126 5127 #define PCI_CAP_MSIX 0x11 /*MSI-X capability ID*/ 5128 #define PCI_MSIX_CONTROL_SHIFT 16 5129 #define PCI_MSIX_TABLE_SIZE_MASK 0x07FF 5130 #define PCI_MSIX_TABLE_ENABLE_MASK 0x8000 5131 5132 5133 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_ID)) 5134 #define PCI_CAP_LIST_ID_DEF 5135 #endif 5136 #if (defined(__LINUX)) || (defined(PCI_CAP_LIST_NEXT)) 5137 #define PCI_CAP_LIST_NEXT_DEF 5138 #endif 5139 #if (defined(__LINUX)) || (defined(PCI_STATUS)) 5140 #define PCI_STATUS_DEF 5141 #endif 5142 #if (defined(__LINUX)) || (defined(PCI_STATUS_CAP_LIST)) 5143 #define PCI_STATUS_CAP_LIST_DEF 5144 #endif 5145 5146 5147 #define MDIO_REG_BANK_CL73_IEEEB0 0x0 5148 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 5149 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 5150 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 5151 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 5152 5153 #define MDIO_REG_BANK_CL73_IEEEB1 0x10 5154 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 5155 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 5156 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 5157 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 5158 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 5159 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 5160 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 5161 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 5162 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 5163 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 5164 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 5165 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 5166 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 5167 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 5168 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 5169 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 5170 5171 #define MDIO_REG_BANK_RX0 0x80b0 5172 #define MDIO_RX0_RX_STATUS 0x10 5173 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 5174 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 5175 #define MDIO_RX0_RX_EQ_BOOST 0x1c 5176 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5177 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 5178 5179 #define MDIO_REG_BANK_RX1 0x80c0 5180 #define MDIO_RX1_RX_EQ_BOOST 0x1c 5181 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5182 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 5183 5184 #define MDIO_REG_BANK_RX2 0x80d0 5185 #define MDIO_RX2_RX_EQ_BOOST 0x1c 5186 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5187 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 5188 5189 #define MDIO_REG_BANK_RX3 0x80e0 5190 #define MDIO_RX3_RX_EQ_BOOST 0x1c 5191 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5192 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 5193 5194 #define MDIO_REG_BANK_RX_ALL 0x80f0 5195 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 5196 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 5197 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 5198 5199 #define MDIO_REG_BANK_TX0 0x8060 5200 #define MDIO_TX0_TX_DRIVER 0x17 5201 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 5202 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 5203 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 5204 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 5205 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5206 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 5207 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 5208 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 5209 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 5210 5211 #define MDIO_REG_BANK_TX1 0x8070 5212 #define MDIO_TX1_TX_DRIVER 0x17 5213 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 5214 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 5215 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 5216 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 5217 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5218 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 5219 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 5220 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 5221 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 5222 5223 #define MDIO_REG_BANK_TX2 0x8080 5224 #define MDIO_TX2_TX_DRIVER 0x17 5225 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 5226 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 5227 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 5228 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 5229 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5230 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 5231 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 5232 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 5233 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 5234 5235 #define MDIO_REG_BANK_TX3 0x8090 5236 #define MDIO_TX3_TX_DRIVER 0x17 5237 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 5238 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 5239 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 5240 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 5241 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 5242 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 5243 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 5244 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 5245 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 5246 5247 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 5248 #define MDIO_BLOCK0_XGXS_CONTROL 0x10 5249 5250 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 5251 #define MDIO_BLOCK1_LANE_CTRL0 0x15 5252 #define MDIO_BLOCK1_LANE_CTRL1 0x16 5253 #define MDIO_BLOCK1_LANE_CTRL2 0x17 5254 #define MDIO_BLOCK1_LANE_PRBS 0x19 5255 5256 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 5257 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 5258 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 5259 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 5260 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 5261 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 5262 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 5263 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 5264 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 5265 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 5266 5267 #define MDIO_REG_BANK_GP_STATUS 0x8120 5268 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 5269 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 5270 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 5271 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 5272 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 5273 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 5274 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 5275 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 5276 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 5277 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 5278 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 5279 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 5280 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 5281 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 5282 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 5283 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 5284 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 5285 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 5286 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 5287 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 5288 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 5289 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 5290 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 5291 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 5292 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 5293 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 5294 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 5295 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 5296 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 5297 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 5298 5299 5300 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 5301 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 5302 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 5303 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 5304 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 5305 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 5306 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 5307 5308 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 5309 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 5310 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 5311 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 5312 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 5313 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 5314 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 5315 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 5316 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 5317 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 5318 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 5319 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 5320 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 5321 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 5322 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 5323 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 5324 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 5325 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 5326 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 5327 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 5328 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 5329 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 5330 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 5331 #define MDIO_SERDES_DIGITAL_MISC1 0x18 5332 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 5333 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 5334 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 5335 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 5336 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 5337 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 5338 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 5339 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 5340 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 5341 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 5342 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 5343 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 5344 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 5345 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 5346 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 5347 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 5348 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 5349 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 5350 5351 #define MDIO_REG_BANK_OVER_1G 0x8320 5352 #define MDIO_OVER_1G_DIGCTL_3_4 0x14 5353 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 5354 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 5355 #define MDIO_OVER_1G_UP1 0x19 5356 #define MDIO_OVER_1G_UP1_2_5G 0x0001 5357 #define MDIO_OVER_1G_UP1_5G 0x0002 5358 #define MDIO_OVER_1G_UP1_6G 0x0004 5359 #define MDIO_OVER_1G_UP1_10G 0x0010 5360 #define MDIO_OVER_1G_UP1_10GH 0x0008 5361 #define MDIO_OVER_1G_UP1_12G 0x0020 5362 #define MDIO_OVER_1G_UP1_12_5G 0x0040 5363 #define MDIO_OVER_1G_UP1_13G 0x0080 5364 #define MDIO_OVER_1G_UP1_15G 0x0100 5365 #define MDIO_OVER_1G_UP1_16G 0x0200 5366 #define MDIO_OVER_1G_UP2 0x1A 5367 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 5368 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 5369 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 5370 #define MDIO_OVER_1G_UP3 0x1B 5371 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 5372 #define MDIO_OVER_1G_LP_UP1 0x1C 5373 #define MDIO_OVER_1G_LP_UP2 0x1D 5374 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 5375 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 5376 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 5377 #define MDIO_OVER_1G_LP_UP3 0x1E 5378 5379 #define MDIO_REG_BANK_REMOTE_PHY 0x8330 5380 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 5381 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 5382 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 5383 5384 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 5385 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 5386 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 5387 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 5388 5389 #define MDIO_REG_BANK_CL73_USERB0 0x8370 5390 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 5391 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 5392 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 5393 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 5394 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 5395 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 5396 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 5397 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 5398 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 5399 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 5400 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 5401 5402 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 5403 #define MDIO_AER_BLOCK_AER_REG 0x1E 5404 5405 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 5406 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 5407 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 5408 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 5409 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 5410 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 5411 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 5412 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 5413 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 5414 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 5415 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 5416 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 5417 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 5418 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 5419 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 5420 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 5421 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 5422 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 5423 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 5424 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 5425 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 5426 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 5427 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 5428 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 5429 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 5430 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 5431 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 5432 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 5433 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 5434 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 5435 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 5436 /*WhenthelinkpartnerisinSGMIImode(bit0=1), then 5437 bit15=link, bit12=duplex, bits11:10=speed, bit14=acknowledge. 5438 Theotherbitsarereservedandshouldbezero*/ 5439 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 5440 5441 5442 #define MDIO_PMA_DEVAD 0x1 5443 /*ieee*/ 5444 #define MDIO_PMA_REG_CTRL 0x0 5445 #define MDIO_PMA_REG_STATUS 0x1 5446 #define MDIO_PMA_REG_10G_CTRL2 0x7 5447 #define MDIO_PMA_REG_TX_DISABLE 0x0009 5448 #define MDIO_PMA_REG_RX_SD 0xa 5449 /*bnx2x*/ 5450 #define MDIO_PMA_REG_BNX2X_CTRL 0x0096 5451 #define MDIO_PMA_REG_FEC_CTRL 0x00ab 5452 #define MDIO_PMA_LASI_RXCTRL 0x9000 5453 #define MDIO_PMA_LASI_TXCTRL 0x9001 5454 #define MDIO_PMA_LASI_CTRL 0x9002 5455 #define MDIO_PMA_LASI_RXSTAT 0x9003 5456 #define MDIO_PMA_LASI_TXSTAT 0x9004 5457 #define MDIO_PMA_LASI_STAT 0x9005 5458 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 5459 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 5460 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 5461 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 5462 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 5463 #define MDIO_PMA_REG_MISC_CTRL 0xca0a 5464 #define MDIO_PMA_REG_GEN_CTRL 0xca10 5465 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 5466 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 5467 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 5468 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 5469 #define MDIO_PMA_REG_ROM_VER1 0xca19 5470 #define MDIO_PMA_REG_ROM_VER2 0xca1a 5471 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 5472 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 5473 #define MDIO_PMA_REG_PLL_CTRL 0xca1e 5474 #define MDIO_PMA_REG_MISC_CTRL0 0xca23 5475 #define MDIO_PMA_REG_LRM_MODE 0xca3f 5476 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 5477 #define MDIO_PMA_REG_MISC_CTRL1 0xca85 5478 5479 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 5480 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 5481 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 5482 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 5483 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 5484 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 5485 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 5486 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 5487 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 5488 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 5489 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 5490 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 5491 5492 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 5493 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 5494 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 5495 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 5496 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 5497 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 5498 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 5499 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 5500 #define MDIO_PMA_REG_8727_PCS_GP 0xc842 5501 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 5502 5503 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309 5504 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 5505 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 5506 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 5507 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 5508 5509 #define MDIO_PMA_REG_7101_RESET 0xc000 5510 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 5511 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 5512 #define MDIO_PMA_REG_7101_VER1 0xc026 5513 #define MDIO_PMA_REG_7101_VER2 0xc027 5514 5515 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 5516 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 5517 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 5518 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832 5519 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 5520 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838 5521 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 5522 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 5523 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 5524 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 5525 5526 5527 #define MDIO_WIS_DEVAD 0x2 5528 /*bnx2x*/ 5529 #define MDIO_WIS_REG_LASI_CNTL 0x9002 5530 #define MDIO_WIS_REG_LASI_STATUS 0x9005 5531 5532 #define MDIO_PCS_DEVAD 0x3 5533 #define MDIO_PCS_REG_STATUS 0x0020 5534 #define MDIO_PCS_REG_LASI_STATUS 0x9005 5535 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 5536 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 5537 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 5538 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 5539 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 5540 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 5541 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 5542 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 5543 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 5544 5545 5546 #define MDIO_XS_DEVAD 0x4 5547 #define MDIO_XS_REG_STATUS 0x0001 5548 #define MDIO_XS_PLL_SEQUENCER 0x8000 5549 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 5550 5551 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc 5552 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc 5553 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc 5554 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec 5555 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc 5556 5557 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 5558 5559 #define MDIO_AN_DEVAD 0x7 5560 /*ieee*/ 5561 #define MDIO_AN_REG_CTRL 0x0000 5562 #define MDIO_AN_REG_STATUS 0x0001 5563 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 5564 #define MDIO_AN_REG_ADV_PAUSE 0x0010 5565 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 5566 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 5567 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 5568 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 5569 #define MDIO_AN_REG_ADV 0x0011 5570 #define MDIO_AN_REG_ADV2 0x0012 5571 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 5572 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 5573 #define MDIO_AN_REG_MASTER_STATUS 0x0021 5574 #define MDIO_AN_REG_EEE_ADV 0x003c 5575 #define MDIO_AN_REG_LP_EEE_ADV 0x003d 5576 /*bnx2x*/ 5577 #define MDIO_AN_REG_LINK_STATUS 0x8304 5578 #define MDIO_AN_REG_CL37_CL73 0x8370 5579 #define MDIO_AN_REG_CL37_AN 0xffe0 5580 #define MDIO_AN_REG_CL37_FC_LD 0xffe4 5581 #define MDIO_AN_REG_CL37_FC_LP 0xffe5 5582 #define MDIO_AN_REG_1000T_STATUS 0xffea 5583 5584 #define MDIO_AN_REG_8073_2_5G 0x8329 5585 #define MDIO_AN_REG_8073_BAM 0x8350 5586 5587 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 5588 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 5589 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 5590 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 5591 #define MDIO_AN_REG_848xx_ID_MSB 0xffe2 5592 #define BNX2X84858_PHY_ID 0x600d 5593 #define MDIO_AN_REG_848xx_ID_LSB 0xffe3 5594 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 5595 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 5596 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 5597 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 5598 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 5599 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 5600 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 5601 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 5602 #define MDIO_AN_REG_8481_INTERRUPT_MASK 0xfffb 5603 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 5604 5605 /* BNX2X84823 only */ 5606 #define MDIO_CTL_DEVAD 0x1e 5607 #define MDIO_CTL_REG_84823_MEDIA 0x401a 5608 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 5609 /* These pins configure the BNX2X84823 interface to MAC after reset. */ 5610 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 5611 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 5612 /* These pins configure the BNX2X84823 interface to Line after reset. */ 5613 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 5614 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 5615 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 5616 /* When this pin is active high during reset, 10GBASE-T core is power 5617 * down, When it is active low the 10GBASE-T is power up 5618 */ 5619 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 5620 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 5621 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 5622 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 5623 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 5624 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 5625 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 5626 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 5627 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 5628 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 5629 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 5630 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 5631 /* BNX2X84858 only */ 5632 #define MDIO_PMA_REG_84858_ALLOW_GPHY_ACT 0x8000 5633 5634 /* BNX2X84833 only */ 5635 #define MDIO_84833_TOP_CFG_FW_REV 0x400f 5636 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 5637 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 5638 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 5639 #define MDIO_84833_SUPER_ISOLATE 0x8000 5640 /* These are mailbox register set used by 84833/84858. */ 5641 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005 5642 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006 5643 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007 5644 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008 5645 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009 5646 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037 5647 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038 5648 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039 5649 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a 5650 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b 5651 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c 5652 #define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0) 5653 #define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26) 5654 #define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27) 5655 #define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28) 5656 #define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29) 5657 #define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30) 5658 #define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31) 5659 5660 /* Mailbox command set used by 84833/84858 */ 5661 #define PHY848xx_CMD_SET_PAIR_SWAP 0x8001 5662 #define PHY848xx_CMD_GET_EEE_MODE 0x8008 5663 #define PHY848xx_CMD_SET_EEE_MODE 0x8009 5664 #define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031 5665 /* Mailbox status set used by 84833 only */ 5666 #define PHY84833_STATUS_CMD_RECEIVED 0x0001 5667 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 5668 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 5669 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 5670 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 5671 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 5672 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 5673 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 5674 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 5675 /* Mailbox Process */ 5676 #define PHY84833_MB_PROCESS1 1 5677 #define PHY84833_MB_PROCESS2 2 5678 #define PHY84833_MB_PROCESS3 3 5679 5680 /* Mailbox status set used by 84858 only */ 5681 #define PHY84858_STATUS_CMD_RECEIVED 0x0001 5682 #define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002 5683 #define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004 5684 #define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008 5685 #define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb 5686 5687 5688 /* Warpcore clause 45 addressing */ 5689 #define MDIO_WC_DEVAD 0x3 5690 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 5691 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 5692 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 5693 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 5694 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 5695 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 5696 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 5697 #define MDIO_WC_REG_PCS_STATUS2 0x0021 5698 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 5699 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 5700 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 5701 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 5702 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 5703 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 5704 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 5705 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018 5706 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a 5707 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 5708 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 5709 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 5710 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 5711 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 5712 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01 5713 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e 5714 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 5715 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 5716 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 5717 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 5718 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 5719 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 5720 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 5721 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 5722 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 5723 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 5724 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 5725 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 5726 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 5727 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 5728 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 5729 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa 5730 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 5731 #define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a 5732 #define MDIO_WC_REG_XGXS_STATUS3 0x8129 5733 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 5734 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 5735 #define MDIO_WC_REG_XGXS_STATUS4 0x813c 5736 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 5737 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 5738 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 5739 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 5740 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 5741 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 5742 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 5743 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 5744 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 5745 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 5746 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 5747 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 5748 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 5749 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 5750 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 5751 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 5752 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 5753 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 5754 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 5755 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 5756 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 5757 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 5758 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 5759 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 5760 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 5761 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 5762 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e 5763 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) 5764 #define MDIO_WC_REG_DSC_SMC 0x8213 5765 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 5766 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 5767 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 5768 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 5769 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 5770 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 5771 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 5772 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 5773 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 5774 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 5775 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 5776 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 5777 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 5778 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 5779 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 5780 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 5781 #define AUTODET_EN (1 << 4) 5782 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 5783 #define EN_PARALLEL_DET 1 5784 #define FILTER_FORCE_LINK (1 << 2) 5785 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 5786 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 5787 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 5788 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 5789 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329 5790 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 5791 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 5792 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e 5793 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 5794 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 5795 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d 5796 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 5797 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 5798 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 5799 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 5800 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 5801 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 5802 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 5803 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 5804 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b 5805 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 5806 #define MDIO_WC_REG_TX66_CONTROL 0x83b0 5807 #define MDIO_WC_REG_RX66_CONTROL 0x83c0 5808 #define MDIO_WC_REG_RX66_SCW0 0x83c2 5809 #define MDIO_WC_REG_RX66_SCW1 0x83c3 5810 #define MDIO_WC_REG_RX66_SCW2 0x83c4 5811 #define MDIO_WC_REG_RX66_SCW3 0x83c5 5812 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 5813 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 5814 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 5815 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 5816 #define MDIO_WC_REG_FX100_CTRL1 0x8400 5817 #define MDIO_WC_REG_FX100_CTRL3 0x8402 5818 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 5819 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 5820 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 5821 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 5822 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a 5823 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b 5824 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 5825 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 5826 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 5827 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 5828 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 5829 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2 5830 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 5831 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 5832 5833 #define MDIO_WC_REG_AERBLK_AER 0xffde 5834 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 5835 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 5836 5837 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 5838 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 5839 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 5840 5841 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 5842 5843 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 5844 5845 /* 54618se */ 5846 #define MDIO_REG_GPHY_MII_STATUS 0x1 5847 #define MDIO_REG_GPHY_PHYID_LSB 0x3 5848 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 5849 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 5850 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000 5851 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe 5852 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 5853 #define MDIO_REG_GPHY_BASET_EXT_CTRL 0x10 5854 #define MDIO_REG_GPHY_TX_HIGH_LATENCY 0x1 5855 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 5856 #define MDIO_REG_GPHY_EXP_ACCESS 0x17 5857 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 5858 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 5859 #define MDIO_REG_GPHY_SHADOW_ACCESS 0x18 5860 #define MDIO_REG_GPHY_SHADOW_AUX_CTRL (0x0) 5861 #define MDIO_REG_GPHY_SHADOW_MISC_CTRL (0x7) 5862 #define MDIO_REG_GPHY_AUX_STATUS 0x19 5863 #define MDIO_REG_INTR_STATUS 0x1a 5864 #define MDIO_REG_INTR_MASK 0x1b 5865 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 5866 #define MDIO_REG_GPHY_SHADOW 0x1c 5867 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 5868 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 5869 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 5870 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 5871 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 5872 5873 #define IGU_FUNC_BASE 0x0400 5874 5875 #define IGU_ADDR_MSIX 0x0000 5876 #define IGU_ADDR_INT_ACK 0x0200 5877 #define IGU_ADDR_PROD_UPD 0x0201 5878 #define IGU_ADDR_ATTN_BITS_UPD 0x0202 5879 #define IGU_ADDR_ATTN_BITS_SET 0x0203 5880 #define IGU_ADDR_ATTN_BITS_CLR 0x0204 5881 #define IGU_ADDR_COALESCE_NOW 0x0205 5882 #define IGU_ADDR_SIMD_MASK 0x0206 5883 #define IGU_ADDR_SIMD_NOMASK 0x0207 5884 #define IGU_ADDR_MSI_CTL 0x0210 5885 #define IGU_ADDR_MSI_ADDR_LO 0x0211 5886 #define IGU_ADDR_MSI_ADDR_HI 0x0212 5887 #define IGU_ADDR_MSI_DATA 0x0213 5888 5889 5890 #define IGU_USE_REGISTER_ustorm_type_0_sb_cleanup 0 5891 #define IGU_USE_REGISTER_ustorm_type_1_sb_cleanup 1 5892 #define IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 2 5893 #define IGU_USE_REGISTER_cstorm_type_1_sb_cleanup 3 5894 5895 #define COMMAND_REG_INT_ACK 0x0 5896 #define COMMAND_REG_PROD_UPD 0x4 5897 #define COMMAND_REG_ATTN_BITS_UPD 0x8 5898 #define COMMAND_REG_ATTN_BITS_SET 0xc 5899 #define COMMAND_REG_ATTN_BITS_CLR 0x10 5900 #define COMMAND_REG_COALESCE_NOW 0x14 5901 #define COMMAND_REG_SIMD_MASK 0x18 5902 #define COMMAND_REG_SIMD_NOMASK 0x1c 5903 5904 5905 #define IGU_MEM_BASE 0x0000 5906 5907 #define IGU_MEM_MSIX_BASE 0x0000 5908 #define IGU_MEM_MSIX_UPPER 0x007f 5909 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff 5910 5911 #define IGU_MEM_PBA_MSIX_BASE 0x0200 5912 #define IGU_MEM_PBA_MSIX_UPPER 0x0200 5913 5914 #define IGU_CMD_BACKWARD_COMP_PROD_UPD 0x0201 5915 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff 5916 5917 #define IGU_CMD_INT_ACK_BASE 0x0400 5918 #define IGU_CMD_INT_ACK_UPPER \ 5919 (IGU_CMD_INT_ACK_BASE + MAX_SB_PER_PATH - 1) 5920 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x04ff 5921 5922 #define IGU_CMD_E2_PROD_UPD_BASE 0x0500 5923 #define IGU_CMD_E2_PROD_UPD_UPPER \ 5924 (IGU_CMD_E2_PROD_UPD_BASE + MAX_SB_PER_PATH - 1) 5925 #define IGU_CMD_E2_PROD_UPD_RESERVED_UPPER 0x059f 5926 5927 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05a0 5928 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05a1 5929 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05a2 5930 5931 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05a3 5932 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05a4 5933 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05a5 5934 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05a6 5935 5936 5937 #define IGU_REG_RESERVED_UPPER 0x05ff 5938 5939 #define IGU_SEG_IDX_ATTN 2 5940 #define IGU_SEG_IDX_DEFAULT 1 5941 /* Fields of IGU PF CONFIGURATION REGISTER */ 5942 #define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 5943 #define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 5944 #define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 5945 #define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 5946 #define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 5947 #define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 5948 5949 /* Fields of IGU VF CONFIGURATION REGISTER */ 5950 #define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 5951 #define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 5952 #define IGU_VF_CONF_PARENT_MASK (0x3<<2) /* Parent PF */ 5953 #define IGU_VF_CONF_PARENT_SHIFT 2 /* Parent PF */ 5954 #define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 5955 5956 5957 #define IGU_BC_DSB_NUM_SEGS 5 5958 #define IGU_BC_NDSB_NUM_SEGS 2 5959 #define IGU_NORM_DSB_NUM_SEGS 2 5960 #define IGU_NORM_NDSB_NUM_SEGS 1 5961 #define IGU_BC_BASE_DSB_PROD 128 5962 #define IGU_NORM_BASE_DSB_PROD 136 5963 5964 /* FID (if VF - [6] = 0; [5:0] = VF number; if PF - [6] = 1; \ 5965 [5:2] = 0; [1:0] = PF number) */ 5966 #define IGU_FID_ENCODE_IS_PF (0x1<<6) 5967 #define IGU_FID_ENCODE_IS_PF_SHIFT 6 5968 #define IGU_FID_VF_NUM_MASK (0x3f) 5969 #define IGU_FID_PF_NUM_MASK (0x7) 5970 5971 #define IGU_REG_MAPPING_MEMORY_VALID (1<<0) 5972 #define IGU_REG_MAPPING_MEMORY_VECTOR_MASK (0x3F<<1) 5973 #define IGU_REG_MAPPING_MEMORY_VECTOR_SHIFT 1 5974 #define IGU_REG_MAPPING_MEMORY_FID_MASK (0x7F<<7) 5975 #define IGU_REG_MAPPING_MEMORY_FID_SHIFT 7 5976 5977 5978 #define CDU_REGION_NUMBER_XCM_AG 2 5979 #define CDU_REGION_NUMBER_UCM_AG 4 5980 5981 5982 /* String-to-compress [31:8] = CID (all 24 bits) 5983 * String-to-compress [7:4] = Region 5984 * String-to-compress [3:0] = Type 5985 */ 5986 #define CDU_VALID_DATA(_cid, _region, _type) \ 5987 (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf))) 5988 #define CDU_CRC8(_cid, _region, _type) \ 5989 (ecore_calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff)) 5990 #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \ 5991 (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f)) 5992 #define CDU_RSRVD_VALUE_TYPE_B(_crc, _type) \ 5993 (0x80 | ((_type)&0xf << 3) | ((CDU_CRC8(_cid, _region, _type)) & 0x7)) 5994 #define CDU_RSRVD_INVALIDATE_CONTEXT_VALUE(_val) ((_val) & ~0x80) 5995 5996 #endif /* ECORE_REG_H */ 5997