1 /*- 2 * Copyright (c) 2007-2013 Cavium Inc. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Copyright (c) 2013-2015 Brocade Communications Systems, Inc. 9 * Copyright (c) 2015-2018 Cavium Inc. 10 * All rights reserved. 11 * www.cavium.com 12 * 13 * See LICENSE.bnx2x_pmd for copyright and licensing details. 14 */ 15 16 #ifndef ECORE_INIT_OPS_H 17 #define ECORE_INIT_OPS_H 18 19 static int ecore_gunzip(struct bnx2x_softc *sc, const uint8_t *zbuf, int len); 20 static void ecore_write_dmae_phys_len(struct bnx2x_softc *sc, 21 ecore_dma_addr_t phys_addr, uint32_t addr, 22 uint32_t len); 23 24 static void ecore_init_str_wr(struct bnx2x_softc *sc, uint32_t addr, 25 const uint32_t *data, uint32_t len) 26 { 27 uint32_t i; 28 29 for (i = 0; i < len; i++) 30 REG_WR(sc, addr + i*4, data[i]); 31 } 32 33 static void ecore_write_big_buf(struct bnx2x_softc *sc, uint32_t addr, uint32_t len) 34 { 35 if (DMAE_READY(sc)) 36 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len); 37 38 else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len); 39 } 40 41 static void ecore_init_fill(struct bnx2x_softc *sc, uint32_t addr, int fill, 42 uint32_t len) 43 { 44 uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4)); 45 uint32_t buf_len32 = buf_len/4; 46 uint32_t i; 47 48 ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len); 49 50 for (i = 0; i < len; i += buf_len32) { 51 uint32_t cur_len = min(buf_len32, len - i); 52 53 ecore_write_big_buf(sc, addr + i*4, cur_len); 54 } 55 } 56 57 static void ecore_write_big_buf_wb(struct bnx2x_softc *sc, uint32_t addr, uint32_t len) 58 { 59 if (DMAE_READY(sc)) 60 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len); 61 62 else ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len); 63 } 64 65 static void ecore_init_wr_64(struct bnx2x_softc *sc, uint32_t addr, 66 const uint32_t *data, uint32_t len64) 67 { 68 uint32_t buf_len32 = FW_BUF_SIZE/4; 69 uint32_t len = len64*2; 70 uint64_t data64 = 0; 71 uint32_t i; 72 73 /* 64 bit value is in a blob: first low DWORD, then high DWORD */ 74 data64 = HILO_U64((*(data + 1)), (*data)); 75 76 len64 = min((uint32_t)(FW_BUF_SIZE/8), len64); 77 for (i = 0; i < len64; i++) { 78 uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i; 79 80 *pdata = data64; 81 } 82 83 for (i = 0; i < len; i += buf_len32) { 84 uint32_t cur_len = min(buf_len32, len - i); 85 86 ecore_write_big_buf_wb(sc, addr + i*4, cur_len); 87 } 88 } 89 90 /********************************************************* 91 There are different blobs for each PRAM section. 92 In addition, each blob write operation is divided into a few operations 93 in order to decrease the amount of phys. contiguous buffer needed. 94 Thus, when we select a blob the address may be with some offset 95 from the beginning of PRAM section. 96 The same holds for the INT_TABLE sections. 97 **********************************************************/ 98 #define IF_IS_INT_TABLE_ADDR(base, addr) \ 99 if (((base) <= (addr)) && ((base) + 0x400 >= (addr))) 100 101 #define IF_IS_PRAM_ADDR(base, addr) \ 102 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr))) 103 104 static const uint8_t *ecore_sel_blob(struct bnx2x_softc *sc, uint32_t addr, 105 const uint8_t *data) 106 { 107 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr) 108 data = INIT_TSEM_INT_TABLE_DATA(sc); 109 else 110 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr) 111 data = INIT_CSEM_INT_TABLE_DATA(sc); 112 else 113 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr) 114 data = INIT_USEM_INT_TABLE_DATA(sc); 115 else 116 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr) 117 data = INIT_XSEM_INT_TABLE_DATA(sc); 118 else 119 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr) 120 data = INIT_TSEM_PRAM_DATA(sc); 121 else 122 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr) 123 data = INIT_CSEM_PRAM_DATA(sc); 124 else 125 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr) 126 data = INIT_USEM_PRAM_DATA(sc); 127 else 128 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr) 129 data = INIT_XSEM_PRAM_DATA(sc); 130 131 return data; 132 } 133 134 static void ecore_init_wr_wb(struct bnx2x_softc *sc, uint32_t addr, 135 const uint32_t *data, uint32_t len) 136 { 137 if (DMAE_READY(sc)) 138 VIRT_WR_DMAE_LEN(sc, data, addr, len, 0); 139 140 else ecore_init_str_wr(sc, addr, data, len); 141 } 142 143 static void ecore_wr_64(struct bnx2x_softc *sc, uint32_t reg, uint32_t val_lo, 144 uint32_t val_hi) 145 { 146 uint32_t wb_write[2]; 147 148 wb_write[0] = val_lo; 149 wb_write[1] = val_hi; 150 REG_WR_DMAE_LEN(sc, reg, wb_write, 2); 151 } 152 153 static void ecore_init_wr_zp(struct bnx2x_softc *sc, uint32_t addr, uint32_t len, 154 uint32_t blob_off) 155 { 156 const uint8_t *data = NULL; 157 int rc; 158 uint32_t i; 159 160 data = ecore_sel_blob(sc, addr, data) + blob_off*4; 161 162 rc = ecore_gunzip(sc, data, len); 163 if (rc) 164 return; 165 166 /* gunzip_outlen is in dwords */ 167 len = GUNZIP_OUTLEN(sc); 168 for (i = 0; i < len; i++) 169 ((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t) 170 ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]); 171 172 ecore_write_big_buf_wb(sc, addr, len); 173 } 174 175 static void ecore_init_block(struct bnx2x_softc *sc, uint32_t block, uint32_t stage) 176 { 177 uint16_t op_start = 178 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage, 179 STAGE_START)]; 180 uint16_t op_end = 181 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage, 182 STAGE_END)]; 183 const union init_op *op; 184 uint32_t op_idx, op_type, addr, len; 185 const uint32_t *data, *data_base; 186 187 /* If empty block */ 188 if (op_start == op_end) 189 return; 190 191 data_base = INIT_DATA(sc); 192 193 for (op_idx = op_start; op_idx < op_end; op_idx++) { 194 195 op = (const union init_op *)&(INIT_OPS(sc)[op_idx]); 196 /* Get generic data */ 197 op_type = op->raw.op; 198 addr = op->raw.offset; 199 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and 200 * OP_WR64 (we assume that op_arr_write and op_write have the 201 * same structure). 202 */ 203 len = op->arr_wr.data_len; 204 data = data_base + op->arr_wr.data_off; 205 206 switch (op_type) { 207 case OP_RD: 208 REG_RD(sc, addr); 209 break; 210 case OP_WR: 211 REG_WR(sc, addr, op->write.val); 212 break; 213 case OP_SW: 214 ecore_init_str_wr(sc, addr, data, len); 215 break; 216 case OP_WB: 217 ecore_init_wr_wb(sc, addr, data, len); 218 break; 219 case OP_ZR: 220 case OP_WB_ZR: 221 ecore_init_fill(sc, addr, 0, op->zero.len); 222 break; 223 case OP_ZP: 224 ecore_init_wr_zp(sc, addr, len, op->arr_wr.data_off); 225 break; 226 case OP_WR_64: 227 ecore_init_wr_64(sc, addr, data, len); 228 break; 229 case OP_IF_MODE_AND: 230 /* if any of the flags doesn't match, skip the 231 * conditional block. 232 */ 233 if ((INIT_MODE_FLAGS(sc) & 234 op->if_mode.mode_bit_map) != 235 op->if_mode.mode_bit_map) 236 op_idx += op->if_mode.cmd_offset; 237 break; 238 case OP_IF_MODE_OR: 239 /* if all the flags don't match, skip the conditional 240 * block. 241 */ 242 if ((INIT_MODE_FLAGS(sc) & 243 op->if_mode.mode_bit_map) == 0) 244 op_idx += op->if_mode.cmd_offset; 245 break; 246 /* the following opcodes are unused at the moment. */ 247 case OP_IF_PHASE: 248 case OP_RT: 249 case OP_DELAY: 250 case OP_VERIFY: 251 default: 252 /* Should never get here! */ 253 254 break; 255 } 256 } 257 } 258 259 260 /**************************************************************************** 261 * PXP Arbiter 262 ****************************************************************************/ 263 /* 264 * This code configures the PCI read/write arbiter 265 * which implements a weighted round robin 266 * between the virtual queues in the chip. 267 * 268 * The values were derived for each PCI max payload and max request size. 269 * since max payload and max request size are only known at run time, 270 * this is done as a separate init stage. 271 */ 272 273 #define NUM_WR_Q 13 274 #define NUM_RD_Q 29 275 #define MAX_RD_ORD 3 276 #define MAX_WR_ORD 2 277 278 /* configuration for one arbiter queue */ 279 struct arb_line { 280 int l; 281 int add; 282 int ubound; 283 }; 284 285 /* derived configuration for each read queue for each max request size */ 286 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = { 287 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, 288 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} }, 289 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} }, 290 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} }, 291 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} }, 292 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 293 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 294 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 295 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} }, 296 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 297 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 298 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 299 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 300 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 301 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 302 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 303 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} }, 304 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 305 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 306 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 307 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 308 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 309 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 310 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 311 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 312 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 313 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 314 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} }, 315 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} } 316 }; 317 318 /* derived configuration for each write queue for each max request size */ 319 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = { 320 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} }, 321 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} }, 322 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 323 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 324 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 325 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} }, 326 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} }, 327 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 328 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} }, 329 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} }, 330 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} }, 331 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} }, 332 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} } 333 }; 334 335 /* register addresses for read queues */ 336 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = { 337 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0, 338 PXP2_REG_RQ_BW_RD_UBOUND0}, 339 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 340 PXP2_REG_PSWRQ_BW_UB1}, 341 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 342 PXP2_REG_PSWRQ_BW_UB2}, 343 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, 344 PXP2_REG_PSWRQ_BW_UB3}, 345 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4, 346 PXP2_REG_RQ_BW_RD_UBOUND4}, 347 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5, 348 PXP2_REG_RQ_BW_RD_UBOUND5}, 349 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, 350 PXP2_REG_PSWRQ_BW_UB6}, 351 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, 352 PXP2_REG_PSWRQ_BW_UB7}, 353 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 354 PXP2_REG_PSWRQ_BW_UB8}, 355 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 356 PXP2_REG_PSWRQ_BW_UB9}, 357 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 358 PXP2_REG_PSWRQ_BW_UB10}, 359 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 360 PXP2_REG_PSWRQ_BW_UB11}, 361 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12, 362 PXP2_REG_RQ_BW_RD_UBOUND12}, 363 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13, 364 PXP2_REG_RQ_BW_RD_UBOUND13}, 365 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14, 366 PXP2_REG_RQ_BW_RD_UBOUND14}, 367 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15, 368 PXP2_REG_RQ_BW_RD_UBOUND15}, 369 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16, 370 PXP2_REG_RQ_BW_RD_UBOUND16}, 371 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17, 372 PXP2_REG_RQ_BW_RD_UBOUND17}, 373 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18, 374 PXP2_REG_RQ_BW_RD_UBOUND18}, 375 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19, 376 PXP2_REG_RQ_BW_RD_UBOUND19}, 377 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20, 378 PXP2_REG_RQ_BW_RD_UBOUND20}, 379 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22, 380 PXP2_REG_RQ_BW_RD_UBOUND22}, 381 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23, 382 PXP2_REG_RQ_BW_RD_UBOUND23}, 383 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24, 384 PXP2_REG_RQ_BW_RD_UBOUND24}, 385 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25, 386 PXP2_REG_RQ_BW_RD_UBOUND25}, 387 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26, 388 PXP2_REG_RQ_BW_RD_UBOUND26}, 389 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27, 390 PXP2_REG_RQ_BW_RD_UBOUND27}, 391 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 392 PXP2_REG_PSWRQ_BW_UB28} 393 }; 394 395 /* register addresses for write queues */ 396 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = { 397 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1, 398 PXP2_REG_PSWRQ_BW_UB1}, 399 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2, 400 PXP2_REG_PSWRQ_BW_UB2}, 401 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3, 402 PXP2_REG_PSWRQ_BW_UB3}, 403 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6, 404 PXP2_REG_PSWRQ_BW_UB6}, 405 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7, 406 PXP2_REG_PSWRQ_BW_UB7}, 407 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8, 408 PXP2_REG_PSWRQ_BW_UB8}, 409 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9, 410 PXP2_REG_PSWRQ_BW_UB9}, 411 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10, 412 PXP2_REG_PSWRQ_BW_UB10}, 413 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11, 414 PXP2_REG_PSWRQ_BW_UB11}, 415 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28, 416 PXP2_REG_PSWRQ_BW_UB28}, 417 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29, 418 PXP2_REG_RQ_BW_WR_UBOUND29}, 419 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30, 420 PXP2_REG_RQ_BW_WR_UBOUND30} 421 }; 422 423 static void ecore_init_pxp_arb(struct bnx2x_softc *sc, int r_order, 424 int w_order) 425 { 426 uint32_t val, i; 427 428 if (r_order > MAX_RD_ORD) { 429 ECORE_MSG("read order of %d order adjusted to %d", 430 r_order, MAX_RD_ORD); 431 r_order = MAX_RD_ORD; 432 } 433 if (w_order > MAX_WR_ORD) { 434 ECORE_MSG("write order of %d order adjusted to %d", 435 w_order, MAX_WR_ORD); 436 w_order = MAX_WR_ORD; 437 } 438 if (CHIP_REV_IS_FPGA(sc)) { 439 ECORE_MSG("write order adjusted to 1 for FPGA"); 440 w_order = 0; 441 } 442 ECORE_MSG("read order %d write order %d", r_order, w_order); 443 444 for (i = 0; i < NUM_RD_Q-1; i++) { 445 REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l); 446 REG_WR(sc, read_arb_addr[i].add, 447 read_arb_data[i][r_order].add); 448 REG_WR(sc, read_arb_addr[i].ubound, 449 read_arb_data[i][r_order].ubound); 450 } 451 452 for (i = 0; i < NUM_WR_Q-1; i++) { 453 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) || 454 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) { 455 456 REG_WR(sc, write_arb_addr[i].l, 457 write_arb_data[i][w_order].l); 458 459 REG_WR(sc, write_arb_addr[i].add, 460 write_arb_data[i][w_order].add); 461 462 REG_WR(sc, write_arb_addr[i].ubound, 463 write_arb_data[i][w_order].ubound); 464 } else { 465 466 val = REG_RD(sc, write_arb_addr[i].l); 467 REG_WR(sc, write_arb_addr[i].l, 468 val | (write_arb_data[i][w_order].l << 10)); 469 470 val = REG_RD(sc, write_arb_addr[i].add); 471 REG_WR(sc, write_arb_addr[i].add, 472 val | (write_arb_data[i][w_order].add << 10)); 473 474 val = REG_RD(sc, write_arb_addr[i].ubound); 475 REG_WR(sc, write_arb_addr[i].ubound, 476 val | (write_arb_data[i][w_order].ubound << 7)); 477 } 478 } 479 480 val = write_arb_data[NUM_WR_Q-1][w_order].add; 481 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10; 482 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17; 483 REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val); 484 485 val = read_arb_data[NUM_RD_Q-1][r_order].add; 486 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10; 487 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17; 488 REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val); 489 490 REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order); 491 REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order); 492 REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order); 493 REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order); 494 495 if (CHIP_IS_E1H(sc) && (r_order == MAX_RD_ORD)) 496 REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00); 497 498 if (CHIP_IS_E3(sc)) 499 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order)); 500 else if (CHIP_IS_E2(sc)) 501 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order)); 502 else 503 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order)); 504 505 /* MPS w_order optimal TH presently TH 506 * 128 0 0 2 507 * 256 1 1 3 508 * >=512 2 2 3 509 */ 510 /* DMAE is special */ 511 if (!CHIP_IS_E1H(sc)) { 512 /* E2 can use optimal TH */ 513 val = w_order; 514 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val); 515 } else { 516 val = ((w_order == 0) ? 2 : 3); 517 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2); 518 } 519 520 REG_WR(sc, PXP2_REG_WR_HC_MPS, val); 521 REG_WR(sc, PXP2_REG_WR_USDM_MPS, val); 522 REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val); 523 REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val); 524 REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val); 525 REG_WR(sc, PXP2_REG_WR_QM_MPS, val); 526 REG_WR(sc, PXP2_REG_WR_TM_MPS, val); 527 REG_WR(sc, PXP2_REG_WR_SRC_MPS, val); 528 REG_WR(sc, PXP2_REG_WR_DBG_MPS, val); 529 REG_WR(sc, PXP2_REG_WR_CDU_MPS, val); 530 531 /* Validate number of tags suppoted by device */ 532 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980 533 val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST); 534 val &= 0xFF; 535 if (val <= 0x20) 536 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20); 537 } 538 539 /**************************************************************************** 540 * ILT management 541 ****************************************************************************/ 542 /* 543 * This codes hides the low level HW interaction for ILT management and 544 * configuration. The API consists of a shadow ILT table which is set by the 545 * driver and a set of routines to use it to configure the HW. 546 * 547 */ 548 549 /* ILT HW init operations */ 550 551 /* ILT memory management operations */ 552 #define ILT_MEMOP_ALLOC 0 553 #define ILT_MEMOP_FREE 1 554 555 /* the phys address is shifted right 12 bits and has an added 556 * 1=valid bit added to the 53rd bit 557 * then since this is a wide register(TM) 558 * we split it into two 32 bit writes 559 */ 560 #define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 561 #define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 562 #define ILT_RANGE(f, l) (((l) << 10) | f) 563 564 static int ecore_ilt_line_mem_op(struct bnx2x_softc *sc, 565 struct ilt_line *line, uint32_t size, uint8_t memop, int cli_num, int i) 566 { 567 #define ECORE_ILT_NAMESIZE 10 568 char str[ECORE_ILT_NAMESIZE]; 569 570 if (memop == ILT_MEMOP_FREE) { 571 ECORE_ILT_FREE(line->page, line->page_mapping, line->size); 572 return 0; 573 } 574 snprintf(str, ECORE_ILT_NAMESIZE, "ILT_%d_%d", cli_num, i); 575 ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size, str); 576 if (!line->page) 577 return -1; 578 line->size = size; 579 return 0; 580 } 581 582 583 static int ecore_ilt_client_mem_op(struct bnx2x_softc *sc, int cli_num, 584 uint8_t memop) 585 { 586 int i, rc = 0; 587 struct ecore_ilt *ilt = SC_ILT(sc); 588 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 589 590 if (!ilt || !ilt->lines) 591 return -1; 592 593 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM)) 594 return 0; 595 596 for (i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) { 597 rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i], 598 ilt_cli->page_size, memop, cli_num, i); 599 } 600 return rc; 601 } 602 603 static inline int ecore_ilt_mem_op_cnic(struct bnx2x_softc *sc, uint8_t memop) 604 { 605 int rc = 0; 606 607 if (CONFIGURE_NIC_MODE(sc)) 608 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop); 609 if (!rc) 610 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop); 611 612 return rc; 613 } 614 615 static int ecore_ilt_mem_op(struct bnx2x_softc *sc, uint8_t memop) 616 { 617 int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop); 618 if (!rc) 619 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop); 620 if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc)) 621 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop); 622 623 return rc; 624 } 625 626 static void ecore_ilt_line_wr(struct bnx2x_softc *sc, int abs_idx, 627 ecore_dma_addr_t page_mapping) 628 { 629 uint32_t reg; 630 631 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8; 632 633 ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping)); 634 } 635 636 static void ecore_ilt_line_init_op(struct bnx2x_softc *sc, 637 struct ecore_ilt *ilt, int idx, uint8_t initop) 638 { 639 ecore_dma_addr_t null_mapping; 640 int abs_idx = ilt->start_line + idx; 641 642 switch (initop) { 643 case INITOP_INIT: 644 /* set in the init-value array */ 645 case INITOP_SET: 646 ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping); 647 break; 648 case INITOP_CLEAR: 649 null_mapping = 0; 650 ecore_ilt_line_wr(sc, abs_idx, null_mapping); 651 break; 652 } 653 } 654 655 static void ecore_ilt_boundry_init_op(struct bnx2x_softc *sc, 656 struct ilt_client_info *ilt_cli, 657 uint32_t ilt_start) 658 { 659 uint32_t start_reg = 0; 660 uint32_t end_reg = 0; 661 662 /* The boundary is either SET or INIT, 663 CLEAR => SET and for now SET ~~ INIT */ 664 665 /* find the appropriate regs */ 666 switch (ilt_cli->client_num) { 667 case ILT_CLIENT_CDU: 668 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT; 669 end_reg = PXP2_REG_RQ_CDU_LAST_ILT; 670 break; 671 case ILT_CLIENT_QM: 672 start_reg = PXP2_REG_RQ_QM_FIRST_ILT; 673 end_reg = PXP2_REG_RQ_QM_LAST_ILT; 674 break; 675 case ILT_CLIENT_SRC: 676 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT; 677 end_reg = PXP2_REG_RQ_SRC_LAST_ILT; 678 break; 679 case ILT_CLIENT_TM: 680 start_reg = PXP2_REG_RQ_TM_FIRST_ILT; 681 end_reg = PXP2_REG_RQ_TM_LAST_ILT; 682 break; 683 } 684 REG_WR(sc, start_reg, (ilt_start + ilt_cli->start)); 685 REG_WR(sc, end_reg, (ilt_start + ilt_cli->end)); 686 } 687 688 static void ecore_ilt_client_init_op_ilt(struct bnx2x_softc *sc, 689 struct ecore_ilt *ilt, 690 struct ilt_client_info *ilt_cli, 691 uint8_t initop) 692 { 693 int i; 694 695 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) 696 return; 697 698 for (i = ilt_cli->start; i <= ilt_cli->end; i++) 699 ecore_ilt_line_init_op(sc, ilt, i, initop); 700 701 /* init/clear the ILT boundries */ 702 ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line); 703 } 704 705 static void ecore_ilt_client_init_op(struct bnx2x_softc *sc, 706 struct ilt_client_info *ilt_cli, uint8_t initop) 707 { 708 struct ecore_ilt *ilt = SC_ILT(sc); 709 710 ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop); 711 } 712 713 static void ecore_ilt_client_id_init_op(struct bnx2x_softc *sc, 714 int cli_num, uint8_t initop) 715 { 716 struct ecore_ilt *ilt = SC_ILT(sc); 717 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 718 719 ecore_ilt_client_init_op(sc, ilt_cli, initop); 720 } 721 722 static inline void ecore_ilt_init_op_cnic(struct bnx2x_softc *sc, uint8_t initop) 723 { 724 if (CONFIGURE_NIC_MODE(sc)) 725 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop); 726 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop); 727 } 728 729 static void ecore_ilt_init_op(struct bnx2x_softc *sc, uint8_t initop) 730 { 731 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop); 732 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop); 733 if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc)) 734 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop); 735 } 736 737 static void ecore_ilt_init_client_psz(struct bnx2x_softc *sc, int cli_num, 738 uint32_t psz_reg, uint8_t initop) 739 { 740 struct ecore_ilt *ilt = SC_ILT(sc); 741 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num]; 742 743 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT) 744 return; 745 746 switch (initop) { 747 case INITOP_INIT: 748 /* set in the init-value array */ 749 case INITOP_SET: 750 REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12)); 751 break; 752 case INITOP_CLEAR: 753 break; 754 } 755 } 756 757 /* 758 * called during init common stage, ilt clients should be initialized 759 * prioir to calling this function 760 */ 761 static void ecore_ilt_init_page_size(struct bnx2x_softc *sc, uint8_t initop) 762 { 763 ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU, 764 PXP2_REG_RQ_CDU_P_SIZE, initop); 765 ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM, 766 PXP2_REG_RQ_QM_P_SIZE, initop); 767 ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC, 768 PXP2_REG_RQ_SRC_P_SIZE, initop); 769 ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM, 770 PXP2_REG_RQ_TM_P_SIZE, initop); 771 } 772 773 /**************************************************************************** 774 * QM initializations 775 ****************************************************************************/ 776 #define QM_QUEUES_PER_FUNC 16 777 #define QM_INIT_MIN_CID_COUNT 31 778 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT) 779 780 /* called during init port stage */ 781 static void ecore_qm_init_cid_count(struct bnx2x_softc *sc, int qm_cid_count, 782 uint8_t initop) 783 { 784 int port = SC_PORT(sc); 785 786 if (QM_INIT(qm_cid_count)) { 787 switch (initop) { 788 case INITOP_INIT: 789 /* set in the init-value array */ 790 case INITOP_SET: 791 REG_WR(sc, QM_REG_CONNNUM_0 + port*4, 792 qm_cid_count/16 - 1); 793 break; 794 case INITOP_CLEAR: 795 break; 796 } 797 } 798 } 799 800 static void ecore_qm_set_ptr_table(struct bnx2x_softc *sc, int qm_cid_count, 801 uint32_t base_reg, uint32_t reg) 802 { 803 int i; 804 uint32_t wb_data[2] = {0, 0}; 805 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) { 806 REG_WR(sc, base_reg + i*4, 807 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC)); 808 ecore_init_wr_wb(sc, reg + i*8, 809 wb_data, 2); 810 } 811 } 812 813 /* called during init common stage */ 814 static void ecore_qm_init_ptr_table(struct bnx2x_softc *sc, int qm_cid_count, 815 uint8_t initop) 816 { 817 if (!QM_INIT(qm_cid_count)) 818 return; 819 820 switch (initop) { 821 case INITOP_INIT: 822 /* set in the init-value array */ 823 case INITOP_SET: 824 ecore_qm_set_ptr_table(sc, qm_cid_count, 825 QM_REG_BASEADDR, QM_REG_PTRTBL); 826 if (CHIP_IS_E1H(sc)) 827 ecore_qm_set_ptr_table(sc, qm_cid_count, 828 QM_REG_BASEADDR_EXT_A, 829 QM_REG_PTRTBL_EXT_A); 830 break; 831 case INITOP_CLEAR: 832 break; 833 } 834 } 835 836 /**************************************************************************** 837 * SRC initializations 838 ****************************************************************************/ 839 #ifdef ECORE_L5 840 /* called during init func stage */ 841 static void ecore_src_init_t2(struct bnx2x_softc *sc, struct src_ent *t2, 842 ecore_dma_addr_t t2_mapping, int src_cid_count) 843 { 844 int i; 845 int port = SC_PORT(sc); 846 847 /* Initialize T2 */ 848 for (i = 0; i < src_cid_count-1; i++) 849 t2[i].next = (uint64_t)(t2_mapping + 850 (i+1)*sizeof(struct src_ent)); 851 852 /* tell the searcher where the T2 table is */ 853 REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count); 854 855 ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16, 856 U64_LO(t2_mapping), U64_HI(t2_mapping)); 857 858 ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16, 859 U64_LO((uint64_t)t2_mapping + 860 (src_cid_count-1) * sizeof(struct src_ent)), 861 U64_HI((uint64_t)t2_mapping + 862 (src_cid_count-1) * sizeof(struct src_ent))); 863 } 864 #endif 865 #endif /* ECORE_INIT_OPS_H */ 866