1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_rxtx.h" 8 #include "axgbe_phy.h" 9 10 #include <rte_time.h> 11 #include <rte_mempool.h> 12 #include <rte_mbuf.h> 13 14 static void 15 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue) 16 { 17 uint16_t i; 18 struct rte_mbuf **sw_ring; 19 20 if (rx_queue) { 21 sw_ring = rx_queue->sw_ring; 22 if (sw_ring) { 23 for (i = 0; i < rx_queue->nb_desc; i++) { 24 if (sw_ring[i]) 25 rte_pktmbuf_free(sw_ring[i]); 26 } 27 rte_free(sw_ring); 28 } 29 rte_free(rx_queue); 30 } 31 } 32 33 void axgbe_dev_rx_queue_release(void *rxq) 34 { 35 axgbe_rx_queue_release(rxq); 36 } 37 38 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 39 uint16_t nb_desc, unsigned int socket_id, 40 const struct rte_eth_rxconf *rx_conf, 41 struct rte_mempool *mp) 42 { 43 PMD_INIT_FUNC_TRACE(); 44 uint32_t size; 45 const struct rte_memzone *dma; 46 struct axgbe_rx_queue *rxq; 47 uint32_t rx_desc = nb_desc; 48 struct axgbe_port *pdata = dev->data->dev_private; 49 50 /* 51 * validate Rx descriptors count 52 * should be power of 2 and less than h/w supported 53 */ 54 if ((!rte_is_power_of_2(rx_desc)) || 55 rx_desc > pdata->rx_desc_count) 56 return -EINVAL; 57 /* First allocate the rx queue data structure */ 58 rxq = rte_zmalloc_socket("ethdev RX queue", 59 sizeof(struct axgbe_rx_queue), 60 RTE_CACHE_LINE_SIZE, socket_id); 61 if (!rxq) { 62 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!"); 63 return -ENOMEM; 64 } 65 66 rxq->cur = 0; 67 rxq->dirty = 0; 68 rxq->pdata = pdata; 69 rxq->mb_pool = mp; 70 rxq->queue_id = queue_idx; 71 rxq->port_id = dev->data->port_id; 72 rxq->nb_desc = rx_desc; 73 rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + 74 (DMA_CH_INC * rxq->queue_id)); 75 rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs + 76 DMA_CH_RDTR_LO); 77 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 78 rxq->crc_len = RTE_ETHER_CRC_LEN; 79 else 80 rxq->crc_len = 0; 81 82 /* CRC strip in AXGBE supports per port not per queue */ 83 pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0; 84 rxq->free_thresh = rx_conf->rx_free_thresh ? 85 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH; 86 if (rxq->free_thresh > rxq->nb_desc) 87 rxq->free_thresh = rxq->nb_desc >> 3; 88 89 /* Allocate RX ring hardware descriptors */ 90 size = rxq->nb_desc * sizeof(union axgbe_rx_desc); 91 dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128, 92 socket_id); 93 if (!dma) { 94 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n"); 95 axgbe_rx_queue_release(rxq); 96 return -ENOMEM; 97 } 98 rxq->ring_phys_addr = (uint64_t)dma->phys_addr; 99 rxq->desc = (volatile union axgbe_rx_desc *)dma->addr; 100 memset((void *)rxq->desc, 0, size); 101 /* Allocate software ring */ 102 size = rxq->nb_desc * sizeof(struct rte_mbuf *); 103 rxq->sw_ring = rte_zmalloc_socket("sw_ring", size, 104 RTE_CACHE_LINE_SIZE, 105 socket_id); 106 if (!rxq->sw_ring) { 107 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n"); 108 axgbe_rx_queue_release(rxq); 109 return -ENOMEM; 110 } 111 dev->data->rx_queues[queue_idx] = rxq; 112 if (!pdata->rx_queues) 113 pdata->rx_queues = dev->data->rx_queues; 114 115 return 0; 116 } 117 118 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata, 119 unsigned int queue) 120 { 121 unsigned int rx_status; 122 unsigned long rx_timeout; 123 124 /* The Rx engine cannot be stopped if it is actively processing 125 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 126 * wait forever though... 127 */ 128 rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 129 rte_get_timer_hz()); 130 131 while (time_before(rte_get_timer_cycles(), rx_timeout)) { 132 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 133 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 134 (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 135 break; 136 137 rte_delay_us(900); 138 } 139 140 if (!time_before(rte_get_timer_cycles(), rx_timeout)) 141 PMD_DRV_LOG(ERR, 142 "timed out waiting for Rx queue %u to empty\n", 143 queue); 144 } 145 146 void axgbe_dev_disable_rx(struct rte_eth_dev *dev) 147 { 148 struct axgbe_rx_queue *rxq; 149 struct axgbe_port *pdata = dev->data->dev_private; 150 unsigned int i; 151 152 /* Disable MAC Rx */ 153 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 154 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 155 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 156 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 157 158 /* Prepare for Rx DMA channel stop */ 159 for (i = 0; i < dev->data->nb_rx_queues; i++) { 160 rxq = dev->data->rx_queues[i]; 161 axgbe_prepare_rx_stop(pdata, i); 162 } 163 /* Disable each Rx queue */ 164 AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 165 for (i = 0; i < dev->data->nb_rx_queues; i++) { 166 rxq = dev->data->rx_queues[i]; 167 /* Disable Rx DMA channel */ 168 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0); 169 } 170 } 171 172 void axgbe_dev_enable_rx(struct rte_eth_dev *dev) 173 { 174 struct axgbe_rx_queue *rxq; 175 struct axgbe_port *pdata = dev->data->dev_private; 176 unsigned int i; 177 unsigned int reg_val = 0; 178 179 for (i = 0; i < dev->data->nb_rx_queues; i++) { 180 rxq = dev->data->rx_queues[i]; 181 /* Enable Rx DMA channel */ 182 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1); 183 } 184 185 reg_val = 0; 186 for (i = 0; i < pdata->rx_q_count; i++) 187 reg_val |= (0x02 << (i << 1)); 188 AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 189 190 /* Enable MAC Rx */ 191 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 192 /* Frame is forwarded after stripping CRC to application*/ 193 if (pdata->crc_strip_enable) { 194 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 195 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 196 } 197 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 198 } 199 200 /* Rx function one to one refresh */ 201 uint16_t 202 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 203 uint16_t nb_pkts) 204 { 205 PMD_INIT_FUNC_TRACE(); 206 uint16_t nb_rx = 0; 207 struct axgbe_rx_queue *rxq = rx_queue; 208 volatile union axgbe_rx_desc *desc; 209 uint64_t old_dirty = rxq->dirty; 210 struct rte_mbuf *mbuf, *tmbuf; 211 unsigned int err; 212 uint32_t error_status; 213 uint16_t idx, pidx, pkt_len; 214 215 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 216 while (nb_rx < nb_pkts) { 217 if (unlikely(idx == rxq->nb_desc)) 218 idx = 0; 219 220 desc = &rxq->desc[idx]; 221 222 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 223 break; 224 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool); 225 if (unlikely(!tmbuf)) { 226 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u" 227 " queue_id = %u\n", 228 (unsigned int)rxq->port_id, 229 (unsigned int)rxq->queue_id); 230 rte_eth_devices[ 231 rxq->port_id].data->rx_mbuf_alloc_failed++; 232 rxq->rx_mbuf_alloc_failed++; 233 break; 234 } 235 pidx = idx + 1; 236 if (unlikely(pidx == rxq->nb_desc)) 237 pidx = 0; 238 239 rte_prefetch0(rxq->sw_ring[pidx]); 240 if ((pidx & 0x3) == 0) { 241 rte_prefetch0(&rxq->desc[pidx]); 242 rte_prefetch0(&rxq->sw_ring[pidx]); 243 } 244 245 mbuf = rxq->sw_ring[idx]; 246 /* Check for any errors and free mbuf*/ 247 err = AXGMAC_GET_BITS_LE(desc->write.desc3, 248 RX_NORMAL_DESC3, ES); 249 error_status = 0; 250 if (unlikely(err)) { 251 error_status = desc->write.desc3 & AXGBE_ERR_STATUS; 252 if ((error_status != AXGBE_L3_CSUM_ERR) && 253 (error_status != AXGBE_L4_CSUM_ERR)) { 254 rxq->errors++; 255 rte_pktmbuf_free(mbuf); 256 goto err_set; 257 } 258 } 259 if (rxq->pdata->rx_csum_enable) { 260 mbuf->ol_flags = 0; 261 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD; 262 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD; 263 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) { 264 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD; 265 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD; 266 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD; 267 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 268 } else if ( 269 unlikely(error_status == AXGBE_L4_CSUM_ERR)) { 270 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD; 271 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD; 272 } 273 } 274 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *)); 275 /* Get the RSS hash */ 276 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) 277 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1); 278 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, 279 PL) - rxq->crc_len; 280 /* Mbuf populate */ 281 mbuf->next = NULL; 282 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 283 mbuf->nb_segs = 1; 284 mbuf->port = rxq->port_id; 285 mbuf->pkt_len = pkt_len; 286 mbuf->data_len = pkt_len; 287 rxq->bytes += pkt_len; 288 rx_pkts[nb_rx++] = mbuf; 289 err_set: 290 rxq->cur++; 291 rxq->sw_ring[idx++] = tmbuf; 292 desc->read.baddr = 293 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf)); 294 memset((void *)(&desc->read.desc2), 0, 8); 295 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1); 296 rxq->dirty++; 297 } 298 rxq->pkts += nb_rx; 299 if (rxq->dirty != old_dirty) { 300 rte_wmb(); 301 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1); 302 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO, 303 low32_value(rxq->ring_phys_addr + 304 (idx * sizeof(union axgbe_rx_desc)))); 305 } 306 307 return nb_rx; 308 } 309 310 /* Tx Apis */ 311 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue) 312 { 313 uint16_t i; 314 struct rte_mbuf **sw_ring; 315 316 if (tx_queue) { 317 sw_ring = tx_queue->sw_ring; 318 if (sw_ring) { 319 for (i = 0; i < tx_queue->nb_desc; i++) { 320 if (sw_ring[i]) 321 rte_pktmbuf_free(sw_ring[i]); 322 } 323 rte_free(sw_ring); 324 } 325 rte_free(tx_queue); 326 } 327 } 328 329 void axgbe_dev_tx_queue_release(void *txq) 330 { 331 axgbe_tx_queue_release(txq); 332 } 333 334 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 335 uint16_t nb_desc, unsigned int socket_id, 336 const struct rte_eth_txconf *tx_conf) 337 { 338 PMD_INIT_FUNC_TRACE(); 339 uint32_t tx_desc; 340 struct axgbe_port *pdata; 341 struct axgbe_tx_queue *txq; 342 unsigned int tsize; 343 const struct rte_memzone *tz; 344 345 tx_desc = nb_desc; 346 pdata = dev->data->dev_private; 347 348 /* 349 * validate tx descriptors count 350 * should be power of 2 and less than h/w supported 351 */ 352 if ((!rte_is_power_of_2(tx_desc)) || 353 tx_desc > pdata->tx_desc_count || 354 tx_desc < AXGBE_MIN_RING_DESC) 355 return -EINVAL; 356 357 /* First allocate the tx queue data structure */ 358 txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue), 359 RTE_CACHE_LINE_SIZE); 360 if (!txq) 361 return -ENOMEM; 362 txq->pdata = pdata; 363 364 txq->nb_desc = tx_desc; 365 txq->free_thresh = tx_conf->tx_free_thresh ? 366 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH; 367 if (txq->free_thresh > txq->nb_desc) 368 txq->free_thresh = (txq->nb_desc >> 1); 369 txq->free_batch_cnt = txq->free_thresh; 370 371 /* In vector_tx path threshold should be multiple of queue_size*/ 372 if (txq->nb_desc % txq->free_thresh != 0) 373 txq->vector_disable = 1; 374 375 if (tx_conf->offloads != 0) 376 txq->vector_disable = 1; 377 378 /* Allocate TX ring hardware descriptors */ 379 tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc); 380 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, 381 tsize, AXGBE_DESC_ALIGN, socket_id); 382 if (!tz) { 383 axgbe_tx_queue_release(txq); 384 return -ENOMEM; 385 } 386 memset(tz->addr, 0, tsize); 387 txq->ring_phys_addr = (uint64_t)tz->phys_addr; 388 txq->desc = tz->addr; 389 txq->queue_id = queue_idx; 390 txq->port_id = dev->data->port_id; 391 txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + 392 (DMA_CH_INC * txq->queue_id)); 393 txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs + 394 DMA_CH_TDTR_LO); 395 txq->cur = 0; 396 txq->dirty = 0; 397 txq->nb_desc_free = txq->nb_desc; 398 /* Allocate software ring */ 399 tsize = txq->nb_desc * sizeof(struct rte_mbuf *); 400 txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize, 401 RTE_CACHE_LINE_SIZE); 402 if (!txq->sw_ring) { 403 axgbe_tx_queue_release(txq); 404 return -ENOMEM; 405 } 406 dev->data->tx_queues[queue_idx] = txq; 407 if (!pdata->tx_queues) 408 pdata->tx_queues = dev->data->tx_queues; 409 410 if (txq->vector_disable) 411 dev->tx_pkt_burst = &axgbe_xmit_pkts; 412 else 413 #ifdef RTE_ARCH_X86 414 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 415 #else 416 dev->tx_pkt_burst = &axgbe_xmit_pkts; 417 #endif 418 419 return 0; 420 } 421 422 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata, 423 unsigned int queue) 424 { 425 unsigned int tx_status; 426 unsigned long tx_timeout; 427 428 /* The Tx engine cannot be stopped if it is actively processing 429 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 430 * wait forever though... 431 */ 432 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 433 rte_get_timer_hz()); 434 while (time_before(rte_get_timer_cycles(), tx_timeout)) { 435 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 436 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 437 (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 438 break; 439 440 rte_delay_us(900); 441 } 442 443 if (!time_before(rte_get_timer_cycles(), tx_timeout)) 444 PMD_DRV_LOG(ERR, 445 "timed out waiting for Tx queue %u to empty\n", 446 queue); 447 } 448 449 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata, 450 unsigned int queue) 451 { 452 unsigned int tx_dsr, tx_pos, tx_qidx; 453 unsigned int tx_status; 454 unsigned long tx_timeout; 455 456 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 457 return axgbe_txq_prepare_tx_stop(pdata, queue); 458 459 /* Calculate the status register to read and the position within */ 460 if (queue < DMA_DSRX_FIRST_QUEUE) { 461 tx_dsr = DMA_DSR0; 462 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 463 } else { 464 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 465 466 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 467 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 468 DMA_DSRX_TPS_START; 469 } 470 471 /* The Tx engine cannot be stopped if it is actively processing 472 * descriptors. Wait for the Tx engine to enter the stopped or 473 * suspended state. Don't wait forever though... 474 */ 475 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 476 rte_get_timer_hz()); 477 while (time_before(rte_get_timer_cycles(), tx_timeout)) { 478 tx_status = AXGMAC_IOREAD(pdata, tx_dsr); 479 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 480 if ((tx_status == DMA_TPS_STOPPED) || 481 (tx_status == DMA_TPS_SUSPENDED)) 482 break; 483 484 rte_delay_us(900); 485 } 486 487 if (!time_before(rte_get_timer_cycles(), tx_timeout)) 488 PMD_DRV_LOG(ERR, 489 "timed out waiting for Tx DMA channel %u to stop\n", 490 queue); 491 } 492 493 void axgbe_dev_disable_tx(struct rte_eth_dev *dev) 494 { 495 struct axgbe_tx_queue *txq; 496 struct axgbe_port *pdata = dev->data->dev_private; 497 unsigned int i; 498 499 /* Prepare for stopping DMA channel */ 500 for (i = 0; i < pdata->tx_q_count; i++) { 501 txq = dev->data->tx_queues[i]; 502 axgbe_prepare_tx_stop(pdata, i); 503 } 504 /* Disable MAC Tx */ 505 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 506 /* Disable each Tx queue*/ 507 for (i = 0; i < pdata->tx_q_count; i++) 508 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 509 0); 510 /* Disable each Tx DMA channel */ 511 for (i = 0; i < dev->data->nb_tx_queues; i++) { 512 txq = dev->data->tx_queues[i]; 513 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0); 514 } 515 } 516 517 void axgbe_dev_enable_tx(struct rte_eth_dev *dev) 518 { 519 struct axgbe_tx_queue *txq; 520 struct axgbe_port *pdata = dev->data->dev_private; 521 unsigned int i; 522 523 for (i = 0; i < dev->data->nb_tx_queues; i++) { 524 txq = dev->data->tx_queues[i]; 525 /* Enable Tx DMA channel */ 526 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1); 527 } 528 /* Enable Tx queue*/ 529 for (i = 0; i < pdata->tx_q_count; i++) 530 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 531 MTL_Q_ENABLED); 532 /* Enable MAC Tx */ 533 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 534 } 535 536 /* Free Tx conformed mbufs */ 537 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq) 538 { 539 volatile struct axgbe_tx_desc *desc; 540 uint16_t idx; 541 542 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty); 543 while (txq->cur != txq->dirty) { 544 if (unlikely(idx == txq->nb_desc)) 545 idx = 0; 546 desc = &txq->desc[idx]; 547 /* Check for ownership */ 548 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN)) 549 return; 550 memset((void *)&desc->desc2, 0, 8); 551 /* Free mbuf */ 552 rte_pktmbuf_free(txq->sw_ring[idx]); 553 txq->sw_ring[idx++] = NULL; 554 txq->dirty++; 555 } 556 } 557 558 /* Tx Descriptor formation 559 * Considering each mbuf requires one desc 560 * mbuf is linear 561 */ 562 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq, 563 struct rte_mbuf *mbuf) 564 { 565 volatile struct axgbe_tx_desc *desc; 566 uint16_t idx; 567 uint64_t mask; 568 569 idx = AXGBE_GET_DESC_IDX(txq, txq->cur); 570 desc = &txq->desc[idx]; 571 572 /* Update buffer address and length */ 573 desc->baddr = rte_mbuf_data_iova(mbuf); 574 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L, 575 mbuf->pkt_len); 576 /* Total msg length to transmit */ 577 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL, 578 mbuf->pkt_len); 579 /* Mark it as First and Last Descriptor */ 580 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1); 581 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1); 582 /* Mark it as a NORMAL descriptor */ 583 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0); 584 /* configure h/w Offload */ 585 mask = mbuf->ol_flags & PKT_TX_L4_MASK; 586 if ((mask == PKT_TX_TCP_CKSUM) || (mask == PKT_TX_UDP_CKSUM)) 587 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3); 588 else if (mbuf->ol_flags & PKT_TX_IP_CKSUM) 589 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1); 590 rte_wmb(); 591 592 /* Set OWN bit */ 593 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1); 594 rte_wmb(); 595 596 /* Save mbuf */ 597 txq->sw_ring[idx] = mbuf; 598 /* Update current index*/ 599 txq->cur++; 600 /* Update stats */ 601 txq->bytes += mbuf->pkt_len; 602 603 return 0; 604 } 605 606 /* Eal supported tx wrapper*/ 607 uint16_t 608 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 609 uint16_t nb_pkts) 610 { 611 PMD_INIT_FUNC_TRACE(); 612 613 if (unlikely(nb_pkts == 0)) 614 return nb_pkts; 615 616 struct axgbe_tx_queue *txq; 617 uint16_t nb_desc_free; 618 uint16_t nb_pkt_sent = 0; 619 uint16_t idx; 620 uint32_t tail_addr; 621 struct rte_mbuf *mbuf; 622 623 txq = (struct axgbe_tx_queue *)tx_queue; 624 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty); 625 626 if (unlikely(nb_desc_free <= txq->free_thresh)) { 627 axgbe_xmit_cleanup(txq); 628 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty); 629 if (unlikely(nb_desc_free == 0)) 630 return 0; 631 } 632 nb_pkts = RTE_MIN(nb_desc_free, nb_pkts); 633 while (nb_pkts--) { 634 mbuf = *tx_pkts++; 635 if (axgbe_xmit_hw(txq, mbuf)) 636 goto out; 637 nb_pkt_sent++; 638 } 639 out: 640 /* Sync read and write */ 641 rte_mb(); 642 idx = AXGBE_GET_DESC_IDX(txq, txq->cur); 643 tail_addr = low32_value(txq->ring_phys_addr + 644 idx * sizeof(struct axgbe_tx_desc)); 645 /* Update tail reg with next immediate address to kick Tx DMA channel*/ 646 AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr); 647 txq->pkts += nb_pkt_sent; 648 return nb_pkt_sent; 649 } 650 651 void axgbe_dev_clear_queues(struct rte_eth_dev *dev) 652 { 653 PMD_INIT_FUNC_TRACE(); 654 uint8_t i; 655 struct axgbe_rx_queue *rxq; 656 struct axgbe_tx_queue *txq; 657 658 for (i = 0; i < dev->data->nb_rx_queues; i++) { 659 rxq = dev->data->rx_queues[i]; 660 661 if (rxq) { 662 axgbe_rx_queue_release(rxq); 663 dev->data->rx_queues[i] = NULL; 664 } 665 } 666 667 for (i = 0; i < dev->data->nb_tx_queues; i++) { 668 txq = dev->data->tx_queues[i]; 669 670 if (txq) { 671 axgbe_tx_queue_release(txq); 672 dev->data->tx_queues[i] = NULL; 673 } 674 } 675 } 676