1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_rxtx.h" 8 #include "axgbe_phy.h" 9 10 #include <rte_time.h> 11 #include <rte_mempool.h> 12 #include <rte_mbuf.h> 13 14 static void 15 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue) 16 { 17 uint16_t i; 18 struct rte_mbuf **sw_ring; 19 20 if (rx_queue) { 21 sw_ring = rx_queue->sw_ring; 22 if (sw_ring) { 23 for (i = 0; i < rx_queue->nb_desc; i++) { 24 if (sw_ring[i]) 25 rte_pktmbuf_free(sw_ring[i]); 26 } 27 rte_free(sw_ring); 28 } 29 rte_free(rx_queue); 30 } 31 } 32 33 void axgbe_dev_rx_queue_release(void *rxq) 34 { 35 axgbe_rx_queue_release(rxq); 36 } 37 38 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 39 uint16_t nb_desc, unsigned int socket_id, 40 const struct rte_eth_rxconf *rx_conf, 41 struct rte_mempool *mp) 42 { 43 PMD_INIT_FUNC_TRACE(); 44 uint32_t size; 45 const struct rte_memzone *dma; 46 struct axgbe_rx_queue *rxq; 47 uint32_t rx_desc = nb_desc; 48 struct axgbe_port *pdata = dev->data->dev_private; 49 50 /* 51 * validate Rx descriptors count 52 * should be power of 2 and less than h/w supported 53 */ 54 if ((!rte_is_power_of_2(rx_desc)) || 55 rx_desc > pdata->rx_desc_count) 56 return -EINVAL; 57 /* First allocate the rx queue data structure */ 58 rxq = rte_zmalloc_socket("ethdev RX queue", 59 sizeof(struct axgbe_rx_queue), 60 RTE_CACHE_LINE_SIZE, socket_id); 61 if (!rxq) { 62 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!"); 63 return -ENOMEM; 64 } 65 66 rxq->cur = 0; 67 rxq->dirty = 0; 68 rxq->pdata = pdata; 69 rxq->mb_pool = mp; 70 rxq->queue_id = queue_idx; 71 rxq->port_id = dev->data->port_id; 72 rxq->nb_desc = rx_desc; 73 rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + 74 (DMA_CH_INC * rxq->queue_id)); 75 rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs + 76 DMA_CH_RDTR_LO); 77 if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC) 78 rxq->crc_len = RTE_ETHER_CRC_LEN; 79 else 80 rxq->crc_len = 0; 81 82 /* CRC strip in AXGBE supports per port not per queue */ 83 pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0; 84 rxq->free_thresh = rx_conf->rx_free_thresh ? 85 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH; 86 if (rxq->free_thresh > rxq->nb_desc) 87 rxq->free_thresh = rxq->nb_desc >> 3; 88 89 /* Allocate RX ring hardware descriptors */ 90 size = rxq->nb_desc * sizeof(union axgbe_rx_desc); 91 dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128, 92 socket_id); 93 if (!dma) { 94 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n"); 95 axgbe_rx_queue_release(rxq); 96 return -ENOMEM; 97 } 98 rxq->ring_phys_addr = (uint64_t)dma->phys_addr; 99 rxq->desc = (volatile union axgbe_rx_desc *)dma->addr; 100 memset((void *)rxq->desc, 0, size); 101 /* Allocate software ring */ 102 size = rxq->nb_desc * sizeof(struct rte_mbuf *); 103 rxq->sw_ring = rte_zmalloc_socket("sw_ring", size, 104 RTE_CACHE_LINE_SIZE, 105 socket_id); 106 if (!rxq->sw_ring) { 107 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n"); 108 axgbe_rx_queue_release(rxq); 109 return -ENOMEM; 110 } 111 dev->data->rx_queues[queue_idx] = rxq; 112 if (!pdata->rx_queues) 113 pdata->rx_queues = dev->data->rx_queues; 114 115 return 0; 116 } 117 118 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata, 119 unsigned int queue) 120 { 121 unsigned int rx_status; 122 unsigned long rx_timeout; 123 124 /* The Rx engine cannot be stopped if it is actively processing 125 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 126 * wait forever though... 127 */ 128 rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 129 rte_get_timer_hz()); 130 131 while (time_before(rte_get_timer_cycles(), rx_timeout)) { 132 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 133 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 134 (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 135 break; 136 137 rte_delay_us(900); 138 } 139 140 if (!time_before(rte_get_timer_cycles(), rx_timeout)) 141 PMD_DRV_LOG(ERR, 142 "timed out waiting for Rx queue %u to empty\n", 143 queue); 144 } 145 146 void axgbe_dev_disable_rx(struct rte_eth_dev *dev) 147 { 148 struct axgbe_rx_queue *rxq; 149 struct axgbe_port *pdata = dev->data->dev_private; 150 unsigned int i; 151 152 /* Disable MAC Rx */ 153 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 154 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 155 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 156 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 157 158 /* Prepare for Rx DMA channel stop */ 159 for (i = 0; i < dev->data->nb_rx_queues; i++) { 160 rxq = dev->data->rx_queues[i]; 161 axgbe_prepare_rx_stop(pdata, i); 162 } 163 /* Disable each Rx queue */ 164 AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 165 for (i = 0; i < dev->data->nb_rx_queues; i++) { 166 rxq = dev->data->rx_queues[i]; 167 /* Disable Rx DMA channel */ 168 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0); 169 } 170 } 171 172 void axgbe_dev_enable_rx(struct rte_eth_dev *dev) 173 { 174 struct axgbe_rx_queue *rxq; 175 struct axgbe_port *pdata = dev->data->dev_private; 176 unsigned int i; 177 unsigned int reg_val = 0; 178 179 for (i = 0; i < dev->data->nb_rx_queues; i++) { 180 rxq = dev->data->rx_queues[i]; 181 /* Enable Rx DMA channel */ 182 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1); 183 } 184 185 reg_val = 0; 186 for (i = 0; i < pdata->rx_q_count; i++) 187 reg_val |= (0x02 << (i << 1)); 188 AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 189 190 /* Enable MAC Rx */ 191 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 192 /* Frame is forwarded after stripping CRC to application*/ 193 if (pdata->crc_strip_enable) { 194 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 195 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 196 } 197 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 198 } 199 200 /* Rx function one to one refresh */ 201 uint16_t 202 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 203 uint16_t nb_pkts) 204 { 205 PMD_INIT_FUNC_TRACE(); 206 uint16_t nb_rx = 0; 207 struct axgbe_rx_queue *rxq = rx_queue; 208 volatile union axgbe_rx_desc *desc; 209 uint64_t old_dirty = rxq->dirty; 210 struct rte_mbuf *mbuf, *tmbuf; 211 unsigned int err; 212 uint32_t error_status; 213 uint16_t idx, pidx, pkt_len; 214 215 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 216 while (nb_rx < nb_pkts) { 217 if (unlikely(idx == rxq->nb_desc)) 218 idx = 0; 219 220 desc = &rxq->desc[idx]; 221 222 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 223 break; 224 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool); 225 if (unlikely(!tmbuf)) { 226 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u" 227 " queue_id = %u\n", 228 (unsigned int)rxq->port_id, 229 (unsigned int)rxq->queue_id); 230 rte_eth_devices[ 231 rxq->port_id].data->rx_mbuf_alloc_failed++; 232 break; 233 } 234 pidx = idx + 1; 235 if (unlikely(pidx == rxq->nb_desc)) 236 pidx = 0; 237 238 rte_prefetch0(rxq->sw_ring[pidx]); 239 if ((pidx & 0x3) == 0) { 240 rte_prefetch0(&rxq->desc[pidx]); 241 rte_prefetch0(&rxq->sw_ring[pidx]); 242 } 243 244 mbuf = rxq->sw_ring[idx]; 245 /* Check for any errors and free mbuf*/ 246 err = AXGMAC_GET_BITS_LE(desc->write.desc3, 247 RX_NORMAL_DESC3, ES); 248 error_status = 0; 249 if (unlikely(err)) { 250 error_status = desc->write.desc3 & AXGBE_ERR_STATUS; 251 if ((error_status != AXGBE_L3_CSUM_ERR) && 252 (error_status != AXGBE_L4_CSUM_ERR)) { 253 rxq->errors++; 254 rte_pktmbuf_free(mbuf); 255 goto err_set; 256 } 257 } 258 if (rxq->pdata->rx_csum_enable) { 259 mbuf->ol_flags = 0; 260 mbuf->ol_flags |= PKT_RX_IP_CKSUM_GOOD; 261 mbuf->ol_flags |= PKT_RX_L4_CKSUM_GOOD; 262 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) { 263 mbuf->ol_flags &= ~PKT_RX_IP_CKSUM_GOOD; 264 mbuf->ol_flags |= PKT_RX_IP_CKSUM_BAD; 265 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD; 266 mbuf->ol_flags |= PKT_RX_L4_CKSUM_UNKNOWN; 267 } else if ( 268 unlikely(error_status == AXGBE_L4_CSUM_ERR)) { 269 mbuf->ol_flags &= ~PKT_RX_L4_CKSUM_GOOD; 270 mbuf->ol_flags |= PKT_RX_L4_CKSUM_BAD; 271 } 272 } 273 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *)); 274 /* Get the RSS hash */ 275 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) 276 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1); 277 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, 278 PL) - rxq->crc_len; 279 /* Mbuf populate */ 280 mbuf->next = NULL; 281 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 282 mbuf->nb_segs = 1; 283 mbuf->port = rxq->port_id; 284 mbuf->pkt_len = pkt_len; 285 mbuf->data_len = pkt_len; 286 rxq->bytes += pkt_len; 287 rx_pkts[nb_rx++] = mbuf; 288 err_set: 289 rxq->cur++; 290 rxq->sw_ring[idx++] = tmbuf; 291 desc->read.baddr = 292 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf)); 293 memset((void *)(&desc->read.desc2), 0, 8); 294 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1); 295 rxq->dirty++; 296 } 297 rxq->pkts += nb_rx; 298 if (rxq->dirty != old_dirty) { 299 rte_wmb(); 300 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1); 301 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO, 302 low32_value(rxq->ring_phys_addr + 303 (idx * sizeof(union axgbe_rx_desc)))); 304 } 305 306 return nb_rx; 307 } 308 309 /* Tx Apis */ 310 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue) 311 { 312 uint16_t i; 313 struct rte_mbuf **sw_ring; 314 315 if (tx_queue) { 316 sw_ring = tx_queue->sw_ring; 317 if (sw_ring) { 318 for (i = 0; i < tx_queue->nb_desc; i++) { 319 if (sw_ring[i]) 320 rte_pktmbuf_free(sw_ring[i]); 321 } 322 rte_free(sw_ring); 323 } 324 rte_free(tx_queue); 325 } 326 } 327 328 void axgbe_dev_tx_queue_release(void *txq) 329 { 330 axgbe_tx_queue_release(txq); 331 } 332 333 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 334 uint16_t nb_desc, unsigned int socket_id, 335 const struct rte_eth_txconf *tx_conf) 336 { 337 PMD_INIT_FUNC_TRACE(); 338 uint32_t tx_desc; 339 struct axgbe_port *pdata; 340 struct axgbe_tx_queue *txq; 341 unsigned int tsize; 342 const struct rte_memzone *tz; 343 344 tx_desc = nb_desc; 345 pdata = dev->data->dev_private; 346 347 /* 348 * validate tx descriptors count 349 * should be power of 2 and less than h/w supported 350 */ 351 if ((!rte_is_power_of_2(tx_desc)) || 352 tx_desc > pdata->tx_desc_count || 353 tx_desc < AXGBE_MIN_RING_DESC) 354 return -EINVAL; 355 356 /* First allocate the tx queue data structure */ 357 txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue), 358 RTE_CACHE_LINE_SIZE); 359 if (!txq) 360 return -ENOMEM; 361 txq->pdata = pdata; 362 363 txq->nb_desc = tx_desc; 364 txq->free_thresh = tx_conf->tx_free_thresh ? 365 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH; 366 if (txq->free_thresh > txq->nb_desc) 367 txq->free_thresh = (txq->nb_desc >> 1); 368 txq->free_batch_cnt = txq->free_thresh; 369 370 /* In vector_tx path threshold should be multiple of queue_size*/ 371 if (txq->nb_desc % txq->free_thresh != 0) 372 txq->vector_disable = 1; 373 374 if (tx_conf->offloads != 0) 375 txq->vector_disable = 1; 376 377 /* Allocate TX ring hardware descriptors */ 378 tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc); 379 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, 380 tsize, AXGBE_DESC_ALIGN, socket_id); 381 if (!tz) { 382 axgbe_tx_queue_release(txq); 383 return -ENOMEM; 384 } 385 memset(tz->addr, 0, tsize); 386 txq->ring_phys_addr = (uint64_t)tz->phys_addr; 387 txq->desc = tz->addr; 388 txq->queue_id = queue_idx; 389 txq->port_id = dev->data->port_id; 390 txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + 391 (DMA_CH_INC * txq->queue_id)); 392 txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs + 393 DMA_CH_TDTR_LO); 394 txq->cur = 0; 395 txq->dirty = 0; 396 txq->nb_desc_free = txq->nb_desc; 397 /* Allocate software ring */ 398 tsize = txq->nb_desc * sizeof(struct rte_mbuf *); 399 txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize, 400 RTE_CACHE_LINE_SIZE); 401 if (!txq->sw_ring) { 402 axgbe_tx_queue_release(txq); 403 return -ENOMEM; 404 } 405 dev->data->tx_queues[queue_idx] = txq; 406 if (!pdata->tx_queues) 407 pdata->tx_queues = dev->data->tx_queues; 408 409 if (txq->vector_disable) 410 dev->tx_pkt_burst = &axgbe_xmit_pkts; 411 else 412 #ifdef RTE_ARCH_X86 413 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 414 #else 415 dev->tx_pkt_burst = &axgbe_xmit_pkts; 416 #endif 417 418 return 0; 419 } 420 421 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata, 422 unsigned int queue) 423 { 424 unsigned int tx_status; 425 unsigned long tx_timeout; 426 427 /* The Tx engine cannot be stopped if it is actively processing 428 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 429 * wait forever though... 430 */ 431 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 432 rte_get_timer_hz()); 433 while (time_before(rte_get_timer_cycles(), tx_timeout)) { 434 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 435 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 436 (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 437 break; 438 439 rte_delay_us(900); 440 } 441 442 if (!time_before(rte_get_timer_cycles(), tx_timeout)) 443 PMD_DRV_LOG(ERR, 444 "timed out waiting for Tx queue %u to empty\n", 445 queue); 446 } 447 448 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata, 449 unsigned int queue) 450 { 451 unsigned int tx_dsr, tx_pos, tx_qidx; 452 unsigned int tx_status; 453 unsigned long tx_timeout; 454 455 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 456 return axgbe_txq_prepare_tx_stop(pdata, queue); 457 458 /* Calculate the status register to read and the position within */ 459 if (queue < DMA_DSRX_FIRST_QUEUE) { 460 tx_dsr = DMA_DSR0; 461 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 462 } else { 463 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 464 465 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 466 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 467 DMA_DSRX_TPS_START; 468 } 469 470 /* The Tx engine cannot be stopped if it is actively processing 471 * descriptors. Wait for the Tx engine to enter the stopped or 472 * suspended state. Don't wait forever though... 473 */ 474 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 475 rte_get_timer_hz()); 476 while (time_before(rte_get_timer_cycles(), tx_timeout)) { 477 tx_status = AXGMAC_IOREAD(pdata, tx_dsr); 478 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 479 if ((tx_status == DMA_TPS_STOPPED) || 480 (tx_status == DMA_TPS_SUSPENDED)) 481 break; 482 483 rte_delay_us(900); 484 } 485 486 if (!time_before(rte_get_timer_cycles(), tx_timeout)) 487 PMD_DRV_LOG(ERR, 488 "timed out waiting for Tx DMA channel %u to stop\n", 489 queue); 490 } 491 492 void axgbe_dev_disable_tx(struct rte_eth_dev *dev) 493 { 494 struct axgbe_tx_queue *txq; 495 struct axgbe_port *pdata = dev->data->dev_private; 496 unsigned int i; 497 498 /* Prepare for stopping DMA channel */ 499 for (i = 0; i < pdata->tx_q_count; i++) { 500 txq = dev->data->tx_queues[i]; 501 axgbe_prepare_tx_stop(pdata, i); 502 } 503 /* Disable MAC Tx */ 504 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 505 /* Disable each Tx queue*/ 506 for (i = 0; i < pdata->tx_q_count; i++) 507 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 508 0); 509 /* Disable each Tx DMA channel */ 510 for (i = 0; i < dev->data->nb_tx_queues; i++) { 511 txq = dev->data->tx_queues[i]; 512 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0); 513 } 514 } 515 516 void axgbe_dev_enable_tx(struct rte_eth_dev *dev) 517 { 518 struct axgbe_tx_queue *txq; 519 struct axgbe_port *pdata = dev->data->dev_private; 520 unsigned int i; 521 522 for (i = 0; i < dev->data->nb_tx_queues; i++) { 523 txq = dev->data->tx_queues[i]; 524 /* Enable Tx DMA channel */ 525 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1); 526 } 527 /* Enable Tx queue*/ 528 for (i = 0; i < pdata->tx_q_count; i++) 529 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 530 MTL_Q_ENABLED); 531 /* Enable MAC Tx */ 532 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 533 } 534 535 /* Free Tx conformed mbufs */ 536 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq) 537 { 538 volatile struct axgbe_tx_desc *desc; 539 uint16_t idx; 540 541 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty); 542 while (txq->cur != txq->dirty) { 543 if (unlikely(idx == txq->nb_desc)) 544 idx = 0; 545 desc = &txq->desc[idx]; 546 /* Check for ownership */ 547 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN)) 548 return; 549 memset((void *)&desc->desc2, 0, 8); 550 /* Free mbuf */ 551 rte_pktmbuf_free(txq->sw_ring[idx]); 552 txq->sw_ring[idx++] = NULL; 553 txq->dirty++; 554 } 555 } 556 557 /* Tx Descriptor formation 558 * Considering each mbuf requires one desc 559 * mbuf is linear 560 */ 561 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq, 562 struct rte_mbuf *mbuf) 563 { 564 volatile struct axgbe_tx_desc *desc; 565 uint16_t idx; 566 uint64_t mask; 567 568 idx = AXGBE_GET_DESC_IDX(txq, txq->cur); 569 desc = &txq->desc[idx]; 570 571 /* Update buffer address and length */ 572 desc->baddr = rte_mbuf_data_iova(mbuf); 573 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L, 574 mbuf->pkt_len); 575 /* Total msg length to transmit */ 576 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL, 577 mbuf->pkt_len); 578 /* Mark it as First and Last Descriptor */ 579 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1); 580 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1); 581 /* Mark it as a NORMAL descriptor */ 582 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0); 583 /* configure h/w Offload */ 584 mask = mbuf->ol_flags & PKT_TX_L4_MASK; 585 if ((mask == PKT_TX_TCP_CKSUM) || (mask == PKT_TX_UDP_CKSUM)) 586 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3); 587 else if (mbuf->ol_flags & PKT_TX_IP_CKSUM) 588 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1); 589 rte_wmb(); 590 591 /* Set OWN bit */ 592 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1); 593 rte_wmb(); 594 595 /* Save mbuf */ 596 txq->sw_ring[idx] = mbuf; 597 /* Update current index*/ 598 txq->cur++; 599 /* Update stats */ 600 txq->bytes += mbuf->pkt_len; 601 602 return 0; 603 } 604 605 /* Eal supported tx wrapper*/ 606 uint16_t 607 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 608 uint16_t nb_pkts) 609 { 610 PMD_INIT_FUNC_TRACE(); 611 612 if (unlikely(nb_pkts == 0)) 613 return nb_pkts; 614 615 struct axgbe_tx_queue *txq; 616 uint16_t nb_desc_free; 617 uint16_t nb_pkt_sent = 0; 618 uint16_t idx; 619 uint32_t tail_addr; 620 struct rte_mbuf *mbuf; 621 622 txq = (struct axgbe_tx_queue *)tx_queue; 623 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty); 624 625 if (unlikely(nb_desc_free <= txq->free_thresh)) { 626 axgbe_xmit_cleanup(txq); 627 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty); 628 if (unlikely(nb_desc_free == 0)) 629 return 0; 630 } 631 nb_pkts = RTE_MIN(nb_desc_free, nb_pkts); 632 while (nb_pkts--) { 633 mbuf = *tx_pkts++; 634 if (axgbe_xmit_hw(txq, mbuf)) 635 goto out; 636 nb_pkt_sent++; 637 } 638 out: 639 /* Sync read and write */ 640 rte_mb(); 641 idx = AXGBE_GET_DESC_IDX(txq, txq->cur); 642 tail_addr = low32_value(txq->ring_phys_addr + 643 idx * sizeof(struct axgbe_tx_desc)); 644 /* Update tail reg with next immediate address to kick Tx DMA channel*/ 645 AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr); 646 txq->pkts += nb_pkt_sent; 647 return nb_pkt_sent; 648 } 649 650 void axgbe_dev_clear_queues(struct rte_eth_dev *dev) 651 { 652 PMD_INIT_FUNC_TRACE(); 653 uint8_t i; 654 struct axgbe_rx_queue *rxq; 655 struct axgbe_tx_queue *txq; 656 657 for (i = 0; i < dev->data->nb_rx_queues; i++) { 658 rxq = dev->data->rx_queues[i]; 659 660 if (rxq) { 661 axgbe_rx_queue_release(rxq); 662 dev->data->rx_queues[i] = NULL; 663 } 664 } 665 666 for (i = 0; i < dev->data->nb_tx_queues; i++) { 667 txq = dev->data->tx_queues[i]; 668 669 if (txq) { 670 axgbe_tx_queue_release(txq); 671 dev->data->tx_queues[i] = NULL; 672 } 673 } 674 } 675