1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_rxtx.h" 8 #include "axgbe_phy.h" 9 10 #include <rte_time.h> 11 #include <rte_mempool.h> 12 #include <rte_mbuf.h> 13 #include <rte_vect.h> 14 15 static void 16 axgbe_rx_queue_release(struct axgbe_rx_queue *rx_queue) 17 { 18 uint16_t i; 19 struct rte_mbuf **sw_ring; 20 21 if (rx_queue) { 22 sw_ring = rx_queue->sw_ring; 23 if (sw_ring) { 24 for (i = 0; i < rx_queue->nb_desc; i++) { 25 rte_pktmbuf_free(sw_ring[i]); 26 } 27 rte_free(sw_ring); 28 } 29 rte_free(rx_queue); 30 } 31 } 32 33 void axgbe_dev_rx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx) 34 { 35 axgbe_rx_queue_release(dev->data->rx_queues[queue_idx]); 36 } 37 38 int axgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 39 uint16_t nb_desc, unsigned int socket_id, 40 const struct rte_eth_rxconf *rx_conf, 41 struct rte_mempool *mp) 42 { 43 PMD_INIT_FUNC_TRACE(); 44 uint32_t size; 45 const struct rte_memzone *dma; 46 struct axgbe_rx_queue *rxq; 47 uint32_t rx_desc = nb_desc; 48 struct axgbe_port *pdata = dev->data->dev_private; 49 50 /* 51 * validate Rx descriptors count 52 * should be power of 2 and less than h/w supported 53 */ 54 if ((!rte_is_power_of_2(rx_desc)) || 55 rx_desc > pdata->rx_desc_count) 56 return -EINVAL; 57 /* First allocate the rx queue data structure */ 58 rxq = rte_zmalloc_socket("ethdev RX queue", 59 sizeof(struct axgbe_rx_queue), 60 RTE_CACHE_LINE_SIZE, socket_id); 61 if (!rxq) { 62 PMD_INIT_LOG(ERR, "rte_zmalloc for rxq failed!"); 63 return -ENOMEM; 64 } 65 66 rxq->cur = 0; 67 rxq->dirty = 0; 68 rxq->pdata = pdata; 69 rxq->mb_pool = mp; 70 rxq->queue_id = queue_idx; 71 rxq->port_id = dev->data->port_id; 72 rxq->nb_desc = rx_desc; 73 rxq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + 74 (DMA_CH_INC * rxq->queue_id)); 75 rxq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)rxq->dma_regs + 76 DMA_CH_RDTR_LO); 77 if (dev->data->dev_conf.rxmode.offloads & RTE_ETH_RX_OFFLOAD_KEEP_CRC) 78 rxq->crc_len = RTE_ETHER_CRC_LEN; 79 else 80 rxq->crc_len = 0; 81 82 /* CRC strip in AXGBE supports per port not per queue */ 83 pdata->crc_strip_enable = (rxq->crc_len == 0) ? 1 : 0; 84 rxq->free_thresh = rx_conf->rx_free_thresh ? 85 rx_conf->rx_free_thresh : AXGBE_RX_FREE_THRESH; 86 if (rxq->free_thresh > rxq->nb_desc) 87 rxq->free_thresh = rxq->nb_desc >> 3; 88 89 /* Allocate RX ring hardware descriptors */ 90 size = rxq->nb_desc * sizeof(union axgbe_rx_desc); 91 dma = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx, size, 128, 92 socket_id); 93 if (!dma) { 94 PMD_DRV_LOG(ERR, "ring_dma_zone_reserve for rx_ring failed\n"); 95 axgbe_rx_queue_release(rxq); 96 return -ENOMEM; 97 } 98 rxq->ring_phys_addr = (uint64_t)dma->iova; 99 rxq->desc = (volatile union axgbe_rx_desc *)dma->addr; 100 memset((void *)rxq->desc, 0, size); 101 /* Allocate software ring */ 102 size = rxq->nb_desc * sizeof(struct rte_mbuf *); 103 rxq->sw_ring = rte_zmalloc_socket("sw_ring", size, 104 RTE_CACHE_LINE_SIZE, 105 socket_id); 106 if (!rxq->sw_ring) { 107 PMD_DRV_LOG(ERR, "rte_zmalloc for sw_ring failed\n"); 108 axgbe_rx_queue_release(rxq); 109 return -ENOMEM; 110 } 111 dev->data->rx_queues[queue_idx] = rxq; 112 if (!pdata->rx_queues) 113 pdata->rx_queues = dev->data->rx_queues; 114 115 return 0; 116 } 117 118 static void axgbe_prepare_rx_stop(struct axgbe_port *pdata, 119 unsigned int queue) 120 { 121 unsigned int rx_status; 122 unsigned long rx_timeout; 123 124 /* The Rx engine cannot be stopped if it is actively processing 125 * packets. Wait for the Rx queue to empty the Rx fifo. Don't 126 * wait forever though... 127 */ 128 rx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 129 rte_get_timer_hz()); 130 131 while (time_before(rte_get_timer_cycles(), rx_timeout)) { 132 rx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_RQDR); 133 if ((AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, PRXQ) == 0) && 134 (AXGMAC_GET_BITS(rx_status, MTL_Q_RQDR, RXQSTS) == 0)) 135 break; 136 137 rte_delay_us(900); 138 } 139 140 if (!time_before(rte_get_timer_cycles(), rx_timeout)) 141 PMD_DRV_LOG(ERR, 142 "timed out waiting for Rx queue %u to empty\n", 143 queue); 144 } 145 146 void axgbe_dev_disable_rx(struct rte_eth_dev *dev) 147 { 148 struct axgbe_rx_queue *rxq; 149 struct axgbe_port *pdata = dev->data->dev_private; 150 unsigned int i; 151 152 /* Disable MAC Rx */ 153 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0); 154 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0); 155 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0); 156 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0); 157 158 /* Prepare for Rx DMA channel stop */ 159 for (i = 0; i < dev->data->nb_rx_queues; i++) { 160 rxq = dev->data->rx_queues[i]; 161 axgbe_prepare_rx_stop(pdata, i); 162 } 163 /* Disable each Rx queue */ 164 AXGMAC_IOWRITE(pdata, MAC_RQC0R, 0); 165 for (i = 0; i < dev->data->nb_rx_queues; i++) { 166 rxq = dev->data->rx_queues[i]; 167 /* Disable Rx DMA channel */ 168 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 0); 169 } 170 } 171 172 void axgbe_dev_enable_rx(struct rte_eth_dev *dev) 173 { 174 struct axgbe_rx_queue *rxq; 175 struct axgbe_port *pdata = dev->data->dev_private; 176 unsigned int i; 177 unsigned int reg_val = 0; 178 179 for (i = 0; i < dev->data->nb_rx_queues; i++) { 180 rxq = dev->data->rx_queues[i]; 181 /* Enable Rx DMA channel */ 182 AXGMAC_DMA_IOWRITE_BITS(rxq, DMA_CH_RCR, SR, 1); 183 } 184 185 reg_val = 0; 186 for (i = 0; i < pdata->rx_q_count; i++) 187 reg_val |= (0x02 << (i << 1)); 188 AXGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val); 189 190 /* Enable MAC Rx */ 191 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1); 192 /* Frame is forwarded after stripping CRC to application*/ 193 if (pdata->crc_strip_enable) { 194 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1); 195 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1); 196 } 197 AXGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1); 198 } 199 200 /* Rx function one to one refresh */ 201 uint16_t 202 axgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, 203 uint16_t nb_pkts) 204 { 205 PMD_INIT_FUNC_TRACE(); 206 uint16_t nb_rx = 0; 207 struct axgbe_rx_queue *rxq = rx_queue; 208 volatile union axgbe_rx_desc *desc; 209 uint64_t old_dirty = rxq->dirty; 210 struct rte_mbuf *mbuf, *tmbuf; 211 unsigned int err, etlt; 212 uint32_t error_status; 213 uint16_t idx, pidx, pkt_len; 214 uint64_t offloads; 215 216 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 217 while (nb_rx < nb_pkts) { 218 if (unlikely(idx == rxq->nb_desc)) 219 idx = 0; 220 221 desc = &rxq->desc[idx]; 222 223 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 224 break; 225 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool); 226 if (unlikely(!tmbuf)) { 227 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u" 228 " queue_id = %u\n", 229 (unsigned int)rxq->port_id, 230 (unsigned int)rxq->queue_id); 231 rte_eth_devices[ 232 rxq->port_id].data->rx_mbuf_alloc_failed++; 233 rxq->rx_mbuf_alloc_failed++; 234 break; 235 } 236 pidx = idx + 1; 237 if (unlikely(pidx == rxq->nb_desc)) 238 pidx = 0; 239 240 rte_prefetch0(rxq->sw_ring[pidx]); 241 if ((pidx & 0x3) == 0) { 242 rte_prefetch0(&rxq->desc[pidx]); 243 rte_prefetch0(&rxq->sw_ring[pidx]); 244 } 245 246 mbuf = rxq->sw_ring[idx]; 247 /* Check for any errors and free mbuf*/ 248 err = AXGMAC_GET_BITS_LE(desc->write.desc3, 249 RX_NORMAL_DESC3, ES); 250 error_status = 0; 251 if (unlikely(err)) { 252 error_status = desc->write.desc3 & AXGBE_ERR_STATUS; 253 if ((error_status != AXGBE_L3_CSUM_ERR) && 254 (error_status != AXGBE_L4_CSUM_ERR)) { 255 rxq->errors++; 256 rte_pktmbuf_free(mbuf); 257 goto err_set; 258 } 259 } 260 if (rxq->pdata->rx_csum_enable) { 261 mbuf->ol_flags = 0; 262 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; 263 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; 264 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) { 265 mbuf->ol_flags &= ~RTE_MBUF_F_RX_IP_CKSUM_GOOD; 266 mbuf->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_BAD; 267 mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_GOOD; 268 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN; 269 } else if ( 270 unlikely(error_status == AXGBE_L4_CSUM_ERR)) { 271 mbuf->ol_flags &= ~RTE_MBUF_F_RX_L4_CKSUM_GOOD; 272 mbuf->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_BAD; 273 } 274 } 275 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *)); 276 /* Get the RSS hash */ 277 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) 278 mbuf->hash.rss = rte_le_to_cpu_32(desc->write.desc1); 279 etlt = AXGMAC_GET_BITS_LE(desc->write.desc3, 280 RX_NORMAL_DESC3, ETLT); 281 offloads = rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads; 282 if (!err || !etlt) { 283 if (etlt == RX_CVLAN_TAG_PRESENT) { 284 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN; 285 mbuf->vlan_tci = 286 AXGMAC_GET_BITS_LE(desc->write.desc0, 287 RX_NORMAL_DESC0, OVT); 288 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 289 mbuf->ol_flags |= RTE_MBUF_F_RX_VLAN_STRIPPED; 290 else 291 mbuf->ol_flags &= ~RTE_MBUF_F_RX_VLAN_STRIPPED; 292 } else { 293 mbuf->ol_flags &= 294 ~(RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED); 295 mbuf->vlan_tci = 0; 296 } 297 } 298 /* Indicate if a Context Descriptor is next */ 299 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, CDA)) 300 mbuf->ol_flags |= RTE_MBUF_F_RX_IEEE1588_PTP 301 | RTE_MBUF_F_RX_IEEE1588_TMST; 302 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, 303 PL) - rxq->crc_len; 304 /* Mbuf populate */ 305 mbuf->next = NULL; 306 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 307 mbuf->nb_segs = 1; 308 mbuf->port = rxq->port_id; 309 mbuf->pkt_len = pkt_len; 310 mbuf->data_len = pkt_len; 311 rxq->bytes += pkt_len; 312 rx_pkts[nb_rx++] = mbuf; 313 err_set: 314 rxq->cur++; 315 rxq->sw_ring[idx++] = tmbuf; 316 desc->read.baddr = 317 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf)); 318 memset((void *)(&desc->read.desc2), 0, 8); 319 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1); 320 rxq->dirty++; 321 } 322 rxq->pkts += nb_rx; 323 if (rxq->dirty != old_dirty) { 324 rte_wmb(); 325 idx = AXGBE_GET_DESC_IDX(rxq, rxq->dirty - 1); 326 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO, 327 low32_value(rxq->ring_phys_addr + 328 (idx * sizeof(union axgbe_rx_desc)))); 329 } 330 331 return nb_rx; 332 } 333 334 335 uint16_t eth_axgbe_recv_scattered_pkts(void *rx_queue, 336 struct rte_mbuf **rx_pkts, uint16_t nb_pkts) 337 { 338 PMD_INIT_FUNC_TRACE(); 339 uint16_t nb_rx = 0; 340 struct axgbe_rx_queue *rxq = rx_queue; 341 volatile union axgbe_rx_desc *desc; 342 343 struct rte_mbuf *first_seg = NULL; 344 struct rte_mbuf *mbuf, *tmbuf; 345 unsigned int err = 0, etlt; 346 uint32_t error_status = 0; 347 uint16_t idx, pidx, data_len = 0, pkt_len = 0; 348 uint64_t offloads; 349 350 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 351 while (nb_rx < nb_pkts) { 352 bool eop = 0; 353 next_desc: 354 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 355 356 desc = &rxq->desc[idx]; 357 358 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 359 break; 360 361 tmbuf = rte_mbuf_raw_alloc(rxq->mb_pool); 362 if (unlikely(!tmbuf)) { 363 PMD_DRV_LOG(ERR, "RX mbuf alloc failed port_id = %u" 364 " queue_id = %u\n", 365 (unsigned int)rxq->port_id, 366 (unsigned int)rxq->queue_id); 367 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed++; 368 break; 369 } 370 371 pidx = idx + 1; 372 if (unlikely(pidx == rxq->nb_desc)) 373 pidx = 0; 374 375 rte_prefetch0(rxq->sw_ring[pidx]); 376 if ((pidx & 0x3) == 0) { 377 rte_prefetch0(&rxq->desc[pidx]); 378 rte_prefetch0(&rxq->sw_ring[pidx]); 379 } 380 381 mbuf = rxq->sw_ring[idx]; 382 rte_prefetch1(rte_pktmbuf_mtod(mbuf, void *)); 383 384 if (!AXGMAC_GET_BITS_LE(desc->write.desc3, 385 RX_NORMAL_DESC3, LD)) { 386 eop = 0; 387 pkt_len = rxq->buf_size; 388 data_len = pkt_len; 389 } else { 390 eop = 1; 391 pkt_len = AXGMAC_GET_BITS_LE(desc->write.desc3, 392 RX_NORMAL_DESC3, PL) - rxq->crc_len; 393 data_len = pkt_len % rxq->buf_size; 394 /* Check for any errors and free mbuf*/ 395 err = AXGMAC_GET_BITS_LE(desc->write.desc3, 396 RX_NORMAL_DESC3, ES); 397 error_status = 0; 398 if (unlikely(err)) { 399 error_status = desc->write.desc3 & 400 AXGBE_ERR_STATUS; 401 if (error_status != AXGBE_L3_CSUM_ERR && 402 error_status != AXGBE_L4_CSUM_ERR) { 403 rxq->errors++; 404 rte_pktmbuf_free(mbuf); 405 rte_pktmbuf_free(first_seg); 406 first_seg = NULL; 407 eop = 0; 408 goto err_set; 409 } 410 } 411 412 } 413 /* Mbuf populate */ 414 mbuf->data_off = RTE_PKTMBUF_HEADROOM; 415 mbuf->data_len = data_len; 416 mbuf->pkt_len = data_len; 417 418 if (first_seg != NULL) { 419 if (rte_pktmbuf_chain(first_seg, mbuf) != 0) 420 rte_mempool_put(rxq->mb_pool, 421 first_seg); 422 } else { 423 first_seg = mbuf; 424 } 425 426 /* Get the RSS hash */ 427 if (AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, RSV)) 428 first_seg->hash.rss = 429 rte_le_to_cpu_32(desc->write.desc1); 430 etlt = AXGMAC_GET_BITS_LE(desc->write.desc3, 431 RX_NORMAL_DESC3, ETLT); 432 offloads = rxq->pdata->eth_dev->data->dev_conf.rxmode.offloads; 433 if (!err || !etlt) { 434 if (etlt == RX_CVLAN_TAG_PRESENT) { 435 first_seg->ol_flags |= RTE_MBUF_F_RX_VLAN; 436 first_seg->vlan_tci = 437 AXGMAC_GET_BITS_LE(desc->write.desc0, 438 RX_NORMAL_DESC0, OVT); 439 if (offloads & RTE_ETH_RX_OFFLOAD_VLAN_STRIP) 440 first_seg->ol_flags |= 441 RTE_MBUF_F_RX_VLAN_STRIPPED; 442 else 443 first_seg->ol_flags &= 444 ~RTE_MBUF_F_RX_VLAN_STRIPPED; 445 } else { 446 first_seg->ol_flags &= 447 ~(RTE_MBUF_F_RX_VLAN | 448 RTE_MBUF_F_RX_VLAN_STRIPPED); 449 first_seg->vlan_tci = 0; 450 } 451 } 452 453 err_set: 454 rxq->cur++; 455 rxq->sw_ring[idx] = tmbuf; 456 desc->read.baddr = 457 rte_cpu_to_le_64(rte_mbuf_data_iova_default(tmbuf)); 458 memset((void *)(&desc->read.desc2), 0, 8); 459 AXGMAC_SET_BITS_LE(desc->read.desc3, RX_NORMAL_DESC3, OWN, 1); 460 461 if (!eop) 462 goto next_desc; 463 464 first_seg->pkt_len = pkt_len; 465 rxq->bytes += pkt_len; 466 467 first_seg->port = rxq->port_id; 468 if (rxq->pdata->rx_csum_enable) { 469 first_seg->ol_flags = 0; 470 first_seg->ol_flags |= RTE_MBUF_F_RX_IP_CKSUM_GOOD; 471 first_seg->ol_flags |= RTE_MBUF_F_RX_L4_CKSUM_GOOD; 472 if (unlikely(error_status == AXGBE_L3_CSUM_ERR)) { 473 first_seg->ol_flags &= 474 ~RTE_MBUF_F_RX_IP_CKSUM_GOOD; 475 first_seg->ol_flags |= 476 RTE_MBUF_F_RX_IP_CKSUM_BAD; 477 first_seg->ol_flags &= 478 ~RTE_MBUF_F_RX_L4_CKSUM_GOOD; 479 first_seg->ol_flags |= 480 RTE_MBUF_F_RX_L4_CKSUM_UNKNOWN; 481 } else if (unlikely(error_status 482 == AXGBE_L4_CSUM_ERR)) { 483 first_seg->ol_flags &= 484 ~RTE_MBUF_F_RX_L4_CKSUM_GOOD; 485 first_seg->ol_flags |= 486 RTE_MBUF_F_RX_L4_CKSUM_BAD; 487 } 488 } 489 490 rx_pkts[nb_rx++] = first_seg; 491 492 /* Setup receipt context for a new packet.*/ 493 first_seg = NULL; 494 } 495 496 /* Save receive context.*/ 497 rxq->pkts += nb_rx; 498 499 if (rxq->dirty != rxq->cur) { 500 rte_wmb(); 501 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur - 1); 502 AXGMAC_DMA_IOWRITE(rxq, DMA_CH_RDTR_LO, 503 low32_value(rxq->ring_phys_addr + 504 (idx * sizeof(union axgbe_rx_desc)))); 505 rxq->dirty = rxq->cur; 506 } 507 return nb_rx; 508 } 509 510 /* Tx Apis */ 511 static void axgbe_tx_queue_release(struct axgbe_tx_queue *tx_queue) 512 { 513 uint16_t i; 514 struct rte_mbuf **sw_ring; 515 516 if (tx_queue) { 517 sw_ring = tx_queue->sw_ring; 518 if (sw_ring) { 519 for (i = 0; i < tx_queue->nb_desc; i++) { 520 rte_pktmbuf_free(sw_ring[i]); 521 } 522 rte_free(sw_ring); 523 } 524 rte_free(tx_queue); 525 } 526 } 527 528 void axgbe_dev_tx_queue_release(struct rte_eth_dev *dev, uint16_t queue_idx) 529 { 530 axgbe_tx_queue_release(dev->data->tx_queues[queue_idx]); 531 } 532 533 int axgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 534 uint16_t nb_desc, unsigned int socket_id, 535 const struct rte_eth_txconf *tx_conf) 536 { 537 PMD_INIT_FUNC_TRACE(); 538 uint32_t tx_desc; 539 struct axgbe_port *pdata; 540 struct axgbe_tx_queue *txq; 541 unsigned int tsize; 542 const struct rte_memzone *tz; 543 uint64_t offloads; 544 545 tx_desc = nb_desc; 546 pdata = dev->data->dev_private; 547 548 /* 549 * validate tx descriptors count 550 * should be power of 2 and less than h/w supported 551 */ 552 if ((!rte_is_power_of_2(tx_desc)) || 553 tx_desc > pdata->tx_desc_count || 554 tx_desc < AXGBE_MIN_RING_DESC) 555 return -EINVAL; 556 557 /* First allocate the tx queue data structure */ 558 txq = rte_zmalloc("ethdev TX queue", sizeof(struct axgbe_tx_queue), 559 RTE_CACHE_LINE_SIZE); 560 if (!txq) 561 return -ENOMEM; 562 txq->pdata = pdata; 563 offloads = tx_conf->offloads | 564 txq->pdata->eth_dev->data->dev_conf.txmode.offloads; 565 txq->nb_desc = tx_desc; 566 txq->free_thresh = tx_conf->tx_free_thresh ? 567 tx_conf->tx_free_thresh : AXGBE_TX_FREE_THRESH; 568 if (txq->free_thresh > txq->nb_desc) 569 txq->free_thresh = (txq->nb_desc >> 1); 570 txq->free_batch_cnt = txq->free_thresh; 571 572 /* In vector_tx path threshold should be multiple of queue_size*/ 573 if (txq->nb_desc % txq->free_thresh != 0) 574 txq->vector_disable = 1; 575 576 if (offloads != 0) 577 txq->vector_disable = 1; 578 579 /* Allocate TX ring hardware descriptors */ 580 tsize = txq->nb_desc * sizeof(struct axgbe_tx_desc); 581 tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx, 582 tsize, AXGBE_DESC_ALIGN, socket_id); 583 if (!tz) { 584 axgbe_tx_queue_release(txq); 585 return -ENOMEM; 586 } 587 memset(tz->addr, 0, tsize); 588 txq->ring_phys_addr = (uint64_t)tz->iova; 589 txq->desc = tz->addr; 590 txq->queue_id = queue_idx; 591 txq->port_id = dev->data->port_id; 592 txq->dma_regs = (void *)((uint8_t *)pdata->xgmac_regs + DMA_CH_BASE + 593 (DMA_CH_INC * txq->queue_id)); 594 txq->dma_tail_reg = (volatile uint32_t *)((uint8_t *)txq->dma_regs + 595 DMA_CH_TDTR_LO); 596 txq->cur = 0; 597 txq->dirty = 0; 598 txq->nb_desc_free = txq->nb_desc; 599 /* Allocate software ring */ 600 tsize = txq->nb_desc * sizeof(struct rte_mbuf *); 601 txq->sw_ring = rte_zmalloc("tx_sw_ring", tsize, 602 RTE_CACHE_LINE_SIZE); 603 if (!txq->sw_ring) { 604 axgbe_tx_queue_release(txq); 605 return -ENOMEM; 606 } 607 dev->data->tx_queues[queue_idx] = txq; 608 if (!pdata->tx_queues) 609 pdata->tx_queues = dev->data->tx_queues; 610 611 if (txq->vector_disable || 612 rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_128) 613 dev->tx_pkt_burst = &axgbe_xmit_pkts; 614 else 615 #ifdef RTE_ARCH_X86 616 dev->tx_pkt_burst = &axgbe_xmit_pkts_vec; 617 #else 618 dev->tx_pkt_burst = &axgbe_xmit_pkts; 619 #endif 620 621 return 0; 622 } 623 624 int axgbe_dev_fw_version_get(struct rte_eth_dev *eth_dev, 625 char *fw_version, size_t fw_size) 626 { 627 struct axgbe_port *pdata; 628 struct axgbe_hw_features *hw_feat; 629 int ret; 630 631 pdata = (struct axgbe_port *)eth_dev->data->dev_private; 632 hw_feat = &pdata->hw_feat; 633 634 ret = snprintf(fw_version, fw_size, "%d.%d.%d", 635 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER), 636 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID), 637 AXGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER)); 638 if (ret < 0) 639 return -EINVAL; 640 641 ret += 1; /* add the size of '\0' */ 642 if (fw_size < (size_t)ret) 643 return ret; 644 else 645 return 0; 646 } 647 648 static void axgbe_txq_prepare_tx_stop(struct axgbe_port *pdata, 649 unsigned int queue) 650 { 651 unsigned int tx_status; 652 unsigned long tx_timeout; 653 654 /* The Tx engine cannot be stopped if it is actively processing 655 * packets. Wait for the Tx queue to empty the Tx fifo. Don't 656 * wait forever though... 657 */ 658 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 659 rte_get_timer_hz()); 660 while (time_before(rte_get_timer_cycles(), tx_timeout)) { 661 tx_status = AXGMAC_MTL_IOREAD(pdata, queue, MTL_Q_TQDR); 662 if ((AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TRCSTS) != 1) && 663 (AXGMAC_GET_BITS(tx_status, MTL_Q_TQDR, TXQSTS) == 0)) 664 break; 665 666 rte_delay_us(900); 667 } 668 669 if (!time_before(rte_get_timer_cycles(), tx_timeout)) 670 PMD_DRV_LOG(ERR, 671 "timed out waiting for Tx queue %u to empty\n", 672 queue); 673 } 674 675 static void axgbe_prepare_tx_stop(struct axgbe_port *pdata, 676 unsigned int queue) 677 { 678 unsigned int tx_dsr, tx_pos, tx_qidx; 679 unsigned int tx_status; 680 unsigned long tx_timeout; 681 682 if (AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) > 0x20) 683 return axgbe_txq_prepare_tx_stop(pdata, queue); 684 685 /* Calculate the status register to read and the position within */ 686 if (queue < DMA_DSRX_FIRST_QUEUE) { 687 tx_dsr = DMA_DSR0; 688 tx_pos = (queue * DMA_DSR_Q_WIDTH) + DMA_DSR0_TPS_START; 689 } else { 690 tx_qidx = queue - DMA_DSRX_FIRST_QUEUE; 691 692 tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC); 693 tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) + 694 DMA_DSRX_TPS_START; 695 } 696 697 /* The Tx engine cannot be stopped if it is actively processing 698 * descriptors. Wait for the Tx engine to enter the stopped or 699 * suspended state. Don't wait forever though... 700 */ 701 tx_timeout = rte_get_timer_cycles() + (AXGBE_DMA_STOP_TIMEOUT * 702 rte_get_timer_hz()); 703 while (time_before(rte_get_timer_cycles(), tx_timeout)) { 704 tx_status = AXGMAC_IOREAD(pdata, tx_dsr); 705 tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH); 706 if ((tx_status == DMA_TPS_STOPPED) || 707 (tx_status == DMA_TPS_SUSPENDED)) 708 break; 709 710 rte_delay_us(900); 711 } 712 713 if (!time_before(rte_get_timer_cycles(), tx_timeout)) 714 PMD_DRV_LOG(ERR, 715 "timed out waiting for Tx DMA channel %u to stop\n", 716 queue); 717 } 718 719 void axgbe_dev_disable_tx(struct rte_eth_dev *dev) 720 { 721 struct axgbe_tx_queue *txq; 722 struct axgbe_port *pdata = dev->data->dev_private; 723 unsigned int i; 724 725 /* Prepare for stopping DMA channel */ 726 for (i = 0; i < pdata->tx_q_count; i++) { 727 txq = dev->data->tx_queues[i]; 728 axgbe_prepare_tx_stop(pdata, i); 729 } 730 /* Disable MAC Tx */ 731 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0); 732 /* Disable each Tx queue*/ 733 for (i = 0; i < pdata->tx_q_count; i++) 734 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 735 0); 736 /* Disable each Tx DMA channel */ 737 for (i = 0; i < dev->data->nb_tx_queues; i++) { 738 txq = dev->data->tx_queues[i]; 739 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 0); 740 } 741 } 742 743 void axgbe_dev_enable_tx(struct rte_eth_dev *dev) 744 { 745 struct axgbe_tx_queue *txq; 746 struct axgbe_port *pdata = dev->data->dev_private; 747 unsigned int i; 748 749 for (i = 0; i < dev->data->nb_tx_queues; i++) { 750 txq = dev->data->tx_queues[i]; 751 /* Enable Tx DMA channel */ 752 AXGMAC_DMA_IOWRITE_BITS(txq, DMA_CH_TCR, ST, 1); 753 } 754 /* Enable Tx queue*/ 755 for (i = 0; i < pdata->tx_q_count; i++) 756 AXGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 757 MTL_Q_ENABLED); 758 /* Enable MAC Tx */ 759 AXGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1); 760 } 761 762 /* Free Tx conformed mbufs */ 763 static void axgbe_xmit_cleanup(struct axgbe_tx_queue *txq) 764 { 765 volatile struct axgbe_tx_desc *desc; 766 uint16_t idx; 767 768 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty); 769 while (txq->cur != txq->dirty) { 770 if (unlikely(idx == txq->nb_desc)) 771 idx = 0; 772 desc = &txq->desc[idx]; 773 /* Check for ownership */ 774 if (AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN)) 775 return; 776 memset((void *)&desc->desc2, 0, 8); 777 /* Free mbuf */ 778 rte_pktmbuf_free(txq->sw_ring[idx]); 779 txq->sw_ring[idx++] = NULL; 780 txq->dirty++; 781 } 782 } 783 784 /* Tx Descriptor formation 785 * Considering each mbuf requires one desc 786 * mbuf is linear 787 */ 788 static int axgbe_xmit_hw(struct axgbe_tx_queue *txq, 789 struct rte_mbuf *mbuf) 790 { 791 volatile struct axgbe_tx_desc *desc; 792 uint16_t idx; 793 uint64_t mask; 794 795 idx = AXGBE_GET_DESC_IDX(txq, txq->cur); 796 desc = &txq->desc[idx]; 797 798 /* Update buffer address and length */ 799 desc->baddr = rte_mbuf_data_iova(mbuf); 800 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, HL_B1L, 801 mbuf->pkt_len); 802 /* Total msg length to transmit */ 803 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FL, 804 mbuf->pkt_len); 805 /* Timestamp enablement check */ 806 if (mbuf->ol_flags & RTE_MBUF_F_TX_IEEE1588_TMST) 807 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, TTSE, 1); 808 rte_wmb(); 809 /* Mark it as First and Last Descriptor */ 810 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, FD, 1); 811 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, LD, 1); 812 /* Mark it as a NORMAL descriptor */ 813 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CTXT, 0); 814 /* configure h/w Offload */ 815 mask = mbuf->ol_flags & RTE_MBUF_F_TX_L4_MASK; 816 if (mask == RTE_MBUF_F_TX_TCP_CKSUM || mask == RTE_MBUF_F_TX_UDP_CKSUM) 817 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x3); 818 else if (mbuf->ol_flags & RTE_MBUF_F_TX_IP_CKSUM) 819 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, CIC, 0x1); 820 rte_wmb(); 821 822 if (mbuf->ol_flags & (RTE_MBUF_F_TX_VLAN | RTE_MBUF_F_TX_QINQ)) { 823 /* Mark it as a CONTEXT descriptor */ 824 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3, 825 CTXT, 1); 826 /* Set the VLAN tag */ 827 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3, 828 VT, mbuf->vlan_tci); 829 /* Indicate this descriptor contains the VLAN tag */ 830 AXGMAC_SET_BITS_LE(desc->desc3, TX_CONTEXT_DESC3, 831 VLTV, 1); 832 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 833 TX_NORMAL_DESC2_VLAN_INSERT); 834 } else { 835 AXGMAC_SET_BITS_LE(desc->desc2, TX_NORMAL_DESC2, VTIR, 0x0); 836 } 837 rte_wmb(); 838 839 /* Set OWN bit */ 840 AXGMAC_SET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN, 1); 841 rte_wmb(); 842 843 844 /* Save mbuf */ 845 txq->sw_ring[idx] = mbuf; 846 /* Update current index*/ 847 txq->cur++; 848 /* Update stats */ 849 txq->bytes += mbuf->pkt_len; 850 851 return 0; 852 } 853 854 /* Eal supported tx wrapper*/ 855 uint16_t 856 axgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, 857 uint16_t nb_pkts) 858 { 859 PMD_INIT_FUNC_TRACE(); 860 861 if (unlikely(nb_pkts == 0)) 862 return nb_pkts; 863 864 struct axgbe_tx_queue *txq; 865 uint16_t nb_desc_free; 866 uint16_t nb_pkt_sent = 0; 867 uint16_t idx; 868 uint32_t tail_addr; 869 struct rte_mbuf *mbuf; 870 871 txq = (struct axgbe_tx_queue *)tx_queue; 872 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty); 873 874 if (unlikely(nb_desc_free <= txq->free_thresh)) { 875 axgbe_xmit_cleanup(txq); 876 nb_desc_free = txq->nb_desc - (txq->cur - txq->dirty); 877 if (unlikely(nb_desc_free == 0)) 878 return 0; 879 } 880 nb_pkts = RTE_MIN(nb_desc_free, nb_pkts); 881 while (nb_pkts--) { 882 mbuf = *tx_pkts++; 883 if (axgbe_xmit_hw(txq, mbuf)) 884 goto out; 885 nb_pkt_sent++; 886 } 887 out: 888 /* Sync read and write */ 889 rte_mb(); 890 idx = AXGBE_GET_DESC_IDX(txq, txq->cur); 891 tail_addr = low32_value(txq->ring_phys_addr + 892 idx * sizeof(struct axgbe_tx_desc)); 893 /* Update tail reg with next immediate address to kick Tx DMA channel*/ 894 AXGMAC_DMA_IOWRITE(txq, DMA_CH_TDTR_LO, tail_addr); 895 txq->pkts += nb_pkt_sent; 896 return nb_pkt_sent; 897 } 898 899 void axgbe_dev_clear_queues(struct rte_eth_dev *dev) 900 { 901 PMD_INIT_FUNC_TRACE(); 902 uint8_t i; 903 struct axgbe_rx_queue *rxq; 904 struct axgbe_tx_queue *txq; 905 906 for (i = 0; i < dev->data->nb_rx_queues; i++) { 907 rxq = dev->data->rx_queues[i]; 908 909 if (rxq) { 910 axgbe_rx_queue_release(rxq); 911 dev->data->rx_queues[i] = NULL; 912 } 913 } 914 915 for (i = 0; i < dev->data->nb_tx_queues; i++) { 916 txq = dev->data->tx_queues[i]; 917 918 if (txq) { 919 axgbe_tx_queue_release(txq); 920 dev->data->tx_queues[i] = NULL; 921 } 922 } 923 } 924 925 int 926 axgbe_dev_rx_descriptor_status(void *rx_queue, uint16_t offset) 927 { 928 struct axgbe_rx_queue *rxq = rx_queue; 929 volatile union axgbe_rx_desc *desc; 930 uint16_t idx; 931 932 933 if (unlikely(offset >= rxq->nb_desc)) 934 return -EINVAL; 935 936 if (offset >= rxq->nb_desc - rxq->dirty) 937 return RTE_ETH_RX_DESC_UNAVAIL; 938 939 idx = AXGBE_GET_DESC_IDX(rxq, rxq->cur); 940 desc = &rxq->desc[idx + offset]; 941 942 if (!AXGMAC_GET_BITS_LE(desc->write.desc3, RX_NORMAL_DESC3, OWN)) 943 return RTE_ETH_RX_DESC_DONE; 944 945 return RTE_ETH_RX_DESC_AVAIL; 946 } 947 948 int 949 axgbe_dev_tx_descriptor_status(void *tx_queue, uint16_t offset) 950 { 951 struct axgbe_tx_queue *txq = tx_queue; 952 volatile struct axgbe_tx_desc *desc; 953 uint16_t idx; 954 955 956 if (unlikely(offset >= txq->nb_desc)) 957 return -EINVAL; 958 959 if (offset >= txq->nb_desc - txq->dirty) 960 return RTE_ETH_TX_DESC_UNAVAIL; 961 962 idx = AXGBE_GET_DESC_IDX(txq, txq->dirty + txq->free_batch_cnt - 1); 963 desc = &txq->desc[idx + offset]; 964 965 if (!AXGMAC_GET_BITS_LE(desc->desc3, TX_NORMAL_DESC3, OWN)) 966 return RTE_ETH_TX_DESC_DONE; 967 968 return RTE_ETH_TX_DESC_FULL; 969 } 970