1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(1) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(2) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(3) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(4) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 50 AXGBE_PORT_MODE_MAX, 51 }; 52 53 enum axgbe_conn_type { 54 AXGBE_CONN_TYPE_NONE = 0, 55 AXGBE_CONN_TYPE_SFP, 56 AXGBE_CONN_TYPE_MDIO, 57 AXGBE_CONN_TYPE_RSVD1, 58 AXGBE_CONN_TYPE_BACKPLANE, 59 AXGBE_CONN_TYPE_MAX, 60 }; 61 62 /* SFP/SFP+ related definitions */ 63 enum axgbe_sfp_comm { 64 AXGBE_SFP_COMM_DIRECT = 0, 65 AXGBE_SFP_COMM_PCA9545, 66 }; 67 68 enum axgbe_sfp_cable { 69 AXGBE_SFP_CABLE_UNKNOWN = 0, 70 AXGBE_SFP_CABLE_ACTIVE, 71 AXGBE_SFP_CABLE_PASSIVE, 72 }; 73 74 enum axgbe_sfp_base { 75 AXGBE_SFP_BASE_UNKNOWN = 0, 76 AXGBE_SFP_BASE_1000_T, 77 AXGBE_SFP_BASE_1000_SX, 78 AXGBE_SFP_BASE_1000_LX, 79 AXGBE_SFP_BASE_1000_CX, 80 AXGBE_SFP_BASE_10000_SR, 81 AXGBE_SFP_BASE_10000_LR, 82 AXGBE_SFP_BASE_10000_LRM, 83 AXGBE_SFP_BASE_10000_ER, 84 AXGBE_SFP_BASE_10000_CR, 85 }; 86 87 enum axgbe_sfp_speed { 88 AXGBE_SFP_SPEED_UNKNOWN = 0, 89 AXGBE_SFP_SPEED_100_1000, 90 AXGBE_SFP_SPEED_1000, 91 AXGBE_SFP_SPEED_10000, 92 }; 93 94 /* SFP Serial ID Base ID values relative to an offset of 0 */ 95 #define AXGBE_SFP_BASE_ID 0 96 #define AXGBE_SFP_ID_SFP 0x03 97 98 #define AXGBE_SFP_BASE_EXT_ID 1 99 #define AXGBE_SFP_EXT_ID_SFP 0x04 100 101 #define AXGBE_SFP_BASE_10GBE_CC 3 102 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 103 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 104 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 105 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 106 107 #define AXGBE_SFP_BASE_1GBE_CC 6 108 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 109 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 110 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 111 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 112 113 #define AXGBE_SFP_BASE_CABLE 8 114 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 115 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 116 117 #define AXGBE_SFP_BASE_BR 12 118 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 119 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 120 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 121 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 122 123 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 124 125 #define AXGBE_SFP_BASE_VENDOR_NAME 20 126 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 127 #define AXGBE_SFP_BASE_VENDOR_PN 40 128 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 129 #define AXGBE_SFP_BASE_VENDOR_REV 56 130 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 131 132 #define AXGBE_SFP_BASE_CC 63 133 134 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 135 #define AXGBE_SFP_BASE_VENDOR_SN 4 136 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 137 138 #define AXGBE_SFP_EXTD_DIAG 28 139 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 140 141 #define AXGBE_SFP_EXTD_SFF_8472 30 142 143 #define AXGBE_SFP_EXTD_CC 31 144 145 struct axgbe_sfp_eeprom { 146 u8 base[64]; 147 u8 extd[32]; 148 u8 vendor[32]; 149 }; 150 151 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 152 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 153 154 struct axgbe_sfp_ascii { 155 union { 156 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 157 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 158 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 159 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 160 } u; 161 }; 162 163 /* MDIO PHY reset types */ 164 enum axgbe_mdio_reset { 165 AXGBE_MDIO_RESET_NONE = 0, 166 AXGBE_MDIO_RESET_I2C_GPIO, 167 AXGBE_MDIO_RESET_INT_GPIO, 168 AXGBE_MDIO_RESET_MAX, 169 }; 170 171 /* Re-driver related definitions */ 172 enum axgbe_phy_redrv_if { 173 AXGBE_PHY_REDRV_IF_MDIO = 0, 174 AXGBE_PHY_REDRV_IF_I2C, 175 AXGBE_PHY_REDRV_IF_MAX, 176 }; 177 178 enum axgbe_phy_redrv_model { 179 AXGBE_PHY_REDRV_MODEL_4223 = 0, 180 AXGBE_PHY_REDRV_MODEL_4227, 181 AXGBE_PHY_REDRV_MODEL_MAX, 182 }; 183 184 enum axgbe_phy_redrv_mode { 185 AXGBE_PHY_REDRV_MODE_CX = 5, 186 AXGBE_PHY_REDRV_MODE_SR = 9, 187 }; 188 189 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 190 191 /* PHY related configuration information */ 192 struct axgbe_phy_data { 193 enum axgbe_port_mode port_mode; 194 195 unsigned int port_id; 196 197 unsigned int port_speeds; 198 199 enum axgbe_conn_type conn_type; 200 201 enum axgbe_mode cur_mode; 202 enum axgbe_mode start_mode; 203 204 unsigned int rrc_count; 205 206 unsigned int mdio_addr; 207 208 unsigned int comm_owned; 209 210 /* SFP Support */ 211 enum axgbe_sfp_comm sfp_comm; 212 unsigned int sfp_mux_address; 213 unsigned int sfp_mux_channel; 214 215 unsigned int sfp_gpio_address; 216 unsigned int sfp_gpio_mask; 217 unsigned int sfp_gpio_rx_los; 218 unsigned int sfp_gpio_tx_fault; 219 unsigned int sfp_gpio_mod_absent; 220 unsigned int sfp_gpio_rate_select; 221 222 unsigned int sfp_rx_los; 223 unsigned int sfp_tx_fault; 224 unsigned int sfp_mod_absent; 225 unsigned int sfp_diags; 226 unsigned int sfp_changed; 227 unsigned int sfp_phy_avail; 228 unsigned int sfp_cable_len; 229 enum axgbe_sfp_base sfp_base; 230 enum axgbe_sfp_cable sfp_cable; 231 enum axgbe_sfp_speed sfp_speed; 232 struct axgbe_sfp_eeprom sfp_eeprom; 233 234 /* External PHY support */ 235 enum axgbe_mdio_mode phydev_mode; 236 enum axgbe_mdio_reset mdio_reset; 237 unsigned int mdio_reset_addr; 238 unsigned int mdio_reset_gpio; 239 240 /* Re-driver support */ 241 unsigned int redrv; 242 unsigned int redrv_if; 243 unsigned int redrv_addr; 244 unsigned int redrv_lane; 245 unsigned int redrv_model; 246 247 /* KR AN support */ 248 unsigned int phy_cdr_notrack; 249 unsigned int phy_cdr_delay; 250 }; 251 252 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 253 254 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 255 struct axgbe_i2c_op *i2c_op) 256 { 257 struct axgbe_phy_data *phy_data = pdata->phy_data; 258 259 /* Be sure we own the bus */ 260 if (!phy_data->comm_owned) 261 return -EIO; 262 263 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 264 } 265 266 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 267 unsigned int val) 268 { 269 struct axgbe_phy_data *phy_data = pdata->phy_data; 270 struct axgbe_i2c_op i2c_op; 271 uint16_t *redrv_val; 272 u8 redrv_data[5], csum; 273 unsigned int i, retry; 274 int ret; 275 276 /* High byte of register contains read/write indicator */ 277 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 278 redrv_data[1] = reg & 0xff; 279 redrv_val = (uint16_t *)&redrv_data[2]; 280 *redrv_val = rte_cpu_to_be_16(val); 281 282 /* Calculate 1 byte checksum */ 283 csum = 0; 284 for (i = 0; i < 4; i++) { 285 csum += redrv_data[i]; 286 if (redrv_data[i] > csum) 287 csum++; 288 } 289 redrv_data[4] = ~csum; 290 291 retry = 1; 292 again1: 293 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 294 i2c_op.target = phy_data->redrv_addr; 295 i2c_op.len = sizeof(redrv_data); 296 i2c_op.buf = redrv_data; 297 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 298 if (ret) { 299 if ((ret == -EAGAIN) && retry--) 300 goto again1; 301 302 return ret; 303 } 304 305 retry = 1; 306 again2: 307 i2c_op.cmd = AXGBE_I2C_CMD_READ; 308 i2c_op.target = phy_data->redrv_addr; 309 i2c_op.len = 1; 310 i2c_op.buf = redrv_data; 311 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 312 if (ret) { 313 if ((ret == -EAGAIN) && retry--) 314 goto again2; 315 316 return ret; 317 } 318 319 if (redrv_data[0] != 0xff) { 320 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 321 ret = -EIO; 322 } 323 324 return ret; 325 } 326 327 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 328 void *reg, unsigned int reg_len, 329 void *val, unsigned int val_len) 330 { 331 struct axgbe_i2c_op i2c_op; 332 int retry, ret; 333 334 retry = 1; 335 again1: 336 /* Set the specified register to read */ 337 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 338 i2c_op.target = target; 339 i2c_op.len = reg_len; 340 i2c_op.buf = reg; 341 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 342 if (ret) { 343 if ((ret == -EAGAIN) && retry--) 344 goto again1; 345 346 return ret; 347 } 348 349 retry = 1; 350 again2: 351 /* Read the specified register */ 352 i2c_op.cmd = AXGBE_I2C_CMD_READ; 353 i2c_op.target = target; 354 i2c_op.len = val_len; 355 i2c_op.buf = val; 356 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 357 if ((ret == -EAGAIN) && retry--) 358 goto again2; 359 360 return ret; 361 } 362 363 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 364 { 365 struct axgbe_phy_data *phy_data = pdata->phy_data; 366 struct axgbe_i2c_op i2c_op; 367 uint8_t mux_channel; 368 369 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 370 return 0; 371 372 /* Select no mux channels */ 373 mux_channel = 0; 374 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 375 i2c_op.target = phy_data->sfp_mux_address; 376 i2c_op.len = sizeof(mux_channel); 377 i2c_op.buf = &mux_channel; 378 379 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 380 } 381 382 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 383 { 384 struct axgbe_phy_data *phy_data = pdata->phy_data; 385 struct axgbe_i2c_op i2c_op; 386 u8 mux_channel; 387 388 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 389 return 0; 390 391 /* Select desired mux channel */ 392 mux_channel = 1 << phy_data->sfp_mux_channel; 393 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 394 i2c_op.target = phy_data->sfp_mux_address; 395 i2c_op.len = sizeof(mux_channel); 396 i2c_op.buf = &mux_channel; 397 398 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 399 } 400 401 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 402 { 403 struct axgbe_phy_data *phy_data = pdata->phy_data; 404 405 phy_data->comm_owned = 0; 406 407 pthread_mutex_unlock(&pdata->phy_mutex); 408 } 409 410 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 411 { 412 struct axgbe_phy_data *phy_data = pdata->phy_data; 413 uint64_t timeout; 414 unsigned int mutex_id; 415 416 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 417 * the driver needs to take the software mutex and then the hardware 418 * mutexes before being able to use the busses. 419 */ 420 pthread_mutex_lock(&pdata->phy_mutex); 421 422 if (phy_data->comm_owned) 423 return 0; 424 425 /* Clear the mutexes */ 426 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 427 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 428 429 /* Mutex formats are the same for I2C and MDIO/GPIO */ 430 mutex_id = 0; 431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 432 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 433 434 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 435 while (time_before(rte_get_timer_cycles(), timeout)) { 436 /* Must be all zeroes in order to obtain the mutex */ 437 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 438 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 439 rte_delay_us(100); 440 continue; 441 } 442 443 /* Obtain the mutex */ 444 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 445 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 446 447 phy_data->comm_owned = 1; 448 return 0; 449 } 450 451 pthread_mutex_unlock(&pdata->phy_mutex); 452 453 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 454 455 return -ETIMEDOUT; 456 } 457 458 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 459 { 460 struct axgbe_phy_data *phy_data = pdata->phy_data; 461 462 if (phy_data->sfp_mod_absent) { 463 pdata->phy.speed = SPEED_UNKNOWN; 464 pdata->phy.duplex = DUPLEX_UNKNOWN; 465 pdata->phy.autoneg = AUTONEG_ENABLE; 466 pdata->phy.advertising = pdata->phy.supported; 467 } 468 469 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 470 pdata->phy.advertising &= ~ADVERTISED_TP; 471 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 472 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 473 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 474 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 475 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 476 477 switch (phy_data->sfp_base) { 478 case AXGBE_SFP_BASE_1000_T: 479 case AXGBE_SFP_BASE_1000_SX: 480 case AXGBE_SFP_BASE_1000_LX: 481 case AXGBE_SFP_BASE_1000_CX: 482 pdata->phy.speed = SPEED_UNKNOWN; 483 pdata->phy.duplex = DUPLEX_UNKNOWN; 484 pdata->phy.autoneg = AUTONEG_ENABLE; 485 pdata->phy.advertising |= ADVERTISED_Autoneg; 486 break; 487 case AXGBE_SFP_BASE_10000_SR: 488 case AXGBE_SFP_BASE_10000_LR: 489 case AXGBE_SFP_BASE_10000_LRM: 490 case AXGBE_SFP_BASE_10000_ER: 491 case AXGBE_SFP_BASE_10000_CR: 492 default: 493 pdata->phy.speed = SPEED_10000; 494 pdata->phy.duplex = DUPLEX_FULL; 495 pdata->phy.autoneg = AUTONEG_DISABLE; 496 break; 497 } 498 499 switch (phy_data->sfp_base) { 500 case AXGBE_SFP_BASE_1000_T: 501 case AXGBE_SFP_BASE_1000_CX: 502 case AXGBE_SFP_BASE_10000_CR: 503 pdata->phy.advertising |= ADVERTISED_TP; 504 break; 505 default: 506 pdata->phy.advertising |= ADVERTISED_FIBRE; 507 } 508 509 switch (phy_data->sfp_speed) { 510 case AXGBE_SFP_SPEED_100_1000: 511 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 512 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 513 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 514 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 515 break; 516 case AXGBE_SFP_SPEED_1000: 517 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 518 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 519 break; 520 case AXGBE_SFP_SPEED_10000: 521 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 522 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 523 break; 524 default: 525 /* Choose the fastest supported speed */ 526 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 527 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 528 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 529 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 530 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 531 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 532 } 533 } 534 535 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 536 enum axgbe_sfp_speed sfp_speed) 537 { 538 u8 *sfp_base, min, max; 539 540 sfp_base = sfp_eeprom->base; 541 542 switch (sfp_speed) { 543 case AXGBE_SFP_SPEED_1000: 544 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 545 max = AXGBE_SFP_BASE_BR_1GBE_MAX; 546 break; 547 case AXGBE_SFP_SPEED_10000: 548 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 549 max = AXGBE_SFP_BASE_BR_10GBE_MAX; 550 break; 551 default: 552 return false; 553 } 554 555 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) && 556 (sfp_base[AXGBE_SFP_BASE_BR] <= max)); 557 } 558 559 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 560 { 561 struct axgbe_phy_data *phy_data = pdata->phy_data; 562 563 if (!phy_data->sfp_changed) 564 return; 565 566 phy_data->sfp_phy_avail = 0; 567 568 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 569 return; 570 } 571 572 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 573 { 574 struct axgbe_phy_data *phy_data = pdata->phy_data; 575 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 576 577 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 578 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 579 return false; 580 581 /* Reset PHY - wait for self-clearing reset bit to clear */ 582 pdata->phy_if.phy_impl.reset(pdata); 583 584 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 585 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 586 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 587 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 588 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 589 return true; 590 } 591 592 return false; 593 } 594 595 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 596 { 597 if (axgbe_phy_belfuse_parse_quirks(pdata)) 598 return true; 599 600 return false; 601 } 602 603 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 604 { 605 struct axgbe_phy_data *phy_data = pdata->phy_data; 606 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 607 uint8_t *sfp_base; 608 609 sfp_base = sfp_eeprom->base; 610 611 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 612 return; 613 614 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 615 return; 616 617 axgbe_phy_sfp_parse_quirks(pdata); 618 619 /* Assume ACTIVE cable unless told it is PASSIVE */ 620 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 621 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 622 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 623 } else { 624 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 625 } 626 627 /* Determine the type of SFP */ 628 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 629 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 630 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 631 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 632 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 633 AXGBE_SFP_BASE_10GBE_CC_LRM) 634 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 635 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 636 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 641 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 642 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 643 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 644 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 645 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) && 646 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 647 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 648 649 switch (phy_data->sfp_base) { 650 case AXGBE_SFP_BASE_1000_T: 651 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 652 break; 653 case AXGBE_SFP_BASE_1000_SX: 654 case AXGBE_SFP_BASE_1000_LX: 655 case AXGBE_SFP_BASE_1000_CX: 656 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 657 break; 658 case AXGBE_SFP_BASE_10000_SR: 659 case AXGBE_SFP_BASE_10000_LR: 660 case AXGBE_SFP_BASE_10000_LRM: 661 case AXGBE_SFP_BASE_10000_ER: 662 case AXGBE_SFP_BASE_10000_CR: 663 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 664 break; 665 default: 666 break; 667 } 668 } 669 670 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 671 unsigned int len) 672 { 673 uint8_t cc; 674 675 for (cc = 0; len; buf++, len--) 676 cc += *buf; 677 678 return (cc == cc_in) ? true : false; 679 } 680 681 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 682 { 683 struct axgbe_phy_data *phy_data = pdata->phy_data; 684 struct axgbe_sfp_eeprom sfp_eeprom; 685 uint8_t eeprom_addr; 686 int ret; 687 688 ret = axgbe_phy_sfp_get_mux(pdata); 689 if (ret) { 690 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 691 return ret; 692 } 693 694 /* Read the SFP serial ID eeprom */ 695 eeprom_addr = 0; 696 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 697 &eeprom_addr, sizeof(eeprom_addr), 698 &sfp_eeprom, sizeof(sfp_eeprom)); 699 if (ret) { 700 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 701 goto put; 702 } 703 704 /* Validate the contents read */ 705 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 706 sfp_eeprom.base, 707 sizeof(sfp_eeprom.base) - 1)) { 708 ret = -EINVAL; 709 goto put; 710 } 711 712 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 713 sfp_eeprom.extd, 714 sizeof(sfp_eeprom.extd) - 1)) { 715 ret = -EINVAL; 716 goto put; 717 } 718 719 /* Check for an added or changed SFP */ 720 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 721 phy_data->sfp_changed = 1; 722 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 723 724 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) { 725 uint8_t diag_type; 726 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG]; 727 728 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 729 phy_data->sfp_diags = 1; 730 } 731 } else { 732 phy_data->sfp_changed = 0; 733 } 734 735 put: 736 axgbe_phy_sfp_put_mux(pdata); 737 738 return ret; 739 } 740 741 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 742 { 743 struct axgbe_phy_data *phy_data = pdata->phy_data; 744 unsigned int gpio_input; 745 u8 gpio_reg, gpio_ports[2]; 746 int ret; 747 748 /* Read the input port registers */ 749 gpio_reg = 0; 750 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 751 &gpio_reg, sizeof(gpio_reg), 752 gpio_ports, sizeof(gpio_ports)); 753 if (ret) { 754 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 755 return; 756 } 757 758 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 759 760 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 761 /* No GPIO, just assume the module is present for now */ 762 phy_data->sfp_mod_absent = 0; 763 } else { 764 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 765 phy_data->sfp_mod_absent = 0; 766 } 767 768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 769 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 770 phy_data->sfp_rx_los = 1; 771 772 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 773 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 774 phy_data->sfp_tx_fault = 1; 775 } 776 777 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 778 { 779 struct axgbe_phy_data *phy_data = pdata->phy_data; 780 781 phy_data->sfp_mod_absent = 1; 782 phy_data->sfp_phy_avail = 0; 783 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 784 } 785 786 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 787 { 788 phy_data->sfp_rx_los = 0; 789 phy_data->sfp_tx_fault = 0; 790 phy_data->sfp_mod_absent = 1; 791 phy_data->sfp_diags = 0; 792 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 793 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 794 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 795 } 796 797 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base) 798 { 799 switch (sfp_base) { 800 case AXGBE_SFP_BASE_1000_T: 801 return "1G_T"; 802 case AXGBE_SFP_BASE_1000_SX: 803 return "1G_SX"; 804 case AXGBE_SFP_BASE_1000_LX: 805 return "1G_LX"; 806 case AXGBE_SFP_BASE_1000_CX: 807 return "1G_CX"; 808 case AXGBE_SFP_BASE_10000_SR: 809 return "10G_SR"; 810 case AXGBE_SFP_BASE_10000_LR: 811 return "10G_LR"; 812 case AXGBE_SFP_BASE_10000_LRM: 813 return "10G_LRM"; 814 case AXGBE_SFP_BASE_10000_ER: 815 return "10G_ER"; 816 case AXGBE_SFP_BASE_10000_CR: 817 return "10G_CR"; 818 default: 819 return "Unknown"; 820 } 821 } 822 823 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 824 { 825 struct axgbe_phy_data *phy_data = pdata->phy_data; 826 int ret; 827 828 /* Reset the SFP signals and info */ 829 axgbe_phy_sfp_reset(phy_data); 830 831 ret = axgbe_phy_get_comm_ownership(pdata); 832 if (ret) 833 return; 834 835 /* Read the SFP signals and check for module presence */ 836 axgbe_phy_sfp_signals(pdata); 837 if (phy_data->sfp_mod_absent) { 838 axgbe_phy_sfp_mod_absent(pdata); 839 goto put; 840 } 841 842 ret = axgbe_phy_sfp_read_eeprom(pdata); 843 if (ret) { 844 /* Treat any error as if there isn't an SFP plugged in */ 845 axgbe_phy_sfp_reset(phy_data); 846 axgbe_phy_sfp_mod_absent(pdata); 847 goto put; 848 } 849 850 axgbe_phy_sfp_parse_eeprom(pdata); 851 axgbe_phy_sfp_external_phy(pdata); 852 853 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n", 854 axgbe_base_as_string(phy_data->sfp_base)); 855 856 put: 857 axgbe_phy_sfp_phy_settings(pdata); 858 axgbe_phy_put_comm_ownership(pdata); 859 } 860 861 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 862 { 863 pdata->phy.tx_pause = 0; 864 pdata->phy.rx_pause = 0; 865 } 866 867 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 868 { 869 struct axgbe_phy_data *phy_data = pdata->phy_data; 870 enum axgbe_mode mode; 871 unsigned int ad_reg, lp_reg; 872 873 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 874 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 875 876 /* Use external PHY to determine flow control */ 877 if (pdata->phy.pause_autoneg) 878 axgbe_phy_phydev_flowctrl(pdata); 879 880 /* Compare Advertisement and Link Partner register 2 */ 881 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 882 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 883 if (lp_reg & 0x80) 884 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 885 if (lp_reg & 0x20) 886 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 887 888 ad_reg &= lp_reg; 889 if (ad_reg & 0x80) { 890 switch (phy_data->port_mode) { 891 case AXGBE_PORT_MODE_BACKPLANE: 892 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 893 mode = AXGBE_MODE_KR; 894 break; 895 default: 896 mode = AXGBE_MODE_SFI; 897 break; 898 } 899 } else if (ad_reg & 0x20) { 900 switch (phy_data->port_mode) { 901 case AXGBE_PORT_MODE_BACKPLANE: 902 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 903 mode = AXGBE_MODE_KX_1000; 904 break; 905 case AXGBE_PORT_MODE_1000BASE_X: 906 mode = AXGBE_MODE_X; 907 break; 908 case AXGBE_PORT_MODE_SFP: 909 switch (phy_data->sfp_base) { 910 case AXGBE_SFP_BASE_1000_T: 911 mode = AXGBE_MODE_SGMII_1000; 912 break; 913 case AXGBE_SFP_BASE_1000_SX: 914 case AXGBE_SFP_BASE_1000_LX: 915 case AXGBE_SFP_BASE_1000_CX: 916 default: 917 mode = AXGBE_MODE_X; 918 break; 919 } 920 break; 921 default: 922 mode = AXGBE_MODE_SGMII_1000; 923 break; 924 } 925 } else { 926 mode = AXGBE_MODE_UNKNOWN; 927 } 928 929 /* Compare Advertisement and Link Partner register 3 */ 930 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 931 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 932 if (lp_reg & 0xc000) 933 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 934 935 return mode; 936 } 937 938 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 939 { 940 enum axgbe_mode mode; 941 unsigned int ad_reg, lp_reg; 942 943 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 944 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 945 946 /* Compare Advertisement and Link Partner register 1 */ 947 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 948 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 949 if (lp_reg & 0x400) 950 pdata->phy.lp_advertising |= ADVERTISED_Pause; 951 if (lp_reg & 0x800) 952 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 953 954 if (pdata->phy.pause_autoneg) { 955 /* Set flow control based on auto-negotiation result */ 956 pdata->phy.tx_pause = 0; 957 pdata->phy.rx_pause = 0; 958 959 if (ad_reg & lp_reg & 0x400) { 960 pdata->phy.tx_pause = 1; 961 pdata->phy.rx_pause = 1; 962 } else if (ad_reg & lp_reg & 0x800) { 963 if (ad_reg & 0x400) 964 pdata->phy.rx_pause = 1; 965 else if (lp_reg & 0x400) 966 pdata->phy.tx_pause = 1; 967 } 968 } 969 970 /* Compare Advertisement and Link Partner register 2 */ 971 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 972 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 973 if (lp_reg & 0x80) 974 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 975 if (lp_reg & 0x20) 976 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 977 978 ad_reg &= lp_reg; 979 if (ad_reg & 0x80) 980 mode = AXGBE_MODE_KR; 981 else if (ad_reg & 0x20) 982 mode = AXGBE_MODE_KX_1000; 983 else 984 mode = AXGBE_MODE_UNKNOWN; 985 986 /* Compare Advertisement and Link Partner register 3 */ 987 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 988 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 989 if (lp_reg & 0xc000) 990 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 991 992 return mode; 993 } 994 995 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 996 { 997 enum axgbe_mode mode; 998 999 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 1000 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1001 1002 if (pdata->phy.pause_autoneg) 1003 axgbe_phy_phydev_flowctrl(pdata); 1004 1005 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 1006 case AXGBE_SGMII_AN_LINK_SPEED_100: 1007 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1008 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 1009 mode = AXGBE_MODE_SGMII_100; 1010 } else { 1011 mode = AXGBE_MODE_UNKNOWN; 1012 } 1013 break; 1014 case AXGBE_SGMII_AN_LINK_SPEED_1000: 1015 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1016 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1017 mode = AXGBE_MODE_SGMII_1000; 1018 } else { 1019 /* Half-duplex not supported */ 1020 mode = AXGBE_MODE_UNKNOWN; 1021 } 1022 break; 1023 default: 1024 mode = AXGBE_MODE_UNKNOWN; 1025 break; 1026 } 1027 return mode; 1028 } 1029 1030 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 1031 { 1032 switch (pdata->an_mode) { 1033 case AXGBE_AN_MODE_CL73: 1034 return axgbe_phy_an73_outcome(pdata); 1035 case AXGBE_AN_MODE_CL73_REDRV: 1036 return axgbe_phy_an73_redrv_outcome(pdata); 1037 case AXGBE_AN_MODE_CL37: 1038 case AXGBE_AN_MODE_CL37_SGMII: 1039 return axgbe_phy_an37_sgmii_outcome(pdata); 1040 default: 1041 return AXGBE_MODE_UNKNOWN; 1042 } 1043 } 1044 1045 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1046 { 1047 struct axgbe_phy_data *phy_data = pdata->phy_data; 1048 unsigned int advertising; 1049 1050 /* Without a re-driver, just return current advertising */ 1051 if (!phy_data->redrv) 1052 return pdata->phy.advertising; 1053 1054 /* With the KR re-driver we need to advertise a single speed */ 1055 advertising = pdata->phy.advertising; 1056 advertising &= ~ADVERTISED_1000baseKX_Full; 1057 advertising &= ~ADVERTISED_10000baseKR_Full; 1058 1059 switch (phy_data->port_mode) { 1060 case AXGBE_PORT_MODE_BACKPLANE: 1061 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1062 advertising |= ADVERTISED_10000baseKR_Full; 1063 break; 1064 case AXGBE_PORT_MODE_BACKPLANE_2500: 1065 advertising |= ADVERTISED_1000baseKX_Full; 1066 break; 1067 case AXGBE_PORT_MODE_1000BASE_T: 1068 case AXGBE_PORT_MODE_1000BASE_X: 1069 case AXGBE_PORT_MODE_NBASE_T: 1070 advertising |= ADVERTISED_1000baseKX_Full; 1071 break; 1072 case AXGBE_PORT_MODE_10GBASE_T: 1073 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1074 break; 1075 case AXGBE_PORT_MODE_10GBASE_R: 1076 advertising |= ADVERTISED_10000baseKR_Full; 1077 break; 1078 case AXGBE_PORT_MODE_SFP: 1079 switch (phy_data->sfp_base) { 1080 case AXGBE_SFP_BASE_1000_T: 1081 case AXGBE_SFP_BASE_1000_SX: 1082 case AXGBE_SFP_BASE_1000_LX: 1083 case AXGBE_SFP_BASE_1000_CX: 1084 advertising |= ADVERTISED_1000baseKX_Full; 1085 break; 1086 default: 1087 advertising |= ADVERTISED_10000baseKR_Full; 1088 break; 1089 } 1090 break; 1091 default: 1092 advertising |= ADVERTISED_10000baseKR_Full; 1093 break; 1094 } 1095 1096 return advertising; 1097 } 1098 1099 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1100 { 1101 return 0; 1102 /* Dummy API since there is no case to support 1103 * external phy devices registered through kernel APIs 1104 */ 1105 } 1106 1107 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1108 { 1109 switch (phy_data->sfp_base) { 1110 case AXGBE_SFP_BASE_1000_T: 1111 return AXGBE_AN_MODE_CL37_SGMII; 1112 case AXGBE_SFP_BASE_1000_SX: 1113 case AXGBE_SFP_BASE_1000_LX: 1114 case AXGBE_SFP_BASE_1000_CX: 1115 return AXGBE_AN_MODE_CL37; 1116 default: 1117 return AXGBE_AN_MODE_NONE; 1118 } 1119 } 1120 1121 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1122 { 1123 struct axgbe_phy_data *phy_data = pdata->phy_data; 1124 1125 /* A KR re-driver will always require CL73 AN */ 1126 if (phy_data->redrv) 1127 return AXGBE_AN_MODE_CL73_REDRV; 1128 1129 switch (phy_data->port_mode) { 1130 case AXGBE_PORT_MODE_BACKPLANE: 1131 return AXGBE_AN_MODE_CL73; 1132 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1133 case AXGBE_PORT_MODE_BACKPLANE_2500: 1134 return AXGBE_AN_MODE_NONE; 1135 case AXGBE_PORT_MODE_1000BASE_T: 1136 return AXGBE_AN_MODE_CL37_SGMII; 1137 case AXGBE_PORT_MODE_1000BASE_X: 1138 return AXGBE_AN_MODE_CL37; 1139 case AXGBE_PORT_MODE_NBASE_T: 1140 return AXGBE_AN_MODE_CL37_SGMII; 1141 case AXGBE_PORT_MODE_10GBASE_T: 1142 return AXGBE_AN_MODE_CL73; 1143 case AXGBE_PORT_MODE_10GBASE_R: 1144 return AXGBE_AN_MODE_NONE; 1145 case AXGBE_PORT_MODE_SFP: 1146 return axgbe_phy_an_sfp_mode(phy_data); 1147 default: 1148 return AXGBE_AN_MODE_NONE; 1149 } 1150 } 1151 1152 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1153 enum axgbe_phy_redrv_mode mode) 1154 { 1155 struct axgbe_phy_data *phy_data = pdata->phy_data; 1156 u16 redrv_reg, redrv_val; 1157 1158 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1159 redrv_val = (u16)mode; 1160 1161 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1162 redrv_reg, redrv_val); 1163 } 1164 1165 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1166 enum axgbe_phy_redrv_mode mode) 1167 { 1168 struct axgbe_phy_data *phy_data = pdata->phy_data; 1169 unsigned int redrv_reg; 1170 int ret; 1171 1172 /* Calculate the register to write */ 1173 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1174 1175 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1176 1177 return ret; 1178 } 1179 1180 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1181 { 1182 struct axgbe_phy_data *phy_data = pdata->phy_data; 1183 enum axgbe_phy_redrv_mode mode; 1184 int ret; 1185 1186 if (!phy_data->redrv) 1187 return; 1188 1189 mode = AXGBE_PHY_REDRV_MODE_CX; 1190 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1191 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1192 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1193 mode = AXGBE_PHY_REDRV_MODE_SR; 1194 1195 ret = axgbe_phy_get_comm_ownership(pdata); 1196 if (ret) 1197 return; 1198 1199 if (phy_data->redrv_if) 1200 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1201 else 1202 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1203 1204 axgbe_phy_put_comm_ownership(pdata); 1205 } 1206 1207 static void axgbe_phy_rx_reset(struct axgbe_port *pdata) 1208 { 1209 int reg; 1210 1211 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 1212 XGBE_PCS_PSEQ_STATE_MASK); 1213 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 1214 /* Mailbox command timed out, reset of RX block is required. 1215 * This can be done by asseting the reset bit and wait for 1216 * its compeletion. 1217 */ 1218 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1219 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 1220 rte_delay_us(20); 1221 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1222 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 1223 rte_delay_us(45); 1224 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n"); 1225 } 1226 } 1227 1228 1229 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) 1230 { 1231 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1232 XGBE_PMA_PLL_CTRL_MASK, 1233 enable ? XGBE_PMA_PLL_CTRL_SET 1234 : XGBE_PMA_PLL_CTRL_CLEAR); 1235 1236 /* Wait for command to complete */ 1237 rte_delay_us(150); 1238 } 1239 1240 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, 1241 unsigned int cmd, unsigned int sub_cmd) 1242 { 1243 unsigned int s0 = 0; 1244 unsigned int wait; 1245 /* Clear the PLL so that it helps in power down sequence */ 1246 axgbe_phy_pll_ctrl(pdata, false); 1247 1248 /* Log if a previous command did not complete */ 1249 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 1250 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); 1251 axgbe_phy_rx_reset(pdata); 1252 } 1253 1254 /* Construct the command */ 1255 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1256 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1257 1258 /* Issue the command */ 1259 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1260 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1261 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1262 1263 /* Wait for command to complete */ 1264 wait = AXGBE_RATECHANGE_COUNT; 1265 while (wait--) { 1266 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1267 goto reenable_pll; 1268 rte_delay_us(1500); 1269 } 1270 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1271 /* Reset on error */ 1272 axgbe_phy_rx_reset(pdata); 1273 1274 reenable_pll: 1275 /* Re-enable the PLL control */ 1276 axgbe_phy_pll_ctrl(pdata, true); 1277 1278 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1279 } 1280 1281 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1282 { 1283 1284 1285 /* Receiver Reset Cycle */ 1286 axgbe_phy_perform_ratechange(pdata, 5, 0); 1287 1288 PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); 1289 } 1290 1291 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1292 { 1293 struct axgbe_phy_data *phy_data = pdata->phy_data; 1294 1295 /* Power off */ 1296 axgbe_phy_perform_ratechange(pdata, 0, 0); 1297 1298 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1299 1300 PMD_DRV_LOG(DEBUG, "phy powered off\n"); 1301 } 1302 1303 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1304 { 1305 struct axgbe_phy_data *phy_data = pdata->phy_data; 1306 1307 axgbe_phy_set_redrv_mode(pdata); 1308 1309 /* 10G/SFI */ 1310 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1311 axgbe_phy_perform_ratechange(pdata, 3, 0); 1312 } else { 1313 if (phy_data->sfp_cable_len <= 1) 1314 axgbe_phy_perform_ratechange(pdata, 3, 1); 1315 else if (phy_data->sfp_cable_len <= 3) 1316 axgbe_phy_perform_ratechange(pdata, 3, 2); 1317 else 1318 axgbe_phy_perform_ratechange(pdata, 3, 3); 1319 } 1320 1321 phy_data->cur_mode = AXGBE_MODE_SFI; 1322 1323 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); 1324 } 1325 1326 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1327 { 1328 struct axgbe_phy_data *phy_data = pdata->phy_data; 1329 1330 axgbe_phy_set_redrv_mode(pdata); 1331 1332 /* 10G/KR */ 1333 axgbe_phy_perform_ratechange(pdata, 4, 0); 1334 phy_data->cur_mode = AXGBE_MODE_KR; 1335 1336 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); 1337 } 1338 1339 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1340 { 1341 struct axgbe_phy_data *phy_data = pdata->phy_data; 1342 1343 axgbe_phy_set_redrv_mode(pdata); 1344 1345 /* 2.5G/KX */ 1346 axgbe_phy_perform_ratechange(pdata, 2, 0); 1347 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1348 } 1349 1350 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1351 { 1352 struct axgbe_phy_data *phy_data = pdata->phy_data; 1353 1354 axgbe_phy_set_redrv_mode(pdata); 1355 1356 /* 1G/SGMII */ 1357 axgbe_phy_perform_ratechange(pdata, 1, 2); 1358 1359 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1360 } 1361 1362 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1363 { 1364 struct axgbe_phy_data *phy_data = pdata->phy_data; 1365 1366 return phy_data->cur_mode; 1367 } 1368 1369 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1370 { 1371 struct axgbe_phy_data *phy_data = pdata->phy_data; 1372 1373 /* No switching if not 10GBase-T */ 1374 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1375 return axgbe_phy_cur_mode(pdata); 1376 1377 switch (axgbe_phy_cur_mode(pdata)) { 1378 case AXGBE_MODE_SGMII_100: 1379 case AXGBE_MODE_SGMII_1000: 1380 return AXGBE_MODE_KR; 1381 case AXGBE_MODE_KR: 1382 default: 1383 return AXGBE_MODE_SGMII_1000; 1384 } 1385 } 1386 1387 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1388 __rte_unused) 1389 { 1390 return AXGBE_MODE_KX_2500; 1391 } 1392 1393 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1394 { 1395 /* If we are in KR switch to KX, and vice-versa */ 1396 switch (axgbe_phy_cur_mode(pdata)) { 1397 case AXGBE_MODE_KX_1000: 1398 return AXGBE_MODE_KR; 1399 case AXGBE_MODE_KR: 1400 default: 1401 return AXGBE_MODE_KX_1000; 1402 } 1403 } 1404 1405 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1406 { 1407 struct axgbe_phy_data *phy_data = pdata->phy_data; 1408 1409 switch (phy_data->port_mode) { 1410 case AXGBE_PORT_MODE_BACKPLANE: 1411 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1412 return axgbe_phy_switch_bp_mode(pdata); 1413 case AXGBE_PORT_MODE_BACKPLANE_2500: 1414 return axgbe_phy_switch_bp_2500_mode(pdata); 1415 case AXGBE_PORT_MODE_1000BASE_T: 1416 case AXGBE_PORT_MODE_NBASE_T: 1417 case AXGBE_PORT_MODE_10GBASE_T: 1418 return axgbe_phy_switch_baset_mode(pdata); 1419 case AXGBE_PORT_MODE_1000BASE_X: 1420 case AXGBE_PORT_MODE_10GBASE_R: 1421 case AXGBE_PORT_MODE_SFP: 1422 /* No switching, so just return current mode */ 1423 return axgbe_phy_cur_mode(pdata); 1424 default: 1425 return AXGBE_MODE_UNKNOWN; 1426 } 1427 } 1428 1429 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1430 __rte_unused, 1431 int speed) 1432 { 1433 switch (speed) { 1434 case SPEED_1000: 1435 return AXGBE_MODE_X; 1436 case SPEED_10000: 1437 return AXGBE_MODE_KR; 1438 default: 1439 return AXGBE_MODE_UNKNOWN; 1440 } 1441 } 1442 1443 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1444 __rte_unused, 1445 int speed) 1446 { 1447 switch (speed) { 1448 case SPEED_100: 1449 return AXGBE_MODE_SGMII_100; 1450 case SPEED_1000: 1451 return AXGBE_MODE_SGMII_1000; 1452 case SPEED_10000: 1453 return AXGBE_MODE_KR; 1454 default: 1455 return AXGBE_MODE_UNKNOWN; 1456 } 1457 } 1458 1459 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1460 int speed) 1461 { 1462 switch (speed) { 1463 case SPEED_100: 1464 return AXGBE_MODE_SGMII_100; 1465 case SPEED_1000: 1466 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1467 return AXGBE_MODE_SGMII_1000; 1468 else 1469 return AXGBE_MODE_X; 1470 case SPEED_10000: 1471 case SPEED_UNKNOWN: 1472 return AXGBE_MODE_SFI; 1473 default: 1474 return AXGBE_MODE_UNKNOWN; 1475 } 1476 } 1477 1478 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1479 { 1480 switch (speed) { 1481 case SPEED_2500: 1482 return AXGBE_MODE_KX_2500; 1483 default: 1484 return AXGBE_MODE_UNKNOWN; 1485 } 1486 } 1487 1488 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1489 { 1490 switch (speed) { 1491 case SPEED_1000: 1492 return AXGBE_MODE_KX_1000; 1493 case SPEED_10000: 1494 return AXGBE_MODE_KR; 1495 default: 1496 return AXGBE_MODE_UNKNOWN; 1497 } 1498 } 1499 1500 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1501 int speed) 1502 { 1503 struct axgbe_phy_data *phy_data = pdata->phy_data; 1504 1505 switch (phy_data->port_mode) { 1506 case AXGBE_PORT_MODE_BACKPLANE: 1507 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1508 return axgbe_phy_get_bp_mode(speed); 1509 case AXGBE_PORT_MODE_BACKPLANE_2500: 1510 return axgbe_phy_get_bp_2500_mode(speed); 1511 case AXGBE_PORT_MODE_1000BASE_T: 1512 case AXGBE_PORT_MODE_NBASE_T: 1513 case AXGBE_PORT_MODE_10GBASE_T: 1514 return axgbe_phy_get_baset_mode(phy_data, speed); 1515 case AXGBE_PORT_MODE_1000BASE_X: 1516 case AXGBE_PORT_MODE_10GBASE_R: 1517 return axgbe_phy_get_basex_mode(phy_data, speed); 1518 case AXGBE_PORT_MODE_SFP: 1519 return axgbe_phy_get_sfp_mode(phy_data, speed); 1520 default: 1521 return AXGBE_MODE_UNKNOWN; 1522 } 1523 } 1524 1525 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1526 { 1527 switch (mode) { 1528 case AXGBE_MODE_KR: 1529 axgbe_phy_kr_mode(pdata); 1530 break; 1531 case AXGBE_MODE_SFI: 1532 axgbe_phy_sfi_mode(pdata); 1533 break; 1534 case AXGBE_MODE_KX_2500: 1535 axgbe_phy_kx_2500_mode(pdata); 1536 break; 1537 case AXGBE_MODE_SGMII_1000: 1538 axgbe_phy_sgmii_1000_mode(pdata); 1539 break; 1540 default: 1541 break; 1542 } 1543 } 1544 1545 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1546 enum axgbe_mode mode, u32 advert) 1547 { 1548 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1549 if (pdata->phy.advertising & advert) 1550 return true; 1551 } else { 1552 enum axgbe_mode cur_mode; 1553 1554 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1555 if (cur_mode == mode) 1556 return true; 1557 } 1558 1559 return false; 1560 } 1561 1562 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1563 enum axgbe_mode mode) 1564 { 1565 switch (mode) { 1566 case AXGBE_MODE_X: 1567 return axgbe_phy_check_mode(pdata, mode, 1568 ADVERTISED_1000baseT_Full); 1569 case AXGBE_MODE_KR: 1570 return axgbe_phy_check_mode(pdata, mode, 1571 ADVERTISED_10000baseT_Full); 1572 default: 1573 return false; 1574 } 1575 } 1576 1577 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1578 enum axgbe_mode mode) 1579 { 1580 switch (mode) { 1581 case AXGBE_MODE_SGMII_100: 1582 return axgbe_phy_check_mode(pdata, mode, 1583 ADVERTISED_100baseT_Full); 1584 case AXGBE_MODE_SGMII_1000: 1585 return axgbe_phy_check_mode(pdata, mode, 1586 ADVERTISED_1000baseT_Full); 1587 case AXGBE_MODE_KR: 1588 return axgbe_phy_check_mode(pdata, mode, 1589 ADVERTISED_10000baseT_Full); 1590 default: 1591 return false; 1592 } 1593 } 1594 1595 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1596 enum axgbe_mode mode) 1597 { 1598 struct axgbe_phy_data *phy_data = pdata->phy_data; 1599 1600 switch (mode) { 1601 case AXGBE_MODE_X: 1602 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1603 return false; 1604 return axgbe_phy_check_mode(pdata, mode, 1605 ADVERTISED_1000baseT_Full); 1606 case AXGBE_MODE_SGMII_100: 1607 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1608 return false; 1609 return axgbe_phy_check_mode(pdata, mode, 1610 ADVERTISED_100baseT_Full); 1611 case AXGBE_MODE_SGMII_1000: 1612 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1613 return false; 1614 return axgbe_phy_check_mode(pdata, mode, 1615 ADVERTISED_1000baseT_Full); 1616 case AXGBE_MODE_SFI: 1617 return axgbe_phy_check_mode(pdata, mode, 1618 ADVERTISED_10000baseT_Full); 1619 default: 1620 return false; 1621 } 1622 } 1623 1624 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1625 enum axgbe_mode mode) 1626 { 1627 switch (mode) { 1628 case AXGBE_MODE_KX_2500: 1629 return axgbe_phy_check_mode(pdata, mode, 1630 ADVERTISED_2500baseX_Full); 1631 default: 1632 return false; 1633 } 1634 } 1635 1636 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1637 enum axgbe_mode mode) 1638 { 1639 switch (mode) { 1640 case AXGBE_MODE_KX_1000: 1641 return axgbe_phy_check_mode(pdata, mode, 1642 ADVERTISED_1000baseKX_Full); 1643 case AXGBE_MODE_KR: 1644 return axgbe_phy_check_mode(pdata, mode, 1645 ADVERTISED_10000baseKR_Full); 1646 default: 1647 return false; 1648 } 1649 } 1650 1651 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1652 { 1653 struct axgbe_phy_data *phy_data = pdata->phy_data; 1654 1655 switch (phy_data->port_mode) { 1656 case AXGBE_PORT_MODE_BACKPLANE: 1657 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1658 return axgbe_phy_use_bp_mode(pdata, mode); 1659 case AXGBE_PORT_MODE_BACKPLANE_2500: 1660 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1661 case AXGBE_PORT_MODE_1000BASE_T: 1662 case AXGBE_PORT_MODE_NBASE_T: 1663 case AXGBE_PORT_MODE_10GBASE_T: 1664 return axgbe_phy_use_baset_mode(pdata, mode); 1665 case AXGBE_PORT_MODE_1000BASE_X: 1666 case AXGBE_PORT_MODE_10GBASE_R: 1667 return axgbe_phy_use_basex_mode(pdata, mode); 1668 case AXGBE_PORT_MODE_SFP: 1669 return axgbe_phy_use_sfp_mode(pdata, mode); 1670 default: 1671 return false; 1672 } 1673 } 1674 1675 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1676 { 1677 struct axgbe_phy_data *phy_data = pdata->phy_data; 1678 unsigned int reg; 1679 1680 *an_restart = 0; 1681 1682 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1683 /* Check SFP signals */ 1684 axgbe_phy_sfp_detect(pdata); 1685 1686 if (phy_data->sfp_changed) { 1687 *an_restart = 1; 1688 return 0; 1689 } 1690 1691 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1692 return 0; 1693 } 1694 1695 /* Link status is latched low, so read once to clear 1696 * and then read again to get current state 1697 */ 1698 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1699 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1700 if (reg & MDIO_STAT1_LSTATUS) 1701 return 1; 1702 1703 if (pdata->phy.autoneg == AUTONEG_ENABLE && 1704 phy_data->port_mode == AXGBE_PORT_MODE_BACKPLANE) { 1705 if (rte_bit_relaxed_get32(AXGBE_LINK_INIT, &pdata->dev_state)) { 1706 *an_restart = 1; 1707 } 1708 } 1709 1710 /* No link, attempt a receiver reset cycle */ 1711 if (pdata->vdata->enable_rrc && phy_data->rrc_count++) { 1712 phy_data->rrc_count = 0; 1713 axgbe_phy_rrc(pdata); 1714 } 1715 1716 return 0; 1717 } 1718 1719 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1720 { 1721 struct axgbe_phy_data *phy_data = pdata->phy_data; 1722 1723 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1724 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); 1725 1726 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_MASK); 1727 1728 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1729 GPIO_RX_LOS); 1730 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1731 GPIO_TX_FAULT); 1732 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1733 GPIO_MOD_ABS); 1734 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1735 GPIO_RATE_SELECT); 1736 } 1737 1738 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1739 { 1740 struct axgbe_phy_data *phy_data = pdata->phy_data; 1741 unsigned int mux_addr_hi, mux_addr_lo; 1742 1743 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 1744 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 1745 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1746 return; 1747 1748 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1749 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1750 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_CHAN); 1751 } 1752 1753 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1754 { 1755 axgbe_phy_sfp_comm_setup(pdata); 1756 axgbe_phy_sfp_gpio_setup(pdata); 1757 } 1758 1759 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1760 { 1761 if (!phy_data->redrv) 1762 return false; 1763 1764 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1765 return true; 1766 1767 switch (phy_data->redrv_model) { 1768 case AXGBE_PHY_REDRV_MODEL_4223: 1769 if (phy_data->redrv_lane > 3) 1770 return true; 1771 break; 1772 case AXGBE_PHY_REDRV_MODEL_4227: 1773 if (phy_data->redrv_lane > 1) 1774 return true; 1775 break; 1776 default: 1777 return true; 1778 } 1779 1780 return false; 1781 } 1782 1783 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1784 { 1785 struct axgbe_phy_data *phy_data = pdata->phy_data; 1786 1787 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1788 return 0; 1789 1790 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 1791 switch (phy_data->mdio_reset) { 1792 case AXGBE_MDIO_RESET_NONE: 1793 case AXGBE_MDIO_RESET_I2C_GPIO: 1794 case AXGBE_MDIO_RESET_INT_GPIO: 1795 break; 1796 default: 1797 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1798 phy_data->mdio_reset); 1799 return -EINVAL; 1800 } 1801 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1802 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1803 XP_GET_BITS(pdata->pp3, XP_PROP_3, 1804 MDIO_RESET_I2C_ADDR); 1805 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1806 MDIO_RESET_I2C_GPIO); 1807 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1808 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1809 MDIO_RESET_INT_GPIO); 1810 } 1811 1812 return 0; 1813 } 1814 1815 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1816 { 1817 struct axgbe_phy_data *phy_data = pdata->phy_data; 1818 1819 switch (phy_data->port_mode) { 1820 case AXGBE_PORT_MODE_BACKPLANE: 1821 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1822 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1823 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1824 return false; 1825 break; 1826 case AXGBE_PORT_MODE_BACKPLANE_2500: 1827 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1828 return false; 1829 break; 1830 case AXGBE_PORT_MODE_1000BASE_T: 1831 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1832 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1833 return false; 1834 break; 1835 case AXGBE_PORT_MODE_1000BASE_X: 1836 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1837 return false; 1838 break; 1839 case AXGBE_PORT_MODE_NBASE_T: 1840 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1841 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1842 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1843 return false; 1844 break; 1845 case AXGBE_PORT_MODE_10GBASE_T: 1846 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1847 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1848 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1849 return false; 1850 break; 1851 case AXGBE_PORT_MODE_10GBASE_R: 1852 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1853 return false; 1854 break; 1855 case AXGBE_PORT_MODE_SFP: 1856 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1857 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1858 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1859 return false; 1860 break; 1861 default: 1862 break; 1863 } 1864 1865 return true; 1866 } 1867 1868 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1869 { 1870 struct axgbe_phy_data *phy_data = pdata->phy_data; 1871 1872 switch (phy_data->port_mode) { 1873 case AXGBE_PORT_MODE_BACKPLANE: 1874 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1875 case AXGBE_PORT_MODE_BACKPLANE_2500: 1876 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1877 return false; 1878 break; 1879 case AXGBE_PORT_MODE_1000BASE_T: 1880 case AXGBE_PORT_MODE_1000BASE_X: 1881 case AXGBE_PORT_MODE_NBASE_T: 1882 case AXGBE_PORT_MODE_10GBASE_T: 1883 case AXGBE_PORT_MODE_10GBASE_R: 1884 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1885 return false; 1886 break; 1887 case AXGBE_PORT_MODE_SFP: 1888 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1889 return false; 1890 break; 1891 default: 1892 break; 1893 } 1894 1895 return true; 1896 } 1897 1898 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1899 { 1900 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 1901 return false; 1902 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 1903 return false; 1904 1905 return true; 1906 } 1907 1908 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1909 { 1910 struct axgbe_phy_data *phy_data = pdata->phy_data; 1911 1912 if (!pdata->vdata->an_cdr_workaround) 1913 return; 1914 1915 if (!phy_data->phy_cdr_notrack) 1916 return; 1917 1918 rte_delay_us(phy_data->phy_cdr_delay + 400); 1919 1920 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1921 AXGBE_PMA_CDR_TRACK_EN_MASK, 1922 AXGBE_PMA_CDR_TRACK_EN_ON); 1923 1924 phy_data->phy_cdr_notrack = 0; 1925 } 1926 1927 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1928 { 1929 struct axgbe_phy_data *phy_data = pdata->phy_data; 1930 1931 if (!pdata->vdata->an_cdr_workaround) 1932 return; 1933 1934 if (phy_data->phy_cdr_notrack) 1935 return; 1936 1937 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1938 AXGBE_PMA_CDR_TRACK_EN_MASK, 1939 AXGBE_PMA_CDR_TRACK_EN_OFF); 1940 1941 axgbe_phy_rrc(pdata); 1942 1943 phy_data->phy_cdr_notrack = 1; 1944 } 1945 1946 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1947 { 1948 if (!pdata->cdr_track_early) 1949 axgbe_phy_cdr_track(pdata); 1950 } 1951 1952 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1953 { 1954 if (pdata->cdr_track_early) 1955 axgbe_phy_cdr_track(pdata); 1956 } 1957 1958 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1959 { 1960 struct axgbe_phy_data *phy_data = pdata->phy_data; 1961 1962 switch (pdata->an_mode) { 1963 case AXGBE_AN_MODE_CL73: 1964 case AXGBE_AN_MODE_CL73_REDRV: 1965 if (phy_data->cur_mode != AXGBE_MODE_KR) 1966 break; 1967 1968 axgbe_phy_cdr_track(pdata); 1969 1970 switch (pdata->an_result) { 1971 case AXGBE_AN_READY: 1972 case AXGBE_AN_COMPLETE: 1973 break; 1974 default: 1975 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1976 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1977 break; 1978 } 1979 break; 1980 default: 1981 break; 1982 } 1983 } 1984 1985 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1986 { 1987 struct axgbe_phy_data *phy_data = pdata->phy_data; 1988 1989 switch (pdata->an_mode) { 1990 case AXGBE_AN_MODE_CL73: 1991 case AXGBE_AN_MODE_CL73_REDRV: 1992 if (phy_data->cur_mode != AXGBE_MODE_KR) 1993 break; 1994 1995 axgbe_phy_cdr_notrack(pdata); 1996 break; 1997 default: 1998 break; 1999 } 2000 } 2001 2002 static void axgbe_phy_stop(struct axgbe_port *pdata) 2003 { 2004 struct axgbe_phy_data *phy_data = pdata->phy_data; 2005 2006 /* Reset SFP data */ 2007 axgbe_phy_sfp_reset(phy_data); 2008 axgbe_phy_sfp_mod_absent(pdata); 2009 2010 /* Reset CDR support */ 2011 axgbe_phy_cdr_track(pdata); 2012 2013 /* Power off the PHY */ 2014 axgbe_phy_power_off(pdata); 2015 2016 /* Stop the I2C controller */ 2017 pdata->i2c_if.i2c_stop(pdata); 2018 } 2019 2020 static int axgbe_phy_start(struct axgbe_port *pdata) 2021 { 2022 struct axgbe_phy_data *phy_data = pdata->phy_data; 2023 int ret; 2024 2025 /* Start the I2C controller */ 2026 ret = pdata->i2c_if.i2c_start(pdata); 2027 if (ret) 2028 return ret; 2029 2030 /* Start in highest supported mode */ 2031 axgbe_phy_set_mode(pdata, phy_data->start_mode); 2032 2033 /* Reset CDR support */ 2034 axgbe_phy_cdr_track(pdata); 2035 2036 /* After starting the I2C controller, we can check for an SFP */ 2037 switch (phy_data->port_mode) { 2038 case AXGBE_PORT_MODE_SFP: 2039 axgbe_phy_sfp_detect(pdata); 2040 break; 2041 default: 2042 break; 2043 } 2044 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 2045 2046 return ret; 2047 } 2048 2049 static int axgbe_phy_reset(struct axgbe_port *pdata) 2050 { 2051 struct axgbe_phy_data *phy_data = pdata->phy_data; 2052 enum axgbe_mode cur_mode; 2053 2054 /* Reset by power cycling the PHY */ 2055 cur_mode = phy_data->cur_mode; 2056 axgbe_phy_power_off(pdata); 2057 /* First time reset is done with passed unknown mode*/ 2058 axgbe_phy_set_mode(pdata, cur_mode); 2059 return 0; 2060 } 2061 2062 static int axgbe_phy_init(struct axgbe_port *pdata) 2063 { 2064 struct axgbe_phy_data *phy_data; 2065 int ret; 2066 2067 /* Check if enabled */ 2068 if (!axgbe_phy_port_enabled(pdata)) { 2069 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2070 return -ENODEV; 2071 } 2072 2073 /* Initialize the I2C controller */ 2074 ret = pdata->i2c_if.i2c_init(pdata); 2075 if (ret) 2076 return ret; 2077 2078 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2079 if (!phy_data) { 2080 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2081 return -ENOMEM; 2082 } 2083 pdata->phy_data = phy_data; 2084 2085 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 2086 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 2087 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 2088 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 2089 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 2090 2091 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 2092 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 2093 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 2094 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 2095 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 2096 2097 /* Validate the connection requested */ 2098 if (axgbe_phy_conn_type_mismatch(pdata)) { 2099 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2100 phy_data->port_mode, phy_data->conn_type); 2101 return -EINVAL; 2102 } 2103 2104 /* Validate the mode requested */ 2105 if (axgbe_phy_port_mode_mismatch(pdata)) { 2106 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2107 phy_data->port_mode, phy_data->port_speeds); 2108 return -EINVAL; 2109 } 2110 2111 /* Check for and validate MDIO reset support */ 2112 ret = axgbe_phy_mdio_reset_setup(pdata); 2113 if (ret) 2114 return ret; 2115 2116 /* Validate the re-driver information */ 2117 if (axgbe_phy_redrv_error(phy_data)) { 2118 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2119 return -EINVAL; 2120 } 2121 pdata->kr_redrv = phy_data->redrv; 2122 2123 /* Indicate current mode is unknown */ 2124 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2125 2126 /* Initialize supported features */ 2127 pdata->phy.supported = 0; 2128 2129 switch (phy_data->port_mode) { 2130 /* Backplane support */ 2131 case AXGBE_PORT_MODE_BACKPLANE: 2132 pdata->phy.supported |= SUPPORTED_Autoneg; 2133 /* Fallthrough */ 2134 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2135 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2136 pdata->phy.supported |= SUPPORTED_Backplane; 2137 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2138 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2139 phy_data->start_mode = AXGBE_MODE_KX_1000; 2140 } 2141 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2142 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2143 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2144 pdata->phy.supported |= 2145 SUPPORTED_10000baseR_FEC; 2146 phy_data->start_mode = AXGBE_MODE_KR; 2147 } 2148 2149 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2150 break; 2151 case AXGBE_PORT_MODE_BACKPLANE_2500: 2152 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2153 pdata->phy.supported |= SUPPORTED_Backplane; 2154 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2155 phy_data->start_mode = AXGBE_MODE_KX_2500; 2156 2157 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2158 break; 2159 2160 /* MDIO 1GBase-T support */ 2161 case AXGBE_PORT_MODE_1000BASE_T: 2162 pdata->phy.supported |= SUPPORTED_Autoneg; 2163 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2164 pdata->phy.supported |= SUPPORTED_TP; 2165 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2166 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2167 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2168 } 2169 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2170 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2171 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2172 } 2173 2174 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2175 break; 2176 2177 /* MDIO Base-X support */ 2178 case AXGBE_PORT_MODE_1000BASE_X: 2179 pdata->phy.supported |= SUPPORTED_Autoneg; 2180 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2181 pdata->phy.supported |= SUPPORTED_FIBRE; 2182 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2183 phy_data->start_mode = AXGBE_MODE_X; 2184 2185 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2186 break; 2187 2188 /* MDIO NBase-T support */ 2189 case AXGBE_PORT_MODE_NBASE_T: 2190 pdata->phy.supported |= SUPPORTED_Autoneg; 2191 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2192 pdata->phy.supported |= SUPPORTED_TP; 2193 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2194 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2195 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2196 } 2197 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2198 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2199 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2200 } 2201 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2202 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2203 phy_data->start_mode = AXGBE_MODE_KX_2500; 2204 } 2205 2206 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2207 break; 2208 2209 /* 10GBase-T support */ 2210 case AXGBE_PORT_MODE_10GBASE_T: 2211 pdata->phy.supported |= SUPPORTED_Autoneg; 2212 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2213 pdata->phy.supported |= SUPPORTED_TP; 2214 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2215 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2216 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2217 } 2218 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2219 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2220 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2221 } 2222 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2223 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2224 phy_data->start_mode = AXGBE_MODE_KR; 2225 } 2226 2227 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2228 break; 2229 2230 /* 10GBase-R support */ 2231 case AXGBE_PORT_MODE_10GBASE_R: 2232 pdata->phy.supported |= SUPPORTED_Autoneg; 2233 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2234 pdata->phy.supported |= SUPPORTED_TP; 2235 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2236 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2237 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2238 phy_data->start_mode = AXGBE_MODE_SFI; 2239 2240 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2241 break; 2242 2243 /* SFP support */ 2244 case AXGBE_PORT_MODE_SFP: 2245 pdata->phy.supported |= SUPPORTED_Autoneg; 2246 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2247 pdata->phy.supported |= SUPPORTED_TP; 2248 pdata->phy.supported |= SUPPORTED_FIBRE; 2249 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2250 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2251 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2252 } 2253 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2254 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2255 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2256 } 2257 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2258 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2259 phy_data->start_mode = AXGBE_MODE_SFI; 2260 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2261 pdata->phy.supported |= 2262 SUPPORTED_10000baseR_FEC; 2263 } 2264 2265 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2266 2267 axgbe_phy_sfp_setup(pdata); 2268 break; 2269 default: 2270 return -EINVAL; 2271 } 2272 2273 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2274 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2275 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2276 phy_data->phydev_mode); 2277 if (ret) { 2278 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2279 phy_data->mdio_addr, phy_data->phydev_mode); 2280 return -EINVAL; 2281 } 2282 } 2283 2284 if (phy_data->redrv && !phy_data->redrv_if) { 2285 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2286 AXGBE_MDIO_MODE_CL22); 2287 if (ret) { 2288 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2289 phy_data->redrv_addr); 2290 return -EINVAL; 2291 } 2292 } 2293 2294 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2295 return 0; 2296 } 2297 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2298 { 2299 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2300 2301 phy_impl->init = axgbe_phy_init; 2302 phy_impl->reset = axgbe_phy_reset; 2303 phy_impl->start = axgbe_phy_start; 2304 phy_impl->stop = axgbe_phy_stop; 2305 phy_impl->link_status = axgbe_phy_link_status; 2306 phy_impl->use_mode = axgbe_phy_use_mode; 2307 phy_impl->set_mode = axgbe_phy_set_mode; 2308 phy_impl->get_mode = axgbe_phy_get_mode; 2309 phy_impl->switch_mode = axgbe_phy_switch_mode; 2310 phy_impl->cur_mode = axgbe_phy_cur_mode; 2311 phy_impl->an_mode = axgbe_phy_an_mode; 2312 phy_impl->an_config = axgbe_phy_an_config; 2313 phy_impl->an_advertising = axgbe_phy_an_advertising; 2314 phy_impl->an_outcome = axgbe_phy_an_outcome; 2315 2316 phy_impl->an_pre = axgbe_phy_an_pre; 2317 phy_impl->an_post = axgbe_phy_an_post; 2318 2319 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2320 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2321 } 2322