1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_MAX, 50 }; 51 52 enum axgbe_conn_type { 53 AXGBE_CONN_TYPE_NONE = 0, 54 AXGBE_CONN_TYPE_SFP, 55 AXGBE_CONN_TYPE_MDIO, 56 AXGBE_CONN_TYPE_RSVD1, 57 AXGBE_CONN_TYPE_BACKPLANE, 58 AXGBE_CONN_TYPE_MAX, 59 }; 60 61 /* SFP/SFP+ related definitions */ 62 enum axgbe_sfp_comm { 63 AXGBE_SFP_COMM_DIRECT = 0, 64 AXGBE_SFP_COMM_PCA9545, 65 }; 66 67 enum axgbe_sfp_cable { 68 AXGBE_SFP_CABLE_UNKNOWN = 0, 69 AXGBE_SFP_CABLE_ACTIVE, 70 AXGBE_SFP_CABLE_PASSIVE, 71 }; 72 73 enum axgbe_sfp_base { 74 AXGBE_SFP_BASE_UNKNOWN = 0, 75 AXGBE_SFP_BASE_1000_T, 76 AXGBE_SFP_BASE_1000_SX, 77 AXGBE_SFP_BASE_1000_LX, 78 AXGBE_SFP_BASE_1000_CX, 79 AXGBE_SFP_BASE_10000_SR, 80 AXGBE_SFP_BASE_10000_LR, 81 AXGBE_SFP_BASE_10000_LRM, 82 AXGBE_SFP_BASE_10000_ER, 83 AXGBE_SFP_BASE_10000_CR, 84 }; 85 86 enum axgbe_sfp_speed { 87 AXGBE_SFP_SPEED_UNKNOWN = 0, 88 AXGBE_SFP_SPEED_100_1000, 89 AXGBE_SFP_SPEED_1000, 90 AXGBE_SFP_SPEED_10000, 91 }; 92 93 /* SFP Serial ID Base ID values relative to an offset of 0 */ 94 #define AXGBE_SFP_BASE_ID 0 95 #define AXGBE_SFP_ID_SFP 0x03 96 97 #define AXGBE_SFP_BASE_EXT_ID 1 98 #define AXGBE_SFP_EXT_ID_SFP 0x04 99 100 #define AXGBE_SFP_BASE_10GBE_CC 3 101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 105 106 #define AXGBE_SFP_BASE_1GBE_CC 6 107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 111 112 #define AXGBE_SFP_BASE_CABLE 8 113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 115 116 #define AXGBE_SFP_BASE_BR 12 117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 121 122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 123 124 #define AXGBE_SFP_BASE_VENDOR_NAME 20 125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 126 #define AXGBE_SFP_BASE_VENDOR_PN 40 127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 128 #define AXGBE_SFP_BASE_VENDOR_REV 56 129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 130 131 #define AXGBE_SFP_BASE_CC 63 132 133 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 134 #define AXGBE_SFP_BASE_VENDOR_SN 4 135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 136 137 #define AXGBE_SFP_EXTD_DIAG 28 138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 139 140 #define AXGBE_SFP_EXTD_SFF_8472 30 141 142 #define AXGBE_SFP_EXTD_CC 31 143 144 struct axgbe_sfp_eeprom { 145 u8 base[64]; 146 u8 extd[32]; 147 u8 vendor[32]; 148 }; 149 150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 152 153 struct axgbe_sfp_ascii { 154 union { 155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 159 } u; 160 }; 161 162 /* MDIO PHY reset types */ 163 enum axgbe_mdio_reset { 164 AXGBE_MDIO_RESET_NONE = 0, 165 AXGBE_MDIO_RESET_I2C_GPIO, 166 AXGBE_MDIO_RESET_INT_GPIO, 167 AXGBE_MDIO_RESET_MAX, 168 }; 169 170 /* Re-driver related definitions */ 171 enum axgbe_phy_redrv_if { 172 AXGBE_PHY_REDRV_IF_MDIO = 0, 173 AXGBE_PHY_REDRV_IF_I2C, 174 AXGBE_PHY_REDRV_IF_MAX, 175 }; 176 177 enum axgbe_phy_redrv_model { 178 AXGBE_PHY_REDRV_MODEL_4223 = 0, 179 AXGBE_PHY_REDRV_MODEL_4227, 180 AXGBE_PHY_REDRV_MODEL_MAX, 181 }; 182 183 enum axgbe_phy_redrv_mode { 184 AXGBE_PHY_REDRV_MODE_CX = 5, 185 AXGBE_PHY_REDRV_MODE_SR = 9, 186 }; 187 188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 189 190 /* PHY related configuration information */ 191 struct axgbe_phy_data { 192 enum axgbe_port_mode port_mode; 193 194 unsigned int port_id; 195 196 unsigned int port_speeds; 197 198 enum axgbe_conn_type conn_type; 199 200 enum axgbe_mode cur_mode; 201 enum axgbe_mode start_mode; 202 203 unsigned int rrc_count; 204 205 unsigned int mdio_addr; 206 207 unsigned int comm_owned; 208 209 /* SFP Support */ 210 enum axgbe_sfp_comm sfp_comm; 211 unsigned int sfp_mux_address; 212 unsigned int sfp_mux_channel; 213 214 unsigned int sfp_gpio_address; 215 unsigned int sfp_gpio_mask; 216 unsigned int sfp_gpio_rx_los; 217 unsigned int sfp_gpio_tx_fault; 218 unsigned int sfp_gpio_mod_absent; 219 unsigned int sfp_gpio_rate_select; 220 221 unsigned int sfp_rx_los; 222 unsigned int sfp_tx_fault; 223 unsigned int sfp_mod_absent; 224 unsigned int sfp_diags; 225 unsigned int sfp_changed; 226 unsigned int sfp_phy_avail; 227 unsigned int sfp_cable_len; 228 enum axgbe_sfp_base sfp_base; 229 enum axgbe_sfp_cable sfp_cable; 230 enum axgbe_sfp_speed sfp_speed; 231 struct axgbe_sfp_eeprom sfp_eeprom; 232 233 /* External PHY support */ 234 enum axgbe_mdio_mode phydev_mode; 235 enum axgbe_mdio_reset mdio_reset; 236 unsigned int mdio_reset_addr; 237 unsigned int mdio_reset_gpio; 238 239 /* Re-driver support */ 240 unsigned int redrv; 241 unsigned int redrv_if; 242 unsigned int redrv_addr; 243 unsigned int redrv_lane; 244 unsigned int redrv_model; 245 246 /* KR AN support */ 247 unsigned int phy_cdr_notrack; 248 unsigned int phy_cdr_delay; 249 }; 250 251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 252 253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 254 struct axgbe_i2c_op *i2c_op) 255 { 256 struct axgbe_phy_data *phy_data = pdata->phy_data; 257 258 /* Be sure we own the bus */ 259 if (!phy_data->comm_owned) 260 return -EIO; 261 262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 263 } 264 265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 266 unsigned int val) 267 { 268 struct axgbe_phy_data *phy_data = pdata->phy_data; 269 struct axgbe_i2c_op i2c_op; 270 uint16_t *redrv_val; 271 u8 redrv_data[5], csum; 272 unsigned int i, retry; 273 int ret; 274 275 /* High byte of register contains read/write indicator */ 276 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 277 redrv_data[1] = reg & 0xff; 278 redrv_val = (uint16_t *)&redrv_data[2]; 279 *redrv_val = rte_cpu_to_be_16(val); 280 281 /* Calculate 1 byte checksum */ 282 csum = 0; 283 for (i = 0; i < 4; i++) { 284 csum += redrv_data[i]; 285 if (redrv_data[i] > csum) 286 csum++; 287 } 288 redrv_data[4] = ~csum; 289 290 retry = 1; 291 again1: 292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 293 i2c_op.target = phy_data->redrv_addr; 294 i2c_op.len = sizeof(redrv_data); 295 i2c_op.buf = redrv_data; 296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 297 if (ret) { 298 if ((ret == -EAGAIN) && retry--) 299 goto again1; 300 301 return ret; 302 } 303 304 retry = 1; 305 again2: 306 i2c_op.cmd = AXGBE_I2C_CMD_READ; 307 i2c_op.target = phy_data->redrv_addr; 308 i2c_op.len = 1; 309 i2c_op.buf = redrv_data; 310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 311 if (ret) { 312 if ((ret == -EAGAIN) && retry--) 313 goto again2; 314 315 return ret; 316 } 317 318 if (redrv_data[0] != 0xff) { 319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 320 ret = -EIO; 321 } 322 323 return ret; 324 } 325 326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 327 void *reg, unsigned int reg_len, 328 void *val, unsigned int val_len) 329 { 330 struct axgbe_i2c_op i2c_op; 331 int retry, ret; 332 333 retry = 1; 334 again1: 335 /* Set the specified register to read */ 336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 337 i2c_op.target = target; 338 i2c_op.len = reg_len; 339 i2c_op.buf = reg; 340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 341 if (ret) { 342 if ((ret == -EAGAIN) && retry--) 343 goto again1; 344 345 return ret; 346 } 347 348 retry = 1; 349 again2: 350 /* Read the specfied register */ 351 i2c_op.cmd = AXGBE_I2C_CMD_READ; 352 i2c_op.target = target; 353 i2c_op.len = val_len; 354 i2c_op.buf = val; 355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 356 if ((ret == -EAGAIN) && retry--) 357 goto again2; 358 359 return ret; 360 } 361 362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 363 { 364 struct axgbe_phy_data *phy_data = pdata->phy_data; 365 struct axgbe_i2c_op i2c_op; 366 uint8_t mux_channel; 367 368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 369 return 0; 370 371 /* Select no mux channels */ 372 mux_channel = 0; 373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 374 i2c_op.target = phy_data->sfp_mux_address; 375 i2c_op.len = sizeof(mux_channel); 376 i2c_op.buf = &mux_channel; 377 378 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 379 } 380 381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 382 { 383 struct axgbe_phy_data *phy_data = pdata->phy_data; 384 struct axgbe_i2c_op i2c_op; 385 u8 mux_channel; 386 387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 388 return 0; 389 390 /* Select desired mux channel */ 391 mux_channel = 1 << phy_data->sfp_mux_channel; 392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 393 i2c_op.target = phy_data->sfp_mux_address; 394 i2c_op.len = sizeof(mux_channel); 395 i2c_op.buf = &mux_channel; 396 397 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 398 } 399 400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 401 { 402 struct axgbe_phy_data *phy_data = pdata->phy_data; 403 404 phy_data->comm_owned = 0; 405 406 pthread_mutex_unlock(&pdata->phy_mutex); 407 } 408 409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 410 { 411 struct axgbe_phy_data *phy_data = pdata->phy_data; 412 uint64_t timeout; 413 unsigned int mutex_id; 414 415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 416 * the driver needs to take the software mutex and then the hardware 417 * mutexes before being able to use the busses. 418 */ 419 pthread_mutex_lock(&pdata->phy_mutex); 420 421 if (phy_data->comm_owned) 422 return 0; 423 424 /* Clear the mutexes */ 425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 427 428 /* Mutex formats are the same for I2C and MDIO/GPIO */ 429 mutex_id = 0; 430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 432 433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 434 while (time_before(rte_get_timer_cycles(), timeout)) { 435 /* Must be all zeroes in order to obtain the mutex */ 436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 438 rte_delay_us(100); 439 continue; 440 } 441 442 /* Obtain the mutex */ 443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 445 446 phy_data->comm_owned = 1; 447 return 0; 448 } 449 450 pthread_mutex_unlock(&pdata->phy_mutex); 451 452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 453 454 return -ETIMEDOUT; 455 } 456 457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 458 { 459 struct axgbe_phy_data *phy_data = pdata->phy_data; 460 461 if (phy_data->sfp_mod_absent) { 462 pdata->phy.speed = SPEED_UNKNOWN; 463 pdata->phy.duplex = DUPLEX_UNKNOWN; 464 pdata->phy.autoneg = AUTONEG_ENABLE; 465 pdata->phy.advertising = pdata->phy.supported; 466 } 467 468 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 469 pdata->phy.advertising &= ~ADVERTISED_TP; 470 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 475 476 switch (phy_data->sfp_base) { 477 case AXGBE_SFP_BASE_1000_T: 478 case AXGBE_SFP_BASE_1000_SX: 479 case AXGBE_SFP_BASE_1000_LX: 480 case AXGBE_SFP_BASE_1000_CX: 481 pdata->phy.speed = SPEED_UNKNOWN; 482 pdata->phy.duplex = DUPLEX_UNKNOWN; 483 pdata->phy.autoneg = AUTONEG_ENABLE; 484 pdata->phy.advertising |= ADVERTISED_Autoneg; 485 break; 486 case AXGBE_SFP_BASE_10000_SR: 487 case AXGBE_SFP_BASE_10000_LR: 488 case AXGBE_SFP_BASE_10000_LRM: 489 case AXGBE_SFP_BASE_10000_ER: 490 case AXGBE_SFP_BASE_10000_CR: 491 default: 492 pdata->phy.speed = SPEED_10000; 493 pdata->phy.duplex = DUPLEX_FULL; 494 pdata->phy.autoneg = AUTONEG_DISABLE; 495 break; 496 } 497 498 switch (phy_data->sfp_base) { 499 case AXGBE_SFP_BASE_1000_T: 500 case AXGBE_SFP_BASE_1000_CX: 501 case AXGBE_SFP_BASE_10000_CR: 502 pdata->phy.advertising |= ADVERTISED_TP; 503 break; 504 default: 505 pdata->phy.advertising |= ADVERTISED_FIBRE; 506 } 507 508 switch (phy_data->sfp_speed) { 509 case AXGBE_SFP_SPEED_100_1000: 510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 511 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 514 break; 515 case AXGBE_SFP_SPEED_1000: 516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 518 break; 519 case AXGBE_SFP_SPEED_10000: 520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 522 break; 523 default: 524 /* Choose the fastest supported speed */ 525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 530 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 531 } 532 } 533 534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 535 enum axgbe_sfp_speed sfp_speed) 536 { 537 u8 *sfp_base, min, max; 538 539 sfp_base = sfp_eeprom->base; 540 541 switch (sfp_speed) { 542 case AXGBE_SFP_SPEED_1000: 543 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 544 max = AXGBE_SFP_BASE_BR_1GBE_MAX; 545 break; 546 case AXGBE_SFP_SPEED_10000: 547 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 548 max = AXGBE_SFP_BASE_BR_10GBE_MAX; 549 break; 550 default: 551 return false; 552 } 553 554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) && 555 (sfp_base[AXGBE_SFP_BASE_BR] <= max)); 556 } 557 558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 559 { 560 struct axgbe_phy_data *phy_data = pdata->phy_data; 561 562 if (!phy_data->sfp_changed) 563 return; 564 565 phy_data->sfp_phy_avail = 0; 566 567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 568 return; 569 } 570 571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 572 { 573 struct axgbe_phy_data *phy_data = pdata->phy_data; 574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 575 576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 578 return false; 579 580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 585 return true; 586 } 587 588 return false; 589 } 590 591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 592 { 593 if (axgbe_phy_belfuse_parse_quirks(pdata)) 594 return true; 595 596 return false; 597 } 598 599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 600 { 601 struct axgbe_phy_data *phy_data = pdata->phy_data; 602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 603 uint8_t *sfp_base; 604 605 sfp_base = sfp_eeprom->base; 606 607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 608 return; 609 610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 611 return; 612 613 axgbe_phy_sfp_parse_quirks(pdata); 614 615 /* Assume ACTIVE cable unless told it is PASSIVE */ 616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 619 } else { 620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 621 } 622 623 /* Determine the type of SFP */ 624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 629 AXGBE_SFP_BASE_10GBE_CC_LRM) 630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) && 642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 644 645 switch (phy_data->sfp_base) { 646 case AXGBE_SFP_BASE_1000_T: 647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 648 break; 649 case AXGBE_SFP_BASE_1000_SX: 650 case AXGBE_SFP_BASE_1000_LX: 651 case AXGBE_SFP_BASE_1000_CX: 652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 653 break; 654 case AXGBE_SFP_BASE_10000_SR: 655 case AXGBE_SFP_BASE_10000_LR: 656 case AXGBE_SFP_BASE_10000_LRM: 657 case AXGBE_SFP_BASE_10000_ER: 658 case AXGBE_SFP_BASE_10000_CR: 659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 660 break; 661 default: 662 break; 663 } 664 } 665 666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 667 unsigned int len) 668 { 669 uint8_t cc; 670 671 for (cc = 0; len; buf++, len--) 672 cc += *buf; 673 674 return (cc == cc_in) ? true : false; 675 } 676 677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 678 { 679 struct axgbe_phy_data *phy_data = pdata->phy_data; 680 struct axgbe_sfp_eeprom sfp_eeprom; 681 uint8_t eeprom_addr; 682 int ret; 683 684 ret = axgbe_phy_sfp_get_mux(pdata); 685 if (ret) { 686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 687 return ret; 688 } 689 690 /* Read the SFP serial ID eeprom */ 691 eeprom_addr = 0; 692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 693 &eeprom_addr, sizeof(eeprom_addr), 694 &sfp_eeprom, sizeof(sfp_eeprom)); 695 if (ret) { 696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 697 goto put; 698 } 699 700 /* Validate the contents read */ 701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 702 sfp_eeprom.base, 703 sizeof(sfp_eeprom.base) - 1)) { 704 ret = -EINVAL; 705 goto put; 706 } 707 708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 709 sfp_eeprom.extd, 710 sizeof(sfp_eeprom.extd) - 1)) { 711 ret = -EINVAL; 712 goto put; 713 } 714 715 /* Check for an added or changed SFP */ 716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 717 phy_data->sfp_changed = 1; 718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 719 720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) { 721 uint8_t diag_type; 722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG]; 723 724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 725 phy_data->sfp_diags = 1; 726 } 727 } else { 728 phy_data->sfp_changed = 0; 729 } 730 731 put: 732 axgbe_phy_sfp_put_mux(pdata); 733 734 return ret; 735 } 736 737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 738 { 739 struct axgbe_phy_data *phy_data = pdata->phy_data; 740 unsigned int gpio_input; 741 u8 gpio_reg, gpio_ports[2]; 742 int ret; 743 744 /* Read the input port registers */ 745 gpio_reg = 0; 746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 747 &gpio_reg, sizeof(gpio_reg), 748 gpio_ports, sizeof(gpio_ports)); 749 if (ret) { 750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 751 return; 752 } 753 754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 755 756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 757 /* No GPIO, just assume the module is present for now */ 758 phy_data->sfp_mod_absent = 0; 759 } else { 760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 761 phy_data->sfp_mod_absent = 0; 762 } 763 764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 766 phy_data->sfp_rx_los = 1; 767 768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 770 phy_data->sfp_tx_fault = 1; 771 } 772 773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 774 { 775 struct axgbe_phy_data *phy_data = pdata->phy_data; 776 777 phy_data->sfp_mod_absent = 1; 778 phy_data->sfp_phy_avail = 0; 779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 780 } 781 782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 783 { 784 phy_data->sfp_rx_los = 0; 785 phy_data->sfp_tx_fault = 0; 786 phy_data->sfp_mod_absent = 1; 787 phy_data->sfp_diags = 0; 788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 791 } 792 793 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 794 { 795 struct axgbe_phy_data *phy_data = pdata->phy_data; 796 int ret; 797 798 /* Reset the SFP signals and info */ 799 axgbe_phy_sfp_reset(phy_data); 800 801 ret = axgbe_phy_get_comm_ownership(pdata); 802 if (ret) 803 return; 804 805 /* Read the SFP signals and check for module presence */ 806 axgbe_phy_sfp_signals(pdata); 807 if (phy_data->sfp_mod_absent) { 808 axgbe_phy_sfp_mod_absent(pdata); 809 goto put; 810 } 811 812 ret = axgbe_phy_sfp_read_eeprom(pdata); 813 if (ret) { 814 /* Treat any error as if there isn't an SFP plugged in */ 815 axgbe_phy_sfp_reset(phy_data); 816 axgbe_phy_sfp_mod_absent(pdata); 817 goto put; 818 } 819 820 axgbe_phy_sfp_parse_eeprom(pdata); 821 axgbe_phy_sfp_external_phy(pdata); 822 823 put: 824 axgbe_phy_sfp_phy_settings(pdata); 825 axgbe_phy_put_comm_ownership(pdata); 826 } 827 828 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 829 { 830 pdata->phy.tx_pause = 0; 831 pdata->phy.rx_pause = 0; 832 } 833 834 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 835 { 836 struct axgbe_phy_data *phy_data = pdata->phy_data; 837 enum axgbe_mode mode; 838 unsigned int ad_reg, lp_reg; 839 840 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 841 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 842 843 /* Use external PHY to determine flow control */ 844 if (pdata->phy.pause_autoneg) 845 axgbe_phy_phydev_flowctrl(pdata); 846 847 /* Compare Advertisement and Link Partner register 2 */ 848 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 849 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 850 if (lp_reg & 0x80) 851 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 852 if (lp_reg & 0x20) 853 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 854 855 ad_reg &= lp_reg; 856 if (ad_reg & 0x80) { 857 switch (phy_data->port_mode) { 858 case AXGBE_PORT_MODE_BACKPLANE: 859 mode = AXGBE_MODE_KR; 860 break; 861 default: 862 mode = AXGBE_MODE_SFI; 863 break; 864 } 865 } else if (ad_reg & 0x20) { 866 switch (phy_data->port_mode) { 867 case AXGBE_PORT_MODE_BACKPLANE: 868 mode = AXGBE_MODE_KX_1000; 869 break; 870 case AXGBE_PORT_MODE_1000BASE_X: 871 mode = AXGBE_MODE_X; 872 break; 873 case AXGBE_PORT_MODE_SFP: 874 switch (phy_data->sfp_base) { 875 case AXGBE_SFP_BASE_1000_T: 876 mode = AXGBE_MODE_SGMII_1000; 877 break; 878 case AXGBE_SFP_BASE_1000_SX: 879 case AXGBE_SFP_BASE_1000_LX: 880 case AXGBE_SFP_BASE_1000_CX: 881 default: 882 mode = AXGBE_MODE_X; 883 break; 884 } 885 break; 886 default: 887 mode = AXGBE_MODE_SGMII_1000; 888 break; 889 } 890 } else { 891 mode = AXGBE_MODE_UNKNOWN; 892 } 893 894 /* Compare Advertisement and Link Partner register 3 */ 895 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 896 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 897 if (lp_reg & 0xc000) 898 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 899 900 return mode; 901 } 902 903 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 904 { 905 enum axgbe_mode mode; 906 unsigned int ad_reg, lp_reg; 907 908 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 909 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 910 911 /* Compare Advertisement and Link Partner register 1 */ 912 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 913 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 914 if (lp_reg & 0x400) 915 pdata->phy.lp_advertising |= ADVERTISED_Pause; 916 if (lp_reg & 0x800) 917 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 918 919 if (pdata->phy.pause_autoneg) { 920 /* Set flow control based on auto-negotiation result */ 921 pdata->phy.tx_pause = 0; 922 pdata->phy.rx_pause = 0; 923 924 if (ad_reg & lp_reg & 0x400) { 925 pdata->phy.tx_pause = 1; 926 pdata->phy.rx_pause = 1; 927 } else if (ad_reg & lp_reg & 0x800) { 928 if (ad_reg & 0x400) 929 pdata->phy.rx_pause = 1; 930 else if (lp_reg & 0x400) 931 pdata->phy.tx_pause = 1; 932 } 933 } 934 935 /* Compare Advertisement and Link Partner register 2 */ 936 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 937 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 938 if (lp_reg & 0x80) 939 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 940 if (lp_reg & 0x20) 941 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 942 943 ad_reg &= lp_reg; 944 if (ad_reg & 0x80) 945 mode = AXGBE_MODE_KR; 946 else if (ad_reg & 0x20) 947 mode = AXGBE_MODE_KX_1000; 948 else 949 mode = AXGBE_MODE_UNKNOWN; 950 951 /* Compare Advertisement and Link Partner register 3 */ 952 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 953 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 954 if (lp_reg & 0xc000) 955 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 956 957 return mode; 958 } 959 960 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 961 { 962 enum axgbe_mode mode; 963 964 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 965 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 966 967 if (pdata->phy.pause_autoneg) 968 axgbe_phy_phydev_flowctrl(pdata); 969 970 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 971 case AXGBE_SGMII_AN_LINK_SPEED_100: 972 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 973 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 974 mode = AXGBE_MODE_SGMII_100; 975 } else { 976 mode = AXGBE_MODE_UNKNOWN; 977 } 978 break; 979 case AXGBE_SGMII_AN_LINK_SPEED_1000: 980 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 981 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 982 mode = AXGBE_MODE_SGMII_1000; 983 } else { 984 /* Half-duplex not supported */ 985 mode = AXGBE_MODE_UNKNOWN; 986 } 987 break; 988 default: 989 mode = AXGBE_MODE_UNKNOWN; 990 break; 991 } 992 return mode; 993 } 994 995 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 996 { 997 switch (pdata->an_mode) { 998 case AXGBE_AN_MODE_CL73: 999 return axgbe_phy_an73_outcome(pdata); 1000 case AXGBE_AN_MODE_CL73_REDRV: 1001 return axgbe_phy_an73_redrv_outcome(pdata); 1002 case AXGBE_AN_MODE_CL37: 1003 case AXGBE_AN_MODE_CL37_SGMII: 1004 return axgbe_phy_an37_sgmii_outcome(pdata); 1005 default: 1006 return AXGBE_MODE_UNKNOWN; 1007 } 1008 } 1009 1010 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1011 { 1012 struct axgbe_phy_data *phy_data = pdata->phy_data; 1013 unsigned int advertising; 1014 1015 /* Without a re-driver, just return current advertising */ 1016 if (!phy_data->redrv) 1017 return pdata->phy.advertising; 1018 1019 /* With the KR re-driver we need to advertise a single speed */ 1020 advertising = pdata->phy.advertising; 1021 advertising &= ~ADVERTISED_1000baseKX_Full; 1022 advertising &= ~ADVERTISED_10000baseKR_Full; 1023 1024 switch (phy_data->port_mode) { 1025 case AXGBE_PORT_MODE_BACKPLANE: 1026 advertising |= ADVERTISED_10000baseKR_Full; 1027 break; 1028 case AXGBE_PORT_MODE_BACKPLANE_2500: 1029 advertising |= ADVERTISED_1000baseKX_Full; 1030 break; 1031 case AXGBE_PORT_MODE_1000BASE_T: 1032 case AXGBE_PORT_MODE_1000BASE_X: 1033 case AXGBE_PORT_MODE_NBASE_T: 1034 advertising |= ADVERTISED_1000baseKX_Full; 1035 break; 1036 case AXGBE_PORT_MODE_10GBASE_T: 1037 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1038 break; 1039 case AXGBE_PORT_MODE_10GBASE_R: 1040 advertising |= ADVERTISED_10000baseKR_Full; 1041 break; 1042 case AXGBE_PORT_MODE_SFP: 1043 switch (phy_data->sfp_base) { 1044 case AXGBE_SFP_BASE_1000_T: 1045 case AXGBE_SFP_BASE_1000_SX: 1046 case AXGBE_SFP_BASE_1000_LX: 1047 case AXGBE_SFP_BASE_1000_CX: 1048 advertising |= ADVERTISED_1000baseKX_Full; 1049 break; 1050 default: 1051 advertising |= ADVERTISED_10000baseKR_Full; 1052 break; 1053 } 1054 break; 1055 default: 1056 advertising |= ADVERTISED_10000baseKR_Full; 1057 break; 1058 } 1059 1060 return advertising; 1061 } 1062 1063 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1064 { 1065 return 0; 1066 /* Dummy API since there is no case to support 1067 * external phy devices registred through kerenl apis 1068 */ 1069 } 1070 1071 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1072 { 1073 switch (phy_data->sfp_base) { 1074 case AXGBE_SFP_BASE_1000_T: 1075 return AXGBE_AN_MODE_CL37_SGMII; 1076 case AXGBE_SFP_BASE_1000_SX: 1077 case AXGBE_SFP_BASE_1000_LX: 1078 case AXGBE_SFP_BASE_1000_CX: 1079 return AXGBE_AN_MODE_CL37; 1080 default: 1081 return AXGBE_AN_MODE_NONE; 1082 } 1083 } 1084 1085 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1086 { 1087 struct axgbe_phy_data *phy_data = pdata->phy_data; 1088 1089 /* A KR re-driver will always require CL73 AN */ 1090 if (phy_data->redrv) 1091 return AXGBE_AN_MODE_CL73_REDRV; 1092 1093 switch (phy_data->port_mode) { 1094 case AXGBE_PORT_MODE_BACKPLANE: 1095 return AXGBE_AN_MODE_CL73; 1096 case AXGBE_PORT_MODE_BACKPLANE_2500: 1097 return AXGBE_AN_MODE_NONE; 1098 case AXGBE_PORT_MODE_1000BASE_T: 1099 return AXGBE_AN_MODE_CL37_SGMII; 1100 case AXGBE_PORT_MODE_1000BASE_X: 1101 return AXGBE_AN_MODE_CL37; 1102 case AXGBE_PORT_MODE_NBASE_T: 1103 return AXGBE_AN_MODE_CL37_SGMII; 1104 case AXGBE_PORT_MODE_10GBASE_T: 1105 return AXGBE_AN_MODE_CL73; 1106 case AXGBE_PORT_MODE_10GBASE_R: 1107 return AXGBE_AN_MODE_NONE; 1108 case AXGBE_PORT_MODE_SFP: 1109 return axgbe_phy_an_sfp_mode(phy_data); 1110 default: 1111 return AXGBE_AN_MODE_NONE; 1112 } 1113 } 1114 1115 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1116 enum axgbe_phy_redrv_mode mode) 1117 { 1118 struct axgbe_phy_data *phy_data = pdata->phy_data; 1119 u16 redrv_reg, redrv_val; 1120 1121 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1122 redrv_val = (u16)mode; 1123 1124 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1125 redrv_reg, redrv_val); 1126 } 1127 1128 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1129 enum axgbe_phy_redrv_mode mode) 1130 { 1131 struct axgbe_phy_data *phy_data = pdata->phy_data; 1132 unsigned int redrv_reg; 1133 int ret; 1134 1135 /* Calculate the register to write */ 1136 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1137 1138 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1139 1140 return ret; 1141 } 1142 1143 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1144 { 1145 struct axgbe_phy_data *phy_data = pdata->phy_data; 1146 enum axgbe_phy_redrv_mode mode; 1147 int ret; 1148 1149 if (!phy_data->redrv) 1150 return; 1151 1152 mode = AXGBE_PHY_REDRV_MODE_CX; 1153 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1154 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1155 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1156 mode = AXGBE_PHY_REDRV_MODE_SR; 1157 1158 ret = axgbe_phy_get_comm_ownership(pdata); 1159 if (ret) 1160 return; 1161 1162 if (phy_data->redrv_if) 1163 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1164 else 1165 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1166 1167 axgbe_phy_put_comm_ownership(pdata); 1168 } 1169 1170 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) 1171 { 1172 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1173 return; 1174 } 1175 1176 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata) 1177 { 1178 unsigned int wait; 1179 1180 /* Wait for command to complete */ 1181 wait = AXGBE_RATECHANGE_COUNT; 1182 while (wait--) { 1183 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1184 return; 1185 1186 rte_delay_us(1500); 1187 } 1188 } 1189 1190 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1191 { 1192 unsigned int s0; 1193 1194 axgbe_phy_start_ratechange(pdata); 1195 1196 /* Receiver Reset Cycle */ 1197 s0 = 0; 1198 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5); 1199 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1200 1201 /* Call FW to make the change */ 1202 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1203 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1204 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1205 1206 axgbe_phy_complete_ratechange(pdata); 1207 } 1208 1209 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1210 { 1211 struct axgbe_phy_data *phy_data = pdata->phy_data; 1212 1213 axgbe_phy_start_ratechange(pdata); 1214 1215 /* Call FW to make the change */ 1216 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0); 1217 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1218 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1219 axgbe_phy_complete_ratechange(pdata); 1220 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1221 } 1222 1223 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1224 { 1225 struct axgbe_phy_data *phy_data = pdata->phy_data; 1226 unsigned int s0; 1227 1228 axgbe_phy_set_redrv_mode(pdata); 1229 1230 axgbe_phy_start_ratechange(pdata); 1231 1232 /* 10G/SFI */ 1233 s0 = 0; 1234 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3); 1235 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1236 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1237 } else { 1238 if (phy_data->sfp_cable_len <= 1) 1239 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1); 1240 else if (phy_data->sfp_cable_len <= 3) 1241 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1242 else 1243 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3); 1244 } 1245 1246 /* Call FW to make the change */ 1247 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1248 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1249 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1250 axgbe_phy_complete_ratechange(pdata); 1251 phy_data->cur_mode = AXGBE_MODE_SFI; 1252 } 1253 1254 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1255 { 1256 struct axgbe_phy_data *phy_data = pdata->phy_data; 1257 unsigned int s0; 1258 1259 axgbe_phy_set_redrv_mode(pdata); 1260 1261 axgbe_phy_start_ratechange(pdata); 1262 1263 /* 10G/KR */ 1264 s0 = 0; 1265 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4); 1266 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1267 1268 /* Call FW to make the change */ 1269 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1270 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1271 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1272 axgbe_phy_complete_ratechange(pdata); 1273 phy_data->cur_mode = AXGBE_MODE_KR; 1274 } 1275 1276 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1277 { 1278 struct axgbe_phy_data *phy_data = pdata->phy_data; 1279 unsigned int s0; 1280 1281 axgbe_phy_set_redrv_mode(pdata); 1282 /* 2.5G/KX */ 1283 axgbe_phy_start_ratechange(pdata); 1284 s0 = 0; 1285 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2); 1286 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1287 1288 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1289 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1290 1291 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1292 1293 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1294 } 1295 1296 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1297 { 1298 struct axgbe_phy_data *phy_data = pdata->phy_data; 1299 unsigned int s0; 1300 1301 axgbe_phy_set_redrv_mode(pdata); 1302 1303 /* 1G/SGMII */ 1304 axgbe_phy_start_ratechange(pdata); 1305 s0 = 0; 1306 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1); 1307 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1308 1309 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1310 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1311 1312 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1313 1314 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1315 } 1316 1317 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1318 { 1319 struct axgbe_phy_data *phy_data = pdata->phy_data; 1320 1321 return phy_data->cur_mode; 1322 } 1323 1324 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1325 { 1326 struct axgbe_phy_data *phy_data = pdata->phy_data; 1327 1328 /* No switching if not 10GBase-T */ 1329 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1330 return axgbe_phy_cur_mode(pdata); 1331 1332 switch (axgbe_phy_cur_mode(pdata)) { 1333 case AXGBE_MODE_SGMII_100: 1334 case AXGBE_MODE_SGMII_1000: 1335 return AXGBE_MODE_KR; 1336 case AXGBE_MODE_KR: 1337 default: 1338 return AXGBE_MODE_SGMII_1000; 1339 } 1340 } 1341 1342 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1343 __rte_unused) 1344 { 1345 return AXGBE_MODE_KX_2500; 1346 } 1347 1348 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1349 { 1350 /* If we are in KR switch to KX, and vice-versa */ 1351 switch (axgbe_phy_cur_mode(pdata)) { 1352 case AXGBE_MODE_KX_1000: 1353 return AXGBE_MODE_KR; 1354 case AXGBE_MODE_KR: 1355 default: 1356 return AXGBE_MODE_KX_1000; 1357 } 1358 } 1359 1360 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1361 { 1362 struct axgbe_phy_data *phy_data = pdata->phy_data; 1363 1364 switch (phy_data->port_mode) { 1365 case AXGBE_PORT_MODE_BACKPLANE: 1366 return axgbe_phy_switch_bp_mode(pdata); 1367 case AXGBE_PORT_MODE_BACKPLANE_2500: 1368 return axgbe_phy_switch_bp_2500_mode(pdata); 1369 case AXGBE_PORT_MODE_1000BASE_T: 1370 case AXGBE_PORT_MODE_NBASE_T: 1371 case AXGBE_PORT_MODE_10GBASE_T: 1372 return axgbe_phy_switch_baset_mode(pdata); 1373 case AXGBE_PORT_MODE_1000BASE_X: 1374 case AXGBE_PORT_MODE_10GBASE_R: 1375 case AXGBE_PORT_MODE_SFP: 1376 /* No switching, so just return current mode */ 1377 return axgbe_phy_cur_mode(pdata); 1378 default: 1379 return AXGBE_MODE_UNKNOWN; 1380 } 1381 } 1382 1383 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1384 __rte_unused, 1385 int speed) 1386 { 1387 switch (speed) { 1388 case SPEED_1000: 1389 return AXGBE_MODE_X; 1390 case SPEED_10000: 1391 return AXGBE_MODE_KR; 1392 default: 1393 return AXGBE_MODE_UNKNOWN; 1394 } 1395 } 1396 1397 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1398 __rte_unused, 1399 int speed) 1400 { 1401 switch (speed) { 1402 case SPEED_100: 1403 return AXGBE_MODE_SGMII_100; 1404 case SPEED_1000: 1405 return AXGBE_MODE_SGMII_1000; 1406 case SPEED_10000: 1407 return AXGBE_MODE_KR; 1408 default: 1409 return AXGBE_MODE_UNKNOWN; 1410 } 1411 } 1412 1413 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1414 int speed) 1415 { 1416 switch (speed) { 1417 case SPEED_100: 1418 return AXGBE_MODE_SGMII_100; 1419 case SPEED_1000: 1420 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1421 return AXGBE_MODE_SGMII_1000; 1422 else 1423 return AXGBE_MODE_X; 1424 case SPEED_10000: 1425 case SPEED_UNKNOWN: 1426 return AXGBE_MODE_SFI; 1427 default: 1428 return AXGBE_MODE_UNKNOWN; 1429 } 1430 } 1431 1432 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1433 { 1434 switch (speed) { 1435 case SPEED_2500: 1436 return AXGBE_MODE_KX_2500; 1437 default: 1438 return AXGBE_MODE_UNKNOWN; 1439 } 1440 } 1441 1442 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1443 { 1444 switch (speed) { 1445 case SPEED_1000: 1446 return AXGBE_MODE_KX_1000; 1447 case SPEED_10000: 1448 return AXGBE_MODE_KR; 1449 default: 1450 return AXGBE_MODE_UNKNOWN; 1451 } 1452 } 1453 1454 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1455 int speed) 1456 { 1457 struct axgbe_phy_data *phy_data = pdata->phy_data; 1458 1459 switch (phy_data->port_mode) { 1460 case AXGBE_PORT_MODE_BACKPLANE: 1461 return axgbe_phy_get_bp_mode(speed); 1462 case AXGBE_PORT_MODE_BACKPLANE_2500: 1463 return axgbe_phy_get_bp_2500_mode(speed); 1464 case AXGBE_PORT_MODE_1000BASE_T: 1465 case AXGBE_PORT_MODE_NBASE_T: 1466 case AXGBE_PORT_MODE_10GBASE_T: 1467 return axgbe_phy_get_baset_mode(phy_data, speed); 1468 case AXGBE_PORT_MODE_1000BASE_X: 1469 case AXGBE_PORT_MODE_10GBASE_R: 1470 return axgbe_phy_get_basex_mode(phy_data, speed); 1471 case AXGBE_PORT_MODE_SFP: 1472 return axgbe_phy_get_sfp_mode(phy_data, speed); 1473 default: 1474 return AXGBE_MODE_UNKNOWN; 1475 } 1476 } 1477 1478 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1479 { 1480 switch (mode) { 1481 case AXGBE_MODE_KR: 1482 axgbe_phy_kr_mode(pdata); 1483 break; 1484 case AXGBE_MODE_SFI: 1485 axgbe_phy_sfi_mode(pdata); 1486 break; 1487 case AXGBE_MODE_KX_2500: 1488 axgbe_phy_kx_2500_mode(pdata); 1489 break; 1490 case AXGBE_MODE_SGMII_1000: 1491 axgbe_phy_sgmii_1000_mode(pdata); 1492 break; 1493 default: 1494 break; 1495 } 1496 } 1497 1498 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1499 enum axgbe_mode mode, u32 advert) 1500 { 1501 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1502 if (pdata->phy.advertising & advert) 1503 return true; 1504 } else { 1505 enum axgbe_mode cur_mode; 1506 1507 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1508 if (cur_mode == mode) 1509 return true; 1510 } 1511 1512 return false; 1513 } 1514 1515 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1516 enum axgbe_mode mode) 1517 { 1518 switch (mode) { 1519 case AXGBE_MODE_X: 1520 return axgbe_phy_check_mode(pdata, mode, 1521 ADVERTISED_1000baseT_Full); 1522 case AXGBE_MODE_KR: 1523 return axgbe_phy_check_mode(pdata, mode, 1524 ADVERTISED_10000baseT_Full); 1525 default: 1526 return false; 1527 } 1528 } 1529 1530 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1531 enum axgbe_mode mode) 1532 { 1533 switch (mode) { 1534 case AXGBE_MODE_SGMII_100: 1535 return axgbe_phy_check_mode(pdata, mode, 1536 ADVERTISED_100baseT_Full); 1537 case AXGBE_MODE_SGMII_1000: 1538 return axgbe_phy_check_mode(pdata, mode, 1539 ADVERTISED_1000baseT_Full); 1540 case AXGBE_MODE_KR: 1541 return axgbe_phy_check_mode(pdata, mode, 1542 ADVERTISED_10000baseT_Full); 1543 default: 1544 return false; 1545 } 1546 } 1547 1548 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1549 enum axgbe_mode mode) 1550 { 1551 struct axgbe_phy_data *phy_data = pdata->phy_data; 1552 1553 switch (mode) { 1554 case AXGBE_MODE_X: 1555 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1556 return false; 1557 return axgbe_phy_check_mode(pdata, mode, 1558 ADVERTISED_1000baseT_Full); 1559 case AXGBE_MODE_SGMII_100: 1560 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1561 return false; 1562 return axgbe_phy_check_mode(pdata, mode, 1563 ADVERTISED_100baseT_Full); 1564 case AXGBE_MODE_SGMII_1000: 1565 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1566 return false; 1567 return axgbe_phy_check_mode(pdata, mode, 1568 ADVERTISED_1000baseT_Full); 1569 case AXGBE_MODE_SFI: 1570 return axgbe_phy_check_mode(pdata, mode, 1571 ADVERTISED_10000baseT_Full); 1572 default: 1573 return false; 1574 } 1575 } 1576 1577 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1578 enum axgbe_mode mode) 1579 { 1580 switch (mode) { 1581 case AXGBE_MODE_KX_2500: 1582 return axgbe_phy_check_mode(pdata, mode, 1583 ADVERTISED_2500baseX_Full); 1584 default: 1585 return false; 1586 } 1587 } 1588 1589 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1590 enum axgbe_mode mode) 1591 { 1592 switch (mode) { 1593 case AXGBE_MODE_KX_1000: 1594 return axgbe_phy_check_mode(pdata, mode, 1595 ADVERTISED_1000baseKX_Full); 1596 case AXGBE_MODE_KR: 1597 return axgbe_phy_check_mode(pdata, mode, 1598 ADVERTISED_10000baseKR_Full); 1599 default: 1600 return false; 1601 } 1602 } 1603 1604 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1605 { 1606 struct axgbe_phy_data *phy_data = pdata->phy_data; 1607 1608 switch (phy_data->port_mode) { 1609 case AXGBE_PORT_MODE_BACKPLANE: 1610 return axgbe_phy_use_bp_mode(pdata, mode); 1611 case AXGBE_PORT_MODE_BACKPLANE_2500: 1612 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1613 case AXGBE_PORT_MODE_1000BASE_T: 1614 case AXGBE_PORT_MODE_NBASE_T: 1615 case AXGBE_PORT_MODE_10GBASE_T: 1616 return axgbe_phy_use_baset_mode(pdata, mode); 1617 case AXGBE_PORT_MODE_1000BASE_X: 1618 case AXGBE_PORT_MODE_10GBASE_R: 1619 return axgbe_phy_use_basex_mode(pdata, mode); 1620 case AXGBE_PORT_MODE_SFP: 1621 return axgbe_phy_use_sfp_mode(pdata, mode); 1622 default: 1623 return false; 1624 } 1625 } 1626 1627 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1628 { 1629 struct axgbe_phy_data *phy_data = pdata->phy_data; 1630 unsigned int reg; 1631 1632 *an_restart = 0; 1633 1634 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1635 /* Check SFP signals */ 1636 axgbe_phy_sfp_detect(pdata); 1637 1638 if (phy_data->sfp_changed) { 1639 *an_restart = 1; 1640 return 0; 1641 } 1642 1643 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1644 return 0; 1645 } 1646 1647 /* Link status is latched low, so read once to clear 1648 * and then read again to get current state 1649 */ 1650 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1651 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1652 if (reg & MDIO_STAT1_LSTATUS) 1653 return 1; 1654 1655 /* No link, attempt a receiver reset cycle */ 1656 if (phy_data->rrc_count++) { 1657 phy_data->rrc_count = 0; 1658 axgbe_phy_rrc(pdata); 1659 } 1660 1661 return 0; 1662 } 1663 1664 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1665 { 1666 struct axgbe_phy_data *phy_data = pdata->phy_data; 1667 unsigned int reg; 1668 1669 reg = XP_IOREAD(pdata, XP_PROP_3); 1670 1671 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1672 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 1673 1674 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 1675 1676 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 1677 GPIO_RX_LOS); 1678 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 1679 GPIO_TX_FAULT); 1680 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 1681 GPIO_MOD_ABS); 1682 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 1683 GPIO_RATE_SELECT); 1684 } 1685 1686 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1687 { 1688 struct axgbe_phy_data *phy_data = pdata->phy_data; 1689 unsigned int reg, mux_addr_hi, mux_addr_lo; 1690 1691 reg = XP_IOREAD(pdata, XP_PROP_4); 1692 1693 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 1694 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 1695 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1696 return; 1697 1698 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1699 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1700 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 1701 } 1702 1703 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1704 { 1705 axgbe_phy_sfp_comm_setup(pdata); 1706 axgbe_phy_sfp_gpio_setup(pdata); 1707 } 1708 1709 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1710 { 1711 if (!phy_data->redrv) 1712 return false; 1713 1714 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1715 return true; 1716 1717 switch (phy_data->redrv_model) { 1718 case AXGBE_PHY_REDRV_MODEL_4223: 1719 if (phy_data->redrv_lane > 3) 1720 return true; 1721 break; 1722 case AXGBE_PHY_REDRV_MODEL_4227: 1723 if (phy_data->redrv_lane > 1) 1724 return true; 1725 break; 1726 default: 1727 return true; 1728 } 1729 1730 return false; 1731 } 1732 1733 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1734 { 1735 struct axgbe_phy_data *phy_data = pdata->phy_data; 1736 unsigned int reg; 1737 1738 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1739 return 0; 1740 reg = XP_IOREAD(pdata, XP_PROP_3); 1741 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 1742 switch (phy_data->mdio_reset) { 1743 case AXGBE_MDIO_RESET_NONE: 1744 case AXGBE_MDIO_RESET_I2C_GPIO: 1745 case AXGBE_MDIO_RESET_INT_GPIO: 1746 break; 1747 default: 1748 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1749 phy_data->mdio_reset); 1750 return -EINVAL; 1751 } 1752 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1753 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1754 XP_GET_BITS(reg, XP_PROP_3, 1755 MDIO_RESET_I2C_ADDR); 1756 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1757 MDIO_RESET_I2C_GPIO); 1758 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1759 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1760 MDIO_RESET_INT_GPIO); 1761 } 1762 1763 return 0; 1764 } 1765 1766 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1767 { 1768 struct axgbe_phy_data *phy_data = pdata->phy_data; 1769 1770 switch (phy_data->port_mode) { 1771 case AXGBE_PORT_MODE_BACKPLANE: 1772 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1773 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1774 return false; 1775 break; 1776 case AXGBE_PORT_MODE_BACKPLANE_2500: 1777 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1778 return false; 1779 break; 1780 case AXGBE_PORT_MODE_1000BASE_T: 1781 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1782 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1783 return false; 1784 break; 1785 case AXGBE_PORT_MODE_1000BASE_X: 1786 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1787 return false; 1788 break; 1789 case AXGBE_PORT_MODE_NBASE_T: 1790 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1791 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1792 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1793 return false; 1794 break; 1795 case AXGBE_PORT_MODE_10GBASE_T: 1796 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1797 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1798 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1799 return false; 1800 break; 1801 case AXGBE_PORT_MODE_10GBASE_R: 1802 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1803 return false; 1804 break; 1805 case AXGBE_PORT_MODE_SFP: 1806 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1807 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1808 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1809 return false; 1810 break; 1811 default: 1812 break; 1813 } 1814 1815 return true; 1816 } 1817 1818 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1819 { 1820 struct axgbe_phy_data *phy_data = pdata->phy_data; 1821 1822 switch (phy_data->port_mode) { 1823 case AXGBE_PORT_MODE_BACKPLANE: 1824 case AXGBE_PORT_MODE_BACKPLANE_2500: 1825 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1826 return false; 1827 break; 1828 case AXGBE_PORT_MODE_1000BASE_T: 1829 case AXGBE_PORT_MODE_1000BASE_X: 1830 case AXGBE_PORT_MODE_NBASE_T: 1831 case AXGBE_PORT_MODE_10GBASE_T: 1832 case AXGBE_PORT_MODE_10GBASE_R: 1833 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1834 return false; 1835 break; 1836 case AXGBE_PORT_MODE_SFP: 1837 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1838 return false; 1839 break; 1840 default: 1841 break; 1842 } 1843 1844 return true; 1845 } 1846 1847 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1848 { 1849 unsigned int reg; 1850 1851 reg = XP_IOREAD(pdata, XP_PROP_0); 1852 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 1853 return false; 1854 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 1855 return false; 1856 1857 return true; 1858 } 1859 1860 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1861 { 1862 struct axgbe_phy_data *phy_data = pdata->phy_data; 1863 1864 if (!pdata->vdata->an_cdr_workaround) 1865 return; 1866 1867 if (!phy_data->phy_cdr_notrack) 1868 return; 1869 1870 rte_delay_us(phy_data->phy_cdr_delay + 400); 1871 1872 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1873 AXGBE_PMA_CDR_TRACK_EN_MASK, 1874 AXGBE_PMA_CDR_TRACK_EN_ON); 1875 1876 phy_data->phy_cdr_notrack = 0; 1877 } 1878 1879 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1880 { 1881 struct axgbe_phy_data *phy_data = pdata->phy_data; 1882 1883 if (!pdata->vdata->an_cdr_workaround) 1884 return; 1885 1886 if (phy_data->phy_cdr_notrack) 1887 return; 1888 1889 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1890 AXGBE_PMA_CDR_TRACK_EN_MASK, 1891 AXGBE_PMA_CDR_TRACK_EN_OFF); 1892 1893 axgbe_phy_rrc(pdata); 1894 1895 phy_data->phy_cdr_notrack = 1; 1896 } 1897 1898 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1899 { 1900 if (!pdata->cdr_track_early) 1901 axgbe_phy_cdr_track(pdata); 1902 } 1903 1904 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1905 { 1906 if (pdata->cdr_track_early) 1907 axgbe_phy_cdr_track(pdata); 1908 } 1909 1910 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1911 { 1912 struct axgbe_phy_data *phy_data = pdata->phy_data; 1913 1914 switch (pdata->an_mode) { 1915 case AXGBE_AN_MODE_CL73: 1916 case AXGBE_AN_MODE_CL73_REDRV: 1917 if (phy_data->cur_mode != AXGBE_MODE_KR) 1918 break; 1919 1920 axgbe_phy_cdr_track(pdata); 1921 1922 switch (pdata->an_result) { 1923 case AXGBE_AN_READY: 1924 case AXGBE_AN_COMPLETE: 1925 break; 1926 default: 1927 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1928 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1929 break; 1930 } 1931 break; 1932 default: 1933 break; 1934 } 1935 } 1936 1937 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1938 { 1939 struct axgbe_phy_data *phy_data = pdata->phy_data; 1940 1941 switch (pdata->an_mode) { 1942 case AXGBE_AN_MODE_CL73: 1943 case AXGBE_AN_MODE_CL73_REDRV: 1944 if (phy_data->cur_mode != AXGBE_MODE_KR) 1945 break; 1946 1947 axgbe_phy_cdr_notrack(pdata); 1948 break; 1949 default: 1950 break; 1951 } 1952 } 1953 1954 static void axgbe_phy_stop(struct axgbe_port *pdata) 1955 { 1956 struct axgbe_phy_data *phy_data = pdata->phy_data; 1957 1958 /* Reset SFP data */ 1959 axgbe_phy_sfp_reset(phy_data); 1960 axgbe_phy_sfp_mod_absent(pdata); 1961 1962 /* Reset CDR support */ 1963 axgbe_phy_cdr_track(pdata); 1964 1965 /* Power off the PHY */ 1966 axgbe_phy_power_off(pdata); 1967 1968 /* Stop the I2C controller */ 1969 pdata->i2c_if.i2c_stop(pdata); 1970 } 1971 1972 static int axgbe_phy_start(struct axgbe_port *pdata) 1973 { 1974 struct axgbe_phy_data *phy_data = pdata->phy_data; 1975 int ret; 1976 1977 /* Start the I2C controller */ 1978 ret = pdata->i2c_if.i2c_start(pdata); 1979 if (ret) 1980 return ret; 1981 1982 /* Start in highest supported mode */ 1983 axgbe_phy_set_mode(pdata, phy_data->start_mode); 1984 1985 /* Reset CDR support */ 1986 axgbe_phy_cdr_track(pdata); 1987 1988 /* After starting the I2C controller, we can check for an SFP */ 1989 switch (phy_data->port_mode) { 1990 case AXGBE_PORT_MODE_SFP: 1991 axgbe_phy_sfp_detect(pdata); 1992 break; 1993 default: 1994 break; 1995 } 1996 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 1997 1998 return ret; 1999 } 2000 2001 static int axgbe_phy_reset(struct axgbe_port *pdata) 2002 { 2003 struct axgbe_phy_data *phy_data = pdata->phy_data; 2004 enum axgbe_mode cur_mode; 2005 2006 /* Reset by power cycling the PHY */ 2007 cur_mode = phy_data->cur_mode; 2008 axgbe_phy_power_off(pdata); 2009 /* First time reset is done with passed unknown mode*/ 2010 axgbe_phy_set_mode(pdata, cur_mode); 2011 return 0; 2012 } 2013 2014 static int axgbe_phy_init(struct axgbe_port *pdata) 2015 { 2016 struct axgbe_phy_data *phy_data; 2017 unsigned int reg; 2018 int ret; 2019 2020 /* Check if enabled */ 2021 if (!axgbe_phy_port_enabled(pdata)) { 2022 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2023 return -ENODEV; 2024 } 2025 2026 /* Initialize the I2C controller */ 2027 ret = pdata->i2c_if.i2c_init(pdata); 2028 if (ret) 2029 return ret; 2030 2031 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2032 if (!phy_data) { 2033 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2034 return -ENOMEM; 2035 } 2036 pdata->phy_data = phy_data; 2037 2038 reg = XP_IOREAD(pdata, XP_PROP_0); 2039 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2040 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2041 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2042 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2043 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2044 2045 reg = XP_IOREAD(pdata, XP_PROP_4); 2046 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2047 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2048 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2049 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2050 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2051 2052 /* Validate the connection requested */ 2053 if (axgbe_phy_conn_type_mismatch(pdata)) { 2054 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2055 phy_data->port_mode, phy_data->conn_type); 2056 return -EINVAL; 2057 } 2058 2059 /* Validate the mode requested */ 2060 if (axgbe_phy_port_mode_mismatch(pdata)) { 2061 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2062 phy_data->port_mode, phy_data->port_speeds); 2063 return -EINVAL; 2064 } 2065 2066 /* Check for and validate MDIO reset support */ 2067 ret = axgbe_phy_mdio_reset_setup(pdata); 2068 if (ret) 2069 return ret; 2070 2071 /* Validate the re-driver information */ 2072 if (axgbe_phy_redrv_error(phy_data)) { 2073 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2074 return -EINVAL; 2075 } 2076 pdata->kr_redrv = phy_data->redrv; 2077 2078 /* Indicate current mode is unknown */ 2079 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2080 2081 /* Initialize supported features */ 2082 pdata->phy.supported = 0; 2083 2084 switch (phy_data->port_mode) { 2085 /* Backplane support */ 2086 case AXGBE_PORT_MODE_BACKPLANE: 2087 pdata->phy.supported |= SUPPORTED_Autoneg; 2088 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2089 pdata->phy.supported |= SUPPORTED_Backplane; 2090 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2091 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2092 phy_data->start_mode = AXGBE_MODE_KX_1000; 2093 } 2094 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2095 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2096 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2097 pdata->phy.supported |= 2098 SUPPORTED_10000baseR_FEC; 2099 phy_data->start_mode = AXGBE_MODE_KR; 2100 } 2101 2102 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2103 break; 2104 case AXGBE_PORT_MODE_BACKPLANE_2500: 2105 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2106 pdata->phy.supported |= SUPPORTED_Backplane; 2107 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2108 phy_data->start_mode = AXGBE_MODE_KX_2500; 2109 2110 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2111 break; 2112 2113 /* MDIO 1GBase-T support */ 2114 case AXGBE_PORT_MODE_1000BASE_T: 2115 pdata->phy.supported |= SUPPORTED_Autoneg; 2116 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2117 pdata->phy.supported |= SUPPORTED_TP; 2118 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2119 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2120 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2121 } 2122 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2123 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2124 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2125 } 2126 2127 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2128 break; 2129 2130 /* MDIO Base-X support */ 2131 case AXGBE_PORT_MODE_1000BASE_X: 2132 pdata->phy.supported |= SUPPORTED_Autoneg; 2133 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2134 pdata->phy.supported |= SUPPORTED_FIBRE; 2135 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2136 phy_data->start_mode = AXGBE_MODE_X; 2137 2138 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2139 break; 2140 2141 /* MDIO NBase-T support */ 2142 case AXGBE_PORT_MODE_NBASE_T: 2143 pdata->phy.supported |= SUPPORTED_Autoneg; 2144 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2145 pdata->phy.supported |= SUPPORTED_TP; 2146 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2147 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2148 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2149 } 2150 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2151 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2152 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2153 } 2154 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2155 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2156 phy_data->start_mode = AXGBE_MODE_KX_2500; 2157 } 2158 2159 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2160 break; 2161 2162 /* 10GBase-T support */ 2163 case AXGBE_PORT_MODE_10GBASE_T: 2164 pdata->phy.supported |= SUPPORTED_Autoneg; 2165 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2166 pdata->phy.supported |= SUPPORTED_TP; 2167 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2168 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2169 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2170 } 2171 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2172 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2173 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2174 } 2175 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2176 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2177 phy_data->start_mode = AXGBE_MODE_KR; 2178 } 2179 2180 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2181 break; 2182 2183 /* 10GBase-R support */ 2184 case AXGBE_PORT_MODE_10GBASE_R: 2185 pdata->phy.supported |= SUPPORTED_Autoneg; 2186 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2187 pdata->phy.supported |= SUPPORTED_TP; 2188 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2189 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2190 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2191 phy_data->start_mode = AXGBE_MODE_SFI; 2192 2193 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2194 break; 2195 2196 /* SFP support */ 2197 case AXGBE_PORT_MODE_SFP: 2198 pdata->phy.supported |= SUPPORTED_Autoneg; 2199 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2200 pdata->phy.supported |= SUPPORTED_TP; 2201 pdata->phy.supported |= SUPPORTED_FIBRE; 2202 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2203 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2204 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2205 } 2206 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2207 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2208 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2209 } 2210 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2211 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2212 phy_data->start_mode = AXGBE_MODE_SFI; 2213 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2214 pdata->phy.supported |= 2215 SUPPORTED_10000baseR_FEC; 2216 } 2217 2218 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2219 2220 axgbe_phy_sfp_setup(pdata); 2221 break; 2222 default: 2223 return -EINVAL; 2224 } 2225 2226 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2227 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2228 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2229 phy_data->phydev_mode); 2230 if (ret) { 2231 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2232 phy_data->mdio_addr, phy_data->phydev_mode); 2233 return -EINVAL; 2234 } 2235 } 2236 2237 if (phy_data->redrv && !phy_data->redrv_if) { 2238 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2239 AXGBE_MDIO_MODE_CL22); 2240 if (ret) { 2241 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2242 phy_data->redrv_addr); 2243 return -EINVAL; 2244 } 2245 } 2246 2247 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2248 return 0; 2249 } 2250 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2251 { 2252 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2253 2254 phy_impl->init = axgbe_phy_init; 2255 phy_impl->reset = axgbe_phy_reset; 2256 phy_impl->start = axgbe_phy_start; 2257 phy_impl->stop = axgbe_phy_stop; 2258 phy_impl->link_status = axgbe_phy_link_status; 2259 phy_impl->use_mode = axgbe_phy_use_mode; 2260 phy_impl->set_mode = axgbe_phy_set_mode; 2261 phy_impl->get_mode = axgbe_phy_get_mode; 2262 phy_impl->switch_mode = axgbe_phy_switch_mode; 2263 phy_impl->cur_mode = axgbe_phy_cur_mode; 2264 phy_impl->an_mode = axgbe_phy_an_mode; 2265 phy_impl->an_config = axgbe_phy_an_config; 2266 phy_impl->an_advertising = axgbe_phy_an_advertising; 2267 phy_impl->an_outcome = axgbe_phy_an_outcome; 2268 2269 phy_impl->an_pre = axgbe_phy_an_pre; 2270 phy_impl->an_post = axgbe_phy_an_post; 2271 2272 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2273 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2274 } 2275