1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(1) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(2) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(3) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(4) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 50 AXGBE_PORT_MODE_MAX, 51 }; 52 53 enum axgbe_conn_type { 54 AXGBE_CONN_TYPE_NONE = 0, 55 AXGBE_CONN_TYPE_SFP, 56 AXGBE_CONN_TYPE_MDIO, 57 AXGBE_CONN_TYPE_RSVD1, 58 AXGBE_CONN_TYPE_BACKPLANE, 59 AXGBE_CONN_TYPE_MAX, 60 }; 61 62 /* SFP/SFP+ related definitions */ 63 enum axgbe_sfp_comm { 64 AXGBE_SFP_COMM_DIRECT = 0, 65 AXGBE_SFP_COMM_PCA9545, 66 }; 67 68 enum axgbe_sfp_cable { 69 AXGBE_SFP_CABLE_UNKNOWN = 0, 70 AXGBE_SFP_CABLE_ACTIVE, 71 AXGBE_SFP_CABLE_PASSIVE, 72 AXGBE_SFP_CABLE_FIBER, 73 }; 74 75 enum axgbe_sfp_base { 76 AXGBE_SFP_BASE_UNKNOWN = 0, 77 AXGBE_SFP_BASE_1000_T, 78 AXGBE_SFP_BASE_1000_SX, 79 AXGBE_SFP_BASE_1000_LX, 80 AXGBE_SFP_BASE_1000_CX, 81 AXGBE_SFP_BASE_10000_SR, 82 AXGBE_SFP_BASE_10000_LR, 83 AXGBE_SFP_BASE_10000_LRM, 84 AXGBE_SFP_BASE_10000_ER, 85 AXGBE_SFP_BASE_10000_CR, 86 }; 87 88 enum axgbe_sfp_speed { 89 AXGBE_SFP_SPEED_UNKNOWN = 0, 90 AXGBE_SFP_SPEED_100_1000, 91 AXGBE_SFP_SPEED_1000, 92 AXGBE_SFP_SPEED_10000, 93 }; 94 95 /* SFP Serial ID Base ID values relative to an offset of 0 */ 96 #define AXGBE_SFP_BASE_ID 0 97 #define AXGBE_SFP_ID_SFP 0x03 98 99 #define AXGBE_SFP_BASE_EXT_ID 1 100 #define AXGBE_SFP_EXT_ID_SFP 0x04 101 102 #define AXGBE_SFP_BASE_10GBE_CC 3 103 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 104 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 105 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 106 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 107 108 #define AXGBE_SFP_BASE_1GBE_CC 6 109 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 110 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 111 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 112 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 113 114 #define AXGBE_SFP_BASE_CABLE 8 115 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 116 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 117 118 #define AXGBE_SFP_BASE_BR 12 119 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 120 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 121 122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 123 124 #define AXGBE_SFP_BASE_VENDOR_NAME 20 125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 126 #define AXGBE_SFP_BASE_VENDOR_PN 40 127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 128 #define AXGBE_SFP_BASE_VENDOR_REV 56 129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 130 131 #define AXGBE_SFP_BASE_CC 63 132 133 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 134 #define AXGBE_SFP_BASE_VENDOR_SN 4 135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 136 137 #define AXGBE_SFP_EXTD_DIAG 28 138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 139 140 #define AXGBE_SFP_EXTD_SFF_8472 30 141 142 #define AXGBE_SFP_EXTD_CC 31 143 144 struct axgbe_sfp_eeprom { 145 u8 base[64]; 146 u8 extd[32]; 147 u8 vendor[32]; 148 }; 149 150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 152 153 struct axgbe_sfp_ascii { 154 union { 155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 159 } u; 160 }; 161 162 /* MDIO PHY reset types */ 163 enum axgbe_mdio_reset { 164 AXGBE_MDIO_RESET_NONE = 0, 165 AXGBE_MDIO_RESET_I2C_GPIO, 166 AXGBE_MDIO_RESET_INT_GPIO, 167 AXGBE_MDIO_RESET_MAX, 168 }; 169 170 /* Re-driver related definitions */ 171 enum axgbe_phy_redrv_if { 172 AXGBE_PHY_REDRV_IF_MDIO = 0, 173 AXGBE_PHY_REDRV_IF_I2C, 174 AXGBE_PHY_REDRV_IF_MAX, 175 }; 176 177 enum axgbe_phy_redrv_model { 178 AXGBE_PHY_REDRV_MODEL_4223 = 0, 179 AXGBE_PHY_REDRV_MODEL_4227, 180 AXGBE_PHY_REDRV_MODEL_MAX, 181 }; 182 183 enum axgbe_phy_redrv_mode { 184 AXGBE_PHY_REDRV_MODE_CX = 5, 185 AXGBE_PHY_REDRV_MODE_SR = 9, 186 }; 187 188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 189 190 /* PHY related configuration information */ 191 struct axgbe_phy_data { 192 enum axgbe_port_mode port_mode; 193 194 unsigned int port_id; 195 196 unsigned int port_speeds; 197 198 enum axgbe_conn_type conn_type; 199 200 enum axgbe_mode cur_mode; 201 enum axgbe_mode start_mode; 202 203 unsigned int rrc_count; 204 205 unsigned int mdio_addr; 206 207 /* SFP Support */ 208 enum axgbe_sfp_comm sfp_comm; 209 unsigned int sfp_mux_address; 210 unsigned int sfp_mux_channel; 211 212 unsigned int sfp_gpio_address; 213 unsigned int sfp_gpio_mask; 214 unsigned int sfp_gpio_rx_los; 215 unsigned int sfp_gpio_tx_fault; 216 unsigned int sfp_gpio_mod_absent; 217 unsigned int sfp_gpio_rate_select; 218 219 unsigned int sfp_rx_los; 220 unsigned int sfp_tx_fault; 221 unsigned int sfp_mod_absent; 222 unsigned int sfp_changed; 223 unsigned int sfp_phy_avail; 224 unsigned int sfp_cable_len; 225 enum axgbe_sfp_base sfp_base; 226 enum axgbe_sfp_cable sfp_cable; 227 enum axgbe_sfp_speed sfp_speed; 228 struct axgbe_sfp_eeprom sfp_eeprom; 229 230 /* External PHY support */ 231 enum axgbe_mdio_mode phydev_mode; 232 enum axgbe_mdio_reset mdio_reset; 233 unsigned int mdio_reset_addr; 234 unsigned int mdio_reset_gpio; 235 236 /* Re-driver support */ 237 unsigned int redrv; 238 unsigned int redrv_if; 239 unsigned int redrv_addr; 240 unsigned int redrv_lane; 241 unsigned int redrv_model; 242 243 /* KR AN support */ 244 unsigned int phy_cdr_notrack; 245 unsigned int phy_cdr_delay; 246 }; 247 248 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 249 250 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 251 struct axgbe_i2c_op *i2c_op) 252 { 253 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 254 } 255 256 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 257 unsigned int val) 258 { 259 struct axgbe_phy_data *phy_data = pdata->phy_data; 260 struct axgbe_i2c_op i2c_op; 261 uint16_t *redrv_val; 262 u8 redrv_data[5], csum; 263 unsigned int i, retry; 264 int ret; 265 266 /* High byte of register contains read/write indicator */ 267 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 268 redrv_data[1] = reg & 0xff; 269 redrv_val = (uint16_t *)&redrv_data[2]; 270 *redrv_val = rte_cpu_to_be_16(val); 271 272 /* Calculate 1 byte checksum */ 273 csum = 0; 274 for (i = 0; i < 4; i++) { 275 csum += redrv_data[i]; 276 if (redrv_data[i] > csum) 277 csum++; 278 } 279 redrv_data[4] = ~csum; 280 281 retry = 1; 282 again1: 283 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 284 i2c_op.target = phy_data->redrv_addr; 285 i2c_op.len = sizeof(redrv_data); 286 i2c_op.buf = redrv_data; 287 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 288 if (ret) { 289 if ((ret == -EAGAIN) && retry--) 290 goto again1; 291 292 return ret; 293 } 294 295 retry = 1; 296 again2: 297 i2c_op.cmd = AXGBE_I2C_CMD_READ; 298 i2c_op.target = phy_data->redrv_addr; 299 i2c_op.len = 1; 300 i2c_op.buf = redrv_data; 301 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 302 if (ret) { 303 if ((ret == -EAGAIN) && retry--) 304 goto again2; 305 306 return ret; 307 } 308 309 if (redrv_data[0] != 0xff) { 310 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 311 ret = -EIO; 312 } 313 314 return ret; 315 } 316 317 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 318 void *reg, unsigned int reg_len, 319 void *val, unsigned int val_len) 320 { 321 struct axgbe_i2c_op i2c_op; 322 int retry, ret; 323 324 retry = 1; 325 again1: 326 /* Set the specified register to read */ 327 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 328 i2c_op.target = target; 329 i2c_op.len = reg_len; 330 i2c_op.buf = reg; 331 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 332 if (ret) { 333 if ((ret == -EAGAIN) && retry--) 334 goto again1; 335 336 return ret; 337 } 338 339 retry = 1; 340 again2: 341 /* Read the specified register */ 342 i2c_op.cmd = AXGBE_I2C_CMD_READ; 343 i2c_op.target = target; 344 i2c_op.len = val_len; 345 i2c_op.buf = val; 346 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 347 if ((ret == -EAGAIN) && retry--) 348 goto again2; 349 350 return ret; 351 } 352 353 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 354 { 355 struct axgbe_phy_data *phy_data = pdata->phy_data; 356 struct axgbe_i2c_op i2c_op; 357 uint8_t mux_channel; 358 359 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 360 return 0; 361 362 /* Select no mux channels */ 363 mux_channel = 0; 364 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 365 i2c_op.target = phy_data->sfp_mux_address; 366 i2c_op.len = sizeof(mux_channel); 367 i2c_op.buf = &mux_channel; 368 369 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 370 } 371 372 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 373 { 374 struct axgbe_phy_data *phy_data = pdata->phy_data; 375 struct axgbe_i2c_op i2c_op; 376 u8 mux_channel; 377 378 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 379 return 0; 380 381 /* Select desired mux channel */ 382 mux_channel = 1 << phy_data->sfp_mux_channel; 383 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 384 i2c_op.target = phy_data->sfp_mux_address; 385 i2c_op.len = sizeof(mux_channel); 386 i2c_op.buf = &mux_channel; 387 388 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 389 } 390 391 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 392 { 393 pthread_mutex_unlock(&pdata->phy_mutex); 394 } 395 396 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 397 { 398 struct axgbe_phy_data *phy_data = pdata->phy_data; 399 uint64_t timeout; 400 unsigned int mutex_id; 401 402 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 403 * the driver needs to take the software mutex and then the hardware 404 * mutexes before being able to use the busses. 405 */ 406 pthread_mutex_lock(&pdata->phy_mutex); 407 408 /* Clear the mutexes */ 409 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 410 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 411 412 /* Mutex formats are the same for I2C and MDIO/GPIO */ 413 mutex_id = 0; 414 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 415 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 416 417 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 418 while (time_before(rte_get_timer_cycles(), timeout)) { 419 /* Must be all zeroes in order to obtain the mutex */ 420 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 421 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 422 rte_delay_us(100); 423 continue; 424 } 425 426 /* Obtain the mutex */ 427 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 428 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 429 430 return 0; 431 } 432 433 pthread_mutex_unlock(&pdata->phy_mutex); 434 435 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 436 437 return -ETIMEDOUT; 438 } 439 440 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 441 { 442 struct axgbe_phy_data *phy_data = pdata->phy_data; 443 444 if (phy_data->sfp_mod_absent) { 445 pdata->phy.speed = SPEED_UNKNOWN; 446 pdata->phy.duplex = DUPLEX_UNKNOWN; 447 pdata->phy.autoneg = AUTONEG_ENABLE; 448 pdata->phy.advertising = pdata->phy.supported; 449 } 450 451 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 452 pdata->phy.advertising &= ~ADVERTISED_TP; 453 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 454 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 455 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 456 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 457 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 458 459 switch (phy_data->sfp_base) { 460 case AXGBE_SFP_BASE_1000_T: 461 case AXGBE_SFP_BASE_1000_SX: 462 case AXGBE_SFP_BASE_1000_LX: 463 case AXGBE_SFP_BASE_1000_CX: 464 pdata->phy.speed = SPEED_UNKNOWN; 465 pdata->phy.duplex = DUPLEX_UNKNOWN; 466 pdata->phy.autoneg = AUTONEG_ENABLE; 467 pdata->phy.advertising |= ADVERTISED_Autoneg; 468 break; 469 case AXGBE_SFP_BASE_10000_SR: 470 case AXGBE_SFP_BASE_10000_LR: 471 case AXGBE_SFP_BASE_10000_LRM: 472 case AXGBE_SFP_BASE_10000_ER: 473 case AXGBE_SFP_BASE_10000_CR: 474 default: 475 pdata->phy.speed = SPEED_10000; 476 pdata->phy.duplex = DUPLEX_FULL; 477 pdata->phy.autoneg = AUTONEG_DISABLE; 478 break; 479 } 480 481 switch (phy_data->sfp_base) { 482 case AXGBE_SFP_BASE_1000_T: 483 case AXGBE_SFP_BASE_1000_CX: 484 case AXGBE_SFP_BASE_10000_CR: 485 pdata->phy.advertising |= ADVERTISED_TP; 486 break; 487 default: 488 pdata->phy.advertising |= ADVERTISED_FIBRE; 489 } 490 491 switch (phy_data->sfp_speed) { 492 case AXGBE_SFP_SPEED_100_1000: 493 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 494 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 495 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 496 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 497 break; 498 case AXGBE_SFP_SPEED_1000: 499 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 500 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 501 break; 502 case AXGBE_SFP_SPEED_10000: 503 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 504 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 505 break; 506 default: 507 /* Choose the fastest supported speed */ 508 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 509 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 510 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 511 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 512 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 513 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 514 } 515 } 516 517 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 518 enum axgbe_sfp_speed sfp_speed) 519 { 520 u8 *sfp_base, min; 521 522 sfp_base = sfp_eeprom->base; 523 524 switch (sfp_speed) { 525 case AXGBE_SFP_SPEED_1000: 526 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 527 break; 528 case AXGBE_SFP_SPEED_10000: 529 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 530 break; 531 default: 532 return false; 533 } 534 535 return sfp_base[AXGBE_SFP_BASE_BR] >= min; 536 } 537 538 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 539 { 540 struct axgbe_phy_data *phy_data = pdata->phy_data; 541 542 if (!phy_data->sfp_changed) 543 return; 544 545 phy_data->sfp_phy_avail = 0; 546 547 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 548 return; 549 } 550 551 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 552 { 553 struct axgbe_phy_data *phy_data = pdata->phy_data; 554 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 555 556 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 557 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 558 return false; 559 /* For Bel-Fuse, use the extra AN flag */ 560 pdata->an_again = 1; 561 562 /* Reset PHY - wait for self-clearing reset bit to clear */ 563 pdata->phy_if.phy_impl.reset(pdata); 564 565 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 566 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 567 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 568 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 569 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 570 return true; 571 } 572 573 return false; 574 } 575 576 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 577 { 578 if (axgbe_phy_belfuse_parse_quirks(pdata)) 579 return true; 580 581 return false; 582 } 583 584 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 585 { 586 struct axgbe_phy_data *phy_data = pdata->phy_data; 587 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 588 uint8_t *sfp_base; 589 590 sfp_base = sfp_eeprom->base; 591 592 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 593 return; 594 595 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 596 return; 597 598 axgbe_phy_sfp_parse_quirks(pdata); 599 600 /* Assume FIBER cable unless told otherwise */ 601 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 602 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 603 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 604 } else if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_ACTIVE) { 605 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 606 } else { 607 phy_data->sfp_cable = AXGBE_SFP_CABLE_FIBER; 608 } 609 610 /* Determine the type of SFP */ 611 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_FIBER && 612 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 613 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 614 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 615 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 616 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 617 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 618 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 619 AXGBE_SFP_BASE_10GBE_CC_LRM) 620 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 621 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 622 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 623 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 624 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 625 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 626 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 627 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 628 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 629 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 630 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 631 632 switch (phy_data->sfp_base) { 633 case AXGBE_SFP_BASE_1000_T: 634 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 635 break; 636 case AXGBE_SFP_BASE_1000_SX: 637 case AXGBE_SFP_BASE_1000_LX: 638 case AXGBE_SFP_BASE_1000_CX: 639 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 640 break; 641 case AXGBE_SFP_BASE_10000_SR: 642 case AXGBE_SFP_BASE_10000_LR: 643 case AXGBE_SFP_BASE_10000_LRM: 644 case AXGBE_SFP_BASE_10000_ER: 645 case AXGBE_SFP_BASE_10000_CR: 646 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 647 break; 648 default: 649 break; 650 } 651 } 652 653 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 654 unsigned int len) 655 { 656 uint8_t cc; 657 658 for (cc = 0; len; buf++, len--) 659 cc += *buf; 660 661 return cc == cc_in; 662 } 663 664 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 665 { 666 struct axgbe_phy_data *phy_data = pdata->phy_data; 667 struct axgbe_sfp_eeprom sfp_eeprom; 668 uint8_t eeprom_addr; 669 int ret; 670 671 ret = axgbe_phy_sfp_get_mux(pdata); 672 if (ret) { 673 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 674 return ret; 675 } 676 677 /* Read the SFP serial ID eeprom */ 678 eeprom_addr = 0; 679 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 680 &eeprom_addr, sizeof(eeprom_addr), 681 &sfp_eeprom, sizeof(sfp_eeprom)); 682 if (ret) { 683 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 684 goto put; 685 } 686 687 /* Validate the contents read */ 688 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 689 sfp_eeprom.base, 690 sizeof(sfp_eeprom.base) - 1)) { 691 ret = -EINVAL; 692 goto put; 693 } 694 695 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 696 sfp_eeprom.extd, 697 sizeof(sfp_eeprom.extd) - 1)) { 698 ret = -EINVAL; 699 goto put; 700 } 701 702 /* Check for an added or changed SFP */ 703 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 704 phy_data->sfp_changed = 1; 705 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 706 } else { 707 phy_data->sfp_changed = 0; 708 } 709 710 put: 711 axgbe_phy_sfp_put_mux(pdata); 712 713 return ret; 714 } 715 716 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 717 { 718 struct axgbe_phy_data *phy_data = pdata->phy_data; 719 unsigned int gpio_input; 720 u8 gpio_reg, gpio_ports[2]; 721 int ret; 722 723 /* Read the input port registers */ 724 gpio_reg = 0; 725 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 726 &gpio_reg, sizeof(gpio_reg), 727 gpio_ports, sizeof(gpio_ports)); 728 if (ret) { 729 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 730 return; 731 } 732 733 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 734 735 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 736 /* No GPIO, just assume the module is present for now */ 737 phy_data->sfp_mod_absent = 0; 738 } else { 739 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 740 phy_data->sfp_mod_absent = 0; 741 } 742 743 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 744 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 745 phy_data->sfp_rx_los = 1; 746 747 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 748 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 749 phy_data->sfp_tx_fault = 1; 750 } 751 752 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 753 { 754 struct axgbe_phy_data *phy_data = pdata->phy_data; 755 756 phy_data->sfp_mod_absent = 1; 757 phy_data->sfp_phy_avail = 0; 758 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 759 } 760 761 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 762 { 763 phy_data->sfp_rx_los = 0; 764 phy_data->sfp_tx_fault = 0; 765 phy_data->sfp_mod_absent = 1; 766 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 767 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 768 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 769 } 770 771 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base) 772 { 773 switch (sfp_base) { 774 case AXGBE_SFP_BASE_1000_T: 775 return "1G_T"; 776 case AXGBE_SFP_BASE_1000_SX: 777 return "1G_SX"; 778 case AXGBE_SFP_BASE_1000_LX: 779 return "1G_LX"; 780 case AXGBE_SFP_BASE_1000_CX: 781 return "1G_CX"; 782 case AXGBE_SFP_BASE_10000_SR: 783 return "10G_SR"; 784 case AXGBE_SFP_BASE_10000_LR: 785 return "10G_LR"; 786 case AXGBE_SFP_BASE_10000_LRM: 787 return "10G_LRM"; 788 case AXGBE_SFP_BASE_10000_ER: 789 return "10G_ER"; 790 case AXGBE_SFP_BASE_10000_CR: 791 return "10G_CR"; 792 default: 793 return "Unknown"; 794 } 795 } 796 797 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 798 { 799 struct axgbe_phy_data *phy_data = pdata->phy_data; 800 int ret; 801 802 /* Clear the extra AN flag */ 803 pdata->an_again = 0; 804 805 /* Reset the SFP signals and info */ 806 axgbe_phy_sfp_reset(phy_data); 807 808 ret = axgbe_phy_get_comm_ownership(pdata); 809 if (ret) 810 return; 811 812 /* Read the SFP signals and check for module presence */ 813 axgbe_phy_sfp_signals(pdata); 814 if (phy_data->sfp_mod_absent) { 815 axgbe_phy_sfp_mod_absent(pdata); 816 goto put; 817 } 818 819 ret = axgbe_phy_sfp_read_eeprom(pdata); 820 if (ret) { 821 /* Treat any error as if there isn't an SFP plugged in */ 822 axgbe_phy_sfp_reset(phy_data); 823 axgbe_phy_sfp_mod_absent(pdata); 824 goto put; 825 } 826 827 axgbe_phy_sfp_parse_eeprom(pdata); 828 axgbe_phy_sfp_external_phy(pdata); 829 830 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n", 831 axgbe_base_as_string(phy_data->sfp_base)); 832 833 put: 834 axgbe_phy_sfp_phy_settings(pdata); 835 axgbe_phy_put_comm_ownership(pdata); 836 } 837 838 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 839 { 840 pdata->phy.tx_pause = 0; 841 pdata->phy.rx_pause = 0; 842 } 843 844 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 845 { 846 struct axgbe_phy_data *phy_data = pdata->phy_data; 847 enum axgbe_mode mode; 848 unsigned int ad_reg, lp_reg; 849 850 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 851 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 852 853 /* Use external PHY to determine flow control */ 854 if (pdata->phy.pause_autoneg) 855 axgbe_phy_phydev_flowctrl(pdata); 856 857 /* Compare Advertisement and Link Partner register 2 */ 858 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 859 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 860 if (lp_reg & 0x80) 861 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 862 if (lp_reg & 0x20) 863 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 864 865 ad_reg &= lp_reg; 866 if (ad_reg & 0x80) { 867 switch (phy_data->port_mode) { 868 case AXGBE_PORT_MODE_BACKPLANE: 869 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 870 mode = AXGBE_MODE_KR; 871 break; 872 default: 873 mode = AXGBE_MODE_SFI; 874 break; 875 } 876 } else if (ad_reg & 0x20) { 877 switch (phy_data->port_mode) { 878 case AXGBE_PORT_MODE_BACKPLANE: 879 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 880 mode = AXGBE_MODE_KX_1000; 881 break; 882 case AXGBE_PORT_MODE_1000BASE_X: 883 mode = AXGBE_MODE_X; 884 break; 885 case AXGBE_PORT_MODE_SFP: 886 switch (phy_data->sfp_base) { 887 case AXGBE_SFP_BASE_1000_T: 888 mode = AXGBE_MODE_SGMII_1000; 889 break; 890 case AXGBE_SFP_BASE_1000_SX: 891 case AXGBE_SFP_BASE_1000_LX: 892 case AXGBE_SFP_BASE_1000_CX: 893 default: 894 mode = AXGBE_MODE_X; 895 break; 896 } 897 break; 898 default: 899 mode = AXGBE_MODE_SGMII_1000; 900 break; 901 } 902 } else { 903 mode = AXGBE_MODE_UNKNOWN; 904 } 905 906 /* Compare Advertisement and Link Partner register 3 */ 907 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 908 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 909 if (lp_reg & 0xc000) 910 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 911 912 return mode; 913 } 914 915 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 916 { 917 enum axgbe_mode mode; 918 unsigned int ad_reg, lp_reg; 919 920 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 921 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 922 923 /* Compare Advertisement and Link Partner register 1 */ 924 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 925 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 926 if (lp_reg & 0x400) 927 pdata->phy.lp_advertising |= ADVERTISED_Pause; 928 if (lp_reg & 0x800) 929 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 930 931 if (pdata->phy.pause_autoneg) { 932 /* Set flow control based on auto-negotiation result */ 933 pdata->phy.tx_pause = 0; 934 pdata->phy.rx_pause = 0; 935 936 if (ad_reg & lp_reg & 0x400) { 937 pdata->phy.tx_pause = 1; 938 pdata->phy.rx_pause = 1; 939 } else if (ad_reg & lp_reg & 0x800) { 940 if (ad_reg & 0x400) 941 pdata->phy.rx_pause = 1; 942 else if (lp_reg & 0x400) 943 pdata->phy.tx_pause = 1; 944 } 945 } 946 947 /* Compare Advertisement and Link Partner register 2 */ 948 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 949 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 950 if (lp_reg & 0x80) 951 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 952 if (lp_reg & 0x20) 953 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 954 955 ad_reg &= lp_reg; 956 if (ad_reg & 0x80) 957 mode = AXGBE_MODE_KR; 958 else if (ad_reg & 0x20) 959 mode = AXGBE_MODE_KX_1000; 960 else 961 mode = AXGBE_MODE_UNKNOWN; 962 963 /* Compare Advertisement and Link Partner register 3 */ 964 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 965 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 966 if (lp_reg & 0xc000) 967 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 968 969 return mode; 970 } 971 972 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 973 { 974 enum axgbe_mode mode; 975 976 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 977 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 978 979 if (pdata->phy.pause_autoneg) 980 axgbe_phy_phydev_flowctrl(pdata); 981 982 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 983 case AXGBE_SGMII_AN_LINK_SPEED_100: 984 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 985 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 986 mode = AXGBE_MODE_SGMII_100; 987 } else { 988 mode = AXGBE_MODE_UNKNOWN; 989 } 990 break; 991 case AXGBE_SGMII_AN_LINK_SPEED_1000: 992 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 993 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 994 mode = AXGBE_MODE_SGMII_1000; 995 } else { 996 /* Half-duplex not supported */ 997 mode = AXGBE_MODE_UNKNOWN; 998 } 999 break; 1000 default: 1001 mode = AXGBE_MODE_UNKNOWN; 1002 break; 1003 } 1004 return mode; 1005 } 1006 1007 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 1008 { 1009 switch (pdata->an_mode) { 1010 case AXGBE_AN_MODE_CL73: 1011 return axgbe_phy_an73_outcome(pdata); 1012 case AXGBE_AN_MODE_CL73_REDRV: 1013 return axgbe_phy_an73_redrv_outcome(pdata); 1014 case AXGBE_AN_MODE_CL37: 1015 case AXGBE_AN_MODE_CL37_SGMII: 1016 return axgbe_phy_an37_sgmii_outcome(pdata); 1017 default: 1018 return AXGBE_MODE_UNKNOWN; 1019 } 1020 } 1021 1022 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1023 { 1024 struct axgbe_phy_data *phy_data = pdata->phy_data; 1025 unsigned int advertising; 1026 1027 /* Without a re-driver, just return current advertising */ 1028 if (!phy_data->redrv) 1029 return pdata->phy.advertising; 1030 1031 /* With the KR re-driver we need to advertise a single speed */ 1032 advertising = pdata->phy.advertising; 1033 advertising &= ~ADVERTISED_1000baseKX_Full; 1034 advertising &= ~ADVERTISED_10000baseKR_Full; 1035 1036 switch (phy_data->port_mode) { 1037 case AXGBE_PORT_MODE_BACKPLANE: 1038 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1039 advertising |= ADVERTISED_10000baseKR_Full; 1040 break; 1041 case AXGBE_PORT_MODE_BACKPLANE_2500: 1042 advertising |= ADVERTISED_1000baseKX_Full; 1043 break; 1044 case AXGBE_PORT_MODE_1000BASE_T: 1045 case AXGBE_PORT_MODE_1000BASE_X: 1046 case AXGBE_PORT_MODE_NBASE_T: 1047 advertising |= ADVERTISED_1000baseKX_Full; 1048 break; 1049 case AXGBE_PORT_MODE_10GBASE_T: 1050 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1051 break; 1052 case AXGBE_PORT_MODE_10GBASE_R: 1053 advertising |= ADVERTISED_10000baseKR_Full; 1054 break; 1055 case AXGBE_PORT_MODE_SFP: 1056 switch (phy_data->sfp_base) { 1057 case AXGBE_SFP_BASE_1000_T: 1058 case AXGBE_SFP_BASE_1000_SX: 1059 case AXGBE_SFP_BASE_1000_LX: 1060 case AXGBE_SFP_BASE_1000_CX: 1061 advertising |= ADVERTISED_1000baseKX_Full; 1062 break; 1063 default: 1064 advertising |= ADVERTISED_10000baseKR_Full; 1065 break; 1066 } 1067 break; 1068 default: 1069 advertising |= ADVERTISED_10000baseKR_Full; 1070 break; 1071 } 1072 1073 return advertising; 1074 } 1075 1076 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1077 { 1078 return 0; 1079 /* Dummy API since there is no case to support 1080 * external phy devices registered through kernel APIs 1081 */ 1082 } 1083 1084 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1085 { 1086 switch (phy_data->sfp_base) { 1087 case AXGBE_SFP_BASE_1000_T: 1088 return AXGBE_AN_MODE_CL37_SGMII; 1089 case AXGBE_SFP_BASE_1000_SX: 1090 case AXGBE_SFP_BASE_1000_LX: 1091 case AXGBE_SFP_BASE_1000_CX: 1092 return AXGBE_AN_MODE_CL37; 1093 default: 1094 return AXGBE_AN_MODE_NONE; 1095 } 1096 } 1097 1098 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1099 { 1100 struct axgbe_phy_data *phy_data = pdata->phy_data; 1101 1102 /* A KR re-driver will always require CL73 AN */ 1103 if (phy_data->redrv) 1104 return AXGBE_AN_MODE_CL73_REDRV; 1105 1106 switch (phy_data->port_mode) { 1107 case AXGBE_PORT_MODE_BACKPLANE: 1108 return AXGBE_AN_MODE_CL73; 1109 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1110 case AXGBE_PORT_MODE_BACKPLANE_2500: 1111 return AXGBE_AN_MODE_NONE; 1112 case AXGBE_PORT_MODE_1000BASE_T: 1113 return AXGBE_AN_MODE_CL37_SGMII; 1114 case AXGBE_PORT_MODE_1000BASE_X: 1115 return AXGBE_AN_MODE_CL37; 1116 case AXGBE_PORT_MODE_NBASE_T: 1117 return AXGBE_AN_MODE_CL37_SGMII; 1118 case AXGBE_PORT_MODE_10GBASE_T: 1119 return AXGBE_AN_MODE_CL73; 1120 case AXGBE_PORT_MODE_10GBASE_R: 1121 return AXGBE_AN_MODE_NONE; 1122 case AXGBE_PORT_MODE_SFP: 1123 return axgbe_phy_an_sfp_mode(phy_data); 1124 default: 1125 return AXGBE_AN_MODE_NONE; 1126 } 1127 } 1128 1129 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1130 enum axgbe_phy_redrv_mode mode) 1131 { 1132 struct axgbe_phy_data *phy_data = pdata->phy_data; 1133 u16 redrv_reg, redrv_val; 1134 1135 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1136 redrv_val = (u16)mode; 1137 1138 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1139 redrv_reg, redrv_val); 1140 } 1141 1142 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1143 enum axgbe_phy_redrv_mode mode) 1144 { 1145 struct axgbe_phy_data *phy_data = pdata->phy_data; 1146 unsigned int redrv_reg; 1147 int ret; 1148 1149 /* Calculate the register to write */ 1150 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1151 1152 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1153 1154 return ret; 1155 } 1156 1157 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1158 { 1159 struct axgbe_phy_data *phy_data = pdata->phy_data; 1160 enum axgbe_phy_redrv_mode mode; 1161 int ret; 1162 1163 if (!phy_data->redrv) 1164 return; 1165 1166 mode = AXGBE_PHY_REDRV_MODE_CX; 1167 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1168 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1169 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1170 mode = AXGBE_PHY_REDRV_MODE_SR; 1171 1172 ret = axgbe_phy_get_comm_ownership(pdata); 1173 if (ret) 1174 return; 1175 1176 if (phy_data->redrv_if) 1177 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1178 else 1179 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1180 1181 axgbe_phy_put_comm_ownership(pdata); 1182 } 1183 1184 static void axgbe_phy_rx_reset(struct axgbe_port *pdata) 1185 { 1186 int reg; 1187 1188 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 1189 XGBE_PCS_PSEQ_STATE_MASK); 1190 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 1191 /* Mailbox command timed out, reset of RX block is required. 1192 * This can be done by asseting the reset bit and wait for 1193 * its compeletion. 1194 */ 1195 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1196 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 1197 rte_delay_us(20); 1198 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1199 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 1200 rte_delay_us(45); 1201 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n"); 1202 } 1203 } 1204 1205 1206 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) 1207 { 1208 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ 1209 if (pdata->phy.autoneg != AUTONEG_DISABLE) 1210 return; 1211 1212 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1213 XGBE_PMA_PLL_CTRL_MASK, 1214 enable ? XGBE_PMA_PLL_CTRL_SET 1215 : XGBE_PMA_PLL_CTRL_CLEAR); 1216 1217 /* Wait for command to complete */ 1218 rte_delay_us(150); 1219 } 1220 1221 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, 1222 enum axgbe_mb_cmd cmd, enum axgbe_mb_subcmd sub_cmd) 1223 { 1224 unsigned int s0 = 0; 1225 unsigned int wait; 1226 /* Clear the PLL so that it helps in power down sequence */ 1227 axgbe_phy_pll_ctrl(pdata, false); 1228 1229 /* Log if a previous command did not complete */ 1230 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 1231 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); 1232 axgbe_phy_rx_reset(pdata); 1233 } 1234 1235 /* Construct the command */ 1236 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1237 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1238 1239 /* Issue the command */ 1240 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1241 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1242 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1243 1244 /* Wait for command to complete */ 1245 wait = AXGBE_RATECHANGE_COUNT; 1246 while (wait--) { 1247 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1248 goto reenable_pll; 1249 rte_delay_us(1500); 1250 } 1251 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1252 /* Reset on error */ 1253 axgbe_phy_rx_reset(pdata); 1254 1255 reenable_pll: 1256 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */ 1257 if (cmd != AXGBE_MB_CMD_POWER_OFF && 1258 cmd != AXGBE_MB_CMD_RRC) 1259 axgbe_phy_pll_ctrl(pdata, true); 1260 1261 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1262 } 1263 1264 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1265 { 1266 1267 1268 /* Receiver Reset Cycle */ 1269 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_RRC, AXGBE_MB_SUBCMD_NONE); 1270 1271 PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); 1272 } 1273 1274 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1275 { 1276 struct axgbe_phy_data *phy_data = pdata->phy_data; 1277 1278 /* Power off */ 1279 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_POWER_OFF, AXGBE_MB_SUBCMD_NONE); 1280 1281 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1282 1283 PMD_DRV_LOG(DEBUG, "phy powered off\n"); 1284 } 1285 1286 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1287 { 1288 struct axgbe_phy_data *phy_data = pdata->phy_data; 1289 1290 axgbe_phy_set_redrv_mode(pdata); 1291 1292 /* 10G/SFI */ 1293 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1294 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1295 AXGBE_MB_SUBCMD_ACTIVE); 1296 } else { 1297 if (phy_data->sfp_cable_len <= 1) 1298 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1299 AXGBE_MB_SUBCMD_PASSIVE_1M); 1300 else if (phy_data->sfp_cable_len <= 3) 1301 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1302 AXGBE_MB_SUBCMD_PASSIVE_3M); 1303 else 1304 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1305 AXGBE_MB_SUBCMD_PASSIVE_OTHER); 1306 } 1307 1308 phy_data->cur_mode = AXGBE_MODE_SFI; 1309 1310 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); 1311 } 1312 1313 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1314 { 1315 struct axgbe_phy_data *phy_data = pdata->phy_data; 1316 1317 axgbe_phy_set_redrv_mode(pdata); 1318 1319 /* 10G/KR */ 1320 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_KR, 1321 AXGBE_MB_SUBCMD_NONE); 1322 phy_data->cur_mode = AXGBE_MODE_KR; 1323 1324 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); 1325 } 1326 1327 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1328 { 1329 struct axgbe_phy_data *phy_data = pdata->phy_data; 1330 1331 axgbe_phy_set_redrv_mode(pdata); 1332 1333 /* 2.5G/KX */ 1334 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_2_5G, AXGBE_MB_SUBCMD_NONE); 1335 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1336 } 1337 1338 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1339 { 1340 struct axgbe_phy_data *phy_data = pdata->phy_data; 1341 1342 axgbe_phy_set_redrv_mode(pdata); 1343 1344 /* 1G/SGMII */ 1345 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_1G, AXGBE_MB_SUBCMD_1G_SGMII); 1346 1347 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1348 } 1349 1350 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1351 { 1352 struct axgbe_phy_data *phy_data = pdata->phy_data; 1353 1354 return phy_data->cur_mode; 1355 } 1356 1357 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1358 { 1359 struct axgbe_phy_data *phy_data = pdata->phy_data; 1360 1361 /* No switching if not 10GBase-T */ 1362 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1363 return axgbe_phy_cur_mode(pdata); 1364 1365 switch (axgbe_phy_cur_mode(pdata)) { 1366 case AXGBE_MODE_SGMII_100: 1367 case AXGBE_MODE_SGMII_1000: 1368 return AXGBE_MODE_KR; 1369 case AXGBE_MODE_KR: 1370 default: 1371 return AXGBE_MODE_SGMII_1000; 1372 } 1373 } 1374 1375 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1376 __rte_unused) 1377 { 1378 return AXGBE_MODE_KX_2500; 1379 } 1380 1381 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1382 { 1383 /* If we are in KR switch to KX, and vice-versa */ 1384 switch (axgbe_phy_cur_mode(pdata)) { 1385 case AXGBE_MODE_KX_1000: 1386 return AXGBE_MODE_KR; 1387 case AXGBE_MODE_KR: 1388 default: 1389 return AXGBE_MODE_KX_1000; 1390 } 1391 } 1392 1393 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1394 { 1395 struct axgbe_phy_data *phy_data = pdata->phy_data; 1396 1397 switch (phy_data->port_mode) { 1398 case AXGBE_PORT_MODE_BACKPLANE: 1399 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1400 return axgbe_phy_switch_bp_mode(pdata); 1401 case AXGBE_PORT_MODE_BACKPLANE_2500: 1402 return axgbe_phy_switch_bp_2500_mode(pdata); 1403 case AXGBE_PORT_MODE_1000BASE_T: 1404 case AXGBE_PORT_MODE_NBASE_T: 1405 case AXGBE_PORT_MODE_10GBASE_T: 1406 return axgbe_phy_switch_baset_mode(pdata); 1407 case AXGBE_PORT_MODE_1000BASE_X: 1408 case AXGBE_PORT_MODE_10GBASE_R: 1409 case AXGBE_PORT_MODE_SFP: 1410 /* No switching, so just return current mode */ 1411 return axgbe_phy_cur_mode(pdata); 1412 default: 1413 return AXGBE_MODE_UNKNOWN; 1414 } 1415 } 1416 1417 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1418 __rte_unused, 1419 int speed) 1420 { 1421 switch (speed) { 1422 case SPEED_1000: 1423 return AXGBE_MODE_X; 1424 case SPEED_10000: 1425 return AXGBE_MODE_KR; 1426 default: 1427 return AXGBE_MODE_UNKNOWN; 1428 } 1429 } 1430 1431 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1432 __rte_unused, 1433 int speed) 1434 { 1435 switch (speed) { 1436 case SPEED_100: 1437 return AXGBE_MODE_SGMII_100; 1438 case SPEED_1000: 1439 return AXGBE_MODE_SGMII_1000; 1440 case SPEED_10000: 1441 return AXGBE_MODE_KR; 1442 default: 1443 return AXGBE_MODE_UNKNOWN; 1444 } 1445 } 1446 1447 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1448 int speed) 1449 { 1450 switch (speed) { 1451 case SPEED_100: 1452 return AXGBE_MODE_SGMII_100; 1453 case SPEED_1000: 1454 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1455 return AXGBE_MODE_SGMII_1000; 1456 else 1457 return AXGBE_MODE_X; 1458 case SPEED_10000: 1459 case SPEED_UNKNOWN: 1460 return AXGBE_MODE_SFI; 1461 default: 1462 return AXGBE_MODE_UNKNOWN; 1463 } 1464 } 1465 1466 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1467 { 1468 switch (speed) { 1469 case SPEED_2500: 1470 return AXGBE_MODE_KX_2500; 1471 default: 1472 return AXGBE_MODE_UNKNOWN; 1473 } 1474 } 1475 1476 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1477 { 1478 switch (speed) { 1479 case SPEED_1000: 1480 return AXGBE_MODE_KX_1000; 1481 case SPEED_10000: 1482 return AXGBE_MODE_KR; 1483 default: 1484 return AXGBE_MODE_UNKNOWN; 1485 } 1486 } 1487 1488 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1489 int speed) 1490 { 1491 struct axgbe_phy_data *phy_data = pdata->phy_data; 1492 1493 switch (phy_data->port_mode) { 1494 case AXGBE_PORT_MODE_BACKPLANE: 1495 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1496 return axgbe_phy_get_bp_mode(speed); 1497 case AXGBE_PORT_MODE_BACKPLANE_2500: 1498 return axgbe_phy_get_bp_2500_mode(speed); 1499 case AXGBE_PORT_MODE_1000BASE_T: 1500 case AXGBE_PORT_MODE_NBASE_T: 1501 case AXGBE_PORT_MODE_10GBASE_T: 1502 return axgbe_phy_get_baset_mode(phy_data, speed); 1503 case AXGBE_PORT_MODE_1000BASE_X: 1504 case AXGBE_PORT_MODE_10GBASE_R: 1505 return axgbe_phy_get_basex_mode(phy_data, speed); 1506 case AXGBE_PORT_MODE_SFP: 1507 return axgbe_phy_get_sfp_mode(phy_data, speed); 1508 default: 1509 return AXGBE_MODE_UNKNOWN; 1510 } 1511 } 1512 1513 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1514 { 1515 switch (mode) { 1516 case AXGBE_MODE_KR: 1517 axgbe_phy_kr_mode(pdata); 1518 break; 1519 case AXGBE_MODE_SFI: 1520 axgbe_phy_sfi_mode(pdata); 1521 break; 1522 case AXGBE_MODE_KX_2500: 1523 axgbe_phy_kx_2500_mode(pdata); 1524 break; 1525 case AXGBE_MODE_SGMII_1000: 1526 axgbe_phy_sgmii_1000_mode(pdata); 1527 break; 1528 default: 1529 break; 1530 } 1531 } 1532 1533 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1534 enum axgbe_mode mode, u32 advert) 1535 { 1536 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1537 if (pdata->phy.advertising & advert) 1538 return true; 1539 } else { 1540 enum axgbe_mode cur_mode; 1541 1542 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1543 if (cur_mode == mode) 1544 return true; 1545 } 1546 1547 return false; 1548 } 1549 1550 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1551 enum axgbe_mode mode) 1552 { 1553 switch (mode) { 1554 case AXGBE_MODE_X: 1555 return axgbe_phy_check_mode(pdata, mode, 1556 ADVERTISED_1000baseT_Full); 1557 case AXGBE_MODE_KR: 1558 return axgbe_phy_check_mode(pdata, mode, 1559 ADVERTISED_10000baseT_Full); 1560 default: 1561 return false; 1562 } 1563 } 1564 1565 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1566 enum axgbe_mode mode) 1567 { 1568 switch (mode) { 1569 case AXGBE_MODE_SGMII_100: 1570 return axgbe_phy_check_mode(pdata, mode, 1571 ADVERTISED_100baseT_Full); 1572 case AXGBE_MODE_SGMII_1000: 1573 return axgbe_phy_check_mode(pdata, mode, 1574 ADVERTISED_1000baseT_Full); 1575 case AXGBE_MODE_KR: 1576 return axgbe_phy_check_mode(pdata, mode, 1577 ADVERTISED_10000baseT_Full); 1578 default: 1579 return false; 1580 } 1581 } 1582 1583 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1584 enum axgbe_mode mode) 1585 { 1586 struct axgbe_phy_data *phy_data = pdata->phy_data; 1587 1588 switch (mode) { 1589 case AXGBE_MODE_X: 1590 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1591 return false; 1592 return axgbe_phy_check_mode(pdata, mode, 1593 ADVERTISED_1000baseT_Full); 1594 case AXGBE_MODE_SGMII_100: 1595 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1596 return false; 1597 return axgbe_phy_check_mode(pdata, mode, 1598 ADVERTISED_100baseT_Full); 1599 case AXGBE_MODE_SGMII_1000: 1600 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1601 return false; 1602 return axgbe_phy_check_mode(pdata, mode, 1603 ADVERTISED_1000baseT_Full); 1604 case AXGBE_MODE_SFI: 1605 return axgbe_phy_check_mode(pdata, mode, 1606 ADVERTISED_10000baseT_Full); 1607 default: 1608 return false; 1609 } 1610 } 1611 1612 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1613 enum axgbe_mode mode) 1614 { 1615 switch (mode) { 1616 case AXGBE_MODE_KX_2500: 1617 return axgbe_phy_check_mode(pdata, mode, 1618 ADVERTISED_2500baseX_Full); 1619 default: 1620 return false; 1621 } 1622 } 1623 1624 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1625 enum axgbe_mode mode) 1626 { 1627 switch (mode) { 1628 case AXGBE_MODE_KX_1000: 1629 return axgbe_phy_check_mode(pdata, mode, 1630 ADVERTISED_1000baseKX_Full); 1631 case AXGBE_MODE_KR: 1632 return axgbe_phy_check_mode(pdata, mode, 1633 ADVERTISED_10000baseKR_Full); 1634 default: 1635 return false; 1636 } 1637 } 1638 1639 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1640 { 1641 struct axgbe_phy_data *phy_data = pdata->phy_data; 1642 1643 switch (phy_data->port_mode) { 1644 case AXGBE_PORT_MODE_BACKPLANE: 1645 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1646 return axgbe_phy_use_bp_mode(pdata, mode); 1647 case AXGBE_PORT_MODE_BACKPLANE_2500: 1648 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1649 case AXGBE_PORT_MODE_1000BASE_T: 1650 case AXGBE_PORT_MODE_NBASE_T: 1651 case AXGBE_PORT_MODE_10GBASE_T: 1652 return axgbe_phy_use_baset_mode(pdata, mode); 1653 case AXGBE_PORT_MODE_1000BASE_X: 1654 case AXGBE_PORT_MODE_10GBASE_R: 1655 return axgbe_phy_use_basex_mode(pdata, mode); 1656 case AXGBE_PORT_MODE_SFP: 1657 return axgbe_phy_use_sfp_mode(pdata, mode); 1658 default: 1659 return false; 1660 } 1661 } 1662 1663 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1664 { 1665 struct axgbe_phy_data *phy_data = pdata->phy_data; 1666 unsigned int reg; 1667 1668 *an_restart = 0; 1669 1670 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1671 /* Check SFP signals */ 1672 axgbe_phy_sfp_detect(pdata); 1673 1674 if (phy_data->sfp_changed) { 1675 *an_restart = 1; 1676 return 0; 1677 } 1678 1679 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1680 return 0; 1681 } 1682 1683 /* Link status is latched low, so read once to clear 1684 * and then read again to get current state 1685 */ 1686 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1687 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1688 if (reg & MDIO_STAT1_LSTATUS) 1689 return 1; 1690 1691 if (pdata->phy.autoneg == AUTONEG_ENABLE && 1692 phy_data->port_mode == AXGBE_PORT_MODE_BACKPLANE) { 1693 if (rte_bit_relaxed_get32(AXGBE_LINK_INIT, &pdata->dev_state)) { 1694 *an_restart = 1; 1695 } 1696 } 1697 1698 /* No link, attempt a receiver reset cycle */ 1699 if (pdata->vdata->enable_rrc && phy_data->rrc_count++) { 1700 phy_data->rrc_count = 0; 1701 axgbe_phy_rrc(pdata); 1702 } 1703 1704 return 0; 1705 } 1706 1707 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1708 { 1709 struct axgbe_phy_data *phy_data = pdata->phy_data; 1710 1711 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1712 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); 1713 1714 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_MASK); 1715 1716 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1717 GPIO_RX_LOS); 1718 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1719 GPIO_TX_FAULT); 1720 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1721 GPIO_MOD_ABS); 1722 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1723 GPIO_RATE_SELECT); 1724 } 1725 1726 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1727 { 1728 struct axgbe_phy_data *phy_data = pdata->phy_data; 1729 unsigned int mux_addr_hi, mux_addr_lo; 1730 1731 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 1732 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 1733 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1734 return; 1735 1736 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1737 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1738 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_CHAN); 1739 } 1740 1741 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1742 { 1743 axgbe_phy_sfp_comm_setup(pdata); 1744 axgbe_phy_sfp_gpio_setup(pdata); 1745 } 1746 1747 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1748 { 1749 if (!phy_data->redrv) 1750 return false; 1751 1752 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1753 return true; 1754 1755 switch (phy_data->redrv_model) { 1756 case AXGBE_PHY_REDRV_MODEL_4223: 1757 if (phy_data->redrv_lane > 3) 1758 return true; 1759 break; 1760 case AXGBE_PHY_REDRV_MODEL_4227: 1761 if (phy_data->redrv_lane > 1) 1762 return true; 1763 break; 1764 default: 1765 return true; 1766 } 1767 1768 return false; 1769 } 1770 1771 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1772 { 1773 struct axgbe_phy_data *phy_data = pdata->phy_data; 1774 1775 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1776 return 0; 1777 1778 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 1779 switch (phy_data->mdio_reset) { 1780 case AXGBE_MDIO_RESET_NONE: 1781 case AXGBE_MDIO_RESET_I2C_GPIO: 1782 case AXGBE_MDIO_RESET_INT_GPIO: 1783 break; 1784 default: 1785 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1786 phy_data->mdio_reset); 1787 return -EINVAL; 1788 } 1789 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1790 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1791 XP_GET_BITS(pdata->pp3, XP_PROP_3, 1792 MDIO_RESET_I2C_ADDR); 1793 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1794 MDIO_RESET_I2C_GPIO); 1795 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1796 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1797 MDIO_RESET_INT_GPIO); 1798 } 1799 1800 return 0; 1801 } 1802 1803 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1804 { 1805 struct axgbe_phy_data *phy_data = pdata->phy_data; 1806 1807 switch (phy_data->port_mode) { 1808 case AXGBE_PORT_MODE_BACKPLANE: 1809 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1810 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1811 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1812 return false; 1813 break; 1814 case AXGBE_PORT_MODE_BACKPLANE_2500: 1815 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1816 return false; 1817 break; 1818 case AXGBE_PORT_MODE_1000BASE_T: 1819 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1820 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1821 return false; 1822 break; 1823 case AXGBE_PORT_MODE_1000BASE_X: 1824 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1825 return false; 1826 break; 1827 case AXGBE_PORT_MODE_NBASE_T: 1828 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1829 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1830 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1831 return false; 1832 break; 1833 case AXGBE_PORT_MODE_10GBASE_T: 1834 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1835 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1836 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1837 return false; 1838 break; 1839 case AXGBE_PORT_MODE_10GBASE_R: 1840 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1841 return false; 1842 break; 1843 case AXGBE_PORT_MODE_SFP: 1844 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1845 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1846 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1847 return false; 1848 break; 1849 default: 1850 break; 1851 } 1852 1853 return true; 1854 } 1855 1856 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1857 { 1858 struct axgbe_phy_data *phy_data = pdata->phy_data; 1859 1860 switch (phy_data->port_mode) { 1861 case AXGBE_PORT_MODE_BACKPLANE: 1862 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1863 case AXGBE_PORT_MODE_BACKPLANE_2500: 1864 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1865 return false; 1866 break; 1867 case AXGBE_PORT_MODE_1000BASE_T: 1868 case AXGBE_PORT_MODE_1000BASE_X: 1869 case AXGBE_PORT_MODE_NBASE_T: 1870 case AXGBE_PORT_MODE_10GBASE_T: 1871 case AXGBE_PORT_MODE_10GBASE_R: 1872 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1873 return false; 1874 break; 1875 case AXGBE_PORT_MODE_SFP: 1876 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1877 return false; 1878 break; 1879 default: 1880 break; 1881 } 1882 1883 return true; 1884 } 1885 1886 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1887 { 1888 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 1889 return false; 1890 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 1891 return false; 1892 1893 return true; 1894 } 1895 1896 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1897 { 1898 struct axgbe_phy_data *phy_data = pdata->phy_data; 1899 1900 if (!pdata->vdata->an_cdr_workaround) 1901 return; 1902 1903 if (!phy_data->phy_cdr_notrack) 1904 return; 1905 1906 rte_delay_us(phy_data->phy_cdr_delay + 400); 1907 1908 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1909 AXGBE_PMA_CDR_TRACK_EN_MASK, 1910 AXGBE_PMA_CDR_TRACK_EN_ON); 1911 1912 phy_data->phy_cdr_notrack = 0; 1913 } 1914 1915 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1916 { 1917 struct axgbe_phy_data *phy_data = pdata->phy_data; 1918 1919 if (!pdata->vdata->an_cdr_workaround) 1920 return; 1921 1922 if (phy_data->phy_cdr_notrack) 1923 return; 1924 1925 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1926 AXGBE_PMA_CDR_TRACK_EN_MASK, 1927 AXGBE_PMA_CDR_TRACK_EN_OFF); 1928 1929 axgbe_phy_rrc(pdata); 1930 1931 phy_data->phy_cdr_notrack = 1; 1932 } 1933 1934 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1935 { 1936 if (!pdata->cdr_track_early) 1937 axgbe_phy_cdr_track(pdata); 1938 } 1939 1940 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1941 { 1942 if (pdata->cdr_track_early) 1943 axgbe_phy_cdr_track(pdata); 1944 } 1945 1946 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1947 { 1948 struct axgbe_phy_data *phy_data = pdata->phy_data; 1949 1950 switch (pdata->an_mode) { 1951 case AXGBE_AN_MODE_CL73: 1952 case AXGBE_AN_MODE_CL73_REDRV: 1953 if (phy_data->cur_mode != AXGBE_MODE_KR) 1954 break; 1955 1956 axgbe_phy_cdr_track(pdata); 1957 1958 switch (pdata->an_result) { 1959 case AXGBE_AN_READY: 1960 case AXGBE_AN_COMPLETE: 1961 break; 1962 default: 1963 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1964 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1965 break; 1966 } 1967 break; 1968 default: 1969 break; 1970 } 1971 } 1972 1973 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1974 { 1975 struct axgbe_phy_data *phy_data = pdata->phy_data; 1976 1977 switch (pdata->an_mode) { 1978 case AXGBE_AN_MODE_CL73: 1979 case AXGBE_AN_MODE_CL73_REDRV: 1980 if (phy_data->cur_mode != AXGBE_MODE_KR) 1981 break; 1982 1983 axgbe_phy_cdr_notrack(pdata); 1984 break; 1985 default: 1986 break; 1987 } 1988 } 1989 1990 static void axgbe_phy_stop(struct axgbe_port *pdata) 1991 { 1992 struct axgbe_phy_data *phy_data = pdata->phy_data; 1993 1994 /* Reset SFP data */ 1995 axgbe_phy_sfp_reset(phy_data); 1996 axgbe_phy_sfp_mod_absent(pdata); 1997 1998 /* Reset CDR support */ 1999 axgbe_phy_cdr_track(pdata); 2000 2001 /* Power off the PHY */ 2002 axgbe_phy_power_off(pdata); 2003 2004 /* Stop the I2C controller */ 2005 pdata->i2c_if.i2c_stop(pdata); 2006 } 2007 2008 static int axgbe_phy_start(struct axgbe_port *pdata) 2009 { 2010 struct axgbe_phy_data *phy_data = pdata->phy_data; 2011 int ret; 2012 2013 /* Start the I2C controller */ 2014 ret = pdata->i2c_if.i2c_start(pdata); 2015 if (ret) 2016 return ret; 2017 2018 /* Start in highest supported mode */ 2019 axgbe_phy_set_mode(pdata, phy_data->start_mode); 2020 2021 /* Reset CDR support */ 2022 axgbe_phy_cdr_track(pdata); 2023 2024 /* After starting the I2C controller, we can check for an SFP */ 2025 switch (phy_data->port_mode) { 2026 case AXGBE_PORT_MODE_SFP: 2027 axgbe_phy_sfp_detect(pdata); 2028 break; 2029 default: 2030 break; 2031 } 2032 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 2033 2034 return ret; 2035 } 2036 2037 static int axgbe_phy_reset(struct axgbe_port *pdata) 2038 { 2039 struct axgbe_phy_data *phy_data = pdata->phy_data; 2040 enum axgbe_mode cur_mode; 2041 2042 /* Reset by power cycling the PHY */ 2043 cur_mode = phy_data->cur_mode; 2044 axgbe_phy_power_off(pdata); 2045 /* First time reset is done with passed unknown mode*/ 2046 axgbe_phy_set_mode(pdata, cur_mode); 2047 return 0; 2048 } 2049 2050 static int axgbe_phy_init(struct axgbe_port *pdata) 2051 { 2052 struct axgbe_phy_data *phy_data; 2053 int ret; 2054 2055 /* Check if enabled */ 2056 if (!axgbe_phy_port_enabled(pdata)) { 2057 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2058 return -ENODEV; 2059 } 2060 2061 /* Initialize the I2C controller */ 2062 ret = pdata->i2c_if.i2c_init(pdata); 2063 if (ret) 2064 return ret; 2065 2066 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2067 if (!phy_data) { 2068 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2069 return -ENOMEM; 2070 } 2071 pdata->phy_data = phy_data; 2072 2073 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 2074 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 2075 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 2076 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 2077 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 2078 2079 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 2080 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 2081 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 2082 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 2083 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 2084 2085 /* Validate the connection requested */ 2086 if (axgbe_phy_conn_type_mismatch(pdata)) { 2087 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2088 phy_data->port_mode, phy_data->conn_type); 2089 return -EINVAL; 2090 } 2091 2092 /* Validate the mode requested */ 2093 if (axgbe_phy_port_mode_mismatch(pdata)) { 2094 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2095 phy_data->port_mode, phy_data->port_speeds); 2096 return -EINVAL; 2097 } 2098 2099 /* Check for and validate MDIO reset support */ 2100 ret = axgbe_phy_mdio_reset_setup(pdata); 2101 if (ret) 2102 return ret; 2103 2104 /* Validate the re-driver information */ 2105 if (axgbe_phy_redrv_error(phy_data)) { 2106 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2107 return -EINVAL; 2108 } 2109 pdata->kr_redrv = phy_data->redrv; 2110 2111 /* Indicate current mode is unknown */ 2112 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2113 2114 /* Initialize supported features */ 2115 pdata->phy.supported = 0; 2116 2117 switch (phy_data->port_mode) { 2118 /* Backplane support */ 2119 case AXGBE_PORT_MODE_BACKPLANE: 2120 pdata->phy.supported |= SUPPORTED_Autoneg; 2121 /* Fallthrough */ 2122 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2123 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2124 pdata->phy.supported |= SUPPORTED_Backplane; 2125 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2126 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2127 phy_data->start_mode = AXGBE_MODE_KX_1000; 2128 } 2129 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2130 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2131 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2132 pdata->phy.supported |= 2133 SUPPORTED_10000baseR_FEC; 2134 phy_data->start_mode = AXGBE_MODE_KR; 2135 } 2136 2137 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2138 break; 2139 case AXGBE_PORT_MODE_BACKPLANE_2500: 2140 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2141 pdata->phy.supported |= SUPPORTED_Backplane; 2142 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2143 phy_data->start_mode = AXGBE_MODE_KX_2500; 2144 2145 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2146 break; 2147 2148 /* MDIO 1GBase-T support */ 2149 case AXGBE_PORT_MODE_1000BASE_T: 2150 pdata->phy.supported |= SUPPORTED_Autoneg; 2151 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2152 pdata->phy.supported |= SUPPORTED_TP; 2153 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2154 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2155 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2156 } 2157 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2158 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2159 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2160 } 2161 2162 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2163 break; 2164 2165 /* MDIO Base-X support */ 2166 case AXGBE_PORT_MODE_1000BASE_X: 2167 pdata->phy.supported |= SUPPORTED_Autoneg; 2168 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2169 pdata->phy.supported |= SUPPORTED_FIBRE; 2170 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2171 phy_data->start_mode = AXGBE_MODE_X; 2172 2173 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2174 break; 2175 2176 /* MDIO NBase-T support */ 2177 case AXGBE_PORT_MODE_NBASE_T: 2178 pdata->phy.supported |= SUPPORTED_Autoneg; 2179 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2180 pdata->phy.supported |= SUPPORTED_TP; 2181 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2182 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2183 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2184 } 2185 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2186 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2187 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2188 } 2189 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2190 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2191 phy_data->start_mode = AXGBE_MODE_KX_2500; 2192 } 2193 2194 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2195 break; 2196 2197 /* 10GBase-T support */ 2198 case AXGBE_PORT_MODE_10GBASE_T: 2199 pdata->phy.supported |= SUPPORTED_Autoneg; 2200 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2201 pdata->phy.supported |= SUPPORTED_TP; 2202 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2203 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2204 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2205 } 2206 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2207 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2208 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2209 } 2210 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2211 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2212 phy_data->start_mode = AXGBE_MODE_KR; 2213 } 2214 2215 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2216 break; 2217 2218 /* 10GBase-R support */ 2219 case AXGBE_PORT_MODE_10GBASE_R: 2220 pdata->phy.supported |= SUPPORTED_Autoneg; 2221 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2222 pdata->phy.supported |= SUPPORTED_TP; 2223 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2224 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2225 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2226 phy_data->start_mode = AXGBE_MODE_SFI; 2227 2228 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2229 break; 2230 2231 /* SFP support */ 2232 case AXGBE_PORT_MODE_SFP: 2233 pdata->phy.supported |= SUPPORTED_Autoneg; 2234 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2235 pdata->phy.supported |= SUPPORTED_TP; 2236 pdata->phy.supported |= SUPPORTED_FIBRE; 2237 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2238 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2239 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2240 } 2241 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2242 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2243 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2244 } 2245 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2246 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2247 phy_data->start_mode = AXGBE_MODE_SFI; 2248 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2249 pdata->phy.supported |= 2250 SUPPORTED_10000baseR_FEC; 2251 } 2252 2253 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2254 2255 axgbe_phy_sfp_setup(pdata); 2256 break; 2257 default: 2258 return -EINVAL; 2259 } 2260 2261 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2262 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2263 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2264 phy_data->phydev_mode); 2265 if (ret) { 2266 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2267 phy_data->mdio_addr, phy_data->phydev_mode); 2268 return -EINVAL; 2269 } 2270 } 2271 2272 if (phy_data->redrv && !phy_data->redrv_if) { 2273 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2274 AXGBE_MDIO_MODE_CL22); 2275 if (ret) { 2276 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2277 phy_data->redrv_addr); 2278 return -EINVAL; 2279 } 2280 } 2281 2282 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2283 return 0; 2284 } 2285 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2286 { 2287 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2288 2289 phy_impl->init = axgbe_phy_init; 2290 phy_impl->reset = axgbe_phy_reset; 2291 phy_impl->start = axgbe_phy_start; 2292 phy_impl->stop = axgbe_phy_stop; 2293 phy_impl->link_status = axgbe_phy_link_status; 2294 phy_impl->use_mode = axgbe_phy_use_mode; 2295 phy_impl->set_mode = axgbe_phy_set_mode; 2296 phy_impl->get_mode = axgbe_phy_get_mode; 2297 phy_impl->switch_mode = axgbe_phy_switch_mode; 2298 phy_impl->cur_mode = axgbe_phy_cur_mode; 2299 phy_impl->an_mode = axgbe_phy_an_mode; 2300 phy_impl->an_config = axgbe_phy_an_config; 2301 phy_impl->an_advertising = axgbe_phy_an_advertising; 2302 phy_impl->an_outcome = axgbe_phy_an_outcome; 2303 2304 phy_impl->an_pre = axgbe_phy_an_pre; 2305 phy_impl->an_post = axgbe_phy_an_post; 2306 2307 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2308 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2309 } 2310