1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_MAX, 50 }; 51 52 enum axgbe_conn_type { 53 AXGBE_CONN_TYPE_NONE = 0, 54 AXGBE_CONN_TYPE_SFP, 55 AXGBE_CONN_TYPE_MDIO, 56 AXGBE_CONN_TYPE_RSVD1, 57 AXGBE_CONN_TYPE_BACKPLANE, 58 AXGBE_CONN_TYPE_MAX, 59 }; 60 61 /* SFP/SFP+ related definitions */ 62 enum axgbe_sfp_comm { 63 AXGBE_SFP_COMM_DIRECT = 0, 64 AXGBE_SFP_COMM_PCA9545, 65 }; 66 67 enum axgbe_sfp_cable { 68 AXGBE_SFP_CABLE_UNKNOWN = 0, 69 AXGBE_SFP_CABLE_ACTIVE, 70 AXGBE_SFP_CABLE_PASSIVE, 71 }; 72 73 enum axgbe_sfp_base { 74 AXGBE_SFP_BASE_UNKNOWN = 0, 75 AXGBE_SFP_BASE_1000_T, 76 AXGBE_SFP_BASE_1000_SX, 77 AXGBE_SFP_BASE_1000_LX, 78 AXGBE_SFP_BASE_1000_CX, 79 AXGBE_SFP_BASE_10000_SR, 80 AXGBE_SFP_BASE_10000_LR, 81 AXGBE_SFP_BASE_10000_LRM, 82 AXGBE_SFP_BASE_10000_ER, 83 AXGBE_SFP_BASE_10000_CR, 84 }; 85 86 enum axgbe_sfp_speed { 87 AXGBE_SFP_SPEED_UNKNOWN = 0, 88 AXGBE_SFP_SPEED_100_1000, 89 AXGBE_SFP_SPEED_1000, 90 AXGBE_SFP_SPEED_10000, 91 }; 92 93 /* SFP Serial ID Base ID values relative to an offset of 0 */ 94 #define AXGBE_SFP_BASE_ID 0 95 #define AXGBE_SFP_ID_SFP 0x03 96 97 #define AXGBE_SFP_BASE_EXT_ID 1 98 #define AXGBE_SFP_EXT_ID_SFP 0x04 99 100 #define AXGBE_SFP_BASE_10GBE_CC 3 101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 105 106 #define AXGBE_SFP_BASE_1GBE_CC 6 107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 111 112 #define AXGBE_SFP_BASE_CABLE 8 113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 115 116 #define AXGBE_SFP_BASE_BR 12 117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 121 122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 123 124 #define AXGBE_SFP_BASE_VENDOR_NAME 20 125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 126 #define AXGBE_SFP_BASE_VENDOR_PN 40 127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 128 #define AXGBE_SFP_BASE_VENDOR_REV 56 129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 130 131 #define AXGBE_SFP_BASE_CC 63 132 133 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 134 #define AXGBE_SFP_BASE_VENDOR_SN 4 135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 136 137 #define AXGBE_SFP_EXTD_DIAG 28 138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 139 140 #define AXGBE_SFP_EXTD_SFF_8472 30 141 142 #define AXGBE_SFP_EXTD_CC 31 143 144 struct axgbe_sfp_eeprom { 145 u8 base[64]; 146 u8 extd[32]; 147 u8 vendor[32]; 148 }; 149 150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 152 153 struct axgbe_sfp_ascii { 154 union { 155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 159 } u; 160 }; 161 162 /* MDIO PHY reset types */ 163 enum axgbe_mdio_reset { 164 AXGBE_MDIO_RESET_NONE = 0, 165 AXGBE_MDIO_RESET_I2C_GPIO, 166 AXGBE_MDIO_RESET_INT_GPIO, 167 AXGBE_MDIO_RESET_MAX, 168 }; 169 170 /* Re-driver related definitions */ 171 enum axgbe_phy_redrv_if { 172 AXGBE_PHY_REDRV_IF_MDIO = 0, 173 AXGBE_PHY_REDRV_IF_I2C, 174 AXGBE_PHY_REDRV_IF_MAX, 175 }; 176 177 enum axgbe_phy_redrv_model { 178 AXGBE_PHY_REDRV_MODEL_4223 = 0, 179 AXGBE_PHY_REDRV_MODEL_4227, 180 AXGBE_PHY_REDRV_MODEL_MAX, 181 }; 182 183 enum axgbe_phy_redrv_mode { 184 AXGBE_PHY_REDRV_MODE_CX = 5, 185 AXGBE_PHY_REDRV_MODE_SR = 9, 186 }; 187 188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 189 190 /* PHY related configuration information */ 191 struct axgbe_phy_data { 192 enum axgbe_port_mode port_mode; 193 194 unsigned int port_id; 195 196 unsigned int port_speeds; 197 198 enum axgbe_conn_type conn_type; 199 200 enum axgbe_mode cur_mode; 201 enum axgbe_mode start_mode; 202 203 unsigned int rrc_count; 204 205 unsigned int mdio_addr; 206 207 unsigned int comm_owned; 208 209 /* SFP Support */ 210 enum axgbe_sfp_comm sfp_comm; 211 unsigned int sfp_mux_address; 212 unsigned int sfp_mux_channel; 213 214 unsigned int sfp_gpio_address; 215 unsigned int sfp_gpio_mask; 216 unsigned int sfp_gpio_rx_los; 217 unsigned int sfp_gpio_tx_fault; 218 unsigned int sfp_gpio_mod_absent; 219 unsigned int sfp_gpio_rate_select; 220 221 unsigned int sfp_rx_los; 222 unsigned int sfp_tx_fault; 223 unsigned int sfp_mod_absent; 224 unsigned int sfp_diags; 225 unsigned int sfp_changed; 226 unsigned int sfp_phy_avail; 227 unsigned int sfp_cable_len; 228 enum axgbe_sfp_base sfp_base; 229 enum axgbe_sfp_cable sfp_cable; 230 enum axgbe_sfp_speed sfp_speed; 231 struct axgbe_sfp_eeprom sfp_eeprom; 232 233 /* External PHY support */ 234 enum axgbe_mdio_mode phydev_mode; 235 enum axgbe_mdio_reset mdio_reset; 236 unsigned int mdio_reset_addr; 237 unsigned int mdio_reset_gpio; 238 239 /* Re-driver support */ 240 unsigned int redrv; 241 unsigned int redrv_if; 242 unsigned int redrv_addr; 243 unsigned int redrv_lane; 244 unsigned int redrv_model; 245 246 /* KR AN support */ 247 unsigned int phy_cdr_notrack; 248 unsigned int phy_cdr_delay; 249 }; 250 251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 252 253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 254 struct axgbe_i2c_op *i2c_op) 255 { 256 struct axgbe_phy_data *phy_data = pdata->phy_data; 257 258 /* Be sure we own the bus */ 259 if (!phy_data->comm_owned) 260 return -EIO; 261 262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 263 } 264 265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 266 unsigned int val) 267 { 268 struct axgbe_phy_data *phy_data = pdata->phy_data; 269 struct axgbe_i2c_op i2c_op; 270 uint16_t *redrv_val; 271 u8 redrv_data[5], csum; 272 unsigned int i, retry; 273 int ret; 274 275 /* High byte of register contains read/write indicator */ 276 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 277 redrv_data[1] = reg & 0xff; 278 redrv_val = (uint16_t *)&redrv_data[2]; 279 *redrv_val = rte_cpu_to_be_16(val); 280 281 /* Calculate 1 byte checksum */ 282 csum = 0; 283 for (i = 0; i < 4; i++) { 284 csum += redrv_data[i]; 285 if (redrv_data[i] > csum) 286 csum++; 287 } 288 redrv_data[4] = ~csum; 289 290 retry = 1; 291 again1: 292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 293 i2c_op.target = phy_data->redrv_addr; 294 i2c_op.len = sizeof(redrv_data); 295 i2c_op.buf = redrv_data; 296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 297 if (ret) { 298 if ((ret == -EAGAIN) && retry--) 299 goto again1; 300 301 return ret; 302 } 303 304 retry = 1; 305 again2: 306 i2c_op.cmd = AXGBE_I2C_CMD_READ; 307 i2c_op.target = phy_data->redrv_addr; 308 i2c_op.len = 1; 309 i2c_op.buf = redrv_data; 310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 311 if (ret) { 312 if ((ret == -EAGAIN) && retry--) 313 goto again2; 314 315 return ret; 316 } 317 318 if (redrv_data[0] != 0xff) { 319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 320 ret = -EIO; 321 } 322 323 return ret; 324 } 325 326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 327 void *reg, unsigned int reg_len, 328 void *val, unsigned int val_len) 329 { 330 struct axgbe_i2c_op i2c_op; 331 int retry, ret; 332 333 retry = 1; 334 again1: 335 /* Set the specified register to read */ 336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 337 i2c_op.target = target; 338 i2c_op.len = reg_len; 339 i2c_op.buf = reg; 340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 341 if (ret) { 342 if ((ret == -EAGAIN) && retry--) 343 goto again1; 344 345 return ret; 346 } 347 348 retry = 1; 349 again2: 350 /* Read the specfied register */ 351 i2c_op.cmd = AXGBE_I2C_CMD_READ; 352 i2c_op.target = target; 353 i2c_op.len = val_len; 354 i2c_op.buf = val; 355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 356 if ((ret == -EAGAIN) && retry--) 357 goto again2; 358 359 return ret; 360 } 361 362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 363 { 364 struct axgbe_phy_data *phy_data = pdata->phy_data; 365 struct axgbe_i2c_op i2c_op; 366 uint8_t mux_channel; 367 368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 369 return 0; 370 371 /* Select no mux channels */ 372 mux_channel = 0; 373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 374 i2c_op.target = phy_data->sfp_mux_address; 375 i2c_op.len = sizeof(mux_channel); 376 i2c_op.buf = &mux_channel; 377 378 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 379 } 380 381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 382 { 383 struct axgbe_phy_data *phy_data = pdata->phy_data; 384 struct axgbe_i2c_op i2c_op; 385 u8 mux_channel; 386 387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 388 return 0; 389 390 /* Select desired mux channel */ 391 mux_channel = 1 << phy_data->sfp_mux_channel; 392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 393 i2c_op.target = phy_data->sfp_mux_address; 394 i2c_op.len = sizeof(mux_channel); 395 i2c_op.buf = &mux_channel; 396 397 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 398 } 399 400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 401 { 402 struct axgbe_phy_data *phy_data = pdata->phy_data; 403 404 phy_data->comm_owned = 0; 405 406 pthread_mutex_unlock(&pdata->phy_mutex); 407 } 408 409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 410 { 411 struct axgbe_phy_data *phy_data = pdata->phy_data; 412 uint64_t timeout; 413 unsigned int mutex_id; 414 415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 416 * the driver needs to take the software mutex and then the hardware 417 * mutexes before being able to use the busses. 418 */ 419 pthread_mutex_lock(&pdata->phy_mutex); 420 421 if (phy_data->comm_owned) 422 return 0; 423 424 /* Clear the mutexes */ 425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 427 428 /* Mutex formats are the same for I2C and MDIO/GPIO */ 429 mutex_id = 0; 430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 432 433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 434 while (time_before(rte_get_timer_cycles(), timeout)) { 435 /* Must be all zeroes in order to obtain the mutex */ 436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 438 rte_delay_us(100); 439 continue; 440 } 441 442 /* Obtain the mutex */ 443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 445 446 phy_data->comm_owned = 1; 447 return 0; 448 } 449 450 pthread_mutex_unlock(&pdata->phy_mutex); 451 452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 453 454 return -ETIMEDOUT; 455 } 456 457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 458 { 459 struct axgbe_phy_data *phy_data = pdata->phy_data; 460 461 if (phy_data->sfp_mod_absent) { 462 pdata->phy.speed = SPEED_UNKNOWN; 463 pdata->phy.duplex = DUPLEX_UNKNOWN; 464 pdata->phy.autoneg = AUTONEG_ENABLE; 465 pdata->phy.advertising = pdata->phy.supported; 466 } 467 468 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 469 pdata->phy.advertising &= ~ADVERTISED_TP; 470 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 475 476 switch (phy_data->sfp_base) { 477 case AXGBE_SFP_BASE_1000_T: 478 case AXGBE_SFP_BASE_1000_SX: 479 case AXGBE_SFP_BASE_1000_LX: 480 case AXGBE_SFP_BASE_1000_CX: 481 pdata->phy.speed = SPEED_UNKNOWN; 482 pdata->phy.duplex = DUPLEX_UNKNOWN; 483 pdata->phy.autoneg = AUTONEG_ENABLE; 484 pdata->phy.advertising |= ADVERTISED_Autoneg; 485 break; 486 case AXGBE_SFP_BASE_10000_SR: 487 case AXGBE_SFP_BASE_10000_LR: 488 case AXGBE_SFP_BASE_10000_LRM: 489 case AXGBE_SFP_BASE_10000_ER: 490 case AXGBE_SFP_BASE_10000_CR: 491 default: 492 pdata->phy.speed = SPEED_10000; 493 pdata->phy.duplex = DUPLEX_FULL; 494 pdata->phy.autoneg = AUTONEG_DISABLE; 495 break; 496 } 497 498 switch (phy_data->sfp_base) { 499 case AXGBE_SFP_BASE_1000_T: 500 case AXGBE_SFP_BASE_1000_CX: 501 case AXGBE_SFP_BASE_10000_CR: 502 pdata->phy.advertising |= ADVERTISED_TP; 503 break; 504 default: 505 pdata->phy.advertising |= ADVERTISED_FIBRE; 506 } 507 508 switch (phy_data->sfp_speed) { 509 case AXGBE_SFP_SPEED_100_1000: 510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 511 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 514 break; 515 case AXGBE_SFP_SPEED_1000: 516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 518 break; 519 case AXGBE_SFP_SPEED_10000: 520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 522 break; 523 default: 524 /* Choose the fastest supported speed */ 525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 530 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 531 } 532 } 533 534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 535 enum axgbe_sfp_speed sfp_speed) 536 { 537 u8 *sfp_base, min, max; 538 539 sfp_base = sfp_eeprom->base; 540 541 switch (sfp_speed) { 542 case AXGBE_SFP_SPEED_1000: 543 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 544 max = AXGBE_SFP_BASE_BR_1GBE_MAX; 545 break; 546 case AXGBE_SFP_SPEED_10000: 547 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 548 max = AXGBE_SFP_BASE_BR_10GBE_MAX; 549 break; 550 default: 551 return false; 552 } 553 554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) && 555 (sfp_base[AXGBE_SFP_BASE_BR] <= max)); 556 } 557 558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 559 { 560 struct axgbe_phy_data *phy_data = pdata->phy_data; 561 562 if (!phy_data->sfp_changed) 563 return; 564 565 phy_data->sfp_phy_avail = 0; 566 567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 568 return; 569 } 570 571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 572 { 573 struct axgbe_phy_data *phy_data = pdata->phy_data; 574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 575 576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 578 return false; 579 580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 585 return true; 586 } 587 588 return false; 589 } 590 591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 592 { 593 if (axgbe_phy_belfuse_parse_quirks(pdata)) 594 return true; 595 596 return false; 597 } 598 599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 600 { 601 struct axgbe_phy_data *phy_data = pdata->phy_data; 602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 603 uint8_t *sfp_base; 604 605 sfp_base = sfp_eeprom->base; 606 607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 608 return; 609 610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 611 return; 612 613 axgbe_phy_sfp_parse_quirks(pdata); 614 615 /* Assume ACTIVE cable unless told it is PASSIVE */ 616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 619 } else { 620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 621 } 622 623 /* Determine the type of SFP */ 624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 629 AXGBE_SFP_BASE_10GBE_CC_LRM) 630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) && 642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 644 645 switch (phy_data->sfp_base) { 646 case AXGBE_SFP_BASE_1000_T: 647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 648 break; 649 case AXGBE_SFP_BASE_1000_SX: 650 case AXGBE_SFP_BASE_1000_LX: 651 case AXGBE_SFP_BASE_1000_CX: 652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 653 break; 654 case AXGBE_SFP_BASE_10000_SR: 655 case AXGBE_SFP_BASE_10000_LR: 656 case AXGBE_SFP_BASE_10000_LRM: 657 case AXGBE_SFP_BASE_10000_ER: 658 case AXGBE_SFP_BASE_10000_CR: 659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 660 break; 661 default: 662 break; 663 } 664 } 665 666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 667 unsigned int len) 668 { 669 uint8_t cc; 670 671 for (cc = 0; len; buf++, len--) 672 cc += *buf; 673 674 return (cc == cc_in) ? true : false; 675 } 676 677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 678 { 679 struct axgbe_phy_data *phy_data = pdata->phy_data; 680 struct axgbe_sfp_eeprom sfp_eeprom; 681 uint8_t eeprom_addr; 682 int ret; 683 684 ret = axgbe_phy_sfp_get_mux(pdata); 685 if (ret) { 686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 687 return ret; 688 } 689 690 /* Read the SFP serial ID eeprom */ 691 eeprom_addr = 0; 692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 693 &eeprom_addr, sizeof(eeprom_addr), 694 &sfp_eeprom, sizeof(sfp_eeprom)); 695 if (ret) { 696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 697 goto put; 698 } 699 700 /* Validate the contents read */ 701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 702 sfp_eeprom.base, 703 sizeof(sfp_eeprom.base) - 1)) { 704 ret = -EINVAL; 705 goto put; 706 } 707 708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 709 sfp_eeprom.extd, 710 sizeof(sfp_eeprom.extd) - 1)) { 711 ret = -EINVAL; 712 goto put; 713 } 714 715 /* Check for an added or changed SFP */ 716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 717 phy_data->sfp_changed = 1; 718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 719 720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) { 721 uint8_t diag_type; 722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG]; 723 724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 725 phy_data->sfp_diags = 1; 726 } 727 } else { 728 phy_data->sfp_changed = 0; 729 } 730 731 put: 732 axgbe_phy_sfp_put_mux(pdata); 733 734 return ret; 735 } 736 737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 738 { 739 struct axgbe_phy_data *phy_data = pdata->phy_data; 740 unsigned int gpio_input; 741 u8 gpio_reg, gpio_ports[2]; 742 int ret; 743 744 /* Read the input port registers */ 745 gpio_reg = 0; 746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 747 &gpio_reg, sizeof(gpio_reg), 748 gpio_ports, sizeof(gpio_ports)); 749 if (ret) { 750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 751 return; 752 } 753 754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 755 756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 757 /* No GPIO, just assume the module is present for now */ 758 phy_data->sfp_mod_absent = 0; 759 } else { 760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 761 phy_data->sfp_mod_absent = 0; 762 } 763 764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 766 phy_data->sfp_rx_los = 1; 767 768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 770 phy_data->sfp_tx_fault = 1; 771 } 772 773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 774 { 775 struct axgbe_phy_data *phy_data = pdata->phy_data; 776 777 phy_data->sfp_mod_absent = 1; 778 phy_data->sfp_phy_avail = 0; 779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 780 } 781 782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 783 { 784 phy_data->sfp_rx_los = 0; 785 phy_data->sfp_tx_fault = 0; 786 phy_data->sfp_mod_absent = 1; 787 phy_data->sfp_diags = 0; 788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 791 } 792 793 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 794 { 795 struct axgbe_phy_data *phy_data = pdata->phy_data; 796 int ret; 797 798 /* Reset the SFP signals and info */ 799 axgbe_phy_sfp_reset(phy_data); 800 801 ret = axgbe_phy_get_comm_ownership(pdata); 802 if (ret) 803 return; 804 805 /* Read the SFP signals and check for module presence */ 806 axgbe_phy_sfp_signals(pdata); 807 if (phy_data->sfp_mod_absent) { 808 axgbe_phy_sfp_mod_absent(pdata); 809 goto put; 810 } 811 812 ret = axgbe_phy_sfp_read_eeprom(pdata); 813 if (ret) { 814 /* Treat any error as if there isn't an SFP plugged in */ 815 axgbe_phy_sfp_reset(phy_data); 816 axgbe_phy_sfp_mod_absent(pdata); 817 goto put; 818 } 819 820 axgbe_phy_sfp_parse_eeprom(pdata); 821 axgbe_phy_sfp_external_phy(pdata); 822 823 put: 824 axgbe_phy_sfp_phy_settings(pdata); 825 axgbe_phy_put_comm_ownership(pdata); 826 } 827 828 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 829 { 830 pdata->phy.tx_pause = 0; 831 pdata->phy.rx_pause = 0; 832 } 833 834 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 835 { 836 struct axgbe_phy_data *phy_data = pdata->phy_data; 837 enum axgbe_mode mode; 838 unsigned int ad_reg, lp_reg; 839 840 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 841 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 842 843 /* Use external PHY to determine flow control */ 844 if (pdata->phy.pause_autoneg) 845 axgbe_phy_phydev_flowctrl(pdata); 846 847 /* Compare Advertisement and Link Partner register 2 */ 848 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 849 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 850 if (lp_reg & 0x80) 851 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 852 if (lp_reg & 0x20) 853 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 854 855 ad_reg &= lp_reg; 856 if (ad_reg & 0x80) { 857 switch (phy_data->port_mode) { 858 case AXGBE_PORT_MODE_BACKPLANE: 859 mode = AXGBE_MODE_KR; 860 break; 861 default: 862 mode = AXGBE_MODE_SFI; 863 break; 864 } 865 } else if (ad_reg & 0x20) { 866 switch (phy_data->port_mode) { 867 case AXGBE_PORT_MODE_BACKPLANE: 868 mode = AXGBE_MODE_KX_1000; 869 break; 870 case AXGBE_PORT_MODE_1000BASE_X: 871 mode = AXGBE_MODE_X; 872 break; 873 case AXGBE_PORT_MODE_SFP: 874 switch (phy_data->sfp_base) { 875 case AXGBE_SFP_BASE_1000_T: 876 mode = AXGBE_MODE_SGMII_1000; 877 break; 878 case AXGBE_SFP_BASE_1000_SX: 879 case AXGBE_SFP_BASE_1000_LX: 880 case AXGBE_SFP_BASE_1000_CX: 881 default: 882 mode = AXGBE_MODE_X; 883 break; 884 } 885 break; 886 default: 887 mode = AXGBE_MODE_SGMII_1000; 888 break; 889 } 890 } else { 891 mode = AXGBE_MODE_UNKNOWN; 892 } 893 894 /* Compare Advertisement and Link Partner register 3 */ 895 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 896 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 897 if (lp_reg & 0xc000) 898 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 899 900 return mode; 901 } 902 903 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 904 { 905 enum axgbe_mode mode; 906 unsigned int ad_reg, lp_reg; 907 908 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 909 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 910 911 /* Compare Advertisement and Link Partner register 1 */ 912 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 913 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 914 if (lp_reg & 0x400) 915 pdata->phy.lp_advertising |= ADVERTISED_Pause; 916 if (lp_reg & 0x800) 917 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 918 919 if (pdata->phy.pause_autoneg) { 920 /* Set flow control based on auto-negotiation result */ 921 pdata->phy.tx_pause = 0; 922 pdata->phy.rx_pause = 0; 923 924 if (ad_reg & lp_reg & 0x400) { 925 pdata->phy.tx_pause = 1; 926 pdata->phy.rx_pause = 1; 927 } else if (ad_reg & lp_reg & 0x800) { 928 if (ad_reg & 0x400) 929 pdata->phy.rx_pause = 1; 930 else if (lp_reg & 0x400) 931 pdata->phy.tx_pause = 1; 932 } 933 } 934 935 /* Compare Advertisement and Link Partner register 2 */ 936 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 937 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 938 if (lp_reg & 0x80) 939 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 940 if (lp_reg & 0x20) 941 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 942 943 ad_reg &= lp_reg; 944 if (ad_reg & 0x80) 945 mode = AXGBE_MODE_KR; 946 else if (ad_reg & 0x20) 947 mode = AXGBE_MODE_KX_1000; 948 else 949 mode = AXGBE_MODE_UNKNOWN; 950 951 /* Compare Advertisement and Link Partner register 3 */ 952 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 953 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 954 if (lp_reg & 0xc000) 955 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 956 957 return mode; 958 } 959 960 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 961 { 962 switch (pdata->an_mode) { 963 case AXGBE_AN_MODE_CL73: 964 return axgbe_phy_an73_outcome(pdata); 965 case AXGBE_AN_MODE_CL73_REDRV: 966 return axgbe_phy_an73_redrv_outcome(pdata); 967 case AXGBE_AN_MODE_CL37: 968 case AXGBE_AN_MODE_CL37_SGMII: 969 default: 970 return AXGBE_MODE_UNKNOWN; 971 } 972 } 973 974 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 975 { 976 struct axgbe_phy_data *phy_data = pdata->phy_data; 977 unsigned int advertising; 978 979 /* Without a re-driver, just return current advertising */ 980 if (!phy_data->redrv) 981 return pdata->phy.advertising; 982 983 /* With the KR re-driver we need to advertise a single speed */ 984 advertising = pdata->phy.advertising; 985 advertising &= ~ADVERTISED_1000baseKX_Full; 986 advertising &= ~ADVERTISED_10000baseKR_Full; 987 988 switch (phy_data->port_mode) { 989 case AXGBE_PORT_MODE_BACKPLANE: 990 advertising |= ADVERTISED_10000baseKR_Full; 991 break; 992 case AXGBE_PORT_MODE_BACKPLANE_2500: 993 advertising |= ADVERTISED_1000baseKX_Full; 994 break; 995 case AXGBE_PORT_MODE_1000BASE_T: 996 case AXGBE_PORT_MODE_1000BASE_X: 997 case AXGBE_PORT_MODE_NBASE_T: 998 advertising |= ADVERTISED_1000baseKX_Full; 999 break; 1000 case AXGBE_PORT_MODE_10GBASE_T: 1001 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1002 break; 1003 case AXGBE_PORT_MODE_10GBASE_R: 1004 advertising |= ADVERTISED_10000baseKR_Full; 1005 break; 1006 case AXGBE_PORT_MODE_SFP: 1007 switch (phy_data->sfp_base) { 1008 case AXGBE_SFP_BASE_1000_T: 1009 case AXGBE_SFP_BASE_1000_SX: 1010 case AXGBE_SFP_BASE_1000_LX: 1011 case AXGBE_SFP_BASE_1000_CX: 1012 advertising |= ADVERTISED_1000baseKX_Full; 1013 break; 1014 default: 1015 advertising |= ADVERTISED_10000baseKR_Full; 1016 break; 1017 } 1018 break; 1019 default: 1020 advertising |= ADVERTISED_10000baseKR_Full; 1021 break; 1022 } 1023 1024 return advertising; 1025 } 1026 1027 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1028 { 1029 return 0; 1030 /* Dummy API since there is no case to support 1031 * external phy devices registred through kerenl apis 1032 */ 1033 } 1034 1035 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1036 { 1037 switch (phy_data->sfp_base) { 1038 case AXGBE_SFP_BASE_1000_T: 1039 return AXGBE_AN_MODE_CL37_SGMII; 1040 case AXGBE_SFP_BASE_1000_SX: 1041 case AXGBE_SFP_BASE_1000_LX: 1042 case AXGBE_SFP_BASE_1000_CX: 1043 return AXGBE_AN_MODE_CL37; 1044 default: 1045 return AXGBE_AN_MODE_NONE; 1046 } 1047 } 1048 1049 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1050 { 1051 struct axgbe_phy_data *phy_data = pdata->phy_data; 1052 1053 /* A KR re-driver will always require CL73 AN */ 1054 if (phy_data->redrv) 1055 return AXGBE_AN_MODE_CL73_REDRV; 1056 1057 switch (phy_data->port_mode) { 1058 case AXGBE_PORT_MODE_BACKPLANE: 1059 return AXGBE_AN_MODE_CL73; 1060 case AXGBE_PORT_MODE_BACKPLANE_2500: 1061 return AXGBE_AN_MODE_NONE; 1062 case AXGBE_PORT_MODE_1000BASE_T: 1063 return AXGBE_AN_MODE_CL37_SGMII; 1064 case AXGBE_PORT_MODE_1000BASE_X: 1065 return AXGBE_AN_MODE_CL37; 1066 case AXGBE_PORT_MODE_NBASE_T: 1067 return AXGBE_AN_MODE_CL37_SGMII; 1068 case AXGBE_PORT_MODE_10GBASE_T: 1069 return AXGBE_AN_MODE_CL73; 1070 case AXGBE_PORT_MODE_10GBASE_R: 1071 return AXGBE_AN_MODE_NONE; 1072 case AXGBE_PORT_MODE_SFP: 1073 return axgbe_phy_an_sfp_mode(phy_data); 1074 default: 1075 return AXGBE_AN_MODE_NONE; 1076 } 1077 } 1078 1079 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1080 enum axgbe_phy_redrv_mode mode) 1081 { 1082 struct axgbe_phy_data *phy_data = pdata->phy_data; 1083 u16 redrv_reg, redrv_val; 1084 1085 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1086 redrv_val = (u16)mode; 1087 1088 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1089 redrv_reg, redrv_val); 1090 } 1091 1092 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1093 enum axgbe_phy_redrv_mode mode) 1094 { 1095 struct axgbe_phy_data *phy_data = pdata->phy_data; 1096 unsigned int redrv_reg; 1097 int ret; 1098 1099 /* Calculate the register to write */ 1100 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1101 1102 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1103 1104 return ret; 1105 } 1106 1107 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1108 { 1109 struct axgbe_phy_data *phy_data = pdata->phy_data; 1110 enum axgbe_phy_redrv_mode mode; 1111 int ret; 1112 1113 if (!phy_data->redrv) 1114 return; 1115 1116 mode = AXGBE_PHY_REDRV_MODE_CX; 1117 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1118 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1119 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1120 mode = AXGBE_PHY_REDRV_MODE_SR; 1121 1122 ret = axgbe_phy_get_comm_ownership(pdata); 1123 if (ret) 1124 return; 1125 1126 if (phy_data->redrv_if) 1127 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1128 else 1129 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1130 1131 axgbe_phy_put_comm_ownership(pdata); 1132 } 1133 1134 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) 1135 { 1136 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1137 return; 1138 } 1139 1140 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata) 1141 { 1142 unsigned int wait; 1143 1144 /* Wait for command to complete */ 1145 wait = AXGBE_RATECHANGE_COUNT; 1146 while (wait--) { 1147 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1148 return; 1149 1150 rte_delay_us(1500); 1151 } 1152 } 1153 1154 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1155 { 1156 unsigned int s0; 1157 1158 axgbe_phy_start_ratechange(pdata); 1159 1160 /* Receiver Reset Cycle */ 1161 s0 = 0; 1162 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5); 1163 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1164 1165 /* Call FW to make the change */ 1166 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1167 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1168 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1169 1170 axgbe_phy_complete_ratechange(pdata); 1171 } 1172 1173 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1174 { 1175 struct axgbe_phy_data *phy_data = pdata->phy_data; 1176 1177 axgbe_phy_start_ratechange(pdata); 1178 1179 /* Call FW to make the change */ 1180 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0); 1181 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1182 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1183 axgbe_phy_complete_ratechange(pdata); 1184 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1185 } 1186 1187 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1188 { 1189 struct axgbe_phy_data *phy_data = pdata->phy_data; 1190 unsigned int s0; 1191 1192 axgbe_phy_set_redrv_mode(pdata); 1193 1194 axgbe_phy_start_ratechange(pdata); 1195 1196 /* 10G/SFI */ 1197 s0 = 0; 1198 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3); 1199 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1200 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1201 } else { 1202 if (phy_data->sfp_cable_len <= 1) 1203 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1); 1204 else if (phy_data->sfp_cable_len <= 3) 1205 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1206 else 1207 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3); 1208 } 1209 1210 /* Call FW to make the change */ 1211 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1212 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1213 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1214 axgbe_phy_complete_ratechange(pdata); 1215 phy_data->cur_mode = AXGBE_MODE_SFI; 1216 } 1217 1218 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1219 { 1220 struct axgbe_phy_data *phy_data = pdata->phy_data; 1221 unsigned int s0; 1222 1223 axgbe_phy_set_redrv_mode(pdata); 1224 1225 axgbe_phy_start_ratechange(pdata); 1226 1227 /* 10G/KR */ 1228 s0 = 0; 1229 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4); 1230 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1231 1232 /* Call FW to make the change */ 1233 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1234 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1235 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1236 axgbe_phy_complete_ratechange(pdata); 1237 phy_data->cur_mode = AXGBE_MODE_KR; 1238 } 1239 1240 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1241 { 1242 struct axgbe_phy_data *phy_data = pdata->phy_data; 1243 unsigned int s0; 1244 1245 axgbe_phy_set_redrv_mode(pdata); 1246 /* 2.5G/KX */ 1247 axgbe_phy_start_ratechange(pdata); 1248 s0 = 0; 1249 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 2); 1250 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1251 1252 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1253 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1254 1255 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1256 1257 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1258 } 1259 1260 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1261 { 1262 struct axgbe_phy_data *phy_data = pdata->phy_data; 1263 unsigned int s0; 1264 1265 axgbe_phy_set_redrv_mode(pdata); 1266 1267 /* 1G/SGMII */ 1268 axgbe_phy_start_ratechange(pdata); 1269 s0 = 0; 1270 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 1); 1271 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1272 1273 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1274 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1275 1276 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1277 1278 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1279 } 1280 1281 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1282 { 1283 struct axgbe_phy_data *phy_data = pdata->phy_data; 1284 1285 return phy_data->cur_mode; 1286 } 1287 1288 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1289 { 1290 struct axgbe_phy_data *phy_data = pdata->phy_data; 1291 1292 /* No switching if not 10GBase-T */ 1293 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1294 return axgbe_phy_cur_mode(pdata); 1295 1296 switch (axgbe_phy_cur_mode(pdata)) { 1297 case AXGBE_MODE_SGMII_100: 1298 case AXGBE_MODE_SGMII_1000: 1299 return AXGBE_MODE_KR; 1300 case AXGBE_MODE_KR: 1301 default: 1302 return AXGBE_MODE_SGMII_1000; 1303 } 1304 } 1305 1306 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1307 __rte_unused) 1308 { 1309 return AXGBE_MODE_KX_2500; 1310 } 1311 1312 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1313 { 1314 /* If we are in KR switch to KX, and vice-versa */ 1315 switch (axgbe_phy_cur_mode(pdata)) { 1316 case AXGBE_MODE_KX_1000: 1317 return AXGBE_MODE_KR; 1318 case AXGBE_MODE_KR: 1319 default: 1320 return AXGBE_MODE_KX_1000; 1321 } 1322 } 1323 1324 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1325 { 1326 struct axgbe_phy_data *phy_data = pdata->phy_data; 1327 1328 switch (phy_data->port_mode) { 1329 case AXGBE_PORT_MODE_BACKPLANE: 1330 return axgbe_phy_switch_bp_mode(pdata); 1331 case AXGBE_PORT_MODE_BACKPLANE_2500: 1332 return axgbe_phy_switch_bp_2500_mode(pdata); 1333 case AXGBE_PORT_MODE_1000BASE_T: 1334 case AXGBE_PORT_MODE_NBASE_T: 1335 case AXGBE_PORT_MODE_10GBASE_T: 1336 return axgbe_phy_switch_baset_mode(pdata); 1337 case AXGBE_PORT_MODE_1000BASE_X: 1338 case AXGBE_PORT_MODE_10GBASE_R: 1339 case AXGBE_PORT_MODE_SFP: 1340 /* No switching, so just return current mode */ 1341 return axgbe_phy_cur_mode(pdata); 1342 default: 1343 return AXGBE_MODE_UNKNOWN; 1344 } 1345 } 1346 1347 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1348 __rte_unused, 1349 int speed) 1350 { 1351 switch (speed) { 1352 case SPEED_1000: 1353 return AXGBE_MODE_X; 1354 case SPEED_10000: 1355 return AXGBE_MODE_KR; 1356 default: 1357 return AXGBE_MODE_UNKNOWN; 1358 } 1359 } 1360 1361 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1362 __rte_unused, 1363 int speed) 1364 { 1365 switch (speed) { 1366 case SPEED_100: 1367 return AXGBE_MODE_SGMII_100; 1368 case SPEED_1000: 1369 return AXGBE_MODE_SGMII_1000; 1370 case SPEED_10000: 1371 return AXGBE_MODE_KR; 1372 default: 1373 return AXGBE_MODE_UNKNOWN; 1374 } 1375 } 1376 1377 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1378 int speed) 1379 { 1380 switch (speed) { 1381 case SPEED_100: 1382 return AXGBE_MODE_SGMII_100; 1383 case SPEED_1000: 1384 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1385 return AXGBE_MODE_SGMII_1000; 1386 else 1387 return AXGBE_MODE_X; 1388 case SPEED_10000: 1389 case SPEED_UNKNOWN: 1390 return AXGBE_MODE_SFI; 1391 default: 1392 return AXGBE_MODE_UNKNOWN; 1393 } 1394 } 1395 1396 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1397 { 1398 switch (speed) { 1399 case SPEED_2500: 1400 return AXGBE_MODE_KX_2500; 1401 default: 1402 return AXGBE_MODE_UNKNOWN; 1403 } 1404 } 1405 1406 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1407 { 1408 switch (speed) { 1409 case SPEED_1000: 1410 return AXGBE_MODE_KX_1000; 1411 case SPEED_10000: 1412 return AXGBE_MODE_KR; 1413 default: 1414 return AXGBE_MODE_UNKNOWN; 1415 } 1416 } 1417 1418 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1419 int speed) 1420 { 1421 struct axgbe_phy_data *phy_data = pdata->phy_data; 1422 1423 switch (phy_data->port_mode) { 1424 case AXGBE_PORT_MODE_BACKPLANE: 1425 return axgbe_phy_get_bp_mode(speed); 1426 case AXGBE_PORT_MODE_BACKPLANE_2500: 1427 return axgbe_phy_get_bp_2500_mode(speed); 1428 case AXGBE_PORT_MODE_1000BASE_T: 1429 case AXGBE_PORT_MODE_NBASE_T: 1430 case AXGBE_PORT_MODE_10GBASE_T: 1431 return axgbe_phy_get_baset_mode(phy_data, speed); 1432 case AXGBE_PORT_MODE_1000BASE_X: 1433 case AXGBE_PORT_MODE_10GBASE_R: 1434 return axgbe_phy_get_basex_mode(phy_data, speed); 1435 case AXGBE_PORT_MODE_SFP: 1436 return axgbe_phy_get_sfp_mode(phy_data, speed); 1437 default: 1438 return AXGBE_MODE_UNKNOWN; 1439 } 1440 } 1441 1442 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1443 { 1444 switch (mode) { 1445 case AXGBE_MODE_KR: 1446 axgbe_phy_kr_mode(pdata); 1447 break; 1448 case AXGBE_MODE_SFI: 1449 axgbe_phy_sfi_mode(pdata); 1450 break; 1451 case AXGBE_MODE_KX_2500: 1452 axgbe_phy_kx_2500_mode(pdata); 1453 break; 1454 case AXGBE_MODE_SGMII_1000: 1455 axgbe_phy_sgmii_1000_mode(pdata); 1456 break; 1457 default: 1458 break; 1459 } 1460 } 1461 1462 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1463 enum axgbe_mode mode, u32 advert) 1464 { 1465 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1466 if (pdata->phy.advertising & advert) 1467 return true; 1468 } else { 1469 enum axgbe_mode cur_mode; 1470 1471 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1472 if (cur_mode == mode) 1473 return true; 1474 } 1475 1476 return false; 1477 } 1478 1479 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1480 enum axgbe_mode mode) 1481 { 1482 switch (mode) { 1483 case AXGBE_MODE_X: 1484 return axgbe_phy_check_mode(pdata, mode, 1485 ADVERTISED_1000baseT_Full); 1486 case AXGBE_MODE_KR: 1487 return axgbe_phy_check_mode(pdata, mode, 1488 ADVERTISED_10000baseT_Full); 1489 default: 1490 return false; 1491 } 1492 } 1493 1494 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1495 enum axgbe_mode mode) 1496 { 1497 switch (mode) { 1498 case AXGBE_MODE_SGMII_100: 1499 return axgbe_phy_check_mode(pdata, mode, 1500 ADVERTISED_100baseT_Full); 1501 case AXGBE_MODE_SGMII_1000: 1502 return axgbe_phy_check_mode(pdata, mode, 1503 ADVERTISED_1000baseT_Full); 1504 case AXGBE_MODE_KR: 1505 return axgbe_phy_check_mode(pdata, mode, 1506 ADVERTISED_10000baseT_Full); 1507 default: 1508 return false; 1509 } 1510 } 1511 1512 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1513 enum axgbe_mode mode) 1514 { 1515 struct axgbe_phy_data *phy_data = pdata->phy_data; 1516 1517 switch (mode) { 1518 case AXGBE_MODE_X: 1519 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1520 return false; 1521 return axgbe_phy_check_mode(pdata, mode, 1522 ADVERTISED_1000baseT_Full); 1523 case AXGBE_MODE_SGMII_100: 1524 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1525 return false; 1526 return axgbe_phy_check_mode(pdata, mode, 1527 ADVERTISED_100baseT_Full); 1528 case AXGBE_MODE_SGMII_1000: 1529 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1530 return false; 1531 return axgbe_phy_check_mode(pdata, mode, 1532 ADVERTISED_1000baseT_Full); 1533 case AXGBE_MODE_SFI: 1534 return axgbe_phy_check_mode(pdata, mode, 1535 ADVERTISED_10000baseT_Full); 1536 default: 1537 return false; 1538 } 1539 } 1540 1541 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1542 enum axgbe_mode mode) 1543 { 1544 switch (mode) { 1545 case AXGBE_MODE_KX_2500: 1546 return axgbe_phy_check_mode(pdata, mode, 1547 ADVERTISED_2500baseX_Full); 1548 default: 1549 return false; 1550 } 1551 } 1552 1553 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1554 enum axgbe_mode mode) 1555 { 1556 switch (mode) { 1557 case AXGBE_MODE_KX_1000: 1558 return axgbe_phy_check_mode(pdata, mode, 1559 ADVERTISED_1000baseKX_Full); 1560 case AXGBE_MODE_KR: 1561 return axgbe_phy_check_mode(pdata, mode, 1562 ADVERTISED_10000baseKR_Full); 1563 default: 1564 return false; 1565 } 1566 } 1567 1568 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1569 { 1570 struct axgbe_phy_data *phy_data = pdata->phy_data; 1571 1572 switch (phy_data->port_mode) { 1573 case AXGBE_PORT_MODE_BACKPLANE: 1574 return axgbe_phy_use_bp_mode(pdata, mode); 1575 case AXGBE_PORT_MODE_BACKPLANE_2500: 1576 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1577 case AXGBE_PORT_MODE_1000BASE_T: 1578 case AXGBE_PORT_MODE_NBASE_T: 1579 case AXGBE_PORT_MODE_10GBASE_T: 1580 return axgbe_phy_use_baset_mode(pdata, mode); 1581 case AXGBE_PORT_MODE_1000BASE_X: 1582 case AXGBE_PORT_MODE_10GBASE_R: 1583 return axgbe_phy_use_basex_mode(pdata, mode); 1584 case AXGBE_PORT_MODE_SFP: 1585 return axgbe_phy_use_sfp_mode(pdata, mode); 1586 default: 1587 return false; 1588 } 1589 } 1590 1591 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1592 { 1593 struct axgbe_phy_data *phy_data = pdata->phy_data; 1594 unsigned int reg; 1595 1596 *an_restart = 0; 1597 1598 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1599 /* Check SFP signals */ 1600 axgbe_phy_sfp_detect(pdata); 1601 1602 if (phy_data->sfp_changed) { 1603 *an_restart = 1; 1604 return 0; 1605 } 1606 1607 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1608 return 0; 1609 } 1610 1611 /* Link status is latched low, so read once to clear 1612 * and then read again to get current state 1613 */ 1614 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1615 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1616 if (reg & MDIO_STAT1_LSTATUS) 1617 return 1; 1618 1619 /* No link, attempt a receiver reset cycle */ 1620 if (phy_data->rrc_count++) { 1621 phy_data->rrc_count = 0; 1622 axgbe_phy_rrc(pdata); 1623 } 1624 1625 return 0; 1626 } 1627 1628 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1629 { 1630 struct axgbe_phy_data *phy_data = pdata->phy_data; 1631 unsigned int reg; 1632 1633 reg = XP_IOREAD(pdata, XP_PROP_3); 1634 1635 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1636 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 1637 1638 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 1639 1640 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 1641 GPIO_RX_LOS); 1642 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 1643 GPIO_TX_FAULT); 1644 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 1645 GPIO_MOD_ABS); 1646 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 1647 GPIO_RATE_SELECT); 1648 } 1649 1650 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1651 { 1652 struct axgbe_phy_data *phy_data = pdata->phy_data; 1653 unsigned int reg, mux_addr_hi, mux_addr_lo; 1654 1655 reg = XP_IOREAD(pdata, XP_PROP_4); 1656 1657 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 1658 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 1659 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1660 return; 1661 1662 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1663 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1664 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 1665 } 1666 1667 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1668 { 1669 axgbe_phy_sfp_comm_setup(pdata); 1670 axgbe_phy_sfp_gpio_setup(pdata); 1671 } 1672 1673 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1674 { 1675 if (!phy_data->redrv) 1676 return false; 1677 1678 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1679 return true; 1680 1681 switch (phy_data->redrv_model) { 1682 case AXGBE_PHY_REDRV_MODEL_4223: 1683 if (phy_data->redrv_lane > 3) 1684 return true; 1685 break; 1686 case AXGBE_PHY_REDRV_MODEL_4227: 1687 if (phy_data->redrv_lane > 1) 1688 return true; 1689 break; 1690 default: 1691 return true; 1692 } 1693 1694 return false; 1695 } 1696 1697 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1698 { 1699 struct axgbe_phy_data *phy_data = pdata->phy_data; 1700 unsigned int reg; 1701 1702 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1703 return 0; 1704 reg = XP_IOREAD(pdata, XP_PROP_3); 1705 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 1706 switch (phy_data->mdio_reset) { 1707 case AXGBE_MDIO_RESET_NONE: 1708 case AXGBE_MDIO_RESET_I2C_GPIO: 1709 case AXGBE_MDIO_RESET_INT_GPIO: 1710 break; 1711 default: 1712 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1713 phy_data->mdio_reset); 1714 return -EINVAL; 1715 } 1716 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1717 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1718 XP_GET_BITS(reg, XP_PROP_3, 1719 MDIO_RESET_I2C_ADDR); 1720 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1721 MDIO_RESET_I2C_GPIO); 1722 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1723 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1724 MDIO_RESET_INT_GPIO); 1725 } 1726 1727 return 0; 1728 } 1729 1730 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1731 { 1732 struct axgbe_phy_data *phy_data = pdata->phy_data; 1733 1734 switch (phy_data->port_mode) { 1735 case AXGBE_PORT_MODE_BACKPLANE: 1736 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1737 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1738 return false; 1739 break; 1740 case AXGBE_PORT_MODE_BACKPLANE_2500: 1741 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1742 return false; 1743 break; 1744 case AXGBE_PORT_MODE_1000BASE_T: 1745 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1746 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1747 return false; 1748 break; 1749 case AXGBE_PORT_MODE_1000BASE_X: 1750 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1751 return false; 1752 break; 1753 case AXGBE_PORT_MODE_NBASE_T: 1754 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1755 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1756 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1757 return false; 1758 break; 1759 case AXGBE_PORT_MODE_10GBASE_T: 1760 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1761 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1762 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1763 return false; 1764 break; 1765 case AXGBE_PORT_MODE_10GBASE_R: 1766 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1767 return false; 1768 break; 1769 case AXGBE_PORT_MODE_SFP: 1770 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1771 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1772 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1773 return false; 1774 break; 1775 default: 1776 break; 1777 } 1778 1779 return true; 1780 } 1781 1782 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1783 { 1784 struct axgbe_phy_data *phy_data = pdata->phy_data; 1785 1786 switch (phy_data->port_mode) { 1787 case AXGBE_PORT_MODE_BACKPLANE: 1788 case AXGBE_PORT_MODE_BACKPLANE_2500: 1789 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1790 return false; 1791 break; 1792 case AXGBE_PORT_MODE_1000BASE_T: 1793 case AXGBE_PORT_MODE_1000BASE_X: 1794 case AXGBE_PORT_MODE_NBASE_T: 1795 case AXGBE_PORT_MODE_10GBASE_T: 1796 case AXGBE_PORT_MODE_10GBASE_R: 1797 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1798 return false; 1799 break; 1800 case AXGBE_PORT_MODE_SFP: 1801 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1802 return false; 1803 break; 1804 default: 1805 break; 1806 } 1807 1808 return true; 1809 } 1810 1811 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1812 { 1813 unsigned int reg; 1814 1815 reg = XP_IOREAD(pdata, XP_PROP_0); 1816 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 1817 return false; 1818 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 1819 return false; 1820 1821 return true; 1822 } 1823 1824 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1825 { 1826 struct axgbe_phy_data *phy_data = pdata->phy_data; 1827 1828 if (!pdata->vdata->an_cdr_workaround) 1829 return; 1830 1831 if (!phy_data->phy_cdr_notrack) 1832 return; 1833 1834 rte_delay_us(phy_data->phy_cdr_delay + 400); 1835 1836 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1837 AXGBE_PMA_CDR_TRACK_EN_MASK, 1838 AXGBE_PMA_CDR_TRACK_EN_ON); 1839 1840 phy_data->phy_cdr_notrack = 0; 1841 } 1842 1843 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1844 { 1845 struct axgbe_phy_data *phy_data = pdata->phy_data; 1846 1847 if (!pdata->vdata->an_cdr_workaround) 1848 return; 1849 1850 if (phy_data->phy_cdr_notrack) 1851 return; 1852 1853 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1854 AXGBE_PMA_CDR_TRACK_EN_MASK, 1855 AXGBE_PMA_CDR_TRACK_EN_OFF); 1856 1857 axgbe_phy_rrc(pdata); 1858 1859 phy_data->phy_cdr_notrack = 1; 1860 } 1861 1862 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1863 { 1864 if (!pdata->cdr_track_early) 1865 axgbe_phy_cdr_track(pdata); 1866 } 1867 1868 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1869 { 1870 if (pdata->cdr_track_early) 1871 axgbe_phy_cdr_track(pdata); 1872 } 1873 1874 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1875 { 1876 struct axgbe_phy_data *phy_data = pdata->phy_data; 1877 1878 switch (pdata->an_mode) { 1879 case AXGBE_AN_MODE_CL73: 1880 case AXGBE_AN_MODE_CL73_REDRV: 1881 if (phy_data->cur_mode != AXGBE_MODE_KR) 1882 break; 1883 1884 axgbe_phy_cdr_track(pdata); 1885 1886 switch (pdata->an_result) { 1887 case AXGBE_AN_READY: 1888 case AXGBE_AN_COMPLETE: 1889 break; 1890 default: 1891 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1892 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1893 break; 1894 } 1895 break; 1896 default: 1897 break; 1898 } 1899 } 1900 1901 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1902 { 1903 struct axgbe_phy_data *phy_data = pdata->phy_data; 1904 1905 switch (pdata->an_mode) { 1906 case AXGBE_AN_MODE_CL73: 1907 case AXGBE_AN_MODE_CL73_REDRV: 1908 if (phy_data->cur_mode != AXGBE_MODE_KR) 1909 break; 1910 1911 axgbe_phy_cdr_notrack(pdata); 1912 break; 1913 default: 1914 break; 1915 } 1916 } 1917 1918 static void axgbe_phy_stop(struct axgbe_port *pdata) 1919 { 1920 struct axgbe_phy_data *phy_data = pdata->phy_data; 1921 1922 /* Reset SFP data */ 1923 axgbe_phy_sfp_reset(phy_data); 1924 axgbe_phy_sfp_mod_absent(pdata); 1925 1926 /* Reset CDR support */ 1927 axgbe_phy_cdr_track(pdata); 1928 1929 /* Power off the PHY */ 1930 axgbe_phy_power_off(pdata); 1931 1932 /* Stop the I2C controller */ 1933 pdata->i2c_if.i2c_stop(pdata); 1934 } 1935 1936 static int axgbe_phy_start(struct axgbe_port *pdata) 1937 { 1938 struct axgbe_phy_data *phy_data = pdata->phy_data; 1939 int ret; 1940 1941 /* Start the I2C controller */ 1942 ret = pdata->i2c_if.i2c_start(pdata); 1943 if (ret) 1944 return ret; 1945 1946 /* Start in highest supported mode */ 1947 axgbe_phy_set_mode(pdata, phy_data->start_mode); 1948 1949 /* Reset CDR support */ 1950 axgbe_phy_cdr_track(pdata); 1951 1952 /* After starting the I2C controller, we can check for an SFP */ 1953 switch (phy_data->port_mode) { 1954 case AXGBE_PORT_MODE_SFP: 1955 axgbe_phy_sfp_detect(pdata); 1956 break; 1957 default: 1958 break; 1959 } 1960 1961 return ret; 1962 } 1963 1964 static int axgbe_phy_reset(struct axgbe_port *pdata) 1965 { 1966 struct axgbe_phy_data *phy_data = pdata->phy_data; 1967 enum axgbe_mode cur_mode; 1968 1969 /* Reset by power cycling the PHY */ 1970 cur_mode = phy_data->cur_mode; 1971 axgbe_phy_power_off(pdata); 1972 /* First time reset is done with passed unknown mode*/ 1973 axgbe_phy_set_mode(pdata, cur_mode); 1974 return 0; 1975 } 1976 1977 static int axgbe_phy_init(struct axgbe_port *pdata) 1978 { 1979 struct axgbe_phy_data *phy_data; 1980 unsigned int reg; 1981 int ret; 1982 1983 /* Check if enabled */ 1984 if (!axgbe_phy_port_enabled(pdata)) { 1985 PMD_DRV_LOG(ERR, "device is not enabled\n"); 1986 return -ENODEV; 1987 } 1988 1989 /* Initialize the I2C controller */ 1990 ret = pdata->i2c_if.i2c_init(pdata); 1991 if (ret) 1992 return ret; 1993 1994 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 1995 if (!phy_data) { 1996 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 1997 return -ENOMEM; 1998 } 1999 pdata->phy_data = phy_data; 2000 2001 reg = XP_IOREAD(pdata, XP_PROP_0); 2002 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2003 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2004 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2005 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2006 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2007 2008 reg = XP_IOREAD(pdata, XP_PROP_4); 2009 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2010 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2011 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2012 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2013 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2014 2015 /* Validate the connection requested */ 2016 if (axgbe_phy_conn_type_mismatch(pdata)) { 2017 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2018 phy_data->port_mode, phy_data->conn_type); 2019 return -EINVAL; 2020 } 2021 2022 /* Validate the mode requested */ 2023 if (axgbe_phy_port_mode_mismatch(pdata)) { 2024 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2025 phy_data->port_mode, phy_data->port_speeds); 2026 return -EINVAL; 2027 } 2028 2029 /* Check for and validate MDIO reset support */ 2030 ret = axgbe_phy_mdio_reset_setup(pdata); 2031 if (ret) 2032 return ret; 2033 2034 /* Validate the re-driver information */ 2035 if (axgbe_phy_redrv_error(phy_data)) { 2036 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2037 return -EINVAL; 2038 } 2039 pdata->kr_redrv = phy_data->redrv; 2040 2041 /* Indicate current mode is unknown */ 2042 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2043 2044 /* Initialize supported features */ 2045 pdata->phy.supported = 0; 2046 2047 switch (phy_data->port_mode) { 2048 /* Backplane support */ 2049 case AXGBE_PORT_MODE_BACKPLANE: 2050 pdata->phy.supported |= SUPPORTED_Autoneg; 2051 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2052 pdata->phy.supported |= SUPPORTED_Backplane; 2053 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2054 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2055 phy_data->start_mode = AXGBE_MODE_KX_1000; 2056 } 2057 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2058 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2059 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2060 pdata->phy.supported |= 2061 SUPPORTED_10000baseR_FEC; 2062 phy_data->start_mode = AXGBE_MODE_KR; 2063 } 2064 2065 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2066 break; 2067 case AXGBE_PORT_MODE_BACKPLANE_2500: 2068 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2069 pdata->phy.supported |= SUPPORTED_Backplane; 2070 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2071 phy_data->start_mode = AXGBE_MODE_KX_2500; 2072 2073 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2074 break; 2075 2076 /* MDIO 1GBase-T support */ 2077 case AXGBE_PORT_MODE_1000BASE_T: 2078 pdata->phy.supported |= SUPPORTED_Autoneg; 2079 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2080 pdata->phy.supported |= SUPPORTED_TP; 2081 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2082 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2083 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2084 } 2085 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2086 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2087 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2088 } 2089 2090 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2091 break; 2092 2093 /* MDIO Base-X support */ 2094 case AXGBE_PORT_MODE_1000BASE_X: 2095 pdata->phy.supported |= SUPPORTED_Autoneg; 2096 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2097 pdata->phy.supported |= SUPPORTED_FIBRE; 2098 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2099 phy_data->start_mode = AXGBE_MODE_X; 2100 2101 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2102 break; 2103 2104 /* MDIO NBase-T support */ 2105 case AXGBE_PORT_MODE_NBASE_T: 2106 pdata->phy.supported |= SUPPORTED_Autoneg; 2107 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2108 pdata->phy.supported |= SUPPORTED_TP; 2109 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2110 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2111 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2112 } 2113 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2114 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2115 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2116 } 2117 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2118 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2119 phy_data->start_mode = AXGBE_MODE_KX_2500; 2120 } 2121 2122 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2123 break; 2124 2125 /* 10GBase-T support */ 2126 case AXGBE_PORT_MODE_10GBASE_T: 2127 pdata->phy.supported |= SUPPORTED_Autoneg; 2128 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2129 pdata->phy.supported |= SUPPORTED_TP; 2130 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2131 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2132 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2133 } 2134 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2135 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2136 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2137 } 2138 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2139 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2140 phy_data->start_mode = AXGBE_MODE_KR; 2141 } 2142 2143 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2144 break; 2145 2146 /* 10GBase-R support */ 2147 case AXGBE_PORT_MODE_10GBASE_R: 2148 pdata->phy.supported |= SUPPORTED_Autoneg; 2149 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2150 pdata->phy.supported |= SUPPORTED_TP; 2151 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2152 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2153 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2154 phy_data->start_mode = AXGBE_MODE_SFI; 2155 2156 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2157 break; 2158 2159 /* SFP support */ 2160 case AXGBE_PORT_MODE_SFP: 2161 pdata->phy.supported |= SUPPORTED_Autoneg; 2162 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2163 pdata->phy.supported |= SUPPORTED_TP; 2164 pdata->phy.supported |= SUPPORTED_FIBRE; 2165 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2166 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2167 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2168 } 2169 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2170 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2171 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2172 } 2173 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2174 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2175 phy_data->start_mode = AXGBE_MODE_SFI; 2176 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2177 pdata->phy.supported |= 2178 SUPPORTED_10000baseR_FEC; 2179 } 2180 2181 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2182 2183 axgbe_phy_sfp_setup(pdata); 2184 break; 2185 default: 2186 return -EINVAL; 2187 } 2188 2189 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2190 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2191 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2192 phy_data->phydev_mode); 2193 if (ret) { 2194 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2195 phy_data->mdio_addr, phy_data->phydev_mode); 2196 return -EINVAL; 2197 } 2198 } 2199 2200 if (phy_data->redrv && !phy_data->redrv_if) { 2201 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2202 AXGBE_MDIO_MODE_CL22); 2203 if (ret) { 2204 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2205 phy_data->redrv_addr); 2206 return -EINVAL; 2207 } 2208 } 2209 2210 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2211 return 0; 2212 } 2213 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2214 { 2215 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2216 2217 phy_impl->init = axgbe_phy_init; 2218 phy_impl->reset = axgbe_phy_reset; 2219 phy_impl->start = axgbe_phy_start; 2220 phy_impl->stop = axgbe_phy_stop; 2221 phy_impl->link_status = axgbe_phy_link_status; 2222 phy_impl->use_mode = axgbe_phy_use_mode; 2223 phy_impl->set_mode = axgbe_phy_set_mode; 2224 phy_impl->get_mode = axgbe_phy_get_mode; 2225 phy_impl->switch_mode = axgbe_phy_switch_mode; 2226 phy_impl->cur_mode = axgbe_phy_cur_mode; 2227 phy_impl->an_mode = axgbe_phy_an_mode; 2228 phy_impl->an_config = axgbe_phy_an_config; 2229 phy_impl->an_advertising = axgbe_phy_an_advertising; 2230 phy_impl->an_outcome = axgbe_phy_an_outcome; 2231 2232 phy_impl->an_pre = axgbe_phy_an_pre; 2233 phy_impl->an_post = axgbe_phy_an_post; 2234 2235 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2236 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2237 } 2238