1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 enum axgbe_port_mode { 35 AXGBE_PORT_MODE_RSVD = 0, 36 AXGBE_PORT_MODE_BACKPLANE, 37 AXGBE_PORT_MODE_BACKPLANE_2500, 38 AXGBE_PORT_MODE_1000BASE_T, 39 AXGBE_PORT_MODE_1000BASE_X, 40 AXGBE_PORT_MODE_NBASE_T, 41 AXGBE_PORT_MODE_10GBASE_T, 42 AXGBE_PORT_MODE_10GBASE_R, 43 AXGBE_PORT_MODE_SFP, 44 AXGBE_PORT_MODE_MAX, 45 }; 46 47 enum axgbe_conn_type { 48 AXGBE_CONN_TYPE_NONE = 0, 49 AXGBE_CONN_TYPE_SFP, 50 AXGBE_CONN_TYPE_MDIO, 51 AXGBE_CONN_TYPE_RSVD1, 52 AXGBE_CONN_TYPE_BACKPLANE, 53 AXGBE_CONN_TYPE_MAX, 54 }; 55 56 /* SFP/SFP+ related definitions */ 57 enum axgbe_sfp_comm { 58 AXGBE_SFP_COMM_DIRECT = 0, 59 AXGBE_SFP_COMM_PCA9545, 60 }; 61 62 enum axgbe_sfp_cable { 63 AXGBE_SFP_CABLE_UNKNOWN = 0, 64 AXGBE_SFP_CABLE_ACTIVE, 65 AXGBE_SFP_CABLE_PASSIVE, 66 }; 67 68 enum axgbe_sfp_base { 69 AXGBE_SFP_BASE_UNKNOWN = 0, 70 AXGBE_SFP_BASE_1000_T, 71 AXGBE_SFP_BASE_1000_SX, 72 AXGBE_SFP_BASE_1000_LX, 73 AXGBE_SFP_BASE_1000_CX, 74 AXGBE_SFP_BASE_10000_SR, 75 AXGBE_SFP_BASE_10000_LR, 76 AXGBE_SFP_BASE_10000_LRM, 77 AXGBE_SFP_BASE_10000_ER, 78 AXGBE_SFP_BASE_10000_CR, 79 }; 80 81 enum axgbe_sfp_speed { 82 AXGBE_SFP_SPEED_UNKNOWN = 0, 83 AXGBE_SFP_SPEED_100_1000, 84 AXGBE_SFP_SPEED_1000, 85 AXGBE_SFP_SPEED_10000, 86 }; 87 88 /* SFP Serial ID Base ID values relative to an offset of 0 */ 89 #define AXGBE_SFP_BASE_ID 0 90 #define AXGBE_SFP_ID_SFP 0x03 91 92 #define AXGBE_SFP_BASE_EXT_ID 1 93 #define AXGBE_SFP_EXT_ID_SFP 0x04 94 95 #define AXGBE_SFP_BASE_10GBE_CC 3 96 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 97 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 98 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 99 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 100 101 #define AXGBE_SFP_BASE_1GBE_CC 6 102 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 103 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 104 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 105 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 106 107 #define AXGBE_SFP_BASE_CABLE 8 108 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 109 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 110 111 #define AXGBE_SFP_BASE_BR 12 112 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 113 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 114 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 115 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 116 117 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 118 119 #define AXGBE_SFP_BASE_VENDOR_NAME 20 120 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 121 #define AXGBE_SFP_BASE_VENDOR_PN 40 122 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 123 #define AXGBE_SFP_BASE_VENDOR_REV 56 124 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 125 126 #define AXGBE_SFP_BASE_CC 63 127 128 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 129 #define AXGBE_SFP_BASE_VENDOR_SN 4 130 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 131 132 #define AXGBE_SFP_EXTD_DIAG 28 133 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 134 135 #define AXGBE_SFP_EXTD_SFF_8472 30 136 137 #define AXGBE_SFP_EXTD_CC 31 138 139 struct axgbe_sfp_eeprom { 140 u8 base[64]; 141 u8 extd[32]; 142 u8 vendor[32]; 143 }; 144 145 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 146 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 147 148 struct axgbe_sfp_ascii { 149 union { 150 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 151 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 152 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 153 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 154 } u; 155 }; 156 157 /* MDIO PHY reset types */ 158 enum axgbe_mdio_reset { 159 AXGBE_MDIO_RESET_NONE = 0, 160 AXGBE_MDIO_RESET_I2C_GPIO, 161 AXGBE_MDIO_RESET_INT_GPIO, 162 AXGBE_MDIO_RESET_MAX, 163 }; 164 165 /* Re-driver related definitions */ 166 enum axgbe_phy_redrv_if { 167 AXGBE_PHY_REDRV_IF_MDIO = 0, 168 AXGBE_PHY_REDRV_IF_I2C, 169 AXGBE_PHY_REDRV_IF_MAX, 170 }; 171 172 enum axgbe_phy_redrv_model { 173 AXGBE_PHY_REDRV_MODEL_4223 = 0, 174 AXGBE_PHY_REDRV_MODEL_4227, 175 AXGBE_PHY_REDRV_MODEL_MAX, 176 }; 177 178 enum axgbe_phy_redrv_mode { 179 AXGBE_PHY_REDRV_MODE_CX = 5, 180 AXGBE_PHY_REDRV_MODE_SR = 9, 181 }; 182 183 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 184 185 /* PHY related configuration information */ 186 struct axgbe_phy_data { 187 enum axgbe_port_mode port_mode; 188 189 unsigned int port_id; 190 191 unsigned int port_speeds; 192 193 enum axgbe_conn_type conn_type; 194 195 enum axgbe_mode cur_mode; 196 enum axgbe_mode start_mode; 197 198 unsigned int rrc_count; 199 200 unsigned int mdio_addr; 201 202 unsigned int comm_owned; 203 204 /* SFP Support */ 205 enum axgbe_sfp_comm sfp_comm; 206 unsigned int sfp_mux_address; 207 unsigned int sfp_mux_channel; 208 209 unsigned int sfp_gpio_address; 210 unsigned int sfp_gpio_mask; 211 unsigned int sfp_gpio_rx_los; 212 unsigned int sfp_gpio_tx_fault; 213 unsigned int sfp_gpio_mod_absent; 214 unsigned int sfp_gpio_rate_select; 215 216 unsigned int sfp_rx_los; 217 unsigned int sfp_tx_fault; 218 unsigned int sfp_mod_absent; 219 unsigned int sfp_diags; 220 unsigned int sfp_changed; 221 unsigned int sfp_phy_avail; 222 unsigned int sfp_cable_len; 223 enum axgbe_sfp_base sfp_base; 224 enum axgbe_sfp_cable sfp_cable; 225 enum axgbe_sfp_speed sfp_speed; 226 struct axgbe_sfp_eeprom sfp_eeprom; 227 228 /* External PHY support */ 229 enum axgbe_mdio_mode phydev_mode; 230 enum axgbe_mdio_reset mdio_reset; 231 unsigned int mdio_reset_addr; 232 unsigned int mdio_reset_gpio; 233 234 /* Re-driver support */ 235 unsigned int redrv; 236 unsigned int redrv_if; 237 unsigned int redrv_addr; 238 unsigned int redrv_lane; 239 unsigned int redrv_model; 240 }; 241 242 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 243 { 244 struct axgbe_phy_data *phy_data = pdata->phy_data; 245 unsigned int reg; 246 247 reg = XP_IOREAD(pdata, XP_PROP_3); 248 249 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 250 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 251 252 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 253 254 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 255 GPIO_RX_LOS); 256 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 257 GPIO_TX_FAULT); 258 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 259 GPIO_MOD_ABS); 260 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 261 GPIO_RATE_SELECT); 262 } 263 264 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 265 { 266 struct axgbe_phy_data *phy_data = pdata->phy_data; 267 unsigned int reg, mux_addr_hi, mux_addr_lo; 268 269 reg = XP_IOREAD(pdata, XP_PROP_4); 270 271 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 272 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 273 if (mux_addr_lo == AXGBE_SFP_DIRECT) 274 return; 275 276 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 277 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 278 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 279 } 280 281 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 282 { 283 axgbe_phy_sfp_comm_setup(pdata); 284 axgbe_phy_sfp_gpio_setup(pdata); 285 } 286 287 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 288 { 289 if (!phy_data->redrv) 290 return false; 291 292 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 293 return true; 294 295 switch (phy_data->redrv_model) { 296 case AXGBE_PHY_REDRV_MODEL_4223: 297 if (phy_data->redrv_lane > 3) 298 return true; 299 break; 300 case AXGBE_PHY_REDRV_MODEL_4227: 301 if (phy_data->redrv_lane > 1) 302 return true; 303 break; 304 default: 305 return true; 306 } 307 308 return false; 309 } 310 311 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 312 { 313 struct axgbe_phy_data *phy_data = pdata->phy_data; 314 unsigned int reg; 315 316 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 317 return 0; 318 reg = XP_IOREAD(pdata, XP_PROP_3); 319 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 320 switch (phy_data->mdio_reset) { 321 case AXGBE_MDIO_RESET_NONE: 322 case AXGBE_MDIO_RESET_I2C_GPIO: 323 case AXGBE_MDIO_RESET_INT_GPIO: 324 break; 325 default: 326 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 327 phy_data->mdio_reset); 328 return -EINVAL; 329 } 330 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 331 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 332 XP_GET_BITS(reg, XP_PROP_3, 333 MDIO_RESET_I2C_ADDR); 334 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 335 MDIO_RESET_I2C_GPIO); 336 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 337 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 338 MDIO_RESET_INT_GPIO); 339 } 340 341 return 0; 342 } 343 344 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 345 { 346 struct axgbe_phy_data *phy_data = pdata->phy_data; 347 348 switch (phy_data->port_mode) { 349 case AXGBE_PORT_MODE_BACKPLANE: 350 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 351 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 352 return false; 353 break; 354 case AXGBE_PORT_MODE_BACKPLANE_2500: 355 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 356 return false; 357 break; 358 case AXGBE_PORT_MODE_1000BASE_T: 359 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 360 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 361 return false; 362 break; 363 case AXGBE_PORT_MODE_1000BASE_X: 364 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 365 return false; 366 break; 367 case AXGBE_PORT_MODE_NBASE_T: 368 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 369 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 370 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 371 return false; 372 break; 373 case AXGBE_PORT_MODE_10GBASE_T: 374 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 375 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 376 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 377 return false; 378 break; 379 case AXGBE_PORT_MODE_10GBASE_R: 380 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 381 return false; 382 break; 383 case AXGBE_PORT_MODE_SFP: 384 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 385 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 386 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 387 return false; 388 break; 389 default: 390 break; 391 } 392 393 return true; 394 } 395 396 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 397 { 398 struct axgbe_phy_data *phy_data = pdata->phy_data; 399 400 switch (phy_data->port_mode) { 401 case AXGBE_PORT_MODE_BACKPLANE: 402 case AXGBE_PORT_MODE_BACKPLANE_2500: 403 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 404 return false; 405 break; 406 case AXGBE_PORT_MODE_1000BASE_T: 407 case AXGBE_PORT_MODE_1000BASE_X: 408 case AXGBE_PORT_MODE_NBASE_T: 409 case AXGBE_PORT_MODE_10GBASE_T: 410 case AXGBE_PORT_MODE_10GBASE_R: 411 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 412 return false; 413 break; 414 case AXGBE_PORT_MODE_SFP: 415 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 416 return false; 417 break; 418 default: 419 break; 420 } 421 422 return true; 423 } 424 425 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 426 { 427 unsigned int reg; 428 429 reg = XP_IOREAD(pdata, XP_PROP_0); 430 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 431 return false; 432 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 433 return false; 434 435 return true; 436 } 437 438 static int axgbe_phy_init(struct axgbe_port *pdata) 439 { 440 struct axgbe_phy_data *phy_data; 441 unsigned int reg; 442 int ret; 443 444 /* Check if enabled */ 445 if (!axgbe_phy_port_enabled(pdata)) { 446 PMD_DRV_LOG(ERR, "device is not enabled\n"); 447 return -ENODEV; 448 } 449 450 /* Initialize the I2C controller */ 451 ret = pdata->i2c_if.i2c_init(pdata); 452 if (ret) 453 return ret; 454 455 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 456 if (!phy_data) { 457 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 458 return -ENOMEM; 459 } 460 pdata->phy_data = phy_data; 461 462 reg = XP_IOREAD(pdata, XP_PROP_0); 463 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 464 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 465 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 466 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 467 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 468 469 reg = XP_IOREAD(pdata, XP_PROP_4); 470 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 471 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 472 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 473 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 474 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 475 476 /* Validate the connection requested */ 477 if (axgbe_phy_conn_type_mismatch(pdata)) { 478 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 479 phy_data->port_mode, phy_data->conn_type); 480 return -EINVAL; 481 } 482 483 /* Validate the mode requested */ 484 if (axgbe_phy_port_mode_mismatch(pdata)) { 485 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 486 phy_data->port_mode, phy_data->port_speeds); 487 return -EINVAL; 488 } 489 490 /* Check for and validate MDIO reset support */ 491 ret = axgbe_phy_mdio_reset_setup(pdata); 492 if (ret) 493 return ret; 494 495 /* Validate the re-driver information */ 496 if (axgbe_phy_redrv_error(phy_data)) { 497 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 498 return -EINVAL; 499 } 500 pdata->kr_redrv = phy_data->redrv; 501 502 /* Indicate current mode is unknown */ 503 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 504 505 /* Initialize supported features */ 506 pdata->phy.supported = 0; 507 508 switch (phy_data->port_mode) { 509 /* Backplane support */ 510 case AXGBE_PORT_MODE_BACKPLANE: 511 pdata->phy.supported |= SUPPORTED_Autoneg; 512 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 513 pdata->phy.supported |= SUPPORTED_Backplane; 514 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 515 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 516 phy_data->start_mode = AXGBE_MODE_KX_1000; 517 } 518 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 519 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 520 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 521 pdata->phy.supported |= 522 SUPPORTED_10000baseR_FEC; 523 phy_data->start_mode = AXGBE_MODE_KR; 524 } 525 526 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 527 break; 528 case AXGBE_PORT_MODE_BACKPLANE_2500: 529 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 530 pdata->phy.supported |= SUPPORTED_Backplane; 531 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 532 phy_data->start_mode = AXGBE_MODE_KX_2500; 533 534 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 535 break; 536 537 /* MDIO 1GBase-T support */ 538 case AXGBE_PORT_MODE_1000BASE_T: 539 pdata->phy.supported |= SUPPORTED_Autoneg; 540 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 541 pdata->phy.supported |= SUPPORTED_TP; 542 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 543 pdata->phy.supported |= SUPPORTED_100baseT_Full; 544 phy_data->start_mode = AXGBE_MODE_SGMII_100; 545 } 546 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 547 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 548 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 549 } 550 551 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 552 break; 553 554 /* MDIO Base-X support */ 555 case AXGBE_PORT_MODE_1000BASE_X: 556 pdata->phy.supported |= SUPPORTED_Autoneg; 557 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 558 pdata->phy.supported |= SUPPORTED_FIBRE; 559 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 560 phy_data->start_mode = AXGBE_MODE_X; 561 562 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 563 break; 564 565 /* MDIO NBase-T support */ 566 case AXGBE_PORT_MODE_NBASE_T: 567 pdata->phy.supported |= SUPPORTED_Autoneg; 568 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 569 pdata->phy.supported |= SUPPORTED_TP; 570 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 571 pdata->phy.supported |= SUPPORTED_100baseT_Full; 572 phy_data->start_mode = AXGBE_MODE_SGMII_100; 573 } 574 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 575 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 576 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 577 } 578 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 579 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 580 phy_data->start_mode = AXGBE_MODE_KX_2500; 581 } 582 583 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 584 break; 585 586 /* 10GBase-T support */ 587 case AXGBE_PORT_MODE_10GBASE_T: 588 pdata->phy.supported |= SUPPORTED_Autoneg; 589 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 590 pdata->phy.supported |= SUPPORTED_TP; 591 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 592 pdata->phy.supported |= SUPPORTED_100baseT_Full; 593 phy_data->start_mode = AXGBE_MODE_SGMII_100; 594 } 595 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 596 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 597 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 598 } 599 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 600 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 601 phy_data->start_mode = AXGBE_MODE_KR; 602 } 603 604 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 605 break; 606 607 /* 10GBase-R support */ 608 case AXGBE_PORT_MODE_10GBASE_R: 609 pdata->phy.supported |= SUPPORTED_Autoneg; 610 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 611 pdata->phy.supported |= SUPPORTED_TP; 612 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 613 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 614 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 615 phy_data->start_mode = AXGBE_MODE_SFI; 616 617 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 618 break; 619 620 /* SFP support */ 621 case AXGBE_PORT_MODE_SFP: 622 pdata->phy.supported |= SUPPORTED_Autoneg; 623 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 624 pdata->phy.supported |= SUPPORTED_TP; 625 pdata->phy.supported |= SUPPORTED_FIBRE; 626 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 627 pdata->phy.supported |= SUPPORTED_100baseT_Full; 628 phy_data->start_mode = AXGBE_MODE_SGMII_100; 629 } 630 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 631 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 632 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 633 } 634 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 635 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 636 phy_data->start_mode = AXGBE_MODE_SFI; 637 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 638 pdata->phy.supported |= 639 SUPPORTED_10000baseR_FEC; 640 } 641 642 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 643 644 axgbe_phy_sfp_setup(pdata); 645 break; 646 default: 647 return -EINVAL; 648 } 649 650 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 651 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 652 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 653 phy_data->phydev_mode); 654 if (ret) { 655 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 656 phy_data->mdio_addr, phy_data->phydev_mode); 657 return -EINVAL; 658 } 659 } 660 661 if (phy_data->redrv && !phy_data->redrv_if) { 662 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 663 AXGBE_MDIO_MODE_CL22); 664 if (ret) { 665 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 666 phy_data->redrv_addr); 667 return -EINVAL; 668 } 669 } 670 return 0; 671 } 672 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 673 { 674 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 675 676 phy_impl->init = axgbe_phy_init; 677 } 678