1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(1) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(2) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(3) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(4) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 50 AXGBE_PORT_MODE_MAX, 51 }; 52 53 enum axgbe_conn_type { 54 AXGBE_CONN_TYPE_NONE = 0, 55 AXGBE_CONN_TYPE_SFP, 56 AXGBE_CONN_TYPE_MDIO, 57 AXGBE_CONN_TYPE_RSVD1, 58 AXGBE_CONN_TYPE_BACKPLANE, 59 AXGBE_CONN_TYPE_MAX, 60 }; 61 62 /* SFP/SFP+ related definitions */ 63 enum axgbe_sfp_comm { 64 AXGBE_SFP_COMM_DIRECT = 0, 65 AXGBE_SFP_COMM_PCA9545, 66 }; 67 68 enum axgbe_sfp_cable { 69 AXGBE_SFP_CABLE_UNKNOWN = 0, 70 AXGBE_SFP_CABLE_ACTIVE, 71 AXGBE_SFP_CABLE_PASSIVE, 72 AXGBE_SFP_CABLE_FIBER, 73 }; 74 75 enum axgbe_sfp_base { 76 AXGBE_SFP_BASE_UNKNOWN = 0, 77 AXGBE_SFP_BASE_1000_T, 78 AXGBE_SFP_BASE_1000_SX, 79 AXGBE_SFP_BASE_1000_LX, 80 AXGBE_SFP_BASE_1000_CX, 81 AXGBE_SFP_BASE_10000_SR, 82 AXGBE_SFP_BASE_10000_LR, 83 AXGBE_SFP_BASE_10000_LRM, 84 AXGBE_SFP_BASE_10000_ER, 85 AXGBE_SFP_BASE_10000_CR, 86 }; 87 88 enum axgbe_sfp_speed { 89 AXGBE_SFP_SPEED_UNKNOWN = 0, 90 AXGBE_SFP_SPEED_100_1000, 91 AXGBE_SFP_SPEED_1000, 92 AXGBE_SFP_SPEED_10000, 93 }; 94 95 /* SFP Serial ID Base ID values relative to an offset of 0 */ 96 #define AXGBE_SFP_BASE_ID 0 97 #define AXGBE_SFP_ID_SFP 0x03 98 99 #define AXGBE_SFP_BASE_EXT_ID 1 100 #define AXGBE_SFP_EXT_ID_SFP 0x04 101 102 #define AXGBE_SFP_BASE_10GBE_CC 3 103 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 104 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 105 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 106 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 107 108 #define AXGBE_SFP_BASE_1GBE_CC 6 109 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 110 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 111 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 112 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 113 114 #define AXGBE_SFP_BASE_CABLE 8 115 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 116 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 117 118 #define AXGBE_SFP_BASE_BR 12 119 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 120 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 121 122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 123 124 #define AXGBE_SFP_BASE_VENDOR_NAME 20 125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 126 #define AXGBE_SFP_BASE_VENDOR_PN 40 127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 128 #define AXGBE_SFP_BASE_VENDOR_REV 56 129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 130 131 #define AXGBE_SFP_BASE_CC 63 132 133 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 134 #define AXGBE_SFP_BASE_VENDOR_SN 4 135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 136 137 #define AXGBE_SFP_EXTD_DIAG 28 138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 139 140 #define AXGBE_SFP_EXTD_SFF_8472 30 141 142 #define AXGBE_SFP_EXTD_CC 31 143 144 struct axgbe_sfp_eeprom { 145 u8 base[64]; 146 u8 extd[32]; 147 u8 vendor[32]; 148 }; 149 150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 152 153 struct axgbe_sfp_ascii { 154 union { 155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 159 } u; 160 }; 161 162 /* MDIO PHY reset types */ 163 enum axgbe_mdio_reset { 164 AXGBE_MDIO_RESET_NONE = 0, 165 AXGBE_MDIO_RESET_I2C_GPIO, 166 AXGBE_MDIO_RESET_INT_GPIO, 167 AXGBE_MDIO_RESET_MAX, 168 }; 169 170 /* Re-driver related definitions */ 171 enum axgbe_phy_redrv_if { 172 AXGBE_PHY_REDRV_IF_MDIO = 0, 173 AXGBE_PHY_REDRV_IF_I2C, 174 AXGBE_PHY_REDRV_IF_MAX, 175 }; 176 177 enum axgbe_phy_redrv_model { 178 AXGBE_PHY_REDRV_MODEL_4223 = 0, 179 AXGBE_PHY_REDRV_MODEL_4227, 180 AXGBE_PHY_REDRV_MODEL_MAX, 181 }; 182 183 enum axgbe_phy_redrv_mode { 184 AXGBE_PHY_REDRV_MODE_CX = 5, 185 AXGBE_PHY_REDRV_MODE_SR = 9, 186 }; 187 188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 189 190 /* PHY related configuration information */ 191 struct axgbe_phy_data { 192 enum axgbe_port_mode port_mode; 193 194 unsigned int port_id; 195 196 unsigned int port_speeds; 197 198 enum axgbe_conn_type conn_type; 199 200 enum axgbe_mode cur_mode; 201 enum axgbe_mode start_mode; 202 203 unsigned int rrc_count; 204 205 unsigned int mdio_addr; 206 207 /* SFP Support */ 208 enum axgbe_sfp_comm sfp_comm; 209 unsigned int sfp_mux_address; 210 unsigned int sfp_mux_channel; 211 212 unsigned int sfp_gpio_address; 213 unsigned int sfp_gpio_mask; 214 unsigned int sfp_gpio_rx_los; 215 unsigned int sfp_gpio_tx_fault; 216 unsigned int sfp_gpio_mod_absent; 217 unsigned int sfp_gpio_rate_select; 218 219 unsigned int sfp_rx_los; 220 unsigned int sfp_tx_fault; 221 unsigned int sfp_mod_absent; 222 unsigned int sfp_changed; 223 unsigned int sfp_phy_avail; 224 unsigned int sfp_cable_len; 225 enum axgbe_sfp_base sfp_base; 226 enum axgbe_sfp_cable sfp_cable; 227 enum axgbe_sfp_speed sfp_speed; 228 struct axgbe_sfp_eeprom sfp_eeprom; 229 230 /* External PHY support */ 231 enum axgbe_mdio_mode phydev_mode; 232 enum axgbe_mdio_reset mdio_reset; 233 unsigned int mdio_reset_addr; 234 unsigned int mdio_reset_gpio; 235 236 /* Re-driver support */ 237 unsigned int redrv; 238 unsigned int redrv_if; 239 unsigned int redrv_addr; 240 unsigned int redrv_lane; 241 unsigned int redrv_model; 242 243 /* KR AN support */ 244 unsigned int phy_cdr_notrack; 245 unsigned int phy_cdr_delay; 246 }; 247 248 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 249 250 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 251 struct axgbe_i2c_op *i2c_op) 252 { 253 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 254 } 255 256 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 257 unsigned int val) 258 { 259 struct axgbe_phy_data *phy_data = pdata->phy_data; 260 struct axgbe_i2c_op i2c_op; 261 uint16_t *redrv_val; 262 u8 redrv_data[5], csum; 263 unsigned int i, retry; 264 int ret; 265 266 /* High byte of register contains read/write indicator */ 267 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 268 redrv_data[1] = reg & 0xff; 269 redrv_val = (uint16_t *)&redrv_data[2]; 270 *redrv_val = rte_cpu_to_be_16(val); 271 272 /* Calculate 1 byte checksum */ 273 csum = 0; 274 for (i = 0; i < 4; i++) { 275 csum += redrv_data[i]; 276 if (redrv_data[i] > csum) 277 csum++; 278 } 279 redrv_data[4] = ~csum; 280 281 retry = 1; 282 again1: 283 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 284 i2c_op.target = phy_data->redrv_addr; 285 i2c_op.len = sizeof(redrv_data); 286 i2c_op.buf = redrv_data; 287 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 288 if (ret) { 289 if ((ret == -EAGAIN) && retry--) 290 goto again1; 291 292 return ret; 293 } 294 295 retry = 1; 296 again2: 297 i2c_op.cmd = AXGBE_I2C_CMD_READ; 298 i2c_op.target = phy_data->redrv_addr; 299 i2c_op.len = 1; 300 i2c_op.buf = redrv_data; 301 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 302 if (ret) { 303 if ((ret == -EAGAIN) && retry--) 304 goto again2; 305 306 return ret; 307 } 308 309 if (redrv_data[0] != 0xff) { 310 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 311 ret = -EIO; 312 } 313 314 return ret; 315 } 316 317 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 318 void *reg, unsigned int reg_len, 319 void *val, unsigned int val_len) 320 { 321 struct axgbe_i2c_op i2c_op; 322 int retry, ret; 323 324 retry = 1; 325 again1: 326 /* Set the specified register to read */ 327 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 328 i2c_op.target = target; 329 i2c_op.len = reg_len; 330 i2c_op.buf = reg; 331 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 332 if (ret) { 333 if ((ret == -EAGAIN) && retry--) 334 goto again1; 335 336 return ret; 337 } 338 339 retry = 1; 340 again2: 341 /* Read the specified register */ 342 i2c_op.cmd = AXGBE_I2C_CMD_READ; 343 i2c_op.target = target; 344 i2c_op.len = val_len; 345 i2c_op.buf = val; 346 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 347 if ((ret == -EAGAIN) && retry--) 348 goto again2; 349 350 return ret; 351 } 352 353 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 354 { 355 struct axgbe_phy_data *phy_data = pdata->phy_data; 356 struct axgbe_i2c_op i2c_op; 357 uint8_t mux_channel; 358 359 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 360 return 0; 361 362 /* Select no mux channels */ 363 mux_channel = 0; 364 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 365 i2c_op.target = phy_data->sfp_mux_address; 366 i2c_op.len = sizeof(mux_channel); 367 i2c_op.buf = &mux_channel; 368 369 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 370 } 371 372 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 373 { 374 struct axgbe_phy_data *phy_data = pdata->phy_data; 375 struct axgbe_i2c_op i2c_op; 376 u8 mux_channel; 377 378 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 379 return 0; 380 381 /* Select desired mux channel */ 382 mux_channel = 1 << phy_data->sfp_mux_channel; 383 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 384 i2c_op.target = phy_data->sfp_mux_address; 385 i2c_op.len = sizeof(mux_channel); 386 i2c_op.buf = &mux_channel; 387 388 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 389 } 390 391 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 392 { 393 pthread_mutex_unlock(&pdata->phy_mutex); 394 } 395 396 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 397 { 398 struct axgbe_phy_data *phy_data = pdata->phy_data; 399 uint64_t timeout; 400 unsigned int mutex_id; 401 402 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 403 * the driver needs to take the software mutex and then the hardware 404 * mutexes before being able to use the busses. 405 */ 406 pthread_mutex_lock(&pdata->phy_mutex); 407 408 /* Clear the mutexes */ 409 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 410 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 411 412 /* Mutex formats are the same for I2C and MDIO/GPIO */ 413 mutex_id = 0; 414 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 415 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 416 417 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 418 while (time_before(rte_get_timer_cycles(), timeout)) { 419 /* Must be all zeroes in order to obtain the mutex */ 420 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 421 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 422 rte_delay_us(100); 423 continue; 424 } 425 426 /* Obtain the mutex */ 427 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 428 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 429 430 return 0; 431 } 432 433 pthread_mutex_unlock(&pdata->phy_mutex); 434 435 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 436 437 return -ETIMEDOUT; 438 } 439 440 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 441 { 442 struct axgbe_phy_data *phy_data = pdata->phy_data; 443 444 if (phy_data->sfp_mod_absent) { 445 pdata->phy.speed = SPEED_UNKNOWN; 446 pdata->phy.duplex = DUPLEX_UNKNOWN; 447 pdata->phy.autoneg = AUTONEG_ENABLE; 448 pdata->phy.advertising = pdata->phy.supported; 449 } 450 451 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 452 pdata->phy.advertising &= ~ADVERTISED_TP; 453 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 454 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 455 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 456 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 457 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 458 459 switch (phy_data->sfp_base) { 460 case AXGBE_SFP_BASE_1000_T: 461 case AXGBE_SFP_BASE_1000_SX: 462 case AXGBE_SFP_BASE_1000_LX: 463 case AXGBE_SFP_BASE_1000_CX: 464 pdata->phy.speed = SPEED_UNKNOWN; 465 pdata->phy.duplex = DUPLEX_UNKNOWN; 466 pdata->phy.autoneg = AUTONEG_ENABLE; 467 pdata->phy.advertising |= ADVERTISED_Autoneg; 468 break; 469 case AXGBE_SFP_BASE_10000_SR: 470 case AXGBE_SFP_BASE_10000_LR: 471 case AXGBE_SFP_BASE_10000_LRM: 472 case AXGBE_SFP_BASE_10000_ER: 473 case AXGBE_SFP_BASE_10000_CR: 474 default: 475 pdata->phy.speed = SPEED_10000; 476 pdata->phy.duplex = DUPLEX_FULL; 477 pdata->phy.autoneg = AUTONEG_DISABLE; 478 break; 479 } 480 481 switch (phy_data->sfp_base) { 482 case AXGBE_SFP_BASE_1000_T: 483 case AXGBE_SFP_BASE_1000_CX: 484 case AXGBE_SFP_BASE_10000_CR: 485 pdata->phy.advertising |= ADVERTISED_TP; 486 break; 487 default: 488 pdata->phy.advertising |= ADVERTISED_FIBRE; 489 } 490 491 switch (phy_data->sfp_speed) { 492 case AXGBE_SFP_SPEED_100_1000: 493 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 494 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 495 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 496 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 497 break; 498 case AXGBE_SFP_SPEED_1000: 499 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 500 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 501 break; 502 case AXGBE_SFP_SPEED_10000: 503 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 504 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 505 break; 506 default: 507 /* Choose the fastest supported speed */ 508 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 509 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 510 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 511 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 512 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 513 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 514 } 515 } 516 517 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 518 enum axgbe_sfp_speed sfp_speed) 519 { 520 u8 *sfp_base, min; 521 522 sfp_base = sfp_eeprom->base; 523 524 switch (sfp_speed) { 525 case AXGBE_SFP_SPEED_1000: 526 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 527 break; 528 case AXGBE_SFP_SPEED_10000: 529 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 530 break; 531 default: 532 return false; 533 } 534 535 return sfp_base[AXGBE_SFP_BASE_BR] >= min; 536 } 537 538 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 539 { 540 struct axgbe_phy_data *phy_data = pdata->phy_data; 541 542 if (!phy_data->sfp_changed) 543 return; 544 545 phy_data->sfp_phy_avail = 0; 546 547 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 548 return; 549 } 550 551 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 552 { 553 struct axgbe_phy_data *phy_data = pdata->phy_data; 554 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 555 556 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 557 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 558 return false; 559 560 /* Reset PHY - wait for self-clearing reset bit to clear */ 561 pdata->phy_if.phy_impl.reset(pdata); 562 563 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 564 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 565 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 566 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 567 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 568 return true; 569 } 570 571 return false; 572 } 573 574 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 575 { 576 if (axgbe_phy_belfuse_parse_quirks(pdata)) 577 return true; 578 579 return false; 580 } 581 582 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 583 { 584 struct axgbe_phy_data *phy_data = pdata->phy_data; 585 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 586 uint8_t *sfp_base; 587 588 sfp_base = sfp_eeprom->base; 589 590 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 591 return; 592 593 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 594 return; 595 596 axgbe_phy_sfp_parse_quirks(pdata); 597 598 /* Assume FIBER cable unless told otherwise */ 599 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 600 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 601 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 602 } else if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_ACTIVE) { 603 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 604 } else { 605 phy_data->sfp_cable = AXGBE_SFP_CABLE_FIBER; 606 } 607 608 /* Determine the type of SFP */ 609 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_FIBER && 610 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 611 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 612 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 613 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 614 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 615 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 616 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 617 AXGBE_SFP_BASE_10GBE_CC_LRM) 618 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 619 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 620 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 621 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 622 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 623 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 624 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 625 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 626 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 627 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 628 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 629 630 switch (phy_data->sfp_base) { 631 case AXGBE_SFP_BASE_1000_T: 632 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 633 break; 634 case AXGBE_SFP_BASE_1000_SX: 635 case AXGBE_SFP_BASE_1000_LX: 636 case AXGBE_SFP_BASE_1000_CX: 637 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 638 break; 639 case AXGBE_SFP_BASE_10000_SR: 640 case AXGBE_SFP_BASE_10000_LR: 641 case AXGBE_SFP_BASE_10000_LRM: 642 case AXGBE_SFP_BASE_10000_ER: 643 case AXGBE_SFP_BASE_10000_CR: 644 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 645 break; 646 default: 647 break; 648 } 649 } 650 651 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 652 unsigned int len) 653 { 654 uint8_t cc; 655 656 for (cc = 0; len; buf++, len--) 657 cc += *buf; 658 659 return (cc == cc_in) ? true : false; 660 } 661 662 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 663 { 664 struct axgbe_phy_data *phy_data = pdata->phy_data; 665 struct axgbe_sfp_eeprom sfp_eeprom; 666 uint8_t eeprom_addr; 667 int ret; 668 669 ret = axgbe_phy_sfp_get_mux(pdata); 670 if (ret) { 671 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 672 return ret; 673 } 674 675 /* Read the SFP serial ID eeprom */ 676 eeprom_addr = 0; 677 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 678 &eeprom_addr, sizeof(eeprom_addr), 679 &sfp_eeprom, sizeof(sfp_eeprom)); 680 if (ret) { 681 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 682 goto put; 683 } 684 685 /* Validate the contents read */ 686 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 687 sfp_eeprom.base, 688 sizeof(sfp_eeprom.base) - 1)) { 689 ret = -EINVAL; 690 goto put; 691 } 692 693 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 694 sfp_eeprom.extd, 695 sizeof(sfp_eeprom.extd) - 1)) { 696 ret = -EINVAL; 697 goto put; 698 } 699 700 /* Check for an added or changed SFP */ 701 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 702 phy_data->sfp_changed = 1; 703 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 704 } else { 705 phy_data->sfp_changed = 0; 706 } 707 708 put: 709 axgbe_phy_sfp_put_mux(pdata); 710 711 return ret; 712 } 713 714 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 715 { 716 struct axgbe_phy_data *phy_data = pdata->phy_data; 717 unsigned int gpio_input; 718 u8 gpio_reg, gpio_ports[2]; 719 int ret; 720 721 /* Read the input port registers */ 722 gpio_reg = 0; 723 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 724 &gpio_reg, sizeof(gpio_reg), 725 gpio_ports, sizeof(gpio_ports)); 726 if (ret) { 727 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 728 return; 729 } 730 731 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 732 733 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 734 /* No GPIO, just assume the module is present for now */ 735 phy_data->sfp_mod_absent = 0; 736 } else { 737 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 738 phy_data->sfp_mod_absent = 0; 739 } 740 741 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 742 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 743 phy_data->sfp_rx_los = 1; 744 745 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 746 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 747 phy_data->sfp_tx_fault = 1; 748 } 749 750 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 751 { 752 struct axgbe_phy_data *phy_data = pdata->phy_data; 753 754 phy_data->sfp_mod_absent = 1; 755 phy_data->sfp_phy_avail = 0; 756 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 757 } 758 759 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 760 { 761 phy_data->sfp_rx_los = 0; 762 phy_data->sfp_tx_fault = 0; 763 phy_data->sfp_mod_absent = 1; 764 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 765 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 766 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 767 } 768 769 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base) 770 { 771 switch (sfp_base) { 772 case AXGBE_SFP_BASE_1000_T: 773 return "1G_T"; 774 case AXGBE_SFP_BASE_1000_SX: 775 return "1G_SX"; 776 case AXGBE_SFP_BASE_1000_LX: 777 return "1G_LX"; 778 case AXGBE_SFP_BASE_1000_CX: 779 return "1G_CX"; 780 case AXGBE_SFP_BASE_10000_SR: 781 return "10G_SR"; 782 case AXGBE_SFP_BASE_10000_LR: 783 return "10G_LR"; 784 case AXGBE_SFP_BASE_10000_LRM: 785 return "10G_LRM"; 786 case AXGBE_SFP_BASE_10000_ER: 787 return "10G_ER"; 788 case AXGBE_SFP_BASE_10000_CR: 789 return "10G_CR"; 790 default: 791 return "Unknown"; 792 } 793 } 794 795 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 796 { 797 struct axgbe_phy_data *phy_data = pdata->phy_data; 798 int ret; 799 800 /* Reset the SFP signals and info */ 801 axgbe_phy_sfp_reset(phy_data); 802 803 ret = axgbe_phy_get_comm_ownership(pdata); 804 if (ret) 805 return; 806 807 /* Read the SFP signals and check for module presence */ 808 axgbe_phy_sfp_signals(pdata); 809 if (phy_data->sfp_mod_absent) { 810 axgbe_phy_sfp_mod_absent(pdata); 811 goto put; 812 } 813 814 ret = axgbe_phy_sfp_read_eeprom(pdata); 815 if (ret) { 816 /* Treat any error as if there isn't an SFP plugged in */ 817 axgbe_phy_sfp_reset(phy_data); 818 axgbe_phy_sfp_mod_absent(pdata); 819 goto put; 820 } 821 822 axgbe_phy_sfp_parse_eeprom(pdata); 823 axgbe_phy_sfp_external_phy(pdata); 824 825 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n", 826 axgbe_base_as_string(phy_data->sfp_base)); 827 828 put: 829 axgbe_phy_sfp_phy_settings(pdata); 830 axgbe_phy_put_comm_ownership(pdata); 831 } 832 833 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 834 { 835 pdata->phy.tx_pause = 0; 836 pdata->phy.rx_pause = 0; 837 } 838 839 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 840 { 841 struct axgbe_phy_data *phy_data = pdata->phy_data; 842 enum axgbe_mode mode; 843 unsigned int ad_reg, lp_reg; 844 845 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 846 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 847 848 /* Use external PHY to determine flow control */ 849 if (pdata->phy.pause_autoneg) 850 axgbe_phy_phydev_flowctrl(pdata); 851 852 /* Compare Advertisement and Link Partner register 2 */ 853 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 854 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 855 if (lp_reg & 0x80) 856 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 857 if (lp_reg & 0x20) 858 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 859 860 ad_reg &= lp_reg; 861 if (ad_reg & 0x80) { 862 switch (phy_data->port_mode) { 863 case AXGBE_PORT_MODE_BACKPLANE: 864 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 865 mode = AXGBE_MODE_KR; 866 break; 867 default: 868 mode = AXGBE_MODE_SFI; 869 break; 870 } 871 } else if (ad_reg & 0x20) { 872 switch (phy_data->port_mode) { 873 case AXGBE_PORT_MODE_BACKPLANE: 874 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 875 mode = AXGBE_MODE_KX_1000; 876 break; 877 case AXGBE_PORT_MODE_1000BASE_X: 878 mode = AXGBE_MODE_X; 879 break; 880 case AXGBE_PORT_MODE_SFP: 881 switch (phy_data->sfp_base) { 882 case AXGBE_SFP_BASE_1000_T: 883 mode = AXGBE_MODE_SGMII_1000; 884 break; 885 case AXGBE_SFP_BASE_1000_SX: 886 case AXGBE_SFP_BASE_1000_LX: 887 case AXGBE_SFP_BASE_1000_CX: 888 default: 889 mode = AXGBE_MODE_X; 890 break; 891 } 892 break; 893 default: 894 mode = AXGBE_MODE_SGMII_1000; 895 break; 896 } 897 } else { 898 mode = AXGBE_MODE_UNKNOWN; 899 } 900 901 /* Compare Advertisement and Link Partner register 3 */ 902 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 903 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 904 if (lp_reg & 0xc000) 905 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 906 907 return mode; 908 } 909 910 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 911 { 912 enum axgbe_mode mode; 913 unsigned int ad_reg, lp_reg; 914 915 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 916 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 917 918 /* Compare Advertisement and Link Partner register 1 */ 919 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 920 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 921 if (lp_reg & 0x400) 922 pdata->phy.lp_advertising |= ADVERTISED_Pause; 923 if (lp_reg & 0x800) 924 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 925 926 if (pdata->phy.pause_autoneg) { 927 /* Set flow control based on auto-negotiation result */ 928 pdata->phy.tx_pause = 0; 929 pdata->phy.rx_pause = 0; 930 931 if (ad_reg & lp_reg & 0x400) { 932 pdata->phy.tx_pause = 1; 933 pdata->phy.rx_pause = 1; 934 } else if (ad_reg & lp_reg & 0x800) { 935 if (ad_reg & 0x400) 936 pdata->phy.rx_pause = 1; 937 else if (lp_reg & 0x400) 938 pdata->phy.tx_pause = 1; 939 } 940 } 941 942 /* Compare Advertisement and Link Partner register 2 */ 943 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 944 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 945 if (lp_reg & 0x80) 946 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 947 if (lp_reg & 0x20) 948 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 949 950 ad_reg &= lp_reg; 951 if (ad_reg & 0x80) 952 mode = AXGBE_MODE_KR; 953 else if (ad_reg & 0x20) 954 mode = AXGBE_MODE_KX_1000; 955 else 956 mode = AXGBE_MODE_UNKNOWN; 957 958 /* Compare Advertisement and Link Partner register 3 */ 959 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 960 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 961 if (lp_reg & 0xc000) 962 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 963 964 return mode; 965 } 966 967 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 968 { 969 enum axgbe_mode mode; 970 971 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 972 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 973 974 if (pdata->phy.pause_autoneg) 975 axgbe_phy_phydev_flowctrl(pdata); 976 977 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 978 case AXGBE_SGMII_AN_LINK_SPEED_100: 979 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 980 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 981 mode = AXGBE_MODE_SGMII_100; 982 } else { 983 mode = AXGBE_MODE_UNKNOWN; 984 } 985 break; 986 case AXGBE_SGMII_AN_LINK_SPEED_1000: 987 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 988 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 989 mode = AXGBE_MODE_SGMII_1000; 990 } else { 991 /* Half-duplex not supported */ 992 mode = AXGBE_MODE_UNKNOWN; 993 } 994 break; 995 default: 996 mode = AXGBE_MODE_UNKNOWN; 997 break; 998 } 999 return mode; 1000 } 1001 1002 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 1003 { 1004 switch (pdata->an_mode) { 1005 case AXGBE_AN_MODE_CL73: 1006 return axgbe_phy_an73_outcome(pdata); 1007 case AXGBE_AN_MODE_CL73_REDRV: 1008 return axgbe_phy_an73_redrv_outcome(pdata); 1009 case AXGBE_AN_MODE_CL37: 1010 case AXGBE_AN_MODE_CL37_SGMII: 1011 return axgbe_phy_an37_sgmii_outcome(pdata); 1012 default: 1013 return AXGBE_MODE_UNKNOWN; 1014 } 1015 } 1016 1017 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1018 { 1019 struct axgbe_phy_data *phy_data = pdata->phy_data; 1020 unsigned int advertising; 1021 1022 /* Without a re-driver, just return current advertising */ 1023 if (!phy_data->redrv) 1024 return pdata->phy.advertising; 1025 1026 /* With the KR re-driver we need to advertise a single speed */ 1027 advertising = pdata->phy.advertising; 1028 advertising &= ~ADVERTISED_1000baseKX_Full; 1029 advertising &= ~ADVERTISED_10000baseKR_Full; 1030 1031 switch (phy_data->port_mode) { 1032 case AXGBE_PORT_MODE_BACKPLANE: 1033 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1034 advertising |= ADVERTISED_10000baseKR_Full; 1035 break; 1036 case AXGBE_PORT_MODE_BACKPLANE_2500: 1037 advertising |= ADVERTISED_1000baseKX_Full; 1038 break; 1039 case AXGBE_PORT_MODE_1000BASE_T: 1040 case AXGBE_PORT_MODE_1000BASE_X: 1041 case AXGBE_PORT_MODE_NBASE_T: 1042 advertising |= ADVERTISED_1000baseKX_Full; 1043 break; 1044 case AXGBE_PORT_MODE_10GBASE_T: 1045 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1046 break; 1047 case AXGBE_PORT_MODE_10GBASE_R: 1048 advertising |= ADVERTISED_10000baseKR_Full; 1049 break; 1050 case AXGBE_PORT_MODE_SFP: 1051 switch (phy_data->sfp_base) { 1052 case AXGBE_SFP_BASE_1000_T: 1053 case AXGBE_SFP_BASE_1000_SX: 1054 case AXGBE_SFP_BASE_1000_LX: 1055 case AXGBE_SFP_BASE_1000_CX: 1056 advertising |= ADVERTISED_1000baseKX_Full; 1057 break; 1058 default: 1059 advertising |= ADVERTISED_10000baseKR_Full; 1060 break; 1061 } 1062 break; 1063 default: 1064 advertising |= ADVERTISED_10000baseKR_Full; 1065 break; 1066 } 1067 1068 return advertising; 1069 } 1070 1071 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1072 { 1073 return 0; 1074 /* Dummy API since there is no case to support 1075 * external phy devices registered through kernel APIs 1076 */ 1077 } 1078 1079 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1080 { 1081 switch (phy_data->sfp_base) { 1082 case AXGBE_SFP_BASE_1000_T: 1083 return AXGBE_AN_MODE_CL37_SGMII; 1084 case AXGBE_SFP_BASE_1000_SX: 1085 case AXGBE_SFP_BASE_1000_LX: 1086 case AXGBE_SFP_BASE_1000_CX: 1087 return AXGBE_AN_MODE_CL37; 1088 default: 1089 return AXGBE_AN_MODE_NONE; 1090 } 1091 } 1092 1093 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1094 { 1095 struct axgbe_phy_data *phy_data = pdata->phy_data; 1096 1097 /* A KR re-driver will always require CL73 AN */ 1098 if (phy_data->redrv) 1099 return AXGBE_AN_MODE_CL73_REDRV; 1100 1101 switch (phy_data->port_mode) { 1102 case AXGBE_PORT_MODE_BACKPLANE: 1103 return AXGBE_AN_MODE_CL73; 1104 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1105 case AXGBE_PORT_MODE_BACKPLANE_2500: 1106 return AXGBE_AN_MODE_NONE; 1107 case AXGBE_PORT_MODE_1000BASE_T: 1108 return AXGBE_AN_MODE_CL37_SGMII; 1109 case AXGBE_PORT_MODE_1000BASE_X: 1110 return AXGBE_AN_MODE_CL37; 1111 case AXGBE_PORT_MODE_NBASE_T: 1112 return AXGBE_AN_MODE_CL37_SGMII; 1113 case AXGBE_PORT_MODE_10GBASE_T: 1114 return AXGBE_AN_MODE_CL73; 1115 case AXGBE_PORT_MODE_10GBASE_R: 1116 return AXGBE_AN_MODE_NONE; 1117 case AXGBE_PORT_MODE_SFP: 1118 return axgbe_phy_an_sfp_mode(phy_data); 1119 default: 1120 return AXGBE_AN_MODE_NONE; 1121 } 1122 } 1123 1124 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1125 enum axgbe_phy_redrv_mode mode) 1126 { 1127 struct axgbe_phy_data *phy_data = pdata->phy_data; 1128 u16 redrv_reg, redrv_val; 1129 1130 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1131 redrv_val = (u16)mode; 1132 1133 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1134 redrv_reg, redrv_val); 1135 } 1136 1137 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1138 enum axgbe_phy_redrv_mode mode) 1139 { 1140 struct axgbe_phy_data *phy_data = pdata->phy_data; 1141 unsigned int redrv_reg; 1142 int ret; 1143 1144 /* Calculate the register to write */ 1145 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1146 1147 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1148 1149 return ret; 1150 } 1151 1152 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1153 { 1154 struct axgbe_phy_data *phy_data = pdata->phy_data; 1155 enum axgbe_phy_redrv_mode mode; 1156 int ret; 1157 1158 if (!phy_data->redrv) 1159 return; 1160 1161 mode = AXGBE_PHY_REDRV_MODE_CX; 1162 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1163 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1164 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1165 mode = AXGBE_PHY_REDRV_MODE_SR; 1166 1167 ret = axgbe_phy_get_comm_ownership(pdata); 1168 if (ret) 1169 return; 1170 1171 if (phy_data->redrv_if) 1172 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1173 else 1174 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1175 1176 axgbe_phy_put_comm_ownership(pdata); 1177 } 1178 1179 static void axgbe_phy_rx_reset(struct axgbe_port *pdata) 1180 { 1181 int reg; 1182 1183 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 1184 XGBE_PCS_PSEQ_STATE_MASK); 1185 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 1186 /* Mailbox command timed out, reset of RX block is required. 1187 * This can be done by asseting the reset bit and wait for 1188 * its compeletion. 1189 */ 1190 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1191 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 1192 rte_delay_us(20); 1193 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1194 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 1195 rte_delay_us(45); 1196 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n"); 1197 } 1198 } 1199 1200 1201 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) 1202 { 1203 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ 1204 if (pdata->phy.autoneg != AUTONEG_DISABLE) 1205 return; 1206 1207 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1208 XGBE_PMA_PLL_CTRL_MASK, 1209 enable ? XGBE_PMA_PLL_CTRL_SET 1210 : XGBE_PMA_PLL_CTRL_CLEAR); 1211 1212 /* Wait for command to complete */ 1213 rte_delay_us(150); 1214 } 1215 1216 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, 1217 unsigned int cmd, unsigned int sub_cmd) 1218 { 1219 unsigned int s0 = 0; 1220 unsigned int wait; 1221 /* Clear the PLL so that it helps in power down sequence */ 1222 axgbe_phy_pll_ctrl(pdata, false); 1223 1224 /* Log if a previous command did not complete */ 1225 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 1226 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); 1227 axgbe_phy_rx_reset(pdata); 1228 } 1229 1230 /* Construct the command */ 1231 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1232 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1233 1234 /* Issue the command */ 1235 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1236 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1237 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1238 1239 /* Wait for command to complete */ 1240 wait = AXGBE_RATECHANGE_COUNT; 1241 while (wait--) { 1242 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1243 goto reenable_pll; 1244 rte_delay_us(1500); 1245 } 1246 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1247 /* Reset on error */ 1248 axgbe_phy_rx_reset(pdata); 1249 1250 reenable_pll: 1251 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */ 1252 if (cmd != 0 && cmd != 5) 1253 axgbe_phy_pll_ctrl(pdata, true); 1254 1255 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1256 } 1257 1258 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1259 { 1260 1261 1262 /* Receiver Reset Cycle */ 1263 axgbe_phy_perform_ratechange(pdata, 5, 0); 1264 1265 PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); 1266 } 1267 1268 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1269 { 1270 struct axgbe_phy_data *phy_data = pdata->phy_data; 1271 1272 /* Power off */ 1273 axgbe_phy_perform_ratechange(pdata, 0, 0); 1274 1275 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1276 1277 PMD_DRV_LOG(DEBUG, "phy powered off\n"); 1278 } 1279 1280 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1281 { 1282 struct axgbe_phy_data *phy_data = pdata->phy_data; 1283 1284 axgbe_phy_set_redrv_mode(pdata); 1285 1286 /* 10G/SFI */ 1287 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1288 axgbe_phy_perform_ratechange(pdata, 3, 0); 1289 } else { 1290 if (phy_data->sfp_cable_len <= 1) 1291 axgbe_phy_perform_ratechange(pdata, 3, 1); 1292 else if (phy_data->sfp_cable_len <= 3) 1293 axgbe_phy_perform_ratechange(pdata, 3, 2); 1294 else 1295 axgbe_phy_perform_ratechange(pdata, 3, 3); 1296 } 1297 1298 phy_data->cur_mode = AXGBE_MODE_SFI; 1299 1300 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); 1301 } 1302 1303 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1304 { 1305 struct axgbe_phy_data *phy_data = pdata->phy_data; 1306 1307 axgbe_phy_set_redrv_mode(pdata); 1308 1309 /* 10G/KR */ 1310 axgbe_phy_perform_ratechange(pdata, 4, 0); 1311 phy_data->cur_mode = AXGBE_MODE_KR; 1312 1313 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); 1314 } 1315 1316 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1317 { 1318 struct axgbe_phy_data *phy_data = pdata->phy_data; 1319 1320 axgbe_phy_set_redrv_mode(pdata); 1321 1322 /* 2.5G/KX */ 1323 axgbe_phy_perform_ratechange(pdata, 2, 0); 1324 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1325 } 1326 1327 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1328 { 1329 struct axgbe_phy_data *phy_data = pdata->phy_data; 1330 1331 axgbe_phy_set_redrv_mode(pdata); 1332 1333 /* 1G/SGMII */ 1334 axgbe_phy_perform_ratechange(pdata, 1, 2); 1335 1336 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1337 } 1338 1339 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1340 { 1341 struct axgbe_phy_data *phy_data = pdata->phy_data; 1342 1343 return phy_data->cur_mode; 1344 } 1345 1346 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1347 { 1348 struct axgbe_phy_data *phy_data = pdata->phy_data; 1349 1350 /* No switching if not 10GBase-T */ 1351 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1352 return axgbe_phy_cur_mode(pdata); 1353 1354 switch (axgbe_phy_cur_mode(pdata)) { 1355 case AXGBE_MODE_SGMII_100: 1356 case AXGBE_MODE_SGMII_1000: 1357 return AXGBE_MODE_KR; 1358 case AXGBE_MODE_KR: 1359 default: 1360 return AXGBE_MODE_SGMII_1000; 1361 } 1362 } 1363 1364 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1365 __rte_unused) 1366 { 1367 return AXGBE_MODE_KX_2500; 1368 } 1369 1370 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1371 { 1372 /* If we are in KR switch to KX, and vice-versa */ 1373 switch (axgbe_phy_cur_mode(pdata)) { 1374 case AXGBE_MODE_KX_1000: 1375 return AXGBE_MODE_KR; 1376 case AXGBE_MODE_KR: 1377 default: 1378 return AXGBE_MODE_KX_1000; 1379 } 1380 } 1381 1382 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1383 { 1384 struct axgbe_phy_data *phy_data = pdata->phy_data; 1385 1386 switch (phy_data->port_mode) { 1387 case AXGBE_PORT_MODE_BACKPLANE: 1388 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1389 return axgbe_phy_switch_bp_mode(pdata); 1390 case AXGBE_PORT_MODE_BACKPLANE_2500: 1391 return axgbe_phy_switch_bp_2500_mode(pdata); 1392 case AXGBE_PORT_MODE_1000BASE_T: 1393 case AXGBE_PORT_MODE_NBASE_T: 1394 case AXGBE_PORT_MODE_10GBASE_T: 1395 return axgbe_phy_switch_baset_mode(pdata); 1396 case AXGBE_PORT_MODE_1000BASE_X: 1397 case AXGBE_PORT_MODE_10GBASE_R: 1398 case AXGBE_PORT_MODE_SFP: 1399 /* No switching, so just return current mode */ 1400 return axgbe_phy_cur_mode(pdata); 1401 default: 1402 return AXGBE_MODE_UNKNOWN; 1403 } 1404 } 1405 1406 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1407 __rte_unused, 1408 int speed) 1409 { 1410 switch (speed) { 1411 case SPEED_1000: 1412 return AXGBE_MODE_X; 1413 case SPEED_10000: 1414 return AXGBE_MODE_KR; 1415 default: 1416 return AXGBE_MODE_UNKNOWN; 1417 } 1418 } 1419 1420 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1421 __rte_unused, 1422 int speed) 1423 { 1424 switch (speed) { 1425 case SPEED_100: 1426 return AXGBE_MODE_SGMII_100; 1427 case SPEED_1000: 1428 return AXGBE_MODE_SGMII_1000; 1429 case SPEED_10000: 1430 return AXGBE_MODE_KR; 1431 default: 1432 return AXGBE_MODE_UNKNOWN; 1433 } 1434 } 1435 1436 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1437 int speed) 1438 { 1439 switch (speed) { 1440 case SPEED_100: 1441 return AXGBE_MODE_SGMII_100; 1442 case SPEED_1000: 1443 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1444 return AXGBE_MODE_SGMII_1000; 1445 else 1446 return AXGBE_MODE_X; 1447 case SPEED_10000: 1448 case SPEED_UNKNOWN: 1449 return AXGBE_MODE_SFI; 1450 default: 1451 return AXGBE_MODE_UNKNOWN; 1452 } 1453 } 1454 1455 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1456 { 1457 switch (speed) { 1458 case SPEED_2500: 1459 return AXGBE_MODE_KX_2500; 1460 default: 1461 return AXGBE_MODE_UNKNOWN; 1462 } 1463 } 1464 1465 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1466 { 1467 switch (speed) { 1468 case SPEED_1000: 1469 return AXGBE_MODE_KX_1000; 1470 case SPEED_10000: 1471 return AXGBE_MODE_KR; 1472 default: 1473 return AXGBE_MODE_UNKNOWN; 1474 } 1475 } 1476 1477 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1478 int speed) 1479 { 1480 struct axgbe_phy_data *phy_data = pdata->phy_data; 1481 1482 switch (phy_data->port_mode) { 1483 case AXGBE_PORT_MODE_BACKPLANE: 1484 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1485 return axgbe_phy_get_bp_mode(speed); 1486 case AXGBE_PORT_MODE_BACKPLANE_2500: 1487 return axgbe_phy_get_bp_2500_mode(speed); 1488 case AXGBE_PORT_MODE_1000BASE_T: 1489 case AXGBE_PORT_MODE_NBASE_T: 1490 case AXGBE_PORT_MODE_10GBASE_T: 1491 return axgbe_phy_get_baset_mode(phy_data, speed); 1492 case AXGBE_PORT_MODE_1000BASE_X: 1493 case AXGBE_PORT_MODE_10GBASE_R: 1494 return axgbe_phy_get_basex_mode(phy_data, speed); 1495 case AXGBE_PORT_MODE_SFP: 1496 return axgbe_phy_get_sfp_mode(phy_data, speed); 1497 default: 1498 return AXGBE_MODE_UNKNOWN; 1499 } 1500 } 1501 1502 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1503 { 1504 switch (mode) { 1505 case AXGBE_MODE_KR: 1506 axgbe_phy_kr_mode(pdata); 1507 break; 1508 case AXGBE_MODE_SFI: 1509 axgbe_phy_sfi_mode(pdata); 1510 break; 1511 case AXGBE_MODE_KX_2500: 1512 axgbe_phy_kx_2500_mode(pdata); 1513 break; 1514 case AXGBE_MODE_SGMII_1000: 1515 axgbe_phy_sgmii_1000_mode(pdata); 1516 break; 1517 default: 1518 break; 1519 } 1520 } 1521 1522 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1523 enum axgbe_mode mode, u32 advert) 1524 { 1525 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1526 if (pdata->phy.advertising & advert) 1527 return true; 1528 } else { 1529 enum axgbe_mode cur_mode; 1530 1531 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1532 if (cur_mode == mode) 1533 return true; 1534 } 1535 1536 return false; 1537 } 1538 1539 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1540 enum axgbe_mode mode) 1541 { 1542 switch (mode) { 1543 case AXGBE_MODE_X: 1544 return axgbe_phy_check_mode(pdata, mode, 1545 ADVERTISED_1000baseT_Full); 1546 case AXGBE_MODE_KR: 1547 return axgbe_phy_check_mode(pdata, mode, 1548 ADVERTISED_10000baseT_Full); 1549 default: 1550 return false; 1551 } 1552 } 1553 1554 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1555 enum axgbe_mode mode) 1556 { 1557 switch (mode) { 1558 case AXGBE_MODE_SGMII_100: 1559 return axgbe_phy_check_mode(pdata, mode, 1560 ADVERTISED_100baseT_Full); 1561 case AXGBE_MODE_SGMII_1000: 1562 return axgbe_phy_check_mode(pdata, mode, 1563 ADVERTISED_1000baseT_Full); 1564 case AXGBE_MODE_KR: 1565 return axgbe_phy_check_mode(pdata, mode, 1566 ADVERTISED_10000baseT_Full); 1567 default: 1568 return false; 1569 } 1570 } 1571 1572 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1573 enum axgbe_mode mode) 1574 { 1575 struct axgbe_phy_data *phy_data = pdata->phy_data; 1576 1577 switch (mode) { 1578 case AXGBE_MODE_X: 1579 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1580 return false; 1581 return axgbe_phy_check_mode(pdata, mode, 1582 ADVERTISED_1000baseT_Full); 1583 case AXGBE_MODE_SGMII_100: 1584 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1585 return false; 1586 return axgbe_phy_check_mode(pdata, mode, 1587 ADVERTISED_100baseT_Full); 1588 case AXGBE_MODE_SGMII_1000: 1589 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1590 return false; 1591 return axgbe_phy_check_mode(pdata, mode, 1592 ADVERTISED_1000baseT_Full); 1593 case AXGBE_MODE_SFI: 1594 return axgbe_phy_check_mode(pdata, mode, 1595 ADVERTISED_10000baseT_Full); 1596 default: 1597 return false; 1598 } 1599 } 1600 1601 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1602 enum axgbe_mode mode) 1603 { 1604 switch (mode) { 1605 case AXGBE_MODE_KX_2500: 1606 return axgbe_phy_check_mode(pdata, mode, 1607 ADVERTISED_2500baseX_Full); 1608 default: 1609 return false; 1610 } 1611 } 1612 1613 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1614 enum axgbe_mode mode) 1615 { 1616 switch (mode) { 1617 case AXGBE_MODE_KX_1000: 1618 return axgbe_phy_check_mode(pdata, mode, 1619 ADVERTISED_1000baseKX_Full); 1620 case AXGBE_MODE_KR: 1621 return axgbe_phy_check_mode(pdata, mode, 1622 ADVERTISED_10000baseKR_Full); 1623 default: 1624 return false; 1625 } 1626 } 1627 1628 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1629 { 1630 struct axgbe_phy_data *phy_data = pdata->phy_data; 1631 1632 switch (phy_data->port_mode) { 1633 case AXGBE_PORT_MODE_BACKPLANE: 1634 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1635 return axgbe_phy_use_bp_mode(pdata, mode); 1636 case AXGBE_PORT_MODE_BACKPLANE_2500: 1637 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1638 case AXGBE_PORT_MODE_1000BASE_T: 1639 case AXGBE_PORT_MODE_NBASE_T: 1640 case AXGBE_PORT_MODE_10GBASE_T: 1641 return axgbe_phy_use_baset_mode(pdata, mode); 1642 case AXGBE_PORT_MODE_1000BASE_X: 1643 case AXGBE_PORT_MODE_10GBASE_R: 1644 return axgbe_phy_use_basex_mode(pdata, mode); 1645 case AXGBE_PORT_MODE_SFP: 1646 return axgbe_phy_use_sfp_mode(pdata, mode); 1647 default: 1648 return false; 1649 } 1650 } 1651 1652 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1653 { 1654 struct axgbe_phy_data *phy_data = pdata->phy_data; 1655 unsigned int reg; 1656 1657 *an_restart = 0; 1658 1659 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1660 /* Check SFP signals */ 1661 axgbe_phy_sfp_detect(pdata); 1662 1663 if (phy_data->sfp_changed) { 1664 *an_restart = 1; 1665 return 0; 1666 } 1667 1668 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1669 return 0; 1670 } 1671 1672 /* Link status is latched low, so read once to clear 1673 * and then read again to get current state 1674 */ 1675 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1676 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1677 if (reg & MDIO_STAT1_LSTATUS) 1678 return 1; 1679 1680 if (pdata->phy.autoneg == AUTONEG_ENABLE && 1681 phy_data->port_mode == AXGBE_PORT_MODE_BACKPLANE) { 1682 if (rte_bit_relaxed_get32(AXGBE_LINK_INIT, &pdata->dev_state)) { 1683 *an_restart = 1; 1684 } 1685 } 1686 1687 /* No link, attempt a receiver reset cycle */ 1688 if (pdata->vdata->enable_rrc && phy_data->rrc_count++) { 1689 phy_data->rrc_count = 0; 1690 axgbe_phy_rrc(pdata); 1691 } 1692 1693 return 0; 1694 } 1695 1696 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1697 { 1698 struct axgbe_phy_data *phy_data = pdata->phy_data; 1699 1700 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1701 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); 1702 1703 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_MASK); 1704 1705 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1706 GPIO_RX_LOS); 1707 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1708 GPIO_TX_FAULT); 1709 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1710 GPIO_MOD_ABS); 1711 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1712 GPIO_RATE_SELECT); 1713 } 1714 1715 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1716 { 1717 struct axgbe_phy_data *phy_data = pdata->phy_data; 1718 unsigned int mux_addr_hi, mux_addr_lo; 1719 1720 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 1721 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 1722 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1723 return; 1724 1725 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1726 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1727 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_CHAN); 1728 } 1729 1730 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1731 { 1732 axgbe_phy_sfp_comm_setup(pdata); 1733 axgbe_phy_sfp_gpio_setup(pdata); 1734 } 1735 1736 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1737 { 1738 if (!phy_data->redrv) 1739 return false; 1740 1741 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1742 return true; 1743 1744 switch (phy_data->redrv_model) { 1745 case AXGBE_PHY_REDRV_MODEL_4223: 1746 if (phy_data->redrv_lane > 3) 1747 return true; 1748 break; 1749 case AXGBE_PHY_REDRV_MODEL_4227: 1750 if (phy_data->redrv_lane > 1) 1751 return true; 1752 break; 1753 default: 1754 return true; 1755 } 1756 1757 return false; 1758 } 1759 1760 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1761 { 1762 struct axgbe_phy_data *phy_data = pdata->phy_data; 1763 1764 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1765 return 0; 1766 1767 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 1768 switch (phy_data->mdio_reset) { 1769 case AXGBE_MDIO_RESET_NONE: 1770 case AXGBE_MDIO_RESET_I2C_GPIO: 1771 case AXGBE_MDIO_RESET_INT_GPIO: 1772 break; 1773 default: 1774 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1775 phy_data->mdio_reset); 1776 return -EINVAL; 1777 } 1778 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1779 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1780 XP_GET_BITS(pdata->pp3, XP_PROP_3, 1781 MDIO_RESET_I2C_ADDR); 1782 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1783 MDIO_RESET_I2C_GPIO); 1784 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1785 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1786 MDIO_RESET_INT_GPIO); 1787 } 1788 1789 return 0; 1790 } 1791 1792 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1793 { 1794 struct axgbe_phy_data *phy_data = pdata->phy_data; 1795 1796 switch (phy_data->port_mode) { 1797 case AXGBE_PORT_MODE_BACKPLANE: 1798 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1799 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1800 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1801 return false; 1802 break; 1803 case AXGBE_PORT_MODE_BACKPLANE_2500: 1804 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1805 return false; 1806 break; 1807 case AXGBE_PORT_MODE_1000BASE_T: 1808 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1809 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1810 return false; 1811 break; 1812 case AXGBE_PORT_MODE_1000BASE_X: 1813 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1814 return false; 1815 break; 1816 case AXGBE_PORT_MODE_NBASE_T: 1817 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1818 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1819 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1820 return false; 1821 break; 1822 case AXGBE_PORT_MODE_10GBASE_T: 1823 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1824 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1825 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1826 return false; 1827 break; 1828 case AXGBE_PORT_MODE_10GBASE_R: 1829 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1830 return false; 1831 break; 1832 case AXGBE_PORT_MODE_SFP: 1833 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1834 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1835 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1836 return false; 1837 break; 1838 default: 1839 break; 1840 } 1841 1842 return true; 1843 } 1844 1845 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1846 { 1847 struct axgbe_phy_data *phy_data = pdata->phy_data; 1848 1849 switch (phy_data->port_mode) { 1850 case AXGBE_PORT_MODE_BACKPLANE: 1851 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1852 case AXGBE_PORT_MODE_BACKPLANE_2500: 1853 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1854 return false; 1855 break; 1856 case AXGBE_PORT_MODE_1000BASE_T: 1857 case AXGBE_PORT_MODE_1000BASE_X: 1858 case AXGBE_PORT_MODE_NBASE_T: 1859 case AXGBE_PORT_MODE_10GBASE_T: 1860 case AXGBE_PORT_MODE_10GBASE_R: 1861 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1862 return false; 1863 break; 1864 case AXGBE_PORT_MODE_SFP: 1865 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1866 return false; 1867 break; 1868 default: 1869 break; 1870 } 1871 1872 return true; 1873 } 1874 1875 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1876 { 1877 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 1878 return false; 1879 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 1880 return false; 1881 1882 return true; 1883 } 1884 1885 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1886 { 1887 struct axgbe_phy_data *phy_data = pdata->phy_data; 1888 1889 if (!pdata->vdata->an_cdr_workaround) 1890 return; 1891 1892 if (!phy_data->phy_cdr_notrack) 1893 return; 1894 1895 rte_delay_us(phy_data->phy_cdr_delay + 400); 1896 1897 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1898 AXGBE_PMA_CDR_TRACK_EN_MASK, 1899 AXGBE_PMA_CDR_TRACK_EN_ON); 1900 1901 phy_data->phy_cdr_notrack = 0; 1902 } 1903 1904 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1905 { 1906 struct axgbe_phy_data *phy_data = pdata->phy_data; 1907 1908 if (!pdata->vdata->an_cdr_workaround) 1909 return; 1910 1911 if (phy_data->phy_cdr_notrack) 1912 return; 1913 1914 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1915 AXGBE_PMA_CDR_TRACK_EN_MASK, 1916 AXGBE_PMA_CDR_TRACK_EN_OFF); 1917 1918 axgbe_phy_rrc(pdata); 1919 1920 phy_data->phy_cdr_notrack = 1; 1921 } 1922 1923 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1924 { 1925 if (!pdata->cdr_track_early) 1926 axgbe_phy_cdr_track(pdata); 1927 } 1928 1929 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1930 { 1931 if (pdata->cdr_track_early) 1932 axgbe_phy_cdr_track(pdata); 1933 } 1934 1935 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1936 { 1937 struct axgbe_phy_data *phy_data = pdata->phy_data; 1938 1939 switch (pdata->an_mode) { 1940 case AXGBE_AN_MODE_CL73: 1941 case AXGBE_AN_MODE_CL73_REDRV: 1942 if (phy_data->cur_mode != AXGBE_MODE_KR) 1943 break; 1944 1945 axgbe_phy_cdr_track(pdata); 1946 1947 switch (pdata->an_result) { 1948 case AXGBE_AN_READY: 1949 case AXGBE_AN_COMPLETE: 1950 break; 1951 default: 1952 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1953 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1954 break; 1955 } 1956 break; 1957 default: 1958 break; 1959 } 1960 } 1961 1962 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1963 { 1964 struct axgbe_phy_data *phy_data = pdata->phy_data; 1965 1966 switch (pdata->an_mode) { 1967 case AXGBE_AN_MODE_CL73: 1968 case AXGBE_AN_MODE_CL73_REDRV: 1969 if (phy_data->cur_mode != AXGBE_MODE_KR) 1970 break; 1971 1972 axgbe_phy_cdr_notrack(pdata); 1973 break; 1974 default: 1975 break; 1976 } 1977 } 1978 1979 static void axgbe_phy_stop(struct axgbe_port *pdata) 1980 { 1981 struct axgbe_phy_data *phy_data = pdata->phy_data; 1982 1983 /* Reset SFP data */ 1984 axgbe_phy_sfp_reset(phy_data); 1985 axgbe_phy_sfp_mod_absent(pdata); 1986 1987 /* Reset CDR support */ 1988 axgbe_phy_cdr_track(pdata); 1989 1990 /* Power off the PHY */ 1991 axgbe_phy_power_off(pdata); 1992 1993 /* Stop the I2C controller */ 1994 pdata->i2c_if.i2c_stop(pdata); 1995 } 1996 1997 static int axgbe_phy_start(struct axgbe_port *pdata) 1998 { 1999 struct axgbe_phy_data *phy_data = pdata->phy_data; 2000 int ret; 2001 2002 /* Start the I2C controller */ 2003 ret = pdata->i2c_if.i2c_start(pdata); 2004 if (ret) 2005 return ret; 2006 2007 /* Start in highest supported mode */ 2008 axgbe_phy_set_mode(pdata, phy_data->start_mode); 2009 2010 /* Reset CDR support */ 2011 axgbe_phy_cdr_track(pdata); 2012 2013 /* After starting the I2C controller, we can check for an SFP */ 2014 switch (phy_data->port_mode) { 2015 case AXGBE_PORT_MODE_SFP: 2016 axgbe_phy_sfp_detect(pdata); 2017 break; 2018 default: 2019 break; 2020 } 2021 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 2022 2023 return ret; 2024 } 2025 2026 static int axgbe_phy_reset(struct axgbe_port *pdata) 2027 { 2028 struct axgbe_phy_data *phy_data = pdata->phy_data; 2029 enum axgbe_mode cur_mode; 2030 2031 /* Reset by power cycling the PHY */ 2032 cur_mode = phy_data->cur_mode; 2033 axgbe_phy_power_off(pdata); 2034 /* First time reset is done with passed unknown mode*/ 2035 axgbe_phy_set_mode(pdata, cur_mode); 2036 return 0; 2037 } 2038 2039 static int axgbe_phy_init(struct axgbe_port *pdata) 2040 { 2041 struct axgbe_phy_data *phy_data; 2042 int ret; 2043 2044 /* Check if enabled */ 2045 if (!axgbe_phy_port_enabled(pdata)) { 2046 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2047 return -ENODEV; 2048 } 2049 2050 /* Initialize the I2C controller */ 2051 ret = pdata->i2c_if.i2c_init(pdata); 2052 if (ret) 2053 return ret; 2054 2055 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2056 if (!phy_data) { 2057 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2058 return -ENOMEM; 2059 } 2060 pdata->phy_data = phy_data; 2061 2062 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 2063 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 2064 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 2065 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 2066 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 2067 2068 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 2069 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 2070 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 2071 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 2072 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 2073 2074 /* Validate the connection requested */ 2075 if (axgbe_phy_conn_type_mismatch(pdata)) { 2076 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2077 phy_data->port_mode, phy_data->conn_type); 2078 return -EINVAL; 2079 } 2080 2081 /* Validate the mode requested */ 2082 if (axgbe_phy_port_mode_mismatch(pdata)) { 2083 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2084 phy_data->port_mode, phy_data->port_speeds); 2085 return -EINVAL; 2086 } 2087 2088 /* Check for and validate MDIO reset support */ 2089 ret = axgbe_phy_mdio_reset_setup(pdata); 2090 if (ret) 2091 return ret; 2092 2093 /* Validate the re-driver information */ 2094 if (axgbe_phy_redrv_error(phy_data)) { 2095 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2096 return -EINVAL; 2097 } 2098 pdata->kr_redrv = phy_data->redrv; 2099 2100 /* Indicate current mode is unknown */ 2101 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2102 2103 /* Initialize supported features */ 2104 pdata->phy.supported = 0; 2105 2106 switch (phy_data->port_mode) { 2107 /* Backplane support */ 2108 case AXGBE_PORT_MODE_BACKPLANE: 2109 pdata->phy.supported |= SUPPORTED_Autoneg; 2110 /* Fallthrough */ 2111 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2112 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2113 pdata->phy.supported |= SUPPORTED_Backplane; 2114 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2115 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2116 phy_data->start_mode = AXGBE_MODE_KX_1000; 2117 } 2118 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2119 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2120 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2121 pdata->phy.supported |= 2122 SUPPORTED_10000baseR_FEC; 2123 phy_data->start_mode = AXGBE_MODE_KR; 2124 } 2125 2126 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2127 break; 2128 case AXGBE_PORT_MODE_BACKPLANE_2500: 2129 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2130 pdata->phy.supported |= SUPPORTED_Backplane; 2131 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2132 phy_data->start_mode = AXGBE_MODE_KX_2500; 2133 2134 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2135 break; 2136 2137 /* MDIO 1GBase-T support */ 2138 case AXGBE_PORT_MODE_1000BASE_T: 2139 pdata->phy.supported |= SUPPORTED_Autoneg; 2140 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2141 pdata->phy.supported |= SUPPORTED_TP; 2142 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2143 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2144 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2145 } 2146 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2147 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2148 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2149 } 2150 2151 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2152 break; 2153 2154 /* MDIO Base-X support */ 2155 case AXGBE_PORT_MODE_1000BASE_X: 2156 pdata->phy.supported |= SUPPORTED_Autoneg; 2157 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2158 pdata->phy.supported |= SUPPORTED_FIBRE; 2159 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2160 phy_data->start_mode = AXGBE_MODE_X; 2161 2162 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2163 break; 2164 2165 /* MDIO NBase-T support */ 2166 case AXGBE_PORT_MODE_NBASE_T: 2167 pdata->phy.supported |= SUPPORTED_Autoneg; 2168 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2169 pdata->phy.supported |= SUPPORTED_TP; 2170 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2171 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2172 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2173 } 2174 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2175 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2176 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2177 } 2178 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2179 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2180 phy_data->start_mode = AXGBE_MODE_KX_2500; 2181 } 2182 2183 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2184 break; 2185 2186 /* 10GBase-T support */ 2187 case AXGBE_PORT_MODE_10GBASE_T: 2188 pdata->phy.supported |= SUPPORTED_Autoneg; 2189 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2190 pdata->phy.supported |= SUPPORTED_TP; 2191 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2192 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2193 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2194 } 2195 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2196 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2197 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2198 } 2199 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2200 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2201 phy_data->start_mode = AXGBE_MODE_KR; 2202 } 2203 2204 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2205 break; 2206 2207 /* 10GBase-R support */ 2208 case AXGBE_PORT_MODE_10GBASE_R: 2209 pdata->phy.supported |= SUPPORTED_Autoneg; 2210 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2211 pdata->phy.supported |= SUPPORTED_TP; 2212 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2213 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2214 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2215 phy_data->start_mode = AXGBE_MODE_SFI; 2216 2217 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2218 break; 2219 2220 /* SFP support */ 2221 case AXGBE_PORT_MODE_SFP: 2222 pdata->phy.supported |= SUPPORTED_Autoneg; 2223 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2224 pdata->phy.supported |= SUPPORTED_TP; 2225 pdata->phy.supported |= SUPPORTED_FIBRE; 2226 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2227 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2228 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2229 } 2230 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2231 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2232 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2233 } 2234 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2235 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2236 phy_data->start_mode = AXGBE_MODE_SFI; 2237 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2238 pdata->phy.supported |= 2239 SUPPORTED_10000baseR_FEC; 2240 } 2241 2242 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2243 2244 axgbe_phy_sfp_setup(pdata); 2245 break; 2246 default: 2247 return -EINVAL; 2248 } 2249 2250 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2251 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2252 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2253 phy_data->phydev_mode); 2254 if (ret) { 2255 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2256 phy_data->mdio_addr, phy_data->phydev_mode); 2257 return -EINVAL; 2258 } 2259 } 2260 2261 if (phy_data->redrv && !phy_data->redrv_if) { 2262 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2263 AXGBE_MDIO_MODE_CL22); 2264 if (ret) { 2265 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2266 phy_data->redrv_addr); 2267 return -EINVAL; 2268 } 2269 } 2270 2271 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2272 return 0; 2273 } 2274 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2275 { 2276 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2277 2278 phy_impl->init = axgbe_phy_init; 2279 phy_impl->reset = axgbe_phy_reset; 2280 phy_impl->start = axgbe_phy_start; 2281 phy_impl->stop = axgbe_phy_stop; 2282 phy_impl->link_status = axgbe_phy_link_status; 2283 phy_impl->use_mode = axgbe_phy_use_mode; 2284 phy_impl->set_mode = axgbe_phy_set_mode; 2285 phy_impl->get_mode = axgbe_phy_get_mode; 2286 phy_impl->switch_mode = axgbe_phy_switch_mode; 2287 phy_impl->cur_mode = axgbe_phy_cur_mode; 2288 phy_impl->an_mode = axgbe_phy_an_mode; 2289 phy_impl->an_config = axgbe_phy_an_config; 2290 phy_impl->an_advertising = axgbe_phy_an_advertising; 2291 phy_impl->an_outcome = axgbe_phy_an_outcome; 2292 2293 phy_impl->an_pre = axgbe_phy_an_pre; 2294 phy_impl->an_post = axgbe_phy_an_post; 2295 2296 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2297 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2298 } 2299