1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_MAX, 50 }; 51 52 enum axgbe_conn_type { 53 AXGBE_CONN_TYPE_NONE = 0, 54 AXGBE_CONN_TYPE_SFP, 55 AXGBE_CONN_TYPE_MDIO, 56 AXGBE_CONN_TYPE_RSVD1, 57 AXGBE_CONN_TYPE_BACKPLANE, 58 AXGBE_CONN_TYPE_MAX, 59 }; 60 61 /* SFP/SFP+ related definitions */ 62 enum axgbe_sfp_comm { 63 AXGBE_SFP_COMM_DIRECT = 0, 64 AXGBE_SFP_COMM_PCA9545, 65 }; 66 67 enum axgbe_sfp_cable { 68 AXGBE_SFP_CABLE_UNKNOWN = 0, 69 AXGBE_SFP_CABLE_ACTIVE, 70 AXGBE_SFP_CABLE_PASSIVE, 71 }; 72 73 enum axgbe_sfp_base { 74 AXGBE_SFP_BASE_UNKNOWN = 0, 75 AXGBE_SFP_BASE_1000_T, 76 AXGBE_SFP_BASE_1000_SX, 77 AXGBE_SFP_BASE_1000_LX, 78 AXGBE_SFP_BASE_1000_CX, 79 AXGBE_SFP_BASE_10000_SR, 80 AXGBE_SFP_BASE_10000_LR, 81 AXGBE_SFP_BASE_10000_LRM, 82 AXGBE_SFP_BASE_10000_ER, 83 AXGBE_SFP_BASE_10000_CR, 84 }; 85 86 enum axgbe_sfp_speed { 87 AXGBE_SFP_SPEED_UNKNOWN = 0, 88 AXGBE_SFP_SPEED_100_1000, 89 AXGBE_SFP_SPEED_1000, 90 AXGBE_SFP_SPEED_10000, 91 }; 92 93 /* SFP Serial ID Base ID values relative to an offset of 0 */ 94 #define AXGBE_SFP_BASE_ID 0 95 #define AXGBE_SFP_ID_SFP 0x03 96 97 #define AXGBE_SFP_BASE_EXT_ID 1 98 #define AXGBE_SFP_EXT_ID_SFP 0x04 99 100 #define AXGBE_SFP_BASE_10GBE_CC 3 101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 105 106 #define AXGBE_SFP_BASE_1GBE_CC 6 107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 111 112 #define AXGBE_SFP_BASE_CABLE 8 113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 115 116 #define AXGBE_SFP_BASE_BR 12 117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 121 122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 123 124 #define AXGBE_SFP_BASE_VENDOR_NAME 20 125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 126 #define AXGBE_SFP_BASE_VENDOR_PN 40 127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 128 #define AXGBE_SFP_BASE_VENDOR_REV 56 129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 130 131 #define AXGBE_SFP_BASE_CC 63 132 133 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 134 #define AXGBE_SFP_BASE_VENDOR_SN 4 135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 136 137 #define AXGBE_SFP_EXTD_DIAG 28 138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 139 140 #define AXGBE_SFP_EXTD_SFF_8472 30 141 142 #define AXGBE_SFP_EXTD_CC 31 143 144 struct axgbe_sfp_eeprom { 145 u8 base[64]; 146 u8 extd[32]; 147 u8 vendor[32]; 148 }; 149 150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 152 153 struct axgbe_sfp_ascii { 154 union { 155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 159 } u; 160 }; 161 162 /* MDIO PHY reset types */ 163 enum axgbe_mdio_reset { 164 AXGBE_MDIO_RESET_NONE = 0, 165 AXGBE_MDIO_RESET_I2C_GPIO, 166 AXGBE_MDIO_RESET_INT_GPIO, 167 AXGBE_MDIO_RESET_MAX, 168 }; 169 170 /* Re-driver related definitions */ 171 enum axgbe_phy_redrv_if { 172 AXGBE_PHY_REDRV_IF_MDIO = 0, 173 AXGBE_PHY_REDRV_IF_I2C, 174 AXGBE_PHY_REDRV_IF_MAX, 175 }; 176 177 enum axgbe_phy_redrv_model { 178 AXGBE_PHY_REDRV_MODEL_4223 = 0, 179 AXGBE_PHY_REDRV_MODEL_4227, 180 AXGBE_PHY_REDRV_MODEL_MAX, 181 }; 182 183 enum axgbe_phy_redrv_mode { 184 AXGBE_PHY_REDRV_MODE_CX = 5, 185 AXGBE_PHY_REDRV_MODE_SR = 9, 186 }; 187 188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 189 190 /* PHY related configuration information */ 191 struct axgbe_phy_data { 192 enum axgbe_port_mode port_mode; 193 194 unsigned int port_id; 195 196 unsigned int port_speeds; 197 198 enum axgbe_conn_type conn_type; 199 200 enum axgbe_mode cur_mode; 201 enum axgbe_mode start_mode; 202 203 unsigned int rrc_count; 204 205 unsigned int mdio_addr; 206 207 unsigned int comm_owned; 208 209 /* SFP Support */ 210 enum axgbe_sfp_comm sfp_comm; 211 unsigned int sfp_mux_address; 212 unsigned int sfp_mux_channel; 213 214 unsigned int sfp_gpio_address; 215 unsigned int sfp_gpio_mask; 216 unsigned int sfp_gpio_rx_los; 217 unsigned int sfp_gpio_tx_fault; 218 unsigned int sfp_gpio_mod_absent; 219 unsigned int sfp_gpio_rate_select; 220 221 unsigned int sfp_rx_los; 222 unsigned int sfp_tx_fault; 223 unsigned int sfp_mod_absent; 224 unsigned int sfp_diags; 225 unsigned int sfp_changed; 226 unsigned int sfp_phy_avail; 227 unsigned int sfp_cable_len; 228 enum axgbe_sfp_base sfp_base; 229 enum axgbe_sfp_cable sfp_cable; 230 enum axgbe_sfp_speed sfp_speed; 231 struct axgbe_sfp_eeprom sfp_eeprom; 232 233 /* External PHY support */ 234 enum axgbe_mdio_mode phydev_mode; 235 enum axgbe_mdio_reset mdio_reset; 236 unsigned int mdio_reset_addr; 237 unsigned int mdio_reset_gpio; 238 239 /* Re-driver support */ 240 unsigned int redrv; 241 unsigned int redrv_if; 242 unsigned int redrv_addr; 243 unsigned int redrv_lane; 244 unsigned int redrv_model; 245 246 /* KR AN support */ 247 unsigned int phy_cdr_notrack; 248 unsigned int phy_cdr_delay; 249 }; 250 251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 252 253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 254 struct axgbe_i2c_op *i2c_op) 255 { 256 struct axgbe_phy_data *phy_data = pdata->phy_data; 257 258 /* Be sure we own the bus */ 259 if (!phy_data->comm_owned) 260 return -EIO; 261 262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 263 } 264 265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 266 unsigned int val) 267 { 268 struct axgbe_phy_data *phy_data = pdata->phy_data; 269 struct axgbe_i2c_op i2c_op; 270 uint16_t *redrv_val; 271 u8 redrv_data[5], csum; 272 unsigned int i, retry; 273 int ret; 274 275 /* High byte of register contains read/write indicator */ 276 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 277 redrv_data[1] = reg & 0xff; 278 redrv_val = (uint16_t *)&redrv_data[2]; 279 *redrv_val = rte_cpu_to_be_16(val); 280 281 /* Calculate 1 byte checksum */ 282 csum = 0; 283 for (i = 0; i < 4; i++) { 284 csum += redrv_data[i]; 285 if (redrv_data[i] > csum) 286 csum++; 287 } 288 redrv_data[4] = ~csum; 289 290 retry = 1; 291 again1: 292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 293 i2c_op.target = phy_data->redrv_addr; 294 i2c_op.len = sizeof(redrv_data); 295 i2c_op.buf = redrv_data; 296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 297 if (ret) { 298 if ((ret == -EAGAIN) && retry--) 299 goto again1; 300 301 return ret; 302 } 303 304 retry = 1; 305 again2: 306 i2c_op.cmd = AXGBE_I2C_CMD_READ; 307 i2c_op.target = phy_data->redrv_addr; 308 i2c_op.len = 1; 309 i2c_op.buf = redrv_data; 310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 311 if (ret) { 312 if ((ret == -EAGAIN) && retry--) 313 goto again2; 314 315 return ret; 316 } 317 318 if (redrv_data[0] != 0xff) { 319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 320 ret = -EIO; 321 } 322 323 return ret; 324 } 325 326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 327 void *reg, unsigned int reg_len, 328 void *val, unsigned int val_len) 329 { 330 struct axgbe_i2c_op i2c_op; 331 int retry, ret; 332 333 retry = 1; 334 again1: 335 /* Set the specified register to read */ 336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 337 i2c_op.target = target; 338 i2c_op.len = reg_len; 339 i2c_op.buf = reg; 340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 341 if (ret) { 342 if ((ret == -EAGAIN) && retry--) 343 goto again1; 344 345 return ret; 346 } 347 348 retry = 1; 349 again2: 350 /* Read the specfied register */ 351 i2c_op.cmd = AXGBE_I2C_CMD_READ; 352 i2c_op.target = target; 353 i2c_op.len = val_len; 354 i2c_op.buf = val; 355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 356 if ((ret == -EAGAIN) && retry--) 357 goto again2; 358 359 return ret; 360 } 361 362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 363 { 364 struct axgbe_phy_data *phy_data = pdata->phy_data; 365 struct axgbe_i2c_op i2c_op; 366 uint8_t mux_channel; 367 368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 369 return 0; 370 371 /* Select no mux channels */ 372 mux_channel = 0; 373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 374 i2c_op.target = phy_data->sfp_mux_address; 375 i2c_op.len = sizeof(mux_channel); 376 i2c_op.buf = &mux_channel; 377 378 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 379 } 380 381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 382 { 383 struct axgbe_phy_data *phy_data = pdata->phy_data; 384 struct axgbe_i2c_op i2c_op; 385 u8 mux_channel; 386 387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 388 return 0; 389 390 /* Select desired mux channel */ 391 mux_channel = 1 << phy_data->sfp_mux_channel; 392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 393 i2c_op.target = phy_data->sfp_mux_address; 394 i2c_op.len = sizeof(mux_channel); 395 i2c_op.buf = &mux_channel; 396 397 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 398 } 399 400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 401 { 402 struct axgbe_phy_data *phy_data = pdata->phy_data; 403 404 phy_data->comm_owned = 0; 405 406 pthread_mutex_unlock(&pdata->phy_mutex); 407 } 408 409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 410 { 411 struct axgbe_phy_data *phy_data = pdata->phy_data; 412 uint64_t timeout; 413 unsigned int mutex_id; 414 415 if (phy_data->comm_owned) 416 return 0; 417 418 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 419 * the driver needs to take the software mutex and then the hardware 420 * mutexes before being able to use the busses. 421 */ 422 pthread_mutex_lock(&pdata->phy_mutex); 423 424 /* Clear the mutexes */ 425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 427 428 /* Mutex formats are the same for I2C and MDIO/GPIO */ 429 mutex_id = 0; 430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 432 433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 434 while (time_before(rte_get_timer_cycles(), timeout)) { 435 /* Must be all zeroes in order to obtain the mutex */ 436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 438 rte_delay_us(100); 439 continue; 440 } 441 442 /* Obtain the mutex */ 443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 445 446 phy_data->comm_owned = 1; 447 return 0; 448 } 449 450 pthread_mutex_unlock(&pdata->phy_mutex); 451 452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 453 454 return -ETIMEDOUT; 455 } 456 457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 458 { 459 struct axgbe_phy_data *phy_data = pdata->phy_data; 460 461 if (phy_data->sfp_mod_absent) { 462 pdata->phy.speed = SPEED_UNKNOWN; 463 pdata->phy.duplex = DUPLEX_UNKNOWN; 464 pdata->phy.autoneg = AUTONEG_ENABLE; 465 pdata->phy.advertising = pdata->phy.supported; 466 } 467 468 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 469 pdata->phy.advertising &= ~ADVERTISED_TP; 470 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 475 476 switch (phy_data->sfp_base) { 477 case AXGBE_SFP_BASE_1000_T: 478 case AXGBE_SFP_BASE_1000_SX: 479 case AXGBE_SFP_BASE_1000_LX: 480 case AXGBE_SFP_BASE_1000_CX: 481 pdata->phy.speed = SPEED_UNKNOWN; 482 pdata->phy.duplex = DUPLEX_UNKNOWN; 483 pdata->phy.autoneg = AUTONEG_ENABLE; 484 pdata->phy.advertising |= ADVERTISED_Autoneg; 485 break; 486 case AXGBE_SFP_BASE_10000_SR: 487 case AXGBE_SFP_BASE_10000_LR: 488 case AXGBE_SFP_BASE_10000_LRM: 489 case AXGBE_SFP_BASE_10000_ER: 490 case AXGBE_SFP_BASE_10000_CR: 491 default: 492 pdata->phy.speed = SPEED_10000; 493 pdata->phy.duplex = DUPLEX_FULL; 494 pdata->phy.autoneg = AUTONEG_DISABLE; 495 break; 496 } 497 498 switch (phy_data->sfp_base) { 499 case AXGBE_SFP_BASE_1000_T: 500 case AXGBE_SFP_BASE_1000_CX: 501 case AXGBE_SFP_BASE_10000_CR: 502 pdata->phy.advertising |= ADVERTISED_TP; 503 break; 504 default: 505 pdata->phy.advertising |= ADVERTISED_FIBRE; 506 } 507 508 switch (phy_data->sfp_speed) { 509 case AXGBE_SFP_SPEED_100_1000: 510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 511 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 514 break; 515 case AXGBE_SFP_SPEED_1000: 516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 518 break; 519 case AXGBE_SFP_SPEED_10000: 520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 522 break; 523 default: 524 /* Choose the fastest supported speed */ 525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 530 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 531 } 532 } 533 534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 535 enum axgbe_sfp_speed sfp_speed) 536 { 537 u8 *sfp_base, min, max; 538 539 sfp_base = sfp_eeprom->base; 540 541 switch (sfp_speed) { 542 case AXGBE_SFP_SPEED_1000: 543 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 544 max = AXGBE_SFP_BASE_BR_1GBE_MAX; 545 break; 546 case AXGBE_SFP_SPEED_10000: 547 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 548 max = AXGBE_SFP_BASE_BR_10GBE_MAX; 549 break; 550 default: 551 return false; 552 } 553 554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) && 555 (sfp_base[AXGBE_SFP_BASE_BR] <= max)); 556 } 557 558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 559 { 560 struct axgbe_phy_data *phy_data = pdata->phy_data; 561 562 if (!phy_data->sfp_changed) 563 return; 564 565 phy_data->sfp_phy_avail = 0; 566 567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 568 return; 569 } 570 571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 572 { 573 struct axgbe_phy_data *phy_data = pdata->phy_data; 574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 575 576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 578 return false; 579 580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 585 return true; 586 } 587 588 return false; 589 } 590 591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 592 { 593 if (axgbe_phy_belfuse_parse_quirks(pdata)) 594 return true; 595 596 return false; 597 } 598 599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 600 { 601 struct axgbe_phy_data *phy_data = pdata->phy_data; 602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 603 uint8_t *sfp_base; 604 605 sfp_base = sfp_eeprom->base; 606 607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 608 return; 609 610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 611 return; 612 613 if (axgbe_phy_sfp_parse_quirks(pdata)) 614 return; 615 616 /* Assume ACTIVE cable unless told it is PASSIVE */ 617 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 618 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 619 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 620 } else { 621 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 622 } 623 624 /* Determine the type of SFP */ 625 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 626 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 627 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 628 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 629 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 630 AXGBE_SFP_BASE_10GBE_CC_LRM) 631 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 632 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 633 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 634 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 635 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 636 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 637 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 638 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 639 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 640 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 641 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 642 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) && 643 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 644 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 645 646 switch (phy_data->sfp_base) { 647 case AXGBE_SFP_BASE_1000_T: 648 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 649 break; 650 case AXGBE_SFP_BASE_1000_SX: 651 case AXGBE_SFP_BASE_1000_LX: 652 case AXGBE_SFP_BASE_1000_CX: 653 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 654 break; 655 case AXGBE_SFP_BASE_10000_SR: 656 case AXGBE_SFP_BASE_10000_LR: 657 case AXGBE_SFP_BASE_10000_LRM: 658 case AXGBE_SFP_BASE_10000_ER: 659 case AXGBE_SFP_BASE_10000_CR: 660 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 661 break; 662 default: 663 break; 664 } 665 } 666 667 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 668 unsigned int len) 669 { 670 uint8_t cc; 671 672 for (cc = 0; len; buf++, len--) 673 cc += *buf; 674 675 return (cc == cc_in) ? true : false; 676 } 677 678 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 679 { 680 struct axgbe_phy_data *phy_data = pdata->phy_data; 681 struct axgbe_sfp_eeprom sfp_eeprom; 682 uint8_t eeprom_addr; 683 int ret; 684 685 ret = axgbe_phy_sfp_get_mux(pdata); 686 if (ret) { 687 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 688 return ret; 689 } 690 691 /* Read the SFP serial ID eeprom */ 692 eeprom_addr = 0; 693 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 694 &eeprom_addr, sizeof(eeprom_addr), 695 &sfp_eeprom, sizeof(sfp_eeprom)); 696 if (ret) { 697 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 698 goto put; 699 } 700 701 /* Validate the contents read */ 702 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 703 sfp_eeprom.base, 704 sizeof(sfp_eeprom.base) - 1)) { 705 ret = -EINVAL; 706 goto put; 707 } 708 709 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 710 sfp_eeprom.extd, 711 sizeof(sfp_eeprom.extd) - 1)) { 712 ret = -EINVAL; 713 goto put; 714 } 715 716 /* Check for an added or changed SFP */ 717 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 718 phy_data->sfp_changed = 1; 719 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 720 721 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) { 722 uint8_t diag_type; 723 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG]; 724 725 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 726 phy_data->sfp_diags = 1; 727 } 728 } else { 729 phy_data->sfp_changed = 0; 730 } 731 732 put: 733 axgbe_phy_sfp_put_mux(pdata); 734 735 return ret; 736 } 737 738 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 739 { 740 struct axgbe_phy_data *phy_data = pdata->phy_data; 741 unsigned int gpio_input; 742 u8 gpio_reg, gpio_ports[2]; 743 int ret; 744 745 /* Read the input port registers */ 746 gpio_reg = 0; 747 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 748 &gpio_reg, sizeof(gpio_reg), 749 gpio_ports, sizeof(gpio_ports)); 750 if (ret) { 751 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 752 return; 753 } 754 755 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 756 757 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 758 /* No GPIO, just assume the module is present for now */ 759 phy_data->sfp_mod_absent = 0; 760 } else { 761 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 762 phy_data->sfp_mod_absent = 0; 763 } 764 765 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 766 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 767 phy_data->sfp_rx_los = 1; 768 769 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 770 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 771 phy_data->sfp_tx_fault = 1; 772 } 773 774 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 775 { 776 struct axgbe_phy_data *phy_data = pdata->phy_data; 777 778 phy_data->sfp_mod_absent = 1; 779 phy_data->sfp_phy_avail = 0; 780 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 781 } 782 783 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 784 { 785 phy_data->sfp_rx_los = 0; 786 phy_data->sfp_tx_fault = 0; 787 phy_data->sfp_mod_absent = 1; 788 phy_data->sfp_diags = 0; 789 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 790 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 791 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 792 } 793 794 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 795 { 796 struct axgbe_phy_data *phy_data = pdata->phy_data; 797 int ret; 798 799 /* Reset the SFP signals and info */ 800 axgbe_phy_sfp_reset(phy_data); 801 802 ret = axgbe_phy_get_comm_ownership(pdata); 803 if (ret) 804 return; 805 806 /* Read the SFP signals and check for module presence */ 807 axgbe_phy_sfp_signals(pdata); 808 if (phy_data->sfp_mod_absent) { 809 axgbe_phy_sfp_mod_absent(pdata); 810 goto put; 811 } 812 813 ret = axgbe_phy_sfp_read_eeprom(pdata); 814 if (ret) { 815 /* Treat any error as if there isn't an SFP plugged in */ 816 axgbe_phy_sfp_reset(phy_data); 817 axgbe_phy_sfp_mod_absent(pdata); 818 goto put; 819 } 820 821 axgbe_phy_sfp_parse_eeprom(pdata); 822 axgbe_phy_sfp_external_phy(pdata); 823 824 put: 825 axgbe_phy_sfp_phy_settings(pdata); 826 axgbe_phy_put_comm_ownership(pdata); 827 } 828 829 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 830 { 831 pdata->phy.tx_pause = 0; 832 pdata->phy.rx_pause = 0; 833 } 834 835 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 836 { 837 struct axgbe_phy_data *phy_data = pdata->phy_data; 838 enum axgbe_mode mode; 839 unsigned int ad_reg, lp_reg; 840 841 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 842 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 843 844 /* Use external PHY to determine flow control */ 845 if (pdata->phy.pause_autoneg) 846 axgbe_phy_phydev_flowctrl(pdata); 847 848 /* Compare Advertisement and Link Partner register 2 */ 849 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 850 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 851 if (lp_reg & 0x80) 852 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 853 if (lp_reg & 0x20) 854 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 855 856 ad_reg &= lp_reg; 857 if (ad_reg & 0x80) { 858 switch (phy_data->port_mode) { 859 case AXGBE_PORT_MODE_BACKPLANE: 860 mode = AXGBE_MODE_KR; 861 break; 862 default: 863 mode = AXGBE_MODE_SFI; 864 break; 865 } 866 } else if (ad_reg & 0x20) { 867 switch (phy_data->port_mode) { 868 case AXGBE_PORT_MODE_BACKPLANE: 869 mode = AXGBE_MODE_KX_1000; 870 break; 871 case AXGBE_PORT_MODE_1000BASE_X: 872 mode = AXGBE_MODE_X; 873 break; 874 case AXGBE_PORT_MODE_SFP: 875 switch (phy_data->sfp_base) { 876 case AXGBE_SFP_BASE_1000_T: 877 mode = AXGBE_MODE_SGMII_1000; 878 break; 879 case AXGBE_SFP_BASE_1000_SX: 880 case AXGBE_SFP_BASE_1000_LX: 881 case AXGBE_SFP_BASE_1000_CX: 882 default: 883 mode = AXGBE_MODE_X; 884 break; 885 } 886 break; 887 default: 888 mode = AXGBE_MODE_SGMII_1000; 889 break; 890 } 891 } else { 892 mode = AXGBE_MODE_UNKNOWN; 893 } 894 895 /* Compare Advertisement and Link Partner register 3 */ 896 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 897 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 898 if (lp_reg & 0xc000) 899 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 900 901 return mode; 902 } 903 904 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 905 { 906 enum axgbe_mode mode; 907 unsigned int ad_reg, lp_reg; 908 909 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 910 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 911 912 /* Compare Advertisement and Link Partner register 1 */ 913 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 914 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 915 if (lp_reg & 0x400) 916 pdata->phy.lp_advertising |= ADVERTISED_Pause; 917 if (lp_reg & 0x800) 918 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 919 920 if (pdata->phy.pause_autoneg) { 921 /* Set flow control based on auto-negotiation result */ 922 pdata->phy.tx_pause = 0; 923 pdata->phy.rx_pause = 0; 924 925 if (ad_reg & lp_reg & 0x400) { 926 pdata->phy.tx_pause = 1; 927 pdata->phy.rx_pause = 1; 928 } else if (ad_reg & lp_reg & 0x800) { 929 if (ad_reg & 0x400) 930 pdata->phy.rx_pause = 1; 931 else if (lp_reg & 0x400) 932 pdata->phy.tx_pause = 1; 933 } 934 } 935 936 /* Compare Advertisement and Link Partner register 2 */ 937 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 938 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 939 if (lp_reg & 0x80) 940 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 941 if (lp_reg & 0x20) 942 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 943 944 ad_reg &= lp_reg; 945 if (ad_reg & 0x80) 946 mode = AXGBE_MODE_KR; 947 else if (ad_reg & 0x20) 948 mode = AXGBE_MODE_KX_1000; 949 else 950 mode = AXGBE_MODE_UNKNOWN; 951 952 /* Compare Advertisement and Link Partner register 3 */ 953 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 954 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 955 if (lp_reg & 0xc000) 956 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 957 958 return mode; 959 } 960 961 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 962 { 963 switch (pdata->an_mode) { 964 case AXGBE_AN_MODE_CL73: 965 return axgbe_phy_an73_outcome(pdata); 966 case AXGBE_AN_MODE_CL73_REDRV: 967 return axgbe_phy_an73_redrv_outcome(pdata); 968 case AXGBE_AN_MODE_CL37: 969 case AXGBE_AN_MODE_CL37_SGMII: 970 default: 971 return AXGBE_MODE_UNKNOWN; 972 } 973 } 974 975 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 976 { 977 struct axgbe_phy_data *phy_data = pdata->phy_data; 978 unsigned int advertising; 979 980 /* Without a re-driver, just return current advertising */ 981 if (!phy_data->redrv) 982 return pdata->phy.advertising; 983 984 /* With the KR re-driver we need to advertise a single speed */ 985 advertising = pdata->phy.advertising; 986 advertising &= ~ADVERTISED_1000baseKX_Full; 987 advertising &= ~ADVERTISED_10000baseKR_Full; 988 989 switch (phy_data->port_mode) { 990 case AXGBE_PORT_MODE_BACKPLANE: 991 advertising |= ADVERTISED_10000baseKR_Full; 992 break; 993 case AXGBE_PORT_MODE_BACKPLANE_2500: 994 advertising |= ADVERTISED_1000baseKX_Full; 995 break; 996 case AXGBE_PORT_MODE_1000BASE_T: 997 case AXGBE_PORT_MODE_1000BASE_X: 998 case AXGBE_PORT_MODE_NBASE_T: 999 advertising |= ADVERTISED_1000baseKX_Full; 1000 break; 1001 case AXGBE_PORT_MODE_10GBASE_T: 1002 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1003 break; 1004 case AXGBE_PORT_MODE_10GBASE_R: 1005 advertising |= ADVERTISED_10000baseKR_Full; 1006 break; 1007 case AXGBE_PORT_MODE_SFP: 1008 switch (phy_data->sfp_base) { 1009 case AXGBE_SFP_BASE_1000_T: 1010 case AXGBE_SFP_BASE_1000_SX: 1011 case AXGBE_SFP_BASE_1000_LX: 1012 case AXGBE_SFP_BASE_1000_CX: 1013 advertising |= ADVERTISED_1000baseKX_Full; 1014 break; 1015 default: 1016 advertising |= ADVERTISED_10000baseKR_Full; 1017 break; 1018 } 1019 break; 1020 default: 1021 advertising |= ADVERTISED_10000baseKR_Full; 1022 break; 1023 } 1024 1025 return advertising; 1026 } 1027 1028 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1029 { 1030 return 0; 1031 /* Dummy API since there is no case to support 1032 * external phy devices registred through kerenl apis 1033 */ 1034 } 1035 1036 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1037 { 1038 switch (phy_data->sfp_base) { 1039 case AXGBE_SFP_BASE_1000_T: 1040 return AXGBE_AN_MODE_CL37_SGMII; 1041 case AXGBE_SFP_BASE_1000_SX: 1042 case AXGBE_SFP_BASE_1000_LX: 1043 case AXGBE_SFP_BASE_1000_CX: 1044 return AXGBE_AN_MODE_CL37; 1045 default: 1046 return AXGBE_AN_MODE_NONE; 1047 } 1048 } 1049 1050 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1051 { 1052 struct axgbe_phy_data *phy_data = pdata->phy_data; 1053 1054 /* A KR re-driver will always require CL73 AN */ 1055 if (phy_data->redrv) 1056 return AXGBE_AN_MODE_CL73_REDRV; 1057 1058 switch (phy_data->port_mode) { 1059 case AXGBE_PORT_MODE_BACKPLANE: 1060 return AXGBE_AN_MODE_CL73; 1061 case AXGBE_PORT_MODE_BACKPLANE_2500: 1062 return AXGBE_AN_MODE_NONE; 1063 case AXGBE_PORT_MODE_1000BASE_T: 1064 return AXGBE_AN_MODE_CL37_SGMII; 1065 case AXGBE_PORT_MODE_1000BASE_X: 1066 return AXGBE_AN_MODE_CL37; 1067 case AXGBE_PORT_MODE_NBASE_T: 1068 return AXGBE_AN_MODE_CL37_SGMII; 1069 case AXGBE_PORT_MODE_10GBASE_T: 1070 return AXGBE_AN_MODE_CL73; 1071 case AXGBE_PORT_MODE_10GBASE_R: 1072 return AXGBE_AN_MODE_NONE; 1073 case AXGBE_PORT_MODE_SFP: 1074 return axgbe_phy_an_sfp_mode(phy_data); 1075 default: 1076 return AXGBE_AN_MODE_NONE; 1077 } 1078 } 1079 1080 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1081 enum axgbe_phy_redrv_mode mode) 1082 { 1083 struct axgbe_phy_data *phy_data = pdata->phy_data; 1084 u16 redrv_reg, redrv_val; 1085 1086 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1087 redrv_val = (u16)mode; 1088 1089 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1090 redrv_reg, redrv_val); 1091 } 1092 1093 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1094 enum axgbe_phy_redrv_mode mode) 1095 { 1096 struct axgbe_phy_data *phy_data = pdata->phy_data; 1097 unsigned int redrv_reg; 1098 int ret; 1099 1100 /* Calculate the register to write */ 1101 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1102 1103 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1104 1105 return ret; 1106 } 1107 1108 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1109 { 1110 struct axgbe_phy_data *phy_data = pdata->phy_data; 1111 enum axgbe_phy_redrv_mode mode; 1112 int ret; 1113 1114 if (!phy_data->redrv) 1115 return; 1116 1117 mode = AXGBE_PHY_REDRV_MODE_CX; 1118 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1119 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1120 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1121 mode = AXGBE_PHY_REDRV_MODE_SR; 1122 1123 ret = axgbe_phy_get_comm_ownership(pdata); 1124 if (ret) 1125 return; 1126 1127 if (phy_data->redrv_if) 1128 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1129 else 1130 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1131 1132 axgbe_phy_put_comm_ownership(pdata); 1133 } 1134 1135 static void axgbe_phy_start_ratechange(struct axgbe_port *pdata) 1136 { 1137 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1138 return; 1139 } 1140 1141 static void axgbe_phy_complete_ratechange(struct axgbe_port *pdata) 1142 { 1143 unsigned int wait; 1144 1145 /* Wait for command to complete */ 1146 wait = AXGBE_RATECHANGE_COUNT; 1147 while (wait--) { 1148 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1149 return; 1150 1151 rte_delay_us(1500); 1152 } 1153 } 1154 1155 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1156 { 1157 unsigned int s0; 1158 1159 axgbe_phy_start_ratechange(pdata); 1160 1161 /* Receiver Reset Cycle */ 1162 s0 = 0; 1163 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 5); 1164 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1165 1166 /* Call FW to make the change */ 1167 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1168 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1169 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1170 1171 axgbe_phy_complete_ratechange(pdata); 1172 } 1173 1174 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1175 { 1176 struct axgbe_phy_data *phy_data = pdata->phy_data; 1177 1178 axgbe_phy_start_ratechange(pdata); 1179 1180 /* Call FW to make the change */ 1181 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, 0); 1182 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1183 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1184 axgbe_phy_complete_ratechange(pdata); 1185 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1186 } 1187 1188 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1189 { 1190 struct axgbe_phy_data *phy_data = pdata->phy_data; 1191 unsigned int s0; 1192 1193 axgbe_phy_set_redrv_mode(pdata); 1194 1195 axgbe_phy_start_ratechange(pdata); 1196 1197 /* 10G/SFI */ 1198 s0 = 0; 1199 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 3); 1200 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1201 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1202 } else { 1203 if (phy_data->sfp_cable_len <= 1) 1204 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 1); 1205 else if (phy_data->sfp_cable_len <= 3) 1206 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 2); 1207 else 1208 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 3); 1209 } 1210 1211 /* Call FW to make the change */ 1212 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1213 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1214 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1215 axgbe_phy_complete_ratechange(pdata); 1216 phy_data->cur_mode = AXGBE_MODE_SFI; 1217 } 1218 1219 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1220 { 1221 struct axgbe_phy_data *phy_data = pdata->phy_data; 1222 unsigned int s0; 1223 1224 axgbe_phy_set_redrv_mode(pdata); 1225 1226 axgbe_phy_start_ratechange(pdata); 1227 1228 /* 10G/KR */ 1229 s0 = 0; 1230 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, 4); 1231 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, 0); 1232 1233 /* Call FW to make the change */ 1234 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1235 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1236 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1237 axgbe_phy_complete_ratechange(pdata); 1238 phy_data->cur_mode = AXGBE_MODE_KR; 1239 } 1240 1241 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1242 { 1243 struct axgbe_phy_data *phy_data = pdata->phy_data; 1244 1245 return phy_data->cur_mode; 1246 } 1247 1248 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1249 { 1250 struct axgbe_phy_data *phy_data = pdata->phy_data; 1251 1252 /* No switching if not 10GBase-T */ 1253 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1254 return axgbe_phy_cur_mode(pdata); 1255 1256 switch (axgbe_phy_cur_mode(pdata)) { 1257 case AXGBE_MODE_SGMII_100: 1258 case AXGBE_MODE_SGMII_1000: 1259 return AXGBE_MODE_KR; 1260 case AXGBE_MODE_KR: 1261 default: 1262 return AXGBE_MODE_SGMII_1000; 1263 } 1264 } 1265 1266 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1267 __rte_unused) 1268 { 1269 return AXGBE_MODE_KX_2500; 1270 } 1271 1272 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1273 { 1274 /* If we are in KR switch to KX, and vice-versa */ 1275 switch (axgbe_phy_cur_mode(pdata)) { 1276 case AXGBE_MODE_KX_1000: 1277 return AXGBE_MODE_KR; 1278 case AXGBE_MODE_KR: 1279 default: 1280 return AXGBE_MODE_KX_1000; 1281 } 1282 } 1283 1284 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1285 { 1286 struct axgbe_phy_data *phy_data = pdata->phy_data; 1287 1288 switch (phy_data->port_mode) { 1289 case AXGBE_PORT_MODE_BACKPLANE: 1290 return axgbe_phy_switch_bp_mode(pdata); 1291 case AXGBE_PORT_MODE_BACKPLANE_2500: 1292 return axgbe_phy_switch_bp_2500_mode(pdata); 1293 case AXGBE_PORT_MODE_1000BASE_T: 1294 case AXGBE_PORT_MODE_NBASE_T: 1295 case AXGBE_PORT_MODE_10GBASE_T: 1296 return axgbe_phy_switch_baset_mode(pdata); 1297 case AXGBE_PORT_MODE_1000BASE_X: 1298 case AXGBE_PORT_MODE_10GBASE_R: 1299 case AXGBE_PORT_MODE_SFP: 1300 /* No switching, so just return current mode */ 1301 return axgbe_phy_cur_mode(pdata); 1302 default: 1303 return AXGBE_MODE_UNKNOWN; 1304 } 1305 } 1306 1307 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1308 __rte_unused, 1309 int speed) 1310 { 1311 switch (speed) { 1312 case SPEED_1000: 1313 return AXGBE_MODE_X; 1314 case SPEED_10000: 1315 return AXGBE_MODE_KR; 1316 default: 1317 return AXGBE_MODE_UNKNOWN; 1318 } 1319 } 1320 1321 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1322 __rte_unused, 1323 int speed) 1324 { 1325 switch (speed) { 1326 case SPEED_100: 1327 return AXGBE_MODE_SGMII_100; 1328 case SPEED_1000: 1329 return AXGBE_MODE_SGMII_1000; 1330 case SPEED_10000: 1331 return AXGBE_MODE_KR; 1332 default: 1333 return AXGBE_MODE_UNKNOWN; 1334 } 1335 } 1336 1337 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1338 int speed) 1339 { 1340 switch (speed) { 1341 case SPEED_100: 1342 return AXGBE_MODE_SGMII_100; 1343 case SPEED_1000: 1344 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1345 return AXGBE_MODE_SGMII_1000; 1346 else 1347 return AXGBE_MODE_X; 1348 case SPEED_10000: 1349 case SPEED_UNKNOWN: 1350 return AXGBE_MODE_SFI; 1351 default: 1352 return AXGBE_MODE_UNKNOWN; 1353 } 1354 } 1355 1356 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1357 { 1358 switch (speed) { 1359 case SPEED_2500: 1360 return AXGBE_MODE_KX_2500; 1361 default: 1362 return AXGBE_MODE_UNKNOWN; 1363 } 1364 } 1365 1366 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1367 { 1368 switch (speed) { 1369 case SPEED_1000: 1370 return AXGBE_MODE_KX_1000; 1371 case SPEED_10000: 1372 return AXGBE_MODE_KR; 1373 default: 1374 return AXGBE_MODE_UNKNOWN; 1375 } 1376 } 1377 1378 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1379 int speed) 1380 { 1381 struct axgbe_phy_data *phy_data = pdata->phy_data; 1382 1383 switch (phy_data->port_mode) { 1384 case AXGBE_PORT_MODE_BACKPLANE: 1385 return axgbe_phy_get_bp_mode(speed); 1386 case AXGBE_PORT_MODE_BACKPLANE_2500: 1387 return axgbe_phy_get_bp_2500_mode(speed); 1388 case AXGBE_PORT_MODE_1000BASE_T: 1389 case AXGBE_PORT_MODE_NBASE_T: 1390 case AXGBE_PORT_MODE_10GBASE_T: 1391 return axgbe_phy_get_baset_mode(phy_data, speed); 1392 case AXGBE_PORT_MODE_1000BASE_X: 1393 case AXGBE_PORT_MODE_10GBASE_R: 1394 return axgbe_phy_get_basex_mode(phy_data, speed); 1395 case AXGBE_PORT_MODE_SFP: 1396 return axgbe_phy_get_sfp_mode(phy_data, speed); 1397 default: 1398 return AXGBE_MODE_UNKNOWN; 1399 } 1400 } 1401 1402 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1403 { 1404 switch (mode) { 1405 case AXGBE_MODE_KR: 1406 axgbe_phy_kr_mode(pdata); 1407 break; 1408 case AXGBE_MODE_SFI: 1409 axgbe_phy_sfi_mode(pdata); 1410 break; 1411 default: 1412 break; 1413 } 1414 } 1415 1416 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1417 enum axgbe_mode mode, u32 advert) 1418 { 1419 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1420 if (pdata->phy.advertising & advert) 1421 return true; 1422 } else { 1423 enum axgbe_mode cur_mode; 1424 1425 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1426 if (cur_mode == mode) 1427 return true; 1428 } 1429 1430 return false; 1431 } 1432 1433 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1434 enum axgbe_mode mode) 1435 { 1436 switch (mode) { 1437 case AXGBE_MODE_X: 1438 return axgbe_phy_check_mode(pdata, mode, 1439 ADVERTISED_1000baseT_Full); 1440 case AXGBE_MODE_KR: 1441 return axgbe_phy_check_mode(pdata, mode, 1442 ADVERTISED_10000baseT_Full); 1443 default: 1444 return false; 1445 } 1446 } 1447 1448 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1449 enum axgbe_mode mode) 1450 { 1451 switch (mode) { 1452 case AXGBE_MODE_SGMII_100: 1453 return axgbe_phy_check_mode(pdata, mode, 1454 ADVERTISED_100baseT_Full); 1455 case AXGBE_MODE_SGMII_1000: 1456 return axgbe_phy_check_mode(pdata, mode, 1457 ADVERTISED_1000baseT_Full); 1458 case AXGBE_MODE_KR: 1459 return axgbe_phy_check_mode(pdata, mode, 1460 ADVERTISED_10000baseT_Full); 1461 default: 1462 return false; 1463 } 1464 } 1465 1466 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1467 enum axgbe_mode mode) 1468 { 1469 struct axgbe_phy_data *phy_data = pdata->phy_data; 1470 1471 switch (mode) { 1472 case AXGBE_MODE_X: 1473 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1474 return false; 1475 return axgbe_phy_check_mode(pdata, mode, 1476 ADVERTISED_1000baseT_Full); 1477 case AXGBE_MODE_SGMII_100: 1478 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1479 return false; 1480 return axgbe_phy_check_mode(pdata, mode, 1481 ADVERTISED_100baseT_Full); 1482 case AXGBE_MODE_SGMII_1000: 1483 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1484 return false; 1485 return axgbe_phy_check_mode(pdata, mode, 1486 ADVERTISED_1000baseT_Full); 1487 case AXGBE_MODE_SFI: 1488 return axgbe_phy_check_mode(pdata, mode, 1489 ADVERTISED_10000baseT_Full); 1490 default: 1491 return false; 1492 } 1493 } 1494 1495 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1496 enum axgbe_mode mode) 1497 { 1498 switch (mode) { 1499 case AXGBE_MODE_KX_2500: 1500 return axgbe_phy_check_mode(pdata, mode, 1501 ADVERTISED_2500baseX_Full); 1502 default: 1503 return false; 1504 } 1505 } 1506 1507 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1508 enum axgbe_mode mode) 1509 { 1510 switch (mode) { 1511 case AXGBE_MODE_KX_1000: 1512 return axgbe_phy_check_mode(pdata, mode, 1513 ADVERTISED_1000baseKX_Full); 1514 case AXGBE_MODE_KR: 1515 return axgbe_phy_check_mode(pdata, mode, 1516 ADVERTISED_10000baseKR_Full); 1517 default: 1518 return false; 1519 } 1520 } 1521 1522 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1523 { 1524 struct axgbe_phy_data *phy_data = pdata->phy_data; 1525 1526 switch (phy_data->port_mode) { 1527 case AXGBE_PORT_MODE_BACKPLANE: 1528 return axgbe_phy_use_bp_mode(pdata, mode); 1529 case AXGBE_PORT_MODE_BACKPLANE_2500: 1530 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1531 case AXGBE_PORT_MODE_1000BASE_T: 1532 case AXGBE_PORT_MODE_NBASE_T: 1533 case AXGBE_PORT_MODE_10GBASE_T: 1534 return axgbe_phy_use_baset_mode(pdata, mode); 1535 case AXGBE_PORT_MODE_1000BASE_X: 1536 case AXGBE_PORT_MODE_10GBASE_R: 1537 return axgbe_phy_use_basex_mode(pdata, mode); 1538 case AXGBE_PORT_MODE_SFP: 1539 return axgbe_phy_use_sfp_mode(pdata, mode); 1540 default: 1541 return false; 1542 } 1543 } 1544 1545 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1546 { 1547 struct axgbe_phy_data *phy_data = pdata->phy_data; 1548 unsigned int reg; 1549 1550 *an_restart = 0; 1551 1552 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1553 /* Check SFP signals */ 1554 axgbe_phy_sfp_detect(pdata); 1555 1556 if (phy_data->sfp_changed) { 1557 *an_restart = 1; 1558 return 0; 1559 } 1560 1561 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1562 return 0; 1563 } 1564 1565 /* Link status is latched low, so read once to clear 1566 * and then read again to get current state 1567 */ 1568 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1569 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1570 if (reg & MDIO_STAT1_LSTATUS) 1571 return 1; 1572 1573 /* No link, attempt a receiver reset cycle */ 1574 if (phy_data->rrc_count++) { 1575 phy_data->rrc_count = 0; 1576 axgbe_phy_rrc(pdata); 1577 } 1578 1579 return 0; 1580 } 1581 1582 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1583 { 1584 struct axgbe_phy_data *phy_data = pdata->phy_data; 1585 unsigned int reg; 1586 1587 reg = XP_IOREAD(pdata, XP_PROP_3); 1588 1589 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1590 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 1591 1592 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 1593 1594 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 1595 GPIO_RX_LOS); 1596 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 1597 GPIO_TX_FAULT); 1598 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 1599 GPIO_MOD_ABS); 1600 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 1601 GPIO_RATE_SELECT); 1602 } 1603 1604 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1605 { 1606 struct axgbe_phy_data *phy_data = pdata->phy_data; 1607 unsigned int reg, mux_addr_hi, mux_addr_lo; 1608 1609 reg = XP_IOREAD(pdata, XP_PROP_4); 1610 1611 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 1612 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 1613 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1614 return; 1615 1616 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1617 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1618 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 1619 } 1620 1621 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1622 { 1623 axgbe_phy_sfp_comm_setup(pdata); 1624 axgbe_phy_sfp_gpio_setup(pdata); 1625 } 1626 1627 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1628 { 1629 if (!phy_data->redrv) 1630 return false; 1631 1632 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1633 return true; 1634 1635 switch (phy_data->redrv_model) { 1636 case AXGBE_PHY_REDRV_MODEL_4223: 1637 if (phy_data->redrv_lane > 3) 1638 return true; 1639 break; 1640 case AXGBE_PHY_REDRV_MODEL_4227: 1641 if (phy_data->redrv_lane > 1) 1642 return true; 1643 break; 1644 default: 1645 return true; 1646 } 1647 1648 return false; 1649 } 1650 1651 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1652 { 1653 struct axgbe_phy_data *phy_data = pdata->phy_data; 1654 unsigned int reg; 1655 1656 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1657 return 0; 1658 reg = XP_IOREAD(pdata, XP_PROP_3); 1659 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 1660 switch (phy_data->mdio_reset) { 1661 case AXGBE_MDIO_RESET_NONE: 1662 case AXGBE_MDIO_RESET_I2C_GPIO: 1663 case AXGBE_MDIO_RESET_INT_GPIO: 1664 break; 1665 default: 1666 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1667 phy_data->mdio_reset); 1668 return -EINVAL; 1669 } 1670 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1671 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1672 XP_GET_BITS(reg, XP_PROP_3, 1673 MDIO_RESET_I2C_ADDR); 1674 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1675 MDIO_RESET_I2C_GPIO); 1676 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1677 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1678 MDIO_RESET_INT_GPIO); 1679 } 1680 1681 return 0; 1682 } 1683 1684 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1685 { 1686 struct axgbe_phy_data *phy_data = pdata->phy_data; 1687 1688 switch (phy_data->port_mode) { 1689 case AXGBE_PORT_MODE_BACKPLANE: 1690 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1691 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1692 return false; 1693 break; 1694 case AXGBE_PORT_MODE_BACKPLANE_2500: 1695 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1696 return false; 1697 break; 1698 case AXGBE_PORT_MODE_1000BASE_T: 1699 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1700 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1701 return false; 1702 break; 1703 case AXGBE_PORT_MODE_1000BASE_X: 1704 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1705 return false; 1706 break; 1707 case AXGBE_PORT_MODE_NBASE_T: 1708 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1709 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1710 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1711 return false; 1712 break; 1713 case AXGBE_PORT_MODE_10GBASE_T: 1714 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1715 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1716 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1717 return false; 1718 break; 1719 case AXGBE_PORT_MODE_10GBASE_R: 1720 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1721 return false; 1722 break; 1723 case AXGBE_PORT_MODE_SFP: 1724 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1725 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1726 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1727 return false; 1728 break; 1729 default: 1730 break; 1731 } 1732 1733 return true; 1734 } 1735 1736 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1737 { 1738 struct axgbe_phy_data *phy_data = pdata->phy_data; 1739 1740 switch (phy_data->port_mode) { 1741 case AXGBE_PORT_MODE_BACKPLANE: 1742 case AXGBE_PORT_MODE_BACKPLANE_2500: 1743 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1744 return false; 1745 break; 1746 case AXGBE_PORT_MODE_1000BASE_T: 1747 case AXGBE_PORT_MODE_1000BASE_X: 1748 case AXGBE_PORT_MODE_NBASE_T: 1749 case AXGBE_PORT_MODE_10GBASE_T: 1750 case AXGBE_PORT_MODE_10GBASE_R: 1751 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1752 return false; 1753 break; 1754 case AXGBE_PORT_MODE_SFP: 1755 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1756 return false; 1757 break; 1758 default: 1759 break; 1760 } 1761 1762 return true; 1763 } 1764 1765 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1766 { 1767 unsigned int reg; 1768 1769 reg = XP_IOREAD(pdata, XP_PROP_0); 1770 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 1771 return false; 1772 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 1773 return false; 1774 1775 return true; 1776 } 1777 1778 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1779 { 1780 struct axgbe_phy_data *phy_data = pdata->phy_data; 1781 1782 if (!pdata->vdata->an_cdr_workaround) 1783 return; 1784 1785 if (!phy_data->phy_cdr_notrack) 1786 return; 1787 1788 rte_delay_us(phy_data->phy_cdr_delay + 400); 1789 1790 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1791 AXGBE_PMA_CDR_TRACK_EN_MASK, 1792 AXGBE_PMA_CDR_TRACK_EN_ON); 1793 1794 phy_data->phy_cdr_notrack = 0; 1795 } 1796 1797 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1798 { 1799 struct axgbe_phy_data *phy_data = pdata->phy_data; 1800 1801 if (!pdata->vdata->an_cdr_workaround) 1802 return; 1803 1804 if (phy_data->phy_cdr_notrack) 1805 return; 1806 1807 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1808 AXGBE_PMA_CDR_TRACK_EN_MASK, 1809 AXGBE_PMA_CDR_TRACK_EN_OFF); 1810 1811 axgbe_phy_rrc(pdata); 1812 1813 phy_data->phy_cdr_notrack = 1; 1814 } 1815 1816 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1817 { 1818 if (!pdata->cdr_track_early) 1819 axgbe_phy_cdr_track(pdata); 1820 } 1821 1822 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1823 { 1824 if (pdata->cdr_track_early) 1825 axgbe_phy_cdr_track(pdata); 1826 } 1827 1828 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1829 { 1830 struct axgbe_phy_data *phy_data = pdata->phy_data; 1831 1832 switch (pdata->an_mode) { 1833 case AXGBE_AN_MODE_CL73: 1834 case AXGBE_AN_MODE_CL73_REDRV: 1835 if (phy_data->cur_mode != AXGBE_MODE_KR) 1836 break; 1837 1838 axgbe_phy_cdr_track(pdata); 1839 1840 switch (pdata->an_result) { 1841 case AXGBE_AN_READY: 1842 case AXGBE_AN_COMPLETE: 1843 break; 1844 default: 1845 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1846 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1847 break; 1848 } 1849 break; 1850 default: 1851 break; 1852 } 1853 } 1854 1855 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1856 { 1857 struct axgbe_phy_data *phy_data = pdata->phy_data; 1858 1859 switch (pdata->an_mode) { 1860 case AXGBE_AN_MODE_CL73: 1861 case AXGBE_AN_MODE_CL73_REDRV: 1862 if (phy_data->cur_mode != AXGBE_MODE_KR) 1863 break; 1864 1865 axgbe_phy_cdr_notrack(pdata); 1866 break; 1867 default: 1868 break; 1869 } 1870 } 1871 1872 static void axgbe_phy_stop(struct axgbe_port *pdata) 1873 { 1874 struct axgbe_phy_data *phy_data = pdata->phy_data; 1875 1876 /* Reset SFP data */ 1877 axgbe_phy_sfp_reset(phy_data); 1878 axgbe_phy_sfp_mod_absent(pdata); 1879 1880 /* Reset CDR support */ 1881 axgbe_phy_cdr_track(pdata); 1882 1883 /* Power off the PHY */ 1884 axgbe_phy_power_off(pdata); 1885 1886 /* Stop the I2C controller */ 1887 pdata->i2c_if.i2c_stop(pdata); 1888 } 1889 1890 static int axgbe_phy_start(struct axgbe_port *pdata) 1891 { 1892 struct axgbe_phy_data *phy_data = pdata->phy_data; 1893 int ret; 1894 1895 /* Start the I2C controller */ 1896 ret = pdata->i2c_if.i2c_start(pdata); 1897 if (ret) 1898 return ret; 1899 1900 /* Start in highest supported mode */ 1901 axgbe_phy_set_mode(pdata, phy_data->start_mode); 1902 1903 /* Reset CDR support */ 1904 axgbe_phy_cdr_track(pdata); 1905 1906 /* After starting the I2C controller, we can check for an SFP */ 1907 switch (phy_data->port_mode) { 1908 case AXGBE_PORT_MODE_SFP: 1909 axgbe_phy_sfp_detect(pdata); 1910 break; 1911 default: 1912 break; 1913 } 1914 1915 return ret; 1916 } 1917 1918 static int axgbe_phy_reset(struct axgbe_port *pdata) 1919 { 1920 struct axgbe_phy_data *phy_data = pdata->phy_data; 1921 enum axgbe_mode cur_mode; 1922 1923 /* Reset by power cycling the PHY */ 1924 cur_mode = phy_data->cur_mode; 1925 axgbe_phy_power_off(pdata); 1926 /* First time reset is done with passed unknown mode*/ 1927 axgbe_phy_set_mode(pdata, cur_mode); 1928 return 0; 1929 } 1930 1931 static int axgbe_phy_init(struct axgbe_port *pdata) 1932 { 1933 struct axgbe_phy_data *phy_data; 1934 unsigned int reg; 1935 int ret; 1936 1937 /* Check if enabled */ 1938 if (!axgbe_phy_port_enabled(pdata)) { 1939 PMD_DRV_LOG(ERR, "device is not enabled\n"); 1940 return -ENODEV; 1941 } 1942 1943 /* Initialize the I2C controller */ 1944 ret = pdata->i2c_if.i2c_init(pdata); 1945 if (ret) 1946 return ret; 1947 1948 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 1949 if (!phy_data) { 1950 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 1951 return -ENOMEM; 1952 } 1953 pdata->phy_data = phy_data; 1954 1955 reg = XP_IOREAD(pdata, XP_PROP_0); 1956 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 1957 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 1958 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 1959 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 1960 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 1961 1962 reg = XP_IOREAD(pdata, XP_PROP_4); 1963 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 1964 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 1965 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 1966 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 1967 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 1968 1969 /* Validate the connection requested */ 1970 if (axgbe_phy_conn_type_mismatch(pdata)) { 1971 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 1972 phy_data->port_mode, phy_data->conn_type); 1973 return -EINVAL; 1974 } 1975 1976 /* Validate the mode requested */ 1977 if (axgbe_phy_port_mode_mismatch(pdata)) { 1978 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 1979 phy_data->port_mode, phy_data->port_speeds); 1980 return -EINVAL; 1981 } 1982 1983 /* Check for and validate MDIO reset support */ 1984 ret = axgbe_phy_mdio_reset_setup(pdata); 1985 if (ret) 1986 return ret; 1987 1988 /* Validate the re-driver information */ 1989 if (axgbe_phy_redrv_error(phy_data)) { 1990 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 1991 return -EINVAL; 1992 } 1993 pdata->kr_redrv = phy_data->redrv; 1994 1995 /* Indicate current mode is unknown */ 1996 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1997 1998 /* Initialize supported features */ 1999 pdata->phy.supported = 0; 2000 2001 switch (phy_data->port_mode) { 2002 /* Backplane support */ 2003 case AXGBE_PORT_MODE_BACKPLANE: 2004 pdata->phy.supported |= SUPPORTED_Autoneg; 2005 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2006 pdata->phy.supported |= SUPPORTED_Backplane; 2007 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2008 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2009 phy_data->start_mode = AXGBE_MODE_KX_1000; 2010 } 2011 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2012 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2013 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2014 pdata->phy.supported |= 2015 SUPPORTED_10000baseR_FEC; 2016 phy_data->start_mode = AXGBE_MODE_KR; 2017 } 2018 2019 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2020 break; 2021 case AXGBE_PORT_MODE_BACKPLANE_2500: 2022 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2023 pdata->phy.supported |= SUPPORTED_Backplane; 2024 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2025 phy_data->start_mode = AXGBE_MODE_KX_2500; 2026 2027 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2028 break; 2029 2030 /* MDIO 1GBase-T support */ 2031 case AXGBE_PORT_MODE_1000BASE_T: 2032 pdata->phy.supported |= SUPPORTED_Autoneg; 2033 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2034 pdata->phy.supported |= SUPPORTED_TP; 2035 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2036 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2037 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2038 } 2039 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2040 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2041 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2042 } 2043 2044 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2045 break; 2046 2047 /* MDIO Base-X support */ 2048 case AXGBE_PORT_MODE_1000BASE_X: 2049 pdata->phy.supported |= SUPPORTED_Autoneg; 2050 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2051 pdata->phy.supported |= SUPPORTED_FIBRE; 2052 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2053 phy_data->start_mode = AXGBE_MODE_X; 2054 2055 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2056 break; 2057 2058 /* MDIO NBase-T support */ 2059 case AXGBE_PORT_MODE_NBASE_T: 2060 pdata->phy.supported |= SUPPORTED_Autoneg; 2061 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2062 pdata->phy.supported |= SUPPORTED_TP; 2063 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2064 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2065 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2066 } 2067 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2068 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2069 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2070 } 2071 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2072 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2073 phy_data->start_mode = AXGBE_MODE_KX_2500; 2074 } 2075 2076 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2077 break; 2078 2079 /* 10GBase-T support */ 2080 case AXGBE_PORT_MODE_10GBASE_T: 2081 pdata->phy.supported |= SUPPORTED_Autoneg; 2082 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2083 pdata->phy.supported |= SUPPORTED_TP; 2084 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2085 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2086 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2087 } 2088 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2089 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2090 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2091 } 2092 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2093 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2094 phy_data->start_mode = AXGBE_MODE_KR; 2095 } 2096 2097 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2098 break; 2099 2100 /* 10GBase-R support */ 2101 case AXGBE_PORT_MODE_10GBASE_R: 2102 pdata->phy.supported |= SUPPORTED_Autoneg; 2103 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2104 pdata->phy.supported |= SUPPORTED_TP; 2105 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2106 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2107 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2108 phy_data->start_mode = AXGBE_MODE_SFI; 2109 2110 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2111 break; 2112 2113 /* SFP support */ 2114 case AXGBE_PORT_MODE_SFP: 2115 pdata->phy.supported |= SUPPORTED_Autoneg; 2116 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2117 pdata->phy.supported |= SUPPORTED_TP; 2118 pdata->phy.supported |= SUPPORTED_FIBRE; 2119 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2120 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2121 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2122 } 2123 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2124 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2125 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2126 } 2127 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2128 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2129 phy_data->start_mode = AXGBE_MODE_SFI; 2130 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2131 pdata->phy.supported |= 2132 SUPPORTED_10000baseR_FEC; 2133 } 2134 2135 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2136 2137 axgbe_phy_sfp_setup(pdata); 2138 break; 2139 default: 2140 return -EINVAL; 2141 } 2142 2143 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2144 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2145 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2146 phy_data->phydev_mode); 2147 if (ret) { 2148 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2149 phy_data->mdio_addr, phy_data->phydev_mode); 2150 return -EINVAL; 2151 } 2152 } 2153 2154 if (phy_data->redrv && !phy_data->redrv_if) { 2155 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2156 AXGBE_MDIO_MODE_CL22); 2157 if (ret) { 2158 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2159 phy_data->redrv_addr); 2160 return -EINVAL; 2161 } 2162 } 2163 2164 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2165 return 0; 2166 } 2167 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2168 { 2169 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2170 2171 phy_impl->init = axgbe_phy_init; 2172 phy_impl->reset = axgbe_phy_reset; 2173 phy_impl->start = axgbe_phy_start; 2174 phy_impl->stop = axgbe_phy_stop; 2175 phy_impl->link_status = axgbe_phy_link_status; 2176 phy_impl->use_mode = axgbe_phy_use_mode; 2177 phy_impl->set_mode = axgbe_phy_set_mode; 2178 phy_impl->get_mode = axgbe_phy_get_mode; 2179 phy_impl->switch_mode = axgbe_phy_switch_mode; 2180 phy_impl->cur_mode = axgbe_phy_cur_mode; 2181 phy_impl->an_mode = axgbe_phy_an_mode; 2182 phy_impl->an_config = axgbe_phy_an_config; 2183 phy_impl->an_advertising = axgbe_phy_an_advertising; 2184 phy_impl->an_outcome = axgbe_phy_an_outcome; 2185 2186 phy_impl->an_pre = axgbe_phy_an_pre; 2187 phy_impl->an_post = axgbe_phy_an_post; 2188 2189 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2190 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2191 } 2192