1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_10 BIT(0) 11 #define AXGBE_PHY_PORT_SPEED_100 BIT(1) 12 #define AXGBE_PHY_PORT_SPEED_1000 BIT(2) 13 #define AXGBE_PHY_PORT_SPEED_2500 BIT(3) 14 #define AXGBE_PHY_PORT_SPEED_10000 BIT(4) 15 16 #define AXGBE_MUTEX_RELEASE 0x80000000 17 18 #define AXGBE_SFP_DIRECT 7 19 20 /* I2C target addresses */ 21 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 22 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 23 #define AXGBE_SFP_PHY_ADDRESS 0x56 24 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 25 26 /* SFP sideband signal indicators */ 27 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 28 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 29 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 30 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 31 32 /* Rate-change complete wait/retry count */ 33 #define AXGBE_RATECHANGE_COUNT 500 34 35 /* CDR delay values for KR support (in usec) */ 36 #define AXGBE_CDR_DELAY_INIT 10000 37 #define AXGBE_CDR_DELAY_INC 10000 38 #define AXGBE_CDR_DELAY_MAX 100000 39 40 enum axgbe_port_mode { 41 AXGBE_PORT_MODE_RSVD = 0, 42 AXGBE_PORT_MODE_BACKPLANE, 43 AXGBE_PORT_MODE_BACKPLANE_2500, 44 AXGBE_PORT_MODE_1000BASE_T, 45 AXGBE_PORT_MODE_1000BASE_X, 46 AXGBE_PORT_MODE_NBASE_T, 47 AXGBE_PORT_MODE_10GBASE_T, 48 AXGBE_PORT_MODE_10GBASE_R, 49 AXGBE_PORT_MODE_SFP, 50 AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 51 AXGBE_PORT_MODE_MAX, 52 }; 53 54 enum axgbe_conn_type { 55 AXGBE_CONN_TYPE_NONE = 0, 56 AXGBE_CONN_TYPE_SFP, 57 AXGBE_CONN_TYPE_MDIO, 58 AXGBE_CONN_TYPE_RSVD1, 59 AXGBE_CONN_TYPE_BACKPLANE, 60 AXGBE_CONN_TYPE_MAX, 61 }; 62 63 /* SFP/SFP+ related definitions */ 64 enum axgbe_sfp_comm { 65 AXGBE_SFP_COMM_DIRECT = 0, 66 AXGBE_SFP_COMM_PCA9545, 67 }; 68 69 enum axgbe_sfp_cable { 70 AXGBE_SFP_CABLE_UNKNOWN = 0, 71 AXGBE_SFP_CABLE_ACTIVE, 72 AXGBE_SFP_CABLE_PASSIVE, 73 AXGBE_SFP_CABLE_FIBER, 74 }; 75 76 enum axgbe_sfp_base { 77 AXGBE_SFP_BASE_UNKNOWN = 0, 78 AXGBE_SFP_BASE_1000_T, 79 AXGBE_SFP_BASE_1000_SX, 80 AXGBE_SFP_BASE_1000_LX, 81 AXGBE_SFP_BASE_1000_CX, 82 AXGBE_SFP_BASE_10000_SR, 83 AXGBE_SFP_BASE_10000_LR, 84 AXGBE_SFP_BASE_10000_LRM, 85 AXGBE_SFP_BASE_10000_ER, 86 AXGBE_SFP_BASE_10000_CR, 87 }; 88 89 enum axgbe_sfp_speed { 90 AXGBE_SFP_SPEED_UNKNOWN = 0, 91 AXGBE_SFP_SPEED_100_1000, 92 AXGBE_SFP_SPEED_1000, 93 AXGBE_SFP_SPEED_10000, 94 }; 95 96 /* SFP Serial ID Base ID values relative to an offset of 0 */ 97 #define AXGBE_SFP_BASE_ID 0 98 #define AXGBE_SFP_ID_SFP 0x03 99 100 #define AXGBE_SFP_BASE_EXT_ID 1 101 #define AXGBE_SFP_EXT_ID_SFP 0x04 102 103 #define AXGBE_SFP_BASE_10GBE_CC 3 104 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 105 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 106 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 107 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 108 109 #define AXGBE_SFP_BASE_1GBE_CC 6 110 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 111 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 112 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 113 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 114 115 #define AXGBE_SFP_BASE_CABLE 8 116 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 117 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 118 119 #define AXGBE_SFP_BASE_BR 12 120 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 121 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 122 123 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 124 125 #define AXGBE_SFP_BASE_VENDOR_NAME 20 126 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 127 #define AXGBE_SFP_BASE_VENDOR_PN 40 128 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 129 #define AXGBE_SFP_BASE_VENDOR_REV 56 130 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 131 132 #define AXGBE_SFP_BASE_CC 63 133 134 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 135 #define AXGBE_SFP_BASE_VENDOR_SN 4 136 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 137 138 #define AXGBE_SFP_EXTD_DIAG 28 139 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 140 141 #define AXGBE_SFP_EXTD_SFF_8472 30 142 143 #define AXGBE_SFP_EXTD_CC 31 144 145 struct axgbe_sfp_eeprom { 146 u8 base[64]; 147 u8 extd[32]; 148 u8 vendor[32]; 149 }; 150 151 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 152 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 153 154 struct axgbe_sfp_ascii { 155 union { 156 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 157 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 158 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 159 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 160 } u; 161 }; 162 163 /* MDIO PHY reset types */ 164 enum axgbe_mdio_reset { 165 AXGBE_MDIO_RESET_NONE = 0, 166 AXGBE_MDIO_RESET_I2C_GPIO, 167 AXGBE_MDIO_RESET_INT_GPIO, 168 AXGBE_MDIO_RESET_MAX, 169 }; 170 171 /* Re-driver related definitions */ 172 enum axgbe_phy_redrv_if { 173 AXGBE_PHY_REDRV_IF_MDIO = 0, 174 AXGBE_PHY_REDRV_IF_I2C, 175 AXGBE_PHY_REDRV_IF_MAX, 176 }; 177 178 enum axgbe_phy_redrv_model { 179 AXGBE_PHY_REDRV_MODEL_4223 = 0, 180 AXGBE_PHY_REDRV_MODEL_4227, 181 AXGBE_PHY_REDRV_MODEL_MAX, 182 }; 183 184 enum axgbe_phy_redrv_mode { 185 AXGBE_PHY_REDRV_MODE_CX = 5, 186 AXGBE_PHY_REDRV_MODE_SR = 9, 187 }; 188 189 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 190 191 /* PHY related configuration information */ 192 struct axgbe_phy_data { 193 enum axgbe_port_mode port_mode; 194 195 unsigned int port_id; 196 197 unsigned int port_speeds; 198 199 enum axgbe_conn_type conn_type; 200 201 enum axgbe_mode cur_mode; 202 enum axgbe_mode start_mode; 203 204 unsigned int rrc_count; 205 206 unsigned int mdio_addr; 207 208 /* SFP Support */ 209 enum axgbe_sfp_comm sfp_comm; 210 unsigned int sfp_mux_address; 211 unsigned int sfp_mux_channel; 212 213 unsigned int sfp_gpio_address; 214 unsigned int sfp_gpio_mask; 215 unsigned int sfp_gpio_rx_los; 216 unsigned int sfp_gpio_tx_fault; 217 unsigned int sfp_gpio_mod_absent; 218 unsigned int sfp_gpio_rate_select; 219 220 unsigned int sfp_rx_los; 221 unsigned int sfp_tx_fault; 222 unsigned int sfp_mod_absent; 223 unsigned int sfp_changed; 224 unsigned int sfp_phy_avail; 225 unsigned int sfp_cable_len; 226 enum axgbe_sfp_base sfp_base; 227 enum axgbe_sfp_cable sfp_cable; 228 enum axgbe_sfp_speed sfp_speed; 229 struct axgbe_sfp_eeprom sfp_eeprom; 230 231 /* External PHY support */ 232 enum axgbe_mdio_mode phydev_mode; 233 enum axgbe_mdio_reset mdio_reset; 234 unsigned int mdio_reset_addr; 235 unsigned int mdio_reset_gpio; 236 237 /* Re-driver support */ 238 unsigned int redrv; 239 unsigned int redrv_if; 240 unsigned int redrv_addr; 241 unsigned int redrv_lane; 242 unsigned int redrv_model; 243 244 /* KR AN support */ 245 unsigned int phy_cdr_notrack; 246 unsigned int phy_cdr_delay; 247 }; 248 249 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 250 251 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 252 struct axgbe_i2c_op *i2c_op) 253 { 254 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 255 } 256 257 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 258 unsigned int val) 259 { 260 struct axgbe_phy_data *phy_data = pdata->phy_data; 261 struct axgbe_i2c_op i2c_op; 262 uint16_t *redrv_val; 263 u8 redrv_data[5], csum; 264 unsigned int i, retry; 265 int ret; 266 267 /* High byte of register contains read/write indicator */ 268 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 269 redrv_data[1] = reg & 0xff; 270 redrv_val = (uint16_t *)&redrv_data[2]; 271 *redrv_val = rte_cpu_to_be_16(val); 272 273 /* Calculate 1 byte checksum */ 274 csum = 0; 275 for (i = 0; i < 4; i++) { 276 csum += redrv_data[i]; 277 if (redrv_data[i] > csum) 278 csum++; 279 } 280 redrv_data[4] = ~csum; 281 282 retry = 1; 283 again1: 284 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 285 i2c_op.target = phy_data->redrv_addr; 286 i2c_op.len = sizeof(redrv_data); 287 i2c_op.buf = redrv_data; 288 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 289 if (ret) { 290 if ((ret == -EAGAIN) && retry--) 291 goto again1; 292 293 return ret; 294 } 295 296 retry = 1; 297 again2: 298 i2c_op.cmd = AXGBE_I2C_CMD_READ; 299 i2c_op.target = phy_data->redrv_addr; 300 i2c_op.len = 1; 301 i2c_op.buf = redrv_data; 302 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 303 if (ret) { 304 if ((ret == -EAGAIN) && retry--) 305 goto again2; 306 307 return ret; 308 } 309 310 if (redrv_data[0] != 0xff) { 311 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 312 ret = -EIO; 313 } 314 315 return ret; 316 } 317 318 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 319 void *reg, unsigned int reg_len, 320 void *val, unsigned int val_len) 321 { 322 struct axgbe_i2c_op i2c_op; 323 int retry, ret; 324 325 retry = 1; 326 again1: 327 /* Set the specified register to read */ 328 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 329 i2c_op.target = target; 330 i2c_op.len = reg_len; 331 i2c_op.buf = reg; 332 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 333 if (ret) { 334 if ((ret == -EAGAIN) && retry--) 335 goto again1; 336 337 return ret; 338 } 339 340 retry = 1; 341 again2: 342 /* Read the specified register */ 343 i2c_op.cmd = AXGBE_I2C_CMD_READ; 344 i2c_op.target = target; 345 i2c_op.len = val_len; 346 i2c_op.buf = val; 347 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 348 if ((ret == -EAGAIN) && retry--) 349 goto again2; 350 351 return ret; 352 } 353 354 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 355 { 356 struct axgbe_phy_data *phy_data = pdata->phy_data; 357 struct axgbe_i2c_op i2c_op; 358 uint8_t mux_channel; 359 360 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 361 return 0; 362 363 /* Select no mux channels */ 364 mux_channel = 0; 365 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 366 i2c_op.target = phy_data->sfp_mux_address; 367 i2c_op.len = sizeof(mux_channel); 368 i2c_op.buf = &mux_channel; 369 370 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 371 } 372 373 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 374 { 375 struct axgbe_phy_data *phy_data = pdata->phy_data; 376 struct axgbe_i2c_op i2c_op; 377 u8 mux_channel; 378 379 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 380 return 0; 381 382 /* Select desired mux channel */ 383 mux_channel = 1 << phy_data->sfp_mux_channel; 384 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 385 i2c_op.target = phy_data->sfp_mux_address; 386 i2c_op.len = sizeof(mux_channel); 387 i2c_op.buf = &mux_channel; 388 389 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 390 } 391 392 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 393 { 394 pthread_mutex_unlock(&pdata->phy_mutex); 395 } 396 397 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 398 { 399 struct axgbe_phy_data *phy_data = pdata->phy_data; 400 uint64_t timeout; 401 unsigned int mutex_id; 402 403 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 404 * the driver needs to take the software mutex and then the hardware 405 * mutexes before being able to use the busses. 406 */ 407 pthread_mutex_lock(&pdata->phy_mutex); 408 409 /* Clear the mutexes */ 410 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 411 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 412 413 /* Mutex formats are the same for I2C and MDIO/GPIO */ 414 mutex_id = 0; 415 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 416 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 417 418 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 419 while (time_before(rte_get_timer_cycles(), timeout)) { 420 /* Must be all zeroes in order to obtain the mutex */ 421 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 422 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 423 rte_delay_us(100); 424 continue; 425 } 426 427 /* Obtain the mutex */ 428 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 429 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 430 431 return 0; 432 } 433 434 pthread_mutex_unlock(&pdata->phy_mutex); 435 436 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 437 438 return -ETIMEDOUT; 439 } 440 441 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 442 { 443 struct axgbe_phy_data *phy_data = pdata->phy_data; 444 445 if (phy_data->sfp_mod_absent) { 446 pdata->phy.speed = SPEED_UNKNOWN; 447 pdata->phy.duplex = DUPLEX_UNKNOWN; 448 pdata->phy.autoneg = AUTONEG_ENABLE; 449 pdata->phy.advertising = pdata->phy.supported; 450 } 451 452 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 453 pdata->phy.advertising &= ~ADVERTISED_TP; 454 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 455 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 456 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 457 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 458 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 459 460 switch (phy_data->sfp_base) { 461 case AXGBE_SFP_BASE_1000_T: 462 case AXGBE_SFP_BASE_1000_SX: 463 case AXGBE_SFP_BASE_1000_LX: 464 case AXGBE_SFP_BASE_1000_CX: 465 pdata->phy.speed = SPEED_UNKNOWN; 466 pdata->phy.duplex = DUPLEX_UNKNOWN; 467 pdata->phy.autoneg = AUTONEG_ENABLE; 468 pdata->phy.advertising |= ADVERTISED_Autoneg; 469 break; 470 case AXGBE_SFP_BASE_10000_SR: 471 case AXGBE_SFP_BASE_10000_LR: 472 case AXGBE_SFP_BASE_10000_LRM: 473 case AXGBE_SFP_BASE_10000_ER: 474 case AXGBE_SFP_BASE_10000_CR: 475 default: 476 pdata->phy.speed = SPEED_10000; 477 pdata->phy.duplex = DUPLEX_FULL; 478 pdata->phy.autoneg = AUTONEG_DISABLE; 479 break; 480 } 481 482 switch (phy_data->sfp_base) { 483 case AXGBE_SFP_BASE_1000_T: 484 case AXGBE_SFP_BASE_1000_CX: 485 case AXGBE_SFP_BASE_10000_CR: 486 pdata->phy.advertising |= ADVERTISED_TP; 487 break; 488 default: 489 pdata->phy.advertising |= ADVERTISED_FIBRE; 490 } 491 492 switch (phy_data->sfp_speed) { 493 case AXGBE_SFP_SPEED_100_1000: 494 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) 495 pdata->phy.advertising |= ADVERTISED_10baseT_Full; 496 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 497 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 498 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 499 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 500 break; 501 case AXGBE_SFP_SPEED_1000: 502 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 503 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 504 break; 505 case AXGBE_SFP_SPEED_10000: 506 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 507 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 508 break; 509 default: 510 /* Choose the fastest supported speed */ 511 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 512 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 513 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 514 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 515 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 516 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 517 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) 518 pdata->phy.advertising |= ADVERTISED_10baseT_Full; 519 } 520 } 521 522 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 523 enum axgbe_sfp_speed sfp_speed) 524 { 525 u8 *sfp_base, min; 526 527 sfp_base = sfp_eeprom->base; 528 529 switch (sfp_speed) { 530 case AXGBE_SFP_SPEED_1000: 531 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 532 break; 533 case AXGBE_SFP_SPEED_10000: 534 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 535 break; 536 default: 537 return false; 538 } 539 540 return sfp_base[AXGBE_SFP_BASE_BR] >= min; 541 } 542 543 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 544 { 545 struct axgbe_phy_data *phy_data = pdata->phy_data; 546 547 if (!phy_data->sfp_changed) 548 return; 549 550 phy_data->sfp_phy_avail = 0; 551 552 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 553 return; 554 } 555 556 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 557 { 558 struct axgbe_phy_data *phy_data = pdata->phy_data; 559 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 560 561 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 562 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 563 return false; 564 /* For Bel-Fuse, use the extra AN flag */ 565 pdata->an_again = 1; 566 567 /* Reset PHY - wait for self-clearing reset bit to clear */ 568 pdata->phy_if.phy_impl.reset(pdata); 569 570 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 571 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 572 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 573 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 574 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 575 return true; 576 } 577 578 return false; 579 } 580 581 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 582 { 583 if (axgbe_phy_belfuse_parse_quirks(pdata)) 584 return true; 585 586 return false; 587 } 588 589 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 590 { 591 struct axgbe_phy_data *phy_data = pdata->phy_data; 592 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 593 uint8_t *sfp_base; 594 595 sfp_base = sfp_eeprom->base; 596 597 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 598 return; 599 600 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 601 return; 602 603 axgbe_phy_sfp_parse_quirks(pdata); 604 605 /* Assume FIBER cable unless told otherwise */ 606 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 607 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 608 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 609 } else if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_ACTIVE) { 610 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 611 } else { 612 phy_data->sfp_cable = AXGBE_SFP_CABLE_FIBER; 613 } 614 615 /* Determine the type of SFP */ 616 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_FIBER && 617 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 618 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 619 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 620 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 621 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 622 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 623 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 624 AXGBE_SFP_BASE_10GBE_CC_LRM) 625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 628 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 629 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 630 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 631 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 632 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 633 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 634 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 635 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 636 637 switch (phy_data->sfp_base) { 638 case AXGBE_SFP_BASE_1000_T: 639 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 640 break; 641 case AXGBE_SFP_BASE_1000_SX: 642 case AXGBE_SFP_BASE_1000_LX: 643 case AXGBE_SFP_BASE_1000_CX: 644 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 645 break; 646 case AXGBE_SFP_BASE_10000_SR: 647 case AXGBE_SFP_BASE_10000_LR: 648 case AXGBE_SFP_BASE_10000_LRM: 649 case AXGBE_SFP_BASE_10000_ER: 650 case AXGBE_SFP_BASE_10000_CR: 651 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 652 break; 653 default: 654 break; 655 } 656 } 657 658 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 659 unsigned int len) 660 { 661 uint8_t cc; 662 663 for (cc = 0; len; buf++, len--) 664 cc += *buf; 665 666 return cc == cc_in; 667 } 668 669 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 670 { 671 struct axgbe_phy_data *phy_data = pdata->phy_data; 672 struct axgbe_sfp_eeprom sfp_eeprom; 673 uint8_t eeprom_addr; 674 int ret; 675 676 ret = axgbe_phy_sfp_get_mux(pdata); 677 if (ret) { 678 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 679 return ret; 680 } 681 682 /* Read the SFP serial ID eeprom */ 683 eeprom_addr = 0; 684 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 685 &eeprom_addr, sizeof(eeprom_addr), 686 &sfp_eeprom, sizeof(sfp_eeprom)); 687 if (ret) { 688 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 689 goto put; 690 } 691 692 /* Validate the contents read */ 693 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 694 sfp_eeprom.base, 695 sizeof(sfp_eeprom.base) - 1)) { 696 ret = -EINVAL; 697 goto put; 698 } 699 700 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 701 sfp_eeprom.extd, 702 sizeof(sfp_eeprom.extd) - 1)) { 703 ret = -EINVAL; 704 goto put; 705 } 706 707 /* Check for an added or changed SFP */ 708 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 709 phy_data->sfp_changed = 1; 710 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 711 } else { 712 phy_data->sfp_changed = 0; 713 } 714 715 put: 716 axgbe_phy_sfp_put_mux(pdata); 717 718 return ret; 719 } 720 721 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 722 { 723 struct axgbe_phy_data *phy_data = pdata->phy_data; 724 unsigned int gpio_input; 725 u8 gpio_reg, gpio_ports[2]; 726 int ret; 727 728 /* Read the input port registers */ 729 gpio_reg = 0; 730 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 731 &gpio_reg, sizeof(gpio_reg), 732 gpio_ports, sizeof(gpio_ports)); 733 if (ret) { 734 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 735 return; 736 } 737 738 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 739 740 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 741 /* No GPIO, just assume the module is present for now */ 742 phy_data->sfp_mod_absent = 0; 743 } else { 744 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 745 phy_data->sfp_mod_absent = 0; 746 } 747 748 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 749 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 750 phy_data->sfp_rx_los = 1; 751 752 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 753 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 754 phy_data->sfp_tx_fault = 1; 755 } 756 757 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 758 { 759 struct axgbe_phy_data *phy_data = pdata->phy_data; 760 761 phy_data->sfp_mod_absent = 1; 762 phy_data->sfp_phy_avail = 0; 763 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 764 } 765 766 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 767 { 768 phy_data->sfp_rx_los = 0; 769 phy_data->sfp_tx_fault = 0; 770 phy_data->sfp_mod_absent = 1; 771 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 772 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 773 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 774 } 775 776 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base) 777 { 778 switch (sfp_base) { 779 case AXGBE_SFP_BASE_1000_T: 780 return "1G_T"; 781 case AXGBE_SFP_BASE_1000_SX: 782 return "1G_SX"; 783 case AXGBE_SFP_BASE_1000_LX: 784 return "1G_LX"; 785 case AXGBE_SFP_BASE_1000_CX: 786 return "1G_CX"; 787 case AXGBE_SFP_BASE_10000_SR: 788 return "10G_SR"; 789 case AXGBE_SFP_BASE_10000_LR: 790 return "10G_LR"; 791 case AXGBE_SFP_BASE_10000_LRM: 792 return "10G_LRM"; 793 case AXGBE_SFP_BASE_10000_ER: 794 return "10G_ER"; 795 case AXGBE_SFP_BASE_10000_CR: 796 return "10G_CR"; 797 default: 798 return "Unknown"; 799 } 800 } 801 802 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 803 { 804 struct axgbe_phy_data *phy_data = pdata->phy_data; 805 int ret; 806 807 /* Clear the extra AN flag */ 808 pdata->an_again = 0; 809 810 /* Reset the SFP signals and info */ 811 axgbe_phy_sfp_reset(phy_data); 812 813 ret = axgbe_phy_get_comm_ownership(pdata); 814 if (ret) 815 return; 816 817 /* Read the SFP signals and check for module presence */ 818 axgbe_phy_sfp_signals(pdata); 819 if (phy_data->sfp_mod_absent) { 820 axgbe_phy_sfp_mod_absent(pdata); 821 goto put; 822 } 823 824 ret = axgbe_phy_sfp_read_eeprom(pdata); 825 if (ret) { 826 /* Treat any error as if there isn't an SFP plugged in */ 827 axgbe_phy_sfp_reset(phy_data); 828 axgbe_phy_sfp_mod_absent(pdata); 829 goto put; 830 } 831 832 axgbe_phy_sfp_parse_eeprom(pdata); 833 axgbe_phy_sfp_external_phy(pdata); 834 835 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n", 836 axgbe_base_as_string(phy_data->sfp_base)); 837 838 put: 839 axgbe_phy_sfp_phy_settings(pdata); 840 axgbe_phy_put_comm_ownership(pdata); 841 } 842 843 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 844 { 845 pdata->phy.tx_pause = 0; 846 pdata->phy.rx_pause = 0; 847 } 848 849 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 850 { 851 struct axgbe_phy_data *phy_data = pdata->phy_data; 852 enum axgbe_mode mode; 853 unsigned int ad_reg, lp_reg; 854 855 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 856 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 857 858 /* Use external PHY to determine flow control */ 859 if (pdata->phy.pause_autoneg) 860 axgbe_phy_phydev_flowctrl(pdata); 861 862 /* Compare Advertisement and Link Partner register 2 */ 863 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 864 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 865 if (lp_reg & 0x80) 866 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 867 if (lp_reg & 0x20) 868 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 869 870 ad_reg &= lp_reg; 871 if (ad_reg & 0x80) { 872 switch (phy_data->port_mode) { 873 case AXGBE_PORT_MODE_BACKPLANE: 874 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 875 mode = AXGBE_MODE_KR; 876 break; 877 default: 878 mode = AXGBE_MODE_SFI; 879 break; 880 } 881 } else if (ad_reg & 0x20) { 882 switch (phy_data->port_mode) { 883 case AXGBE_PORT_MODE_BACKPLANE: 884 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 885 mode = AXGBE_MODE_KX_1000; 886 break; 887 case AXGBE_PORT_MODE_1000BASE_X: 888 mode = AXGBE_MODE_X; 889 break; 890 case AXGBE_PORT_MODE_SFP: 891 switch (phy_data->sfp_base) { 892 case AXGBE_SFP_BASE_1000_T: 893 mode = AXGBE_MODE_SGMII_1000; 894 break; 895 case AXGBE_SFP_BASE_1000_SX: 896 case AXGBE_SFP_BASE_1000_LX: 897 case AXGBE_SFP_BASE_1000_CX: 898 default: 899 mode = AXGBE_MODE_X; 900 break; 901 } 902 break; 903 default: 904 mode = AXGBE_MODE_SGMII_1000; 905 break; 906 } 907 } else { 908 mode = AXGBE_MODE_UNKNOWN; 909 } 910 911 /* Compare Advertisement and Link Partner register 3 */ 912 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 913 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 914 if (lp_reg & 0xc000) 915 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 916 917 return mode; 918 } 919 920 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 921 { 922 enum axgbe_mode mode; 923 unsigned int ad_reg, lp_reg; 924 925 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 926 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 927 928 /* Compare Advertisement and Link Partner register 1 */ 929 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 930 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 931 if (lp_reg & 0x400) 932 pdata->phy.lp_advertising |= ADVERTISED_Pause; 933 if (lp_reg & 0x800) 934 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 935 936 if (pdata->phy.pause_autoneg) { 937 /* Set flow control based on auto-negotiation result */ 938 pdata->phy.tx_pause = 0; 939 pdata->phy.rx_pause = 0; 940 941 if (ad_reg & lp_reg & 0x400) { 942 pdata->phy.tx_pause = 1; 943 pdata->phy.rx_pause = 1; 944 } else if (ad_reg & lp_reg & 0x800) { 945 if (ad_reg & 0x400) 946 pdata->phy.rx_pause = 1; 947 else if (lp_reg & 0x400) 948 pdata->phy.tx_pause = 1; 949 } 950 } 951 952 /* Compare Advertisement and Link Partner register 2 */ 953 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 954 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 955 if (lp_reg & 0x80) 956 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 957 if (lp_reg & 0x20) 958 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 959 960 ad_reg &= lp_reg; 961 if (ad_reg & 0x80) 962 mode = AXGBE_MODE_KR; 963 else if (ad_reg & 0x20) 964 mode = AXGBE_MODE_KX_1000; 965 else 966 mode = AXGBE_MODE_UNKNOWN; 967 968 /* Compare Advertisement and Link Partner register 3 */ 969 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 970 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 971 if (lp_reg & 0xc000) 972 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 973 974 return mode; 975 } 976 977 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 978 { 979 enum axgbe_mode mode; 980 981 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 982 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 983 984 if (pdata->phy.pause_autoneg) 985 axgbe_phy_phydev_flowctrl(pdata); 986 987 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 988 case AXGBE_SGMII_AN_LINK_SPEED_10: 989 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 990 pdata->phy.lp_advertising |= ADVERTISED_10baseT_Full; 991 mode = AXGBE_MODE_SGMII_10; 992 } else { 993 mode = AXGBE_MODE_UNKNOWN; 994 } 995 break; 996 case AXGBE_SGMII_AN_LINK_SPEED_100: 997 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 998 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 999 mode = AXGBE_MODE_SGMII_100; 1000 } else { 1001 mode = AXGBE_MODE_UNKNOWN; 1002 } 1003 break; 1004 case AXGBE_SGMII_AN_LINK_SPEED_1000: 1005 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1006 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1007 mode = AXGBE_MODE_SGMII_1000; 1008 } else { 1009 /* Half-duplex not supported */ 1010 mode = AXGBE_MODE_UNKNOWN; 1011 } 1012 break; 1013 default: 1014 mode = AXGBE_MODE_UNKNOWN; 1015 break; 1016 } 1017 return mode; 1018 } 1019 1020 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 1021 { 1022 switch (pdata->an_mode) { 1023 case AXGBE_AN_MODE_CL73: 1024 return axgbe_phy_an73_outcome(pdata); 1025 case AXGBE_AN_MODE_CL73_REDRV: 1026 return axgbe_phy_an73_redrv_outcome(pdata); 1027 case AXGBE_AN_MODE_CL37: 1028 case AXGBE_AN_MODE_CL37_SGMII: 1029 return axgbe_phy_an37_sgmii_outcome(pdata); 1030 default: 1031 return AXGBE_MODE_UNKNOWN; 1032 } 1033 } 1034 1035 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1036 { 1037 struct axgbe_phy_data *phy_data = pdata->phy_data; 1038 unsigned int advertising; 1039 1040 /* Without a re-driver, just return current advertising */ 1041 if (!phy_data->redrv) 1042 return pdata->phy.advertising; 1043 1044 /* With the KR re-driver we need to advertise a single speed */ 1045 advertising = pdata->phy.advertising; 1046 advertising &= ~ADVERTISED_1000baseKX_Full; 1047 advertising &= ~ADVERTISED_10000baseKR_Full; 1048 1049 switch (phy_data->port_mode) { 1050 case AXGBE_PORT_MODE_BACKPLANE: 1051 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1052 advertising |= ADVERTISED_10000baseKR_Full; 1053 break; 1054 case AXGBE_PORT_MODE_BACKPLANE_2500: 1055 advertising |= ADVERTISED_1000baseKX_Full; 1056 break; 1057 case AXGBE_PORT_MODE_1000BASE_T: 1058 case AXGBE_PORT_MODE_1000BASE_X: 1059 case AXGBE_PORT_MODE_NBASE_T: 1060 advertising |= ADVERTISED_1000baseKX_Full; 1061 break; 1062 case AXGBE_PORT_MODE_10GBASE_T: 1063 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1064 break; 1065 case AXGBE_PORT_MODE_10GBASE_R: 1066 advertising |= ADVERTISED_10000baseKR_Full; 1067 break; 1068 case AXGBE_PORT_MODE_SFP: 1069 switch (phy_data->sfp_base) { 1070 case AXGBE_SFP_BASE_1000_T: 1071 case AXGBE_SFP_BASE_1000_SX: 1072 case AXGBE_SFP_BASE_1000_LX: 1073 case AXGBE_SFP_BASE_1000_CX: 1074 advertising |= ADVERTISED_1000baseKX_Full; 1075 break; 1076 default: 1077 advertising |= ADVERTISED_10000baseKR_Full; 1078 break; 1079 } 1080 break; 1081 default: 1082 advertising |= ADVERTISED_10000baseKR_Full; 1083 break; 1084 } 1085 1086 return advertising; 1087 } 1088 1089 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1090 { 1091 return 0; 1092 /* Dummy API since there is no case to support 1093 * external phy devices registered through kernel APIs 1094 */ 1095 } 1096 1097 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1098 { 1099 switch (phy_data->sfp_base) { 1100 case AXGBE_SFP_BASE_1000_T: 1101 return AXGBE_AN_MODE_CL37_SGMII; 1102 case AXGBE_SFP_BASE_1000_SX: 1103 case AXGBE_SFP_BASE_1000_LX: 1104 case AXGBE_SFP_BASE_1000_CX: 1105 return AXGBE_AN_MODE_CL37; 1106 default: 1107 return AXGBE_AN_MODE_NONE; 1108 } 1109 } 1110 1111 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1112 { 1113 struct axgbe_phy_data *phy_data = pdata->phy_data; 1114 1115 /* A KR re-driver will always require CL73 AN */ 1116 if (phy_data->redrv) 1117 return AXGBE_AN_MODE_CL73_REDRV; 1118 1119 switch (phy_data->port_mode) { 1120 case AXGBE_PORT_MODE_BACKPLANE: 1121 return AXGBE_AN_MODE_CL73; 1122 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1123 case AXGBE_PORT_MODE_BACKPLANE_2500: 1124 return AXGBE_AN_MODE_NONE; 1125 case AXGBE_PORT_MODE_1000BASE_T: 1126 return AXGBE_AN_MODE_CL37_SGMII; 1127 case AXGBE_PORT_MODE_1000BASE_X: 1128 return AXGBE_AN_MODE_CL37; 1129 case AXGBE_PORT_MODE_NBASE_T: 1130 return AXGBE_AN_MODE_CL37_SGMII; 1131 case AXGBE_PORT_MODE_10GBASE_T: 1132 return AXGBE_AN_MODE_CL73; 1133 case AXGBE_PORT_MODE_10GBASE_R: 1134 return AXGBE_AN_MODE_NONE; 1135 case AXGBE_PORT_MODE_SFP: 1136 return axgbe_phy_an_sfp_mode(phy_data); 1137 default: 1138 return AXGBE_AN_MODE_NONE; 1139 } 1140 } 1141 1142 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1143 enum axgbe_phy_redrv_mode mode) 1144 { 1145 struct axgbe_phy_data *phy_data = pdata->phy_data; 1146 u16 redrv_reg, redrv_val; 1147 1148 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1149 redrv_val = (u16)mode; 1150 1151 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1152 redrv_reg, redrv_val); 1153 } 1154 1155 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1156 enum axgbe_phy_redrv_mode mode) 1157 { 1158 struct axgbe_phy_data *phy_data = pdata->phy_data; 1159 unsigned int redrv_reg; 1160 int ret; 1161 1162 /* Calculate the register to write */ 1163 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1164 1165 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1166 1167 return ret; 1168 } 1169 1170 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1171 { 1172 struct axgbe_phy_data *phy_data = pdata->phy_data; 1173 enum axgbe_phy_redrv_mode mode; 1174 int ret; 1175 1176 if (!phy_data->redrv) 1177 return; 1178 1179 mode = AXGBE_PHY_REDRV_MODE_CX; 1180 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1181 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1182 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1183 mode = AXGBE_PHY_REDRV_MODE_SR; 1184 1185 ret = axgbe_phy_get_comm_ownership(pdata); 1186 if (ret) 1187 return; 1188 1189 if (phy_data->redrv_if) 1190 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1191 else 1192 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1193 1194 axgbe_phy_put_comm_ownership(pdata); 1195 } 1196 1197 static void axgbe_phy_rx_reset(struct axgbe_port *pdata) 1198 { 1199 int reg; 1200 1201 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 1202 XGBE_PCS_PSEQ_STATE_MASK); 1203 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 1204 /* Mailbox command timed out, reset of RX block is required. 1205 * This can be done by asseting the reset bit and wait for 1206 * its compeletion. 1207 */ 1208 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1209 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 1210 rte_delay_us(20); 1211 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1212 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 1213 rte_delay_us(45); 1214 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n"); 1215 } 1216 } 1217 1218 1219 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) 1220 { 1221 /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */ 1222 if (pdata->phy.autoneg != AUTONEG_DISABLE) 1223 return; 1224 1225 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1226 XGBE_PMA_PLL_CTRL_MASK, 1227 enable ? XGBE_PMA_PLL_CTRL_SET 1228 : XGBE_PMA_PLL_CTRL_CLEAR); 1229 1230 /* Wait for command to complete */ 1231 rte_delay_us(150); 1232 } 1233 1234 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, 1235 enum axgbe_mb_cmd cmd, enum axgbe_mb_subcmd sub_cmd) 1236 { 1237 unsigned int s0 = 0; 1238 unsigned int wait; 1239 /* Clear the PLL so that it helps in power down sequence */ 1240 axgbe_phy_pll_ctrl(pdata, false); 1241 1242 /* Log if a previous command did not complete */ 1243 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 1244 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); 1245 axgbe_phy_rx_reset(pdata); 1246 } 1247 1248 /* Construct the command */ 1249 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1250 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1251 1252 /* Issue the command */ 1253 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1254 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1255 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1256 1257 /* Wait for command to complete */ 1258 wait = AXGBE_RATECHANGE_COUNT; 1259 while (wait--) { 1260 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1261 goto reenable_pll; 1262 rte_delay_us(1500); 1263 } 1264 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1265 /* Reset on error */ 1266 axgbe_phy_rx_reset(pdata); 1267 1268 reenable_pll: 1269 /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */ 1270 if (cmd != AXGBE_MB_CMD_POWER_OFF && 1271 cmd != AXGBE_MB_CMD_RRC) 1272 axgbe_phy_pll_ctrl(pdata, true); 1273 1274 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1275 } 1276 1277 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1278 { 1279 1280 1281 /* Receiver Reset Cycle */ 1282 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_RRC, AXGBE_MB_SUBCMD_NONE); 1283 1284 PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); 1285 } 1286 1287 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1288 { 1289 struct axgbe_phy_data *phy_data = pdata->phy_data; 1290 1291 /* Power off */ 1292 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_POWER_OFF, AXGBE_MB_SUBCMD_NONE); 1293 1294 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1295 1296 PMD_DRV_LOG(DEBUG, "phy powered off\n"); 1297 } 1298 1299 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1300 { 1301 struct axgbe_phy_data *phy_data = pdata->phy_data; 1302 1303 axgbe_phy_set_redrv_mode(pdata); 1304 1305 /* 10G/SFI */ 1306 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1307 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1308 AXGBE_MB_SUBCMD_ACTIVE); 1309 } else { 1310 if (phy_data->sfp_cable_len <= 1) 1311 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1312 AXGBE_MB_SUBCMD_PASSIVE_1M); 1313 else if (phy_data->sfp_cable_len <= 3) 1314 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1315 AXGBE_MB_SUBCMD_PASSIVE_3M); 1316 else 1317 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_SFI, 1318 AXGBE_MB_SUBCMD_PASSIVE_OTHER); 1319 } 1320 1321 phy_data->cur_mode = AXGBE_MODE_SFI; 1322 1323 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); 1324 } 1325 1326 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1327 { 1328 struct axgbe_phy_data *phy_data = pdata->phy_data; 1329 1330 axgbe_phy_set_redrv_mode(pdata); 1331 1332 /* 10G/KR */ 1333 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_10G_KR, 1334 AXGBE_MB_SUBCMD_NONE); 1335 phy_data->cur_mode = AXGBE_MODE_KR; 1336 1337 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); 1338 } 1339 1340 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1341 { 1342 struct axgbe_phy_data *phy_data = pdata->phy_data; 1343 1344 axgbe_phy_set_redrv_mode(pdata); 1345 1346 /* 2.5G/KX */ 1347 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_2_5G, AXGBE_MB_SUBCMD_NONE); 1348 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1349 } 1350 1351 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1352 { 1353 struct axgbe_phy_data *phy_data = pdata->phy_data; 1354 1355 axgbe_phy_set_redrv_mode(pdata); 1356 1357 /* 1G/SGMII */ 1358 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_1G, AXGBE_MB_SUBCMD_1G_SGMII); 1359 1360 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1361 } 1362 1363 static void axgbe_phy_sgmii_10_mode(struct axgbe_port *pdata) 1364 { 1365 struct axgbe_phy_data *phy_data = pdata->phy_data; 1366 1367 axgbe_phy_set_redrv_mode(pdata); 1368 1369 /* 10M/SGMII */ 1370 axgbe_phy_perform_ratechange(pdata, AXGBE_MB_CMD_SET_1G, AXGBE_MB_SUBCMD_10MBITS); 1371 1372 phy_data->cur_mode = AXGBE_MODE_SGMII_10; 1373 } 1374 1375 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1376 { 1377 struct axgbe_phy_data *phy_data = pdata->phy_data; 1378 1379 return phy_data->cur_mode; 1380 } 1381 1382 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1383 { 1384 struct axgbe_phy_data *phy_data = pdata->phy_data; 1385 1386 /* No switching if not 10GBase-T */ 1387 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1388 return axgbe_phy_cur_mode(pdata); 1389 1390 switch (axgbe_phy_cur_mode(pdata)) { 1391 case AXGBE_MODE_SGMII_10: 1392 case AXGBE_MODE_SGMII_100: 1393 case AXGBE_MODE_SGMII_1000: 1394 return AXGBE_MODE_KR; 1395 case AXGBE_MODE_KR: 1396 default: 1397 return AXGBE_MODE_SGMII_1000; 1398 } 1399 } 1400 1401 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1402 __rte_unused) 1403 { 1404 return AXGBE_MODE_KX_2500; 1405 } 1406 1407 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1408 { 1409 /* If we are in KR switch to KX, and vice-versa */ 1410 switch (axgbe_phy_cur_mode(pdata)) { 1411 case AXGBE_MODE_KX_1000: 1412 return AXGBE_MODE_KR; 1413 case AXGBE_MODE_KR: 1414 default: 1415 return AXGBE_MODE_KX_1000; 1416 } 1417 } 1418 1419 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1420 { 1421 struct axgbe_phy_data *phy_data = pdata->phy_data; 1422 1423 switch (phy_data->port_mode) { 1424 case AXGBE_PORT_MODE_BACKPLANE: 1425 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1426 return axgbe_phy_switch_bp_mode(pdata); 1427 case AXGBE_PORT_MODE_BACKPLANE_2500: 1428 return axgbe_phy_switch_bp_2500_mode(pdata); 1429 case AXGBE_PORT_MODE_1000BASE_T: 1430 case AXGBE_PORT_MODE_NBASE_T: 1431 case AXGBE_PORT_MODE_10GBASE_T: 1432 return axgbe_phy_switch_baset_mode(pdata); 1433 case AXGBE_PORT_MODE_1000BASE_X: 1434 case AXGBE_PORT_MODE_10GBASE_R: 1435 case AXGBE_PORT_MODE_SFP: 1436 /* No switching, so just return current mode */ 1437 return axgbe_phy_cur_mode(pdata); 1438 default: 1439 return AXGBE_MODE_UNKNOWN; 1440 } 1441 } 1442 1443 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1444 __rte_unused, 1445 int speed) 1446 { 1447 switch (speed) { 1448 case SPEED_1000: 1449 return AXGBE_MODE_X; 1450 case SPEED_10000: 1451 return AXGBE_MODE_KR; 1452 default: 1453 return AXGBE_MODE_UNKNOWN; 1454 } 1455 } 1456 1457 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1458 __rte_unused, 1459 int speed) 1460 { 1461 switch (speed) { 1462 case SPEED_10: 1463 return AXGBE_MODE_SGMII_10; 1464 case SPEED_100: 1465 return AXGBE_MODE_SGMII_100; 1466 case SPEED_1000: 1467 return AXGBE_MODE_SGMII_1000; 1468 case SPEED_10000: 1469 return AXGBE_MODE_KR; 1470 default: 1471 return AXGBE_MODE_UNKNOWN; 1472 } 1473 } 1474 1475 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1476 int speed) 1477 { 1478 switch (speed) { 1479 case SPEED_10: 1480 return AXGBE_MODE_SGMII_10; 1481 case SPEED_100: 1482 return AXGBE_MODE_SGMII_100; 1483 case SPEED_1000: 1484 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1485 return AXGBE_MODE_SGMII_1000; 1486 else 1487 return AXGBE_MODE_X; 1488 case SPEED_10000: 1489 case SPEED_UNKNOWN: 1490 return AXGBE_MODE_SFI; 1491 default: 1492 return AXGBE_MODE_UNKNOWN; 1493 } 1494 } 1495 1496 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1497 { 1498 switch (speed) { 1499 case SPEED_2500: 1500 return AXGBE_MODE_KX_2500; 1501 default: 1502 return AXGBE_MODE_UNKNOWN; 1503 } 1504 } 1505 1506 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1507 { 1508 switch (speed) { 1509 case SPEED_1000: 1510 return AXGBE_MODE_KX_1000; 1511 case SPEED_10000: 1512 return AXGBE_MODE_KR; 1513 default: 1514 return AXGBE_MODE_UNKNOWN; 1515 } 1516 } 1517 1518 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1519 int speed) 1520 { 1521 struct axgbe_phy_data *phy_data = pdata->phy_data; 1522 1523 switch (phy_data->port_mode) { 1524 case AXGBE_PORT_MODE_BACKPLANE: 1525 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1526 return axgbe_phy_get_bp_mode(speed); 1527 case AXGBE_PORT_MODE_BACKPLANE_2500: 1528 return axgbe_phy_get_bp_2500_mode(speed); 1529 case AXGBE_PORT_MODE_1000BASE_T: 1530 case AXGBE_PORT_MODE_NBASE_T: 1531 case AXGBE_PORT_MODE_10GBASE_T: 1532 return axgbe_phy_get_baset_mode(phy_data, speed); 1533 case AXGBE_PORT_MODE_1000BASE_X: 1534 case AXGBE_PORT_MODE_10GBASE_R: 1535 return axgbe_phy_get_basex_mode(phy_data, speed); 1536 case AXGBE_PORT_MODE_SFP: 1537 return axgbe_phy_get_sfp_mode(phy_data, speed); 1538 default: 1539 return AXGBE_MODE_UNKNOWN; 1540 } 1541 } 1542 1543 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1544 { 1545 switch (mode) { 1546 case AXGBE_MODE_KR: 1547 axgbe_phy_kr_mode(pdata); 1548 break; 1549 case AXGBE_MODE_SFI: 1550 axgbe_phy_sfi_mode(pdata); 1551 break; 1552 case AXGBE_MODE_KX_2500: 1553 axgbe_phy_kx_2500_mode(pdata); 1554 break; 1555 case AXGBE_MODE_SGMII_1000: 1556 axgbe_phy_sgmii_1000_mode(pdata); 1557 break; 1558 case AXGBE_MODE_SGMII_10: 1559 axgbe_phy_sgmii_10_mode(pdata); 1560 break; 1561 default: 1562 break; 1563 } 1564 } 1565 1566 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1567 enum axgbe_mode mode, u32 advert) 1568 { 1569 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1570 if (pdata->phy.advertising & advert) 1571 return true; 1572 } else { 1573 enum axgbe_mode cur_mode; 1574 1575 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1576 if (cur_mode == mode) 1577 return true; 1578 } 1579 1580 return false; 1581 } 1582 1583 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1584 enum axgbe_mode mode) 1585 { 1586 switch (mode) { 1587 case AXGBE_MODE_X: 1588 return axgbe_phy_check_mode(pdata, mode, 1589 ADVERTISED_1000baseT_Full); 1590 case AXGBE_MODE_KR: 1591 return axgbe_phy_check_mode(pdata, mode, 1592 ADVERTISED_10000baseT_Full); 1593 default: 1594 return false; 1595 } 1596 } 1597 1598 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1599 enum axgbe_mode mode) 1600 { 1601 switch (mode) { 1602 case AXGBE_MODE_SGMII_10: 1603 return axgbe_phy_check_mode(pdata, mode, 1604 ADVERTISED_10baseT_Full); 1605 case AXGBE_MODE_SGMII_100: 1606 return axgbe_phy_check_mode(pdata, mode, 1607 ADVERTISED_100baseT_Full); 1608 case AXGBE_MODE_SGMII_1000: 1609 return axgbe_phy_check_mode(pdata, mode, 1610 ADVERTISED_1000baseT_Full); 1611 case AXGBE_MODE_KR: 1612 return axgbe_phy_check_mode(pdata, mode, 1613 ADVERTISED_10000baseT_Full); 1614 default: 1615 return false; 1616 } 1617 } 1618 1619 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1620 enum axgbe_mode mode) 1621 { 1622 struct axgbe_phy_data *phy_data = pdata->phy_data; 1623 1624 switch (mode) { 1625 case AXGBE_MODE_X: 1626 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1627 return false; 1628 return axgbe_phy_check_mode(pdata, mode, 1629 ADVERTISED_1000baseT_Full); 1630 case AXGBE_MODE_SGMII_10: 1631 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1632 return false; 1633 return axgbe_phy_check_mode(pdata, mode, 1634 ADVERTISED_10baseT_Full); 1635 case AXGBE_MODE_SGMII_100: 1636 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1637 return false; 1638 return axgbe_phy_check_mode(pdata, mode, 1639 ADVERTISED_100baseT_Full); 1640 case AXGBE_MODE_SGMII_1000: 1641 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1642 return false; 1643 return axgbe_phy_check_mode(pdata, mode, 1644 ADVERTISED_1000baseT_Full); 1645 case AXGBE_MODE_SFI: 1646 return axgbe_phy_check_mode(pdata, mode, 1647 ADVERTISED_10000baseT_Full); 1648 default: 1649 return false; 1650 } 1651 } 1652 1653 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1654 enum axgbe_mode mode) 1655 { 1656 switch (mode) { 1657 case AXGBE_MODE_KX_2500: 1658 return axgbe_phy_check_mode(pdata, mode, 1659 ADVERTISED_2500baseX_Full); 1660 default: 1661 return false; 1662 } 1663 } 1664 1665 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1666 enum axgbe_mode mode) 1667 { 1668 switch (mode) { 1669 case AXGBE_MODE_KX_1000: 1670 return axgbe_phy_check_mode(pdata, mode, 1671 ADVERTISED_1000baseKX_Full); 1672 case AXGBE_MODE_KR: 1673 return axgbe_phy_check_mode(pdata, mode, 1674 ADVERTISED_10000baseKR_Full); 1675 default: 1676 return false; 1677 } 1678 } 1679 1680 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1681 { 1682 struct axgbe_phy_data *phy_data = pdata->phy_data; 1683 1684 switch (phy_data->port_mode) { 1685 case AXGBE_PORT_MODE_BACKPLANE: 1686 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1687 return axgbe_phy_use_bp_mode(pdata, mode); 1688 case AXGBE_PORT_MODE_BACKPLANE_2500: 1689 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1690 case AXGBE_PORT_MODE_1000BASE_T: 1691 case AXGBE_PORT_MODE_NBASE_T: 1692 case AXGBE_PORT_MODE_10GBASE_T: 1693 return axgbe_phy_use_baset_mode(pdata, mode); 1694 case AXGBE_PORT_MODE_1000BASE_X: 1695 case AXGBE_PORT_MODE_10GBASE_R: 1696 return axgbe_phy_use_basex_mode(pdata, mode); 1697 case AXGBE_PORT_MODE_SFP: 1698 return axgbe_phy_use_sfp_mode(pdata, mode); 1699 default: 1700 return false; 1701 } 1702 } 1703 1704 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1705 { 1706 struct axgbe_phy_data *phy_data = pdata->phy_data; 1707 unsigned int reg; 1708 1709 *an_restart = 0; 1710 1711 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1712 /* Check SFP signals */ 1713 axgbe_phy_sfp_detect(pdata); 1714 1715 if (phy_data->sfp_changed) { 1716 *an_restart = 1; 1717 return 0; 1718 } 1719 1720 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1721 return 0; 1722 } 1723 1724 /* Link status is latched low, so read once to clear 1725 * and then read again to get current state 1726 */ 1727 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1728 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1729 if (reg & MDIO_STAT1_LSTATUS) 1730 return 1; 1731 1732 if (pdata->phy.autoneg == AUTONEG_ENABLE && 1733 phy_data->port_mode == AXGBE_PORT_MODE_BACKPLANE) { 1734 if (rte_bit_relaxed_get32(AXGBE_LINK_INIT, &pdata->dev_state)) { 1735 *an_restart = 1; 1736 } 1737 } 1738 1739 /* No link, attempt a receiver reset cycle */ 1740 if (pdata->vdata->enable_rrc && phy_data->rrc_count++) { 1741 phy_data->rrc_count = 0; 1742 axgbe_phy_rrc(pdata); 1743 } 1744 1745 return 0; 1746 } 1747 1748 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1749 { 1750 struct axgbe_phy_data *phy_data = pdata->phy_data; 1751 1752 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1753 XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_ADDR); 1754 1755 phy_data->sfp_gpio_mask = XP_GET_BITS(pdata->pp3, XP_PROP_3, GPIO_MASK); 1756 1757 phy_data->sfp_gpio_rx_los = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1758 GPIO_RX_LOS); 1759 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1760 GPIO_TX_FAULT); 1761 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1762 GPIO_MOD_ABS); 1763 phy_data->sfp_gpio_rate_select = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1764 GPIO_RATE_SELECT); 1765 } 1766 1767 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1768 { 1769 struct axgbe_phy_data *phy_data = pdata->phy_data; 1770 unsigned int mux_addr_hi, mux_addr_lo; 1771 1772 mux_addr_hi = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_HI); 1773 mux_addr_lo = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_ADDR_LO); 1774 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1775 return; 1776 1777 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1778 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1779 phy_data->sfp_mux_channel = XP_GET_BITS(pdata->pp4, XP_PROP_4, MUX_CHAN); 1780 } 1781 1782 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1783 { 1784 axgbe_phy_sfp_comm_setup(pdata); 1785 axgbe_phy_sfp_gpio_setup(pdata); 1786 } 1787 1788 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1789 { 1790 if (!phy_data->redrv) 1791 return false; 1792 1793 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1794 return true; 1795 1796 switch (phy_data->redrv_model) { 1797 case AXGBE_PHY_REDRV_MODEL_4223: 1798 if (phy_data->redrv_lane > 3) 1799 return true; 1800 break; 1801 case AXGBE_PHY_REDRV_MODEL_4227: 1802 if (phy_data->redrv_lane > 1) 1803 return true; 1804 break; 1805 default: 1806 return true; 1807 } 1808 1809 return false; 1810 } 1811 1812 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1813 { 1814 struct axgbe_phy_data *phy_data = pdata->phy_data; 1815 1816 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1817 return 0; 1818 1819 phy_data->mdio_reset = XP_GET_BITS(pdata->pp3, XP_PROP_3, MDIO_RESET); 1820 switch (phy_data->mdio_reset) { 1821 case AXGBE_MDIO_RESET_NONE: 1822 case AXGBE_MDIO_RESET_I2C_GPIO: 1823 case AXGBE_MDIO_RESET_INT_GPIO: 1824 break; 1825 default: 1826 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1827 phy_data->mdio_reset); 1828 return -EINVAL; 1829 } 1830 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1831 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1832 XP_GET_BITS(pdata->pp3, XP_PROP_3, 1833 MDIO_RESET_I2C_ADDR); 1834 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1835 MDIO_RESET_I2C_GPIO); 1836 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1837 phy_data->mdio_reset_gpio = XP_GET_BITS(pdata->pp3, XP_PROP_3, 1838 MDIO_RESET_INT_GPIO); 1839 } 1840 1841 return 0; 1842 } 1843 1844 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1845 { 1846 struct axgbe_phy_data *phy_data = pdata->phy_data; 1847 unsigned int ver; 1848 1849 /* 10 Mbps speed is not supported in ver < 30H */ 1850 ver = AXGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER); 1851 if (ver < 0x30 && phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) 1852 return true; 1853 1854 switch (phy_data->port_mode) { 1855 case AXGBE_PORT_MODE_BACKPLANE: 1856 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1857 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1858 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1859 return false; 1860 break; 1861 case AXGBE_PORT_MODE_BACKPLANE_2500: 1862 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1863 return false; 1864 break; 1865 case AXGBE_PORT_MODE_1000BASE_T: 1866 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) || 1867 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1868 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1869 return false; 1870 break; 1871 case AXGBE_PORT_MODE_1000BASE_X: 1872 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1873 return false; 1874 break; 1875 case AXGBE_PORT_MODE_NBASE_T: 1876 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) || 1877 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1878 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1879 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1880 return false; 1881 break; 1882 case AXGBE_PORT_MODE_10GBASE_T: 1883 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) || 1884 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1885 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1886 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1887 return false; 1888 break; 1889 case AXGBE_PORT_MODE_10GBASE_R: 1890 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1891 return false; 1892 break; 1893 case AXGBE_PORT_MODE_SFP: 1894 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) || 1895 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1896 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1897 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1898 return false; 1899 break; 1900 default: 1901 break; 1902 } 1903 1904 return true; 1905 } 1906 1907 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1908 { 1909 struct axgbe_phy_data *phy_data = pdata->phy_data; 1910 1911 switch (phy_data->port_mode) { 1912 case AXGBE_PORT_MODE_BACKPLANE: 1913 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1914 case AXGBE_PORT_MODE_BACKPLANE_2500: 1915 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1916 return false; 1917 break; 1918 case AXGBE_PORT_MODE_1000BASE_T: 1919 case AXGBE_PORT_MODE_1000BASE_X: 1920 case AXGBE_PORT_MODE_NBASE_T: 1921 case AXGBE_PORT_MODE_10GBASE_T: 1922 case AXGBE_PORT_MODE_10GBASE_R: 1923 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1924 return false; 1925 break; 1926 case AXGBE_PORT_MODE_SFP: 1927 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1928 return false; 1929 break; 1930 default: 1931 break; 1932 } 1933 1934 return true; 1935 } 1936 1937 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1938 { 1939 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS)) 1940 return false; 1941 if (!XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE)) 1942 return false; 1943 1944 return true; 1945 } 1946 1947 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1948 { 1949 struct axgbe_phy_data *phy_data = pdata->phy_data; 1950 1951 if (!pdata->vdata->an_cdr_workaround) 1952 return; 1953 1954 if (!phy_data->phy_cdr_notrack) 1955 return; 1956 1957 rte_delay_us(phy_data->phy_cdr_delay + 400); 1958 1959 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1960 AXGBE_PMA_CDR_TRACK_EN_MASK, 1961 AXGBE_PMA_CDR_TRACK_EN_ON); 1962 1963 phy_data->phy_cdr_notrack = 0; 1964 } 1965 1966 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1967 { 1968 struct axgbe_phy_data *phy_data = pdata->phy_data; 1969 1970 if (!pdata->vdata->an_cdr_workaround) 1971 return; 1972 1973 if (phy_data->phy_cdr_notrack) 1974 return; 1975 1976 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1977 AXGBE_PMA_CDR_TRACK_EN_MASK, 1978 AXGBE_PMA_CDR_TRACK_EN_OFF); 1979 1980 axgbe_phy_rrc(pdata); 1981 1982 phy_data->phy_cdr_notrack = 1; 1983 } 1984 1985 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1986 { 1987 if (!pdata->cdr_track_early) 1988 axgbe_phy_cdr_track(pdata); 1989 } 1990 1991 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1992 { 1993 if (pdata->cdr_track_early) 1994 axgbe_phy_cdr_track(pdata); 1995 } 1996 1997 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1998 { 1999 struct axgbe_phy_data *phy_data = pdata->phy_data; 2000 2001 switch (pdata->an_mode) { 2002 case AXGBE_AN_MODE_CL73: 2003 case AXGBE_AN_MODE_CL73_REDRV: 2004 if (phy_data->cur_mode != AXGBE_MODE_KR) 2005 break; 2006 2007 axgbe_phy_cdr_track(pdata); 2008 2009 switch (pdata->an_result) { 2010 case AXGBE_AN_READY: 2011 case AXGBE_AN_COMPLETE: 2012 break; 2013 default: 2014 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 2015 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 2016 break; 2017 } 2018 break; 2019 default: 2020 break; 2021 } 2022 } 2023 2024 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 2025 { 2026 struct axgbe_phy_data *phy_data = pdata->phy_data; 2027 2028 switch (pdata->an_mode) { 2029 case AXGBE_AN_MODE_CL73: 2030 case AXGBE_AN_MODE_CL73_REDRV: 2031 if (phy_data->cur_mode != AXGBE_MODE_KR) 2032 break; 2033 2034 axgbe_phy_cdr_notrack(pdata); 2035 break; 2036 default: 2037 break; 2038 } 2039 } 2040 2041 static void axgbe_phy_stop(struct axgbe_port *pdata) 2042 { 2043 struct axgbe_phy_data *phy_data = pdata->phy_data; 2044 2045 /* Reset SFP data */ 2046 axgbe_phy_sfp_reset(phy_data); 2047 axgbe_phy_sfp_mod_absent(pdata); 2048 2049 /* Reset CDR support */ 2050 axgbe_phy_cdr_track(pdata); 2051 2052 /* Power off the PHY */ 2053 axgbe_phy_power_off(pdata); 2054 2055 /* Stop the I2C controller */ 2056 pdata->i2c_if.i2c_stop(pdata); 2057 } 2058 2059 static int axgbe_phy_start(struct axgbe_port *pdata) 2060 { 2061 struct axgbe_phy_data *phy_data = pdata->phy_data; 2062 int ret; 2063 2064 /* Start the I2C controller */ 2065 ret = pdata->i2c_if.i2c_start(pdata); 2066 if (ret) 2067 return ret; 2068 2069 /* Start in highest supported mode */ 2070 axgbe_phy_set_mode(pdata, phy_data->start_mode); 2071 2072 /* Reset CDR support */ 2073 axgbe_phy_cdr_track(pdata); 2074 2075 /* After starting the I2C controller, we can check for an SFP */ 2076 switch (phy_data->port_mode) { 2077 case AXGBE_PORT_MODE_SFP: 2078 axgbe_phy_sfp_detect(pdata); 2079 break; 2080 default: 2081 break; 2082 } 2083 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 2084 2085 return ret; 2086 } 2087 2088 static int axgbe_phy_reset(struct axgbe_port *pdata) 2089 { 2090 struct axgbe_phy_data *phy_data = pdata->phy_data; 2091 enum axgbe_mode cur_mode; 2092 2093 /* Reset by power cycling the PHY */ 2094 cur_mode = phy_data->cur_mode; 2095 axgbe_phy_power_off(pdata); 2096 /* First time reset is done with passed unknown mode*/ 2097 axgbe_phy_set_mode(pdata, cur_mode); 2098 return 0; 2099 } 2100 2101 static int axgbe_phy_init(struct axgbe_port *pdata) 2102 { 2103 struct axgbe_phy_data *phy_data; 2104 int ret; 2105 2106 /* Check if enabled */ 2107 if (!axgbe_phy_port_enabled(pdata)) { 2108 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2109 return -ENODEV; 2110 } 2111 2112 /* Initialize the I2C controller */ 2113 ret = pdata->i2c_if.i2c_init(pdata); 2114 if (ret) 2115 return ret; 2116 2117 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2118 if (!phy_data) { 2119 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2120 return -ENOMEM; 2121 } 2122 pdata->phy_data = phy_data; 2123 2124 phy_data->port_mode = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_MODE); 2125 phy_data->port_id = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_ID); 2126 phy_data->port_speeds = XP_GET_BITS(pdata->pp0, XP_PROP_0, PORT_SPEEDS); 2127 phy_data->conn_type = XP_GET_BITS(pdata->pp0, XP_PROP_0, CONN_TYPE); 2128 phy_data->mdio_addr = XP_GET_BITS(pdata->pp0, XP_PROP_0, MDIO_ADDR); 2129 2130 phy_data->redrv = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_PRESENT); 2131 phy_data->redrv_if = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_IF); 2132 phy_data->redrv_addr = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_ADDR); 2133 phy_data->redrv_lane = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_LANE); 2134 phy_data->redrv_model = XP_GET_BITS(pdata->pp4, XP_PROP_4, REDRV_MODEL); 2135 2136 /* Validate the connection requested */ 2137 if (axgbe_phy_conn_type_mismatch(pdata)) { 2138 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2139 phy_data->port_mode, phy_data->conn_type); 2140 return -EINVAL; 2141 } 2142 2143 /* Validate the mode requested */ 2144 if (axgbe_phy_port_mode_mismatch(pdata)) { 2145 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2146 phy_data->port_mode, phy_data->port_speeds); 2147 return -EINVAL; 2148 } 2149 2150 /* Check for and validate MDIO reset support */ 2151 ret = axgbe_phy_mdio_reset_setup(pdata); 2152 if (ret) 2153 return ret; 2154 2155 /* Validate the re-driver information */ 2156 if (axgbe_phy_redrv_error(phy_data)) { 2157 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2158 return -EINVAL; 2159 } 2160 pdata->kr_redrv = phy_data->redrv; 2161 2162 /* Indicate current mode is unknown */ 2163 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2164 2165 /* Initialize supported features */ 2166 pdata->phy.supported = 0; 2167 2168 switch (phy_data->port_mode) { 2169 /* Backplane support */ 2170 case AXGBE_PORT_MODE_BACKPLANE: 2171 pdata->phy.supported |= SUPPORTED_Autoneg; 2172 /* Fallthrough */ 2173 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2174 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2175 pdata->phy.supported |= SUPPORTED_Backplane; 2176 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2177 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2178 phy_data->start_mode = AXGBE_MODE_KX_1000; 2179 } 2180 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2181 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2182 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2183 pdata->phy.supported |= 2184 SUPPORTED_10000baseR_FEC; 2185 phy_data->start_mode = AXGBE_MODE_KR; 2186 } 2187 2188 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2189 break; 2190 case AXGBE_PORT_MODE_BACKPLANE_2500: 2191 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2192 pdata->phy.supported |= SUPPORTED_Backplane; 2193 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2194 phy_data->start_mode = AXGBE_MODE_KX_2500; 2195 2196 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2197 break; 2198 2199 /* MDIO 1GBase-T support */ 2200 case AXGBE_PORT_MODE_1000BASE_T: 2201 pdata->phy.supported |= SUPPORTED_Autoneg; 2202 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2203 pdata->phy.supported |= SUPPORTED_TP; 2204 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) { 2205 pdata->phy.supported |= SUPPORTED_10baseT_Full; 2206 phy_data->start_mode = AXGBE_MODE_SGMII_10; 2207 } 2208 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2209 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2210 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2211 } 2212 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2213 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2214 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2215 } 2216 2217 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2218 break; 2219 2220 /* MDIO Base-X support */ 2221 case AXGBE_PORT_MODE_1000BASE_X: 2222 pdata->phy.supported |= SUPPORTED_Autoneg; 2223 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2224 pdata->phy.supported |= SUPPORTED_FIBRE; 2225 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2226 phy_data->start_mode = AXGBE_MODE_X; 2227 2228 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2229 break; 2230 2231 /* MDIO NBase-T support */ 2232 case AXGBE_PORT_MODE_NBASE_T: 2233 pdata->phy.supported |= SUPPORTED_Autoneg; 2234 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2235 pdata->phy.supported |= SUPPORTED_TP; 2236 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) { 2237 pdata->phy.supported |= SUPPORTED_10baseT_Full; 2238 phy_data->start_mode = AXGBE_MODE_SGMII_10; 2239 } 2240 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2241 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2242 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2243 } 2244 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2245 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2246 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2247 } 2248 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2249 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2250 phy_data->start_mode = AXGBE_MODE_KX_2500; 2251 } 2252 2253 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2254 break; 2255 2256 /* 10GBase-T support */ 2257 case AXGBE_PORT_MODE_10GBASE_T: 2258 pdata->phy.supported |= SUPPORTED_Autoneg; 2259 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2260 pdata->phy.supported |= SUPPORTED_TP; 2261 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) { 2262 pdata->phy.supported |= SUPPORTED_10baseT_Full; 2263 phy_data->start_mode = AXGBE_MODE_SGMII_10; 2264 } 2265 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2266 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2267 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2268 } 2269 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2270 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2271 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2272 } 2273 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2274 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2275 phy_data->start_mode = AXGBE_MODE_KR; 2276 } 2277 2278 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2279 break; 2280 2281 /* 10GBase-R support */ 2282 case AXGBE_PORT_MODE_10GBASE_R: 2283 pdata->phy.supported |= SUPPORTED_Autoneg; 2284 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2285 pdata->phy.supported |= SUPPORTED_TP; 2286 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2287 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2288 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2289 phy_data->start_mode = AXGBE_MODE_SFI; 2290 2291 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2292 break; 2293 2294 /* SFP support */ 2295 case AXGBE_PORT_MODE_SFP: 2296 pdata->phy.supported |= SUPPORTED_Autoneg; 2297 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2298 pdata->phy.supported |= SUPPORTED_TP; 2299 pdata->phy.supported |= SUPPORTED_FIBRE; 2300 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10) { 2301 pdata->phy.supported |= SUPPORTED_10baseT_Full; 2302 phy_data->start_mode = AXGBE_MODE_SGMII_10; 2303 } 2304 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2305 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2306 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2307 } 2308 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2309 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2310 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2311 } 2312 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2313 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2314 phy_data->start_mode = AXGBE_MODE_SFI; 2315 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2316 pdata->phy.supported |= 2317 SUPPORTED_10000baseR_FEC; 2318 } 2319 2320 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2321 2322 axgbe_phy_sfp_setup(pdata); 2323 break; 2324 default: 2325 return -EINVAL; 2326 } 2327 2328 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2329 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2330 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2331 phy_data->phydev_mode); 2332 if (ret) { 2333 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2334 phy_data->mdio_addr, phy_data->phydev_mode); 2335 return -EINVAL; 2336 } 2337 } 2338 2339 if (phy_data->redrv && !phy_data->redrv_if) { 2340 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2341 AXGBE_MDIO_MODE_CL22); 2342 if (ret) { 2343 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2344 phy_data->redrv_addr); 2345 return -EINVAL; 2346 } 2347 } 2348 2349 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2350 return 0; 2351 } 2352 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2353 { 2354 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2355 2356 phy_impl->init = axgbe_phy_init; 2357 phy_impl->reset = axgbe_phy_reset; 2358 phy_impl->start = axgbe_phy_start; 2359 phy_impl->stop = axgbe_phy_stop; 2360 phy_impl->link_status = axgbe_phy_link_status; 2361 phy_impl->use_mode = axgbe_phy_use_mode; 2362 phy_impl->set_mode = axgbe_phy_set_mode; 2363 phy_impl->get_mode = axgbe_phy_get_mode; 2364 phy_impl->switch_mode = axgbe_phy_switch_mode; 2365 phy_impl->cur_mode = axgbe_phy_cur_mode; 2366 phy_impl->an_mode = axgbe_phy_an_mode; 2367 phy_impl->an_config = axgbe_phy_an_config; 2368 phy_impl->an_advertising = axgbe_phy_an_advertising; 2369 phy_impl->an_outcome = axgbe_phy_an_outcome; 2370 2371 phy_impl->an_pre = axgbe_phy_an_pre; 2372 phy_impl->an_post = axgbe_phy_an_post; 2373 2374 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2375 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2376 } 2377