1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(1) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(2) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(3) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(4) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG, 50 AXGBE_PORT_MODE_MAX, 51 }; 52 53 enum axgbe_conn_type { 54 AXGBE_CONN_TYPE_NONE = 0, 55 AXGBE_CONN_TYPE_SFP, 56 AXGBE_CONN_TYPE_MDIO, 57 AXGBE_CONN_TYPE_RSVD1, 58 AXGBE_CONN_TYPE_BACKPLANE, 59 AXGBE_CONN_TYPE_MAX, 60 }; 61 62 /* SFP/SFP+ related definitions */ 63 enum axgbe_sfp_comm { 64 AXGBE_SFP_COMM_DIRECT = 0, 65 AXGBE_SFP_COMM_PCA9545, 66 }; 67 68 enum axgbe_sfp_cable { 69 AXGBE_SFP_CABLE_UNKNOWN = 0, 70 AXGBE_SFP_CABLE_ACTIVE, 71 AXGBE_SFP_CABLE_PASSIVE, 72 }; 73 74 enum axgbe_sfp_base { 75 AXGBE_SFP_BASE_UNKNOWN = 0, 76 AXGBE_SFP_BASE_1000_T, 77 AXGBE_SFP_BASE_1000_SX, 78 AXGBE_SFP_BASE_1000_LX, 79 AXGBE_SFP_BASE_1000_CX, 80 AXGBE_SFP_BASE_10000_SR, 81 AXGBE_SFP_BASE_10000_LR, 82 AXGBE_SFP_BASE_10000_LRM, 83 AXGBE_SFP_BASE_10000_ER, 84 AXGBE_SFP_BASE_10000_CR, 85 }; 86 87 enum axgbe_sfp_speed { 88 AXGBE_SFP_SPEED_UNKNOWN = 0, 89 AXGBE_SFP_SPEED_100_1000, 90 AXGBE_SFP_SPEED_1000, 91 AXGBE_SFP_SPEED_10000, 92 }; 93 94 /* SFP Serial ID Base ID values relative to an offset of 0 */ 95 #define AXGBE_SFP_BASE_ID 0 96 #define AXGBE_SFP_ID_SFP 0x03 97 98 #define AXGBE_SFP_BASE_EXT_ID 1 99 #define AXGBE_SFP_EXT_ID_SFP 0x04 100 101 #define AXGBE_SFP_BASE_10GBE_CC 3 102 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 103 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 104 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 105 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 106 107 #define AXGBE_SFP_BASE_1GBE_CC 6 108 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 109 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 110 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 111 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 112 113 #define AXGBE_SFP_BASE_CABLE 8 114 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 115 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 116 117 #define AXGBE_SFP_BASE_BR 12 118 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 119 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 120 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 121 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 122 123 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 124 125 #define AXGBE_SFP_BASE_VENDOR_NAME 20 126 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 127 #define AXGBE_SFP_BASE_VENDOR_PN 40 128 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 129 #define AXGBE_SFP_BASE_VENDOR_REV 56 130 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 131 132 #define AXGBE_SFP_BASE_CC 63 133 134 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 135 #define AXGBE_SFP_BASE_VENDOR_SN 4 136 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 137 138 #define AXGBE_SFP_EXTD_DIAG 28 139 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 140 141 #define AXGBE_SFP_EXTD_SFF_8472 30 142 143 #define AXGBE_SFP_EXTD_CC 31 144 145 struct axgbe_sfp_eeprom { 146 u8 base[64]; 147 u8 extd[32]; 148 u8 vendor[32]; 149 }; 150 151 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 152 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 153 154 struct axgbe_sfp_ascii { 155 union { 156 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 157 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 158 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 159 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 160 } u; 161 }; 162 163 /* MDIO PHY reset types */ 164 enum axgbe_mdio_reset { 165 AXGBE_MDIO_RESET_NONE = 0, 166 AXGBE_MDIO_RESET_I2C_GPIO, 167 AXGBE_MDIO_RESET_INT_GPIO, 168 AXGBE_MDIO_RESET_MAX, 169 }; 170 171 /* Re-driver related definitions */ 172 enum axgbe_phy_redrv_if { 173 AXGBE_PHY_REDRV_IF_MDIO = 0, 174 AXGBE_PHY_REDRV_IF_I2C, 175 AXGBE_PHY_REDRV_IF_MAX, 176 }; 177 178 enum axgbe_phy_redrv_model { 179 AXGBE_PHY_REDRV_MODEL_4223 = 0, 180 AXGBE_PHY_REDRV_MODEL_4227, 181 AXGBE_PHY_REDRV_MODEL_MAX, 182 }; 183 184 enum axgbe_phy_redrv_mode { 185 AXGBE_PHY_REDRV_MODE_CX = 5, 186 AXGBE_PHY_REDRV_MODE_SR = 9, 187 }; 188 189 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 190 191 /* PHY related configuration information */ 192 struct axgbe_phy_data { 193 enum axgbe_port_mode port_mode; 194 195 unsigned int port_id; 196 197 unsigned int port_speeds; 198 199 enum axgbe_conn_type conn_type; 200 201 enum axgbe_mode cur_mode; 202 enum axgbe_mode start_mode; 203 204 unsigned int rrc_count; 205 206 unsigned int mdio_addr; 207 208 unsigned int comm_owned; 209 210 /* SFP Support */ 211 enum axgbe_sfp_comm sfp_comm; 212 unsigned int sfp_mux_address; 213 unsigned int sfp_mux_channel; 214 215 unsigned int sfp_gpio_address; 216 unsigned int sfp_gpio_mask; 217 unsigned int sfp_gpio_rx_los; 218 unsigned int sfp_gpio_tx_fault; 219 unsigned int sfp_gpio_mod_absent; 220 unsigned int sfp_gpio_rate_select; 221 222 unsigned int sfp_rx_los; 223 unsigned int sfp_tx_fault; 224 unsigned int sfp_mod_absent; 225 unsigned int sfp_diags; 226 unsigned int sfp_changed; 227 unsigned int sfp_phy_avail; 228 unsigned int sfp_cable_len; 229 enum axgbe_sfp_base sfp_base; 230 enum axgbe_sfp_cable sfp_cable; 231 enum axgbe_sfp_speed sfp_speed; 232 struct axgbe_sfp_eeprom sfp_eeprom; 233 234 /* External PHY support */ 235 enum axgbe_mdio_mode phydev_mode; 236 enum axgbe_mdio_reset mdio_reset; 237 unsigned int mdio_reset_addr; 238 unsigned int mdio_reset_gpio; 239 240 /* Re-driver support */ 241 unsigned int redrv; 242 unsigned int redrv_if; 243 unsigned int redrv_addr; 244 unsigned int redrv_lane; 245 unsigned int redrv_model; 246 247 /* KR AN support */ 248 unsigned int phy_cdr_notrack; 249 unsigned int phy_cdr_delay; 250 }; 251 252 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 253 254 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 255 struct axgbe_i2c_op *i2c_op) 256 { 257 struct axgbe_phy_data *phy_data = pdata->phy_data; 258 259 /* Be sure we own the bus */ 260 if (!phy_data->comm_owned) 261 return -EIO; 262 263 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 264 } 265 266 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 267 unsigned int val) 268 { 269 struct axgbe_phy_data *phy_data = pdata->phy_data; 270 struct axgbe_i2c_op i2c_op; 271 uint16_t *redrv_val; 272 u8 redrv_data[5], csum; 273 unsigned int i, retry; 274 int ret; 275 276 /* High byte of register contains read/write indicator */ 277 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 278 redrv_data[1] = reg & 0xff; 279 redrv_val = (uint16_t *)&redrv_data[2]; 280 *redrv_val = rte_cpu_to_be_16(val); 281 282 /* Calculate 1 byte checksum */ 283 csum = 0; 284 for (i = 0; i < 4; i++) { 285 csum += redrv_data[i]; 286 if (redrv_data[i] > csum) 287 csum++; 288 } 289 redrv_data[4] = ~csum; 290 291 retry = 1; 292 again1: 293 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 294 i2c_op.target = phy_data->redrv_addr; 295 i2c_op.len = sizeof(redrv_data); 296 i2c_op.buf = redrv_data; 297 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 298 if (ret) { 299 if ((ret == -EAGAIN) && retry--) 300 goto again1; 301 302 return ret; 303 } 304 305 retry = 1; 306 again2: 307 i2c_op.cmd = AXGBE_I2C_CMD_READ; 308 i2c_op.target = phy_data->redrv_addr; 309 i2c_op.len = 1; 310 i2c_op.buf = redrv_data; 311 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 312 if (ret) { 313 if ((ret == -EAGAIN) && retry--) 314 goto again2; 315 316 return ret; 317 } 318 319 if (redrv_data[0] != 0xff) { 320 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 321 ret = -EIO; 322 } 323 324 return ret; 325 } 326 327 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 328 void *reg, unsigned int reg_len, 329 void *val, unsigned int val_len) 330 { 331 struct axgbe_i2c_op i2c_op; 332 int retry, ret; 333 334 retry = 1; 335 again1: 336 /* Set the specified register to read */ 337 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 338 i2c_op.target = target; 339 i2c_op.len = reg_len; 340 i2c_op.buf = reg; 341 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 342 if (ret) { 343 if ((ret == -EAGAIN) && retry--) 344 goto again1; 345 346 return ret; 347 } 348 349 retry = 1; 350 again2: 351 /* Read the specified register */ 352 i2c_op.cmd = AXGBE_I2C_CMD_READ; 353 i2c_op.target = target; 354 i2c_op.len = val_len; 355 i2c_op.buf = val; 356 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 357 if ((ret == -EAGAIN) && retry--) 358 goto again2; 359 360 return ret; 361 } 362 363 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 364 { 365 struct axgbe_phy_data *phy_data = pdata->phy_data; 366 struct axgbe_i2c_op i2c_op; 367 uint8_t mux_channel; 368 369 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 370 return 0; 371 372 /* Select no mux channels */ 373 mux_channel = 0; 374 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 375 i2c_op.target = phy_data->sfp_mux_address; 376 i2c_op.len = sizeof(mux_channel); 377 i2c_op.buf = &mux_channel; 378 379 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 380 } 381 382 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 383 { 384 struct axgbe_phy_data *phy_data = pdata->phy_data; 385 struct axgbe_i2c_op i2c_op; 386 u8 mux_channel; 387 388 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 389 return 0; 390 391 /* Select desired mux channel */ 392 mux_channel = 1 << phy_data->sfp_mux_channel; 393 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 394 i2c_op.target = phy_data->sfp_mux_address; 395 i2c_op.len = sizeof(mux_channel); 396 i2c_op.buf = &mux_channel; 397 398 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 399 } 400 401 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 402 { 403 struct axgbe_phy_data *phy_data = pdata->phy_data; 404 405 phy_data->comm_owned = 0; 406 407 pthread_mutex_unlock(&pdata->phy_mutex); 408 } 409 410 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 411 { 412 struct axgbe_phy_data *phy_data = pdata->phy_data; 413 uint64_t timeout; 414 unsigned int mutex_id; 415 416 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 417 * the driver needs to take the software mutex and then the hardware 418 * mutexes before being able to use the busses. 419 */ 420 pthread_mutex_lock(&pdata->phy_mutex); 421 422 if (phy_data->comm_owned) 423 return 0; 424 425 /* Clear the mutexes */ 426 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 427 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 428 429 /* Mutex formats are the same for I2C and MDIO/GPIO */ 430 mutex_id = 0; 431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 432 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 433 434 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 435 while (time_before(rte_get_timer_cycles(), timeout)) { 436 /* Must be all zeroes in order to obtain the mutex */ 437 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 438 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 439 rte_delay_us(100); 440 continue; 441 } 442 443 /* Obtain the mutex */ 444 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 445 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 446 447 phy_data->comm_owned = 1; 448 return 0; 449 } 450 451 pthread_mutex_unlock(&pdata->phy_mutex); 452 453 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 454 455 return -ETIMEDOUT; 456 } 457 458 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 459 { 460 struct axgbe_phy_data *phy_data = pdata->phy_data; 461 462 if (phy_data->sfp_mod_absent) { 463 pdata->phy.speed = SPEED_UNKNOWN; 464 pdata->phy.duplex = DUPLEX_UNKNOWN; 465 pdata->phy.autoneg = AUTONEG_ENABLE; 466 pdata->phy.advertising = pdata->phy.supported; 467 } 468 469 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 470 pdata->phy.advertising &= ~ADVERTISED_TP; 471 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 472 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 473 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 474 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 475 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 476 477 switch (phy_data->sfp_base) { 478 case AXGBE_SFP_BASE_1000_T: 479 case AXGBE_SFP_BASE_1000_SX: 480 case AXGBE_SFP_BASE_1000_LX: 481 case AXGBE_SFP_BASE_1000_CX: 482 pdata->phy.speed = SPEED_UNKNOWN; 483 pdata->phy.duplex = DUPLEX_UNKNOWN; 484 pdata->phy.autoneg = AUTONEG_ENABLE; 485 pdata->phy.advertising |= ADVERTISED_Autoneg; 486 break; 487 case AXGBE_SFP_BASE_10000_SR: 488 case AXGBE_SFP_BASE_10000_LR: 489 case AXGBE_SFP_BASE_10000_LRM: 490 case AXGBE_SFP_BASE_10000_ER: 491 case AXGBE_SFP_BASE_10000_CR: 492 default: 493 pdata->phy.speed = SPEED_10000; 494 pdata->phy.duplex = DUPLEX_FULL; 495 pdata->phy.autoneg = AUTONEG_DISABLE; 496 break; 497 } 498 499 switch (phy_data->sfp_base) { 500 case AXGBE_SFP_BASE_1000_T: 501 case AXGBE_SFP_BASE_1000_CX: 502 case AXGBE_SFP_BASE_10000_CR: 503 pdata->phy.advertising |= ADVERTISED_TP; 504 break; 505 default: 506 pdata->phy.advertising |= ADVERTISED_FIBRE; 507 } 508 509 switch (phy_data->sfp_speed) { 510 case AXGBE_SFP_SPEED_100_1000: 511 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 512 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 513 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 514 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 515 break; 516 case AXGBE_SFP_SPEED_1000: 517 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 518 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 519 break; 520 case AXGBE_SFP_SPEED_10000: 521 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 522 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 523 break; 524 default: 525 /* Choose the fastest supported speed */ 526 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 527 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 528 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 529 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 530 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 531 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 532 } 533 } 534 535 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 536 enum axgbe_sfp_speed sfp_speed) 537 { 538 u8 *sfp_base, min, max; 539 540 sfp_base = sfp_eeprom->base; 541 542 switch (sfp_speed) { 543 case AXGBE_SFP_SPEED_1000: 544 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 545 max = AXGBE_SFP_BASE_BR_1GBE_MAX; 546 break; 547 case AXGBE_SFP_SPEED_10000: 548 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 549 max = AXGBE_SFP_BASE_BR_10GBE_MAX; 550 break; 551 default: 552 return false; 553 } 554 555 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) && 556 (sfp_base[AXGBE_SFP_BASE_BR] <= max)); 557 } 558 559 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 560 { 561 struct axgbe_phy_data *phy_data = pdata->phy_data; 562 563 if (!phy_data->sfp_changed) 564 return; 565 566 phy_data->sfp_phy_avail = 0; 567 568 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 569 return; 570 } 571 572 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 573 { 574 struct axgbe_phy_data *phy_data = pdata->phy_data; 575 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 576 577 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 578 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 579 return false; 580 581 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 582 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 583 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 584 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 585 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 586 return true; 587 } 588 589 return false; 590 } 591 592 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 593 { 594 if (axgbe_phy_belfuse_parse_quirks(pdata)) 595 return true; 596 597 return false; 598 } 599 600 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 601 { 602 struct axgbe_phy_data *phy_data = pdata->phy_data; 603 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 604 uint8_t *sfp_base; 605 606 sfp_base = sfp_eeprom->base; 607 608 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 609 return; 610 611 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 612 return; 613 614 axgbe_phy_sfp_parse_quirks(pdata); 615 616 /* Assume ACTIVE cable unless told it is PASSIVE */ 617 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 618 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 619 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 620 } else { 621 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 622 } 623 624 /* Determine the type of SFP */ 625 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 626 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 627 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 628 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 629 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 630 AXGBE_SFP_BASE_10GBE_CC_LRM) 631 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 632 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 633 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 634 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 635 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 636 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 637 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 638 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 639 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 640 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 641 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 642 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) && 643 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 644 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 645 646 switch (phy_data->sfp_base) { 647 case AXGBE_SFP_BASE_1000_T: 648 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 649 break; 650 case AXGBE_SFP_BASE_1000_SX: 651 case AXGBE_SFP_BASE_1000_LX: 652 case AXGBE_SFP_BASE_1000_CX: 653 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 654 break; 655 case AXGBE_SFP_BASE_10000_SR: 656 case AXGBE_SFP_BASE_10000_LR: 657 case AXGBE_SFP_BASE_10000_LRM: 658 case AXGBE_SFP_BASE_10000_ER: 659 case AXGBE_SFP_BASE_10000_CR: 660 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 661 break; 662 default: 663 break; 664 } 665 } 666 667 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 668 unsigned int len) 669 { 670 uint8_t cc; 671 672 for (cc = 0; len; buf++, len--) 673 cc += *buf; 674 675 return (cc == cc_in) ? true : false; 676 } 677 678 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 679 { 680 struct axgbe_phy_data *phy_data = pdata->phy_data; 681 struct axgbe_sfp_eeprom sfp_eeprom; 682 uint8_t eeprom_addr; 683 int ret; 684 685 ret = axgbe_phy_sfp_get_mux(pdata); 686 if (ret) { 687 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 688 return ret; 689 } 690 691 /* Read the SFP serial ID eeprom */ 692 eeprom_addr = 0; 693 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 694 &eeprom_addr, sizeof(eeprom_addr), 695 &sfp_eeprom, sizeof(sfp_eeprom)); 696 if (ret) { 697 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 698 goto put; 699 } 700 701 /* Validate the contents read */ 702 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 703 sfp_eeprom.base, 704 sizeof(sfp_eeprom.base) - 1)) { 705 ret = -EINVAL; 706 goto put; 707 } 708 709 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 710 sfp_eeprom.extd, 711 sizeof(sfp_eeprom.extd) - 1)) { 712 ret = -EINVAL; 713 goto put; 714 } 715 716 /* Check for an added or changed SFP */ 717 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 718 phy_data->sfp_changed = 1; 719 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 720 721 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) { 722 uint8_t diag_type; 723 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG]; 724 725 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 726 phy_data->sfp_diags = 1; 727 } 728 } else { 729 phy_data->sfp_changed = 0; 730 } 731 732 put: 733 axgbe_phy_sfp_put_mux(pdata); 734 735 return ret; 736 } 737 738 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 739 { 740 struct axgbe_phy_data *phy_data = pdata->phy_data; 741 unsigned int gpio_input; 742 u8 gpio_reg, gpio_ports[2]; 743 int ret; 744 745 /* Read the input port registers */ 746 gpio_reg = 0; 747 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 748 &gpio_reg, sizeof(gpio_reg), 749 gpio_ports, sizeof(gpio_ports)); 750 if (ret) { 751 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 752 return; 753 } 754 755 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 756 757 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 758 /* No GPIO, just assume the module is present for now */ 759 phy_data->sfp_mod_absent = 0; 760 } else { 761 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 762 phy_data->sfp_mod_absent = 0; 763 } 764 765 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 766 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 767 phy_data->sfp_rx_los = 1; 768 769 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 770 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 771 phy_data->sfp_tx_fault = 1; 772 } 773 774 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 775 { 776 struct axgbe_phy_data *phy_data = pdata->phy_data; 777 778 phy_data->sfp_mod_absent = 1; 779 phy_data->sfp_phy_avail = 0; 780 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 781 } 782 783 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 784 { 785 phy_data->sfp_rx_los = 0; 786 phy_data->sfp_tx_fault = 0; 787 phy_data->sfp_mod_absent = 1; 788 phy_data->sfp_diags = 0; 789 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 790 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 791 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 792 } 793 794 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base) 795 { 796 switch (sfp_base) { 797 case AXGBE_SFP_BASE_1000_T: 798 return "1G_T"; 799 case AXGBE_SFP_BASE_1000_SX: 800 return "1G_SX"; 801 case AXGBE_SFP_BASE_1000_LX: 802 return "1G_LX"; 803 case AXGBE_SFP_BASE_1000_CX: 804 return "1G_CX"; 805 case AXGBE_SFP_BASE_10000_SR: 806 return "10G_SR"; 807 case AXGBE_SFP_BASE_10000_LR: 808 return "10G_LR"; 809 case AXGBE_SFP_BASE_10000_LRM: 810 return "10G_LRM"; 811 case AXGBE_SFP_BASE_10000_ER: 812 return "10G_ER"; 813 case AXGBE_SFP_BASE_10000_CR: 814 return "10G_CR"; 815 default: 816 return "Unknown"; 817 } 818 } 819 820 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 821 { 822 struct axgbe_phy_data *phy_data = pdata->phy_data; 823 int ret; 824 825 /* Reset the SFP signals and info */ 826 axgbe_phy_sfp_reset(phy_data); 827 828 ret = axgbe_phy_get_comm_ownership(pdata); 829 if (ret) 830 return; 831 832 /* Read the SFP signals and check for module presence */ 833 axgbe_phy_sfp_signals(pdata); 834 if (phy_data->sfp_mod_absent) { 835 axgbe_phy_sfp_mod_absent(pdata); 836 goto put; 837 } 838 839 ret = axgbe_phy_sfp_read_eeprom(pdata); 840 if (ret) { 841 /* Treat any error as if there isn't an SFP plugged in */ 842 axgbe_phy_sfp_reset(phy_data); 843 axgbe_phy_sfp_mod_absent(pdata); 844 goto put; 845 } 846 847 axgbe_phy_sfp_parse_eeprom(pdata); 848 axgbe_phy_sfp_external_phy(pdata); 849 850 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n", 851 axgbe_base_as_string(phy_data->sfp_base)); 852 853 put: 854 axgbe_phy_sfp_phy_settings(pdata); 855 axgbe_phy_put_comm_ownership(pdata); 856 } 857 858 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 859 { 860 pdata->phy.tx_pause = 0; 861 pdata->phy.rx_pause = 0; 862 } 863 864 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 865 { 866 struct axgbe_phy_data *phy_data = pdata->phy_data; 867 enum axgbe_mode mode; 868 unsigned int ad_reg, lp_reg; 869 870 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 871 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 872 873 /* Use external PHY to determine flow control */ 874 if (pdata->phy.pause_autoneg) 875 axgbe_phy_phydev_flowctrl(pdata); 876 877 /* Compare Advertisement and Link Partner register 2 */ 878 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 879 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 880 if (lp_reg & 0x80) 881 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 882 if (lp_reg & 0x20) 883 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 884 885 ad_reg &= lp_reg; 886 if (ad_reg & 0x80) { 887 switch (phy_data->port_mode) { 888 case AXGBE_PORT_MODE_BACKPLANE: 889 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 890 mode = AXGBE_MODE_KR; 891 break; 892 default: 893 mode = AXGBE_MODE_SFI; 894 break; 895 } 896 } else if (ad_reg & 0x20) { 897 switch (phy_data->port_mode) { 898 case AXGBE_PORT_MODE_BACKPLANE: 899 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 900 mode = AXGBE_MODE_KX_1000; 901 break; 902 case AXGBE_PORT_MODE_1000BASE_X: 903 mode = AXGBE_MODE_X; 904 break; 905 case AXGBE_PORT_MODE_SFP: 906 switch (phy_data->sfp_base) { 907 case AXGBE_SFP_BASE_1000_T: 908 mode = AXGBE_MODE_SGMII_1000; 909 break; 910 case AXGBE_SFP_BASE_1000_SX: 911 case AXGBE_SFP_BASE_1000_LX: 912 case AXGBE_SFP_BASE_1000_CX: 913 default: 914 mode = AXGBE_MODE_X; 915 break; 916 } 917 break; 918 default: 919 mode = AXGBE_MODE_SGMII_1000; 920 break; 921 } 922 } else { 923 mode = AXGBE_MODE_UNKNOWN; 924 } 925 926 /* Compare Advertisement and Link Partner register 3 */ 927 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 928 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 929 if (lp_reg & 0xc000) 930 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 931 932 return mode; 933 } 934 935 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 936 { 937 enum axgbe_mode mode; 938 unsigned int ad_reg, lp_reg; 939 940 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 941 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 942 943 /* Compare Advertisement and Link Partner register 1 */ 944 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 945 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 946 if (lp_reg & 0x400) 947 pdata->phy.lp_advertising |= ADVERTISED_Pause; 948 if (lp_reg & 0x800) 949 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 950 951 if (pdata->phy.pause_autoneg) { 952 /* Set flow control based on auto-negotiation result */ 953 pdata->phy.tx_pause = 0; 954 pdata->phy.rx_pause = 0; 955 956 if (ad_reg & lp_reg & 0x400) { 957 pdata->phy.tx_pause = 1; 958 pdata->phy.rx_pause = 1; 959 } else if (ad_reg & lp_reg & 0x800) { 960 if (ad_reg & 0x400) 961 pdata->phy.rx_pause = 1; 962 else if (lp_reg & 0x400) 963 pdata->phy.tx_pause = 1; 964 } 965 } 966 967 /* Compare Advertisement and Link Partner register 2 */ 968 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 969 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 970 if (lp_reg & 0x80) 971 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 972 if (lp_reg & 0x20) 973 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 974 975 ad_reg &= lp_reg; 976 if (ad_reg & 0x80) 977 mode = AXGBE_MODE_KR; 978 else if (ad_reg & 0x20) 979 mode = AXGBE_MODE_KX_1000; 980 else 981 mode = AXGBE_MODE_UNKNOWN; 982 983 /* Compare Advertisement and Link Partner register 3 */ 984 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 985 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 986 if (lp_reg & 0xc000) 987 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 988 989 return mode; 990 } 991 992 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 993 { 994 enum axgbe_mode mode; 995 996 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 997 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 998 999 if (pdata->phy.pause_autoneg) 1000 axgbe_phy_phydev_flowctrl(pdata); 1001 1002 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 1003 case AXGBE_SGMII_AN_LINK_SPEED_100: 1004 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1005 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 1006 mode = AXGBE_MODE_SGMII_100; 1007 } else { 1008 mode = AXGBE_MODE_UNKNOWN; 1009 } 1010 break; 1011 case AXGBE_SGMII_AN_LINK_SPEED_1000: 1012 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1013 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1014 mode = AXGBE_MODE_SGMII_1000; 1015 } else { 1016 /* Half-duplex not supported */ 1017 mode = AXGBE_MODE_UNKNOWN; 1018 } 1019 break; 1020 default: 1021 mode = AXGBE_MODE_UNKNOWN; 1022 break; 1023 } 1024 return mode; 1025 } 1026 1027 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 1028 { 1029 switch (pdata->an_mode) { 1030 case AXGBE_AN_MODE_CL73: 1031 return axgbe_phy_an73_outcome(pdata); 1032 case AXGBE_AN_MODE_CL73_REDRV: 1033 return axgbe_phy_an73_redrv_outcome(pdata); 1034 case AXGBE_AN_MODE_CL37: 1035 case AXGBE_AN_MODE_CL37_SGMII: 1036 return axgbe_phy_an37_sgmii_outcome(pdata); 1037 default: 1038 return AXGBE_MODE_UNKNOWN; 1039 } 1040 } 1041 1042 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1043 { 1044 struct axgbe_phy_data *phy_data = pdata->phy_data; 1045 unsigned int advertising; 1046 1047 /* Without a re-driver, just return current advertising */ 1048 if (!phy_data->redrv) 1049 return pdata->phy.advertising; 1050 1051 /* With the KR re-driver we need to advertise a single speed */ 1052 advertising = pdata->phy.advertising; 1053 advertising &= ~ADVERTISED_1000baseKX_Full; 1054 advertising &= ~ADVERTISED_10000baseKR_Full; 1055 1056 switch (phy_data->port_mode) { 1057 case AXGBE_PORT_MODE_BACKPLANE: 1058 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1059 advertising |= ADVERTISED_10000baseKR_Full; 1060 break; 1061 case AXGBE_PORT_MODE_BACKPLANE_2500: 1062 advertising |= ADVERTISED_1000baseKX_Full; 1063 break; 1064 case AXGBE_PORT_MODE_1000BASE_T: 1065 case AXGBE_PORT_MODE_1000BASE_X: 1066 case AXGBE_PORT_MODE_NBASE_T: 1067 advertising |= ADVERTISED_1000baseKX_Full; 1068 break; 1069 case AXGBE_PORT_MODE_10GBASE_T: 1070 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1071 break; 1072 case AXGBE_PORT_MODE_10GBASE_R: 1073 advertising |= ADVERTISED_10000baseKR_Full; 1074 break; 1075 case AXGBE_PORT_MODE_SFP: 1076 switch (phy_data->sfp_base) { 1077 case AXGBE_SFP_BASE_1000_T: 1078 case AXGBE_SFP_BASE_1000_SX: 1079 case AXGBE_SFP_BASE_1000_LX: 1080 case AXGBE_SFP_BASE_1000_CX: 1081 advertising |= ADVERTISED_1000baseKX_Full; 1082 break; 1083 default: 1084 advertising |= ADVERTISED_10000baseKR_Full; 1085 break; 1086 } 1087 break; 1088 default: 1089 advertising |= ADVERTISED_10000baseKR_Full; 1090 break; 1091 } 1092 1093 return advertising; 1094 } 1095 1096 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1097 { 1098 return 0; 1099 /* Dummy API since there is no case to support 1100 * external phy devices registered through kernel APIs 1101 */ 1102 } 1103 1104 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1105 { 1106 switch (phy_data->sfp_base) { 1107 case AXGBE_SFP_BASE_1000_T: 1108 return AXGBE_AN_MODE_CL37_SGMII; 1109 case AXGBE_SFP_BASE_1000_SX: 1110 case AXGBE_SFP_BASE_1000_LX: 1111 case AXGBE_SFP_BASE_1000_CX: 1112 return AXGBE_AN_MODE_CL37; 1113 default: 1114 return AXGBE_AN_MODE_NONE; 1115 } 1116 } 1117 1118 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1119 { 1120 struct axgbe_phy_data *phy_data = pdata->phy_data; 1121 1122 /* A KR re-driver will always require CL73 AN */ 1123 if (phy_data->redrv) 1124 return AXGBE_AN_MODE_CL73_REDRV; 1125 1126 switch (phy_data->port_mode) { 1127 case AXGBE_PORT_MODE_BACKPLANE: 1128 return AXGBE_AN_MODE_CL73; 1129 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1130 case AXGBE_PORT_MODE_BACKPLANE_2500: 1131 return AXGBE_AN_MODE_NONE; 1132 case AXGBE_PORT_MODE_1000BASE_T: 1133 return AXGBE_AN_MODE_CL37_SGMII; 1134 case AXGBE_PORT_MODE_1000BASE_X: 1135 return AXGBE_AN_MODE_CL37; 1136 case AXGBE_PORT_MODE_NBASE_T: 1137 return AXGBE_AN_MODE_CL37_SGMII; 1138 case AXGBE_PORT_MODE_10GBASE_T: 1139 return AXGBE_AN_MODE_CL73; 1140 case AXGBE_PORT_MODE_10GBASE_R: 1141 return AXGBE_AN_MODE_NONE; 1142 case AXGBE_PORT_MODE_SFP: 1143 return axgbe_phy_an_sfp_mode(phy_data); 1144 default: 1145 return AXGBE_AN_MODE_NONE; 1146 } 1147 } 1148 1149 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1150 enum axgbe_phy_redrv_mode mode) 1151 { 1152 struct axgbe_phy_data *phy_data = pdata->phy_data; 1153 u16 redrv_reg, redrv_val; 1154 1155 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1156 redrv_val = (u16)mode; 1157 1158 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1159 redrv_reg, redrv_val); 1160 } 1161 1162 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1163 enum axgbe_phy_redrv_mode mode) 1164 { 1165 struct axgbe_phy_data *phy_data = pdata->phy_data; 1166 unsigned int redrv_reg; 1167 int ret; 1168 1169 /* Calculate the register to write */ 1170 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1171 1172 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1173 1174 return ret; 1175 } 1176 1177 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1178 { 1179 struct axgbe_phy_data *phy_data = pdata->phy_data; 1180 enum axgbe_phy_redrv_mode mode; 1181 int ret; 1182 1183 if (!phy_data->redrv) 1184 return; 1185 1186 mode = AXGBE_PHY_REDRV_MODE_CX; 1187 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1188 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1189 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1190 mode = AXGBE_PHY_REDRV_MODE_SR; 1191 1192 ret = axgbe_phy_get_comm_ownership(pdata); 1193 if (ret) 1194 return; 1195 1196 if (phy_data->redrv_if) 1197 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1198 else 1199 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1200 1201 axgbe_phy_put_comm_ownership(pdata); 1202 } 1203 1204 static void axgbe_phy_rx_reset(struct axgbe_port *pdata) 1205 { 1206 int reg; 1207 1208 reg = XMDIO_READ_BITS(pdata, MDIO_MMD_PCS, MDIO_PCS_DIGITAL_STAT, 1209 XGBE_PCS_PSEQ_STATE_MASK); 1210 if (reg == XGBE_PCS_PSEQ_STATE_POWER_GOOD) { 1211 /* Mailbox command timed out, reset of RX block is required. 1212 * This can be done by asseting the reset bit and wait for 1213 * its compeletion. 1214 */ 1215 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1216 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_ON); 1217 rte_delay_us(20); 1218 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_PMA_RX_CTRL1, 1219 XGBE_PMA_RX_RST_0_MASK, XGBE_PMA_RX_RST_0_RESET_OFF); 1220 rte_delay_us(45); 1221 PMD_DRV_LOG(ERR, "firmware mailbox reset performed\n"); 1222 } 1223 } 1224 1225 1226 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) 1227 { 1228 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1229 XGBE_PMA_PLL_CTRL_MASK, 1230 enable ? XGBE_PMA_PLL_CTRL_SET 1231 : XGBE_PMA_PLL_CTRL_CLEAR); 1232 1233 /* Wait for command to complete */ 1234 rte_delay_us(150); 1235 } 1236 1237 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, 1238 unsigned int cmd, unsigned int sub_cmd) 1239 { 1240 unsigned int s0 = 0; 1241 unsigned int wait; 1242 /* Clear the PLL so that it helps in power down sequence */ 1243 axgbe_phy_pll_ctrl(pdata, false); 1244 1245 /* Log if a previous command did not complete */ 1246 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) { 1247 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); 1248 axgbe_phy_rx_reset(pdata); 1249 } 1250 1251 /* Construct the command */ 1252 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1253 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1254 1255 /* Issue the command */ 1256 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1257 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1258 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1259 1260 /* Wait for command to complete */ 1261 wait = AXGBE_RATECHANGE_COUNT; 1262 while (wait--) { 1263 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1264 goto reenable_pll; 1265 rte_delay_us(1500); 1266 } 1267 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1268 /* Reset on error */ 1269 axgbe_phy_rx_reset(pdata); 1270 1271 reenable_pll: 1272 /* Re-enable the PLL control */ 1273 axgbe_phy_pll_ctrl(pdata, true); 1274 1275 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1276 } 1277 1278 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1279 { 1280 1281 1282 /* Receiver Reset Cycle */ 1283 axgbe_phy_perform_ratechange(pdata, 5, 0); 1284 1285 PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); 1286 } 1287 1288 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1289 { 1290 struct axgbe_phy_data *phy_data = pdata->phy_data; 1291 1292 /* Power off */ 1293 axgbe_phy_perform_ratechange(pdata, 0, 0); 1294 1295 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1296 1297 PMD_DRV_LOG(DEBUG, "phy powered off\n"); 1298 } 1299 1300 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1301 { 1302 struct axgbe_phy_data *phy_data = pdata->phy_data; 1303 1304 axgbe_phy_set_redrv_mode(pdata); 1305 1306 /* 10G/SFI */ 1307 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1308 axgbe_phy_perform_ratechange(pdata, 3, 0); 1309 } else { 1310 if (phy_data->sfp_cable_len <= 1) 1311 axgbe_phy_perform_ratechange(pdata, 3, 1); 1312 else if (phy_data->sfp_cable_len <= 3) 1313 axgbe_phy_perform_ratechange(pdata, 3, 2); 1314 else 1315 axgbe_phy_perform_ratechange(pdata, 3, 3); 1316 } 1317 1318 phy_data->cur_mode = AXGBE_MODE_SFI; 1319 1320 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); 1321 } 1322 1323 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1324 { 1325 struct axgbe_phy_data *phy_data = pdata->phy_data; 1326 1327 axgbe_phy_set_redrv_mode(pdata); 1328 1329 /* 10G/KR */ 1330 axgbe_phy_perform_ratechange(pdata, 4, 0); 1331 phy_data->cur_mode = AXGBE_MODE_KR; 1332 1333 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); 1334 } 1335 1336 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1337 { 1338 struct axgbe_phy_data *phy_data = pdata->phy_data; 1339 1340 axgbe_phy_set_redrv_mode(pdata); 1341 1342 /* 2.5G/KX */ 1343 axgbe_phy_perform_ratechange(pdata, 2, 0); 1344 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1345 } 1346 1347 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1348 { 1349 struct axgbe_phy_data *phy_data = pdata->phy_data; 1350 1351 axgbe_phy_set_redrv_mode(pdata); 1352 1353 /* 1G/SGMII */ 1354 axgbe_phy_perform_ratechange(pdata, 1, 2); 1355 1356 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1357 } 1358 1359 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1360 { 1361 struct axgbe_phy_data *phy_data = pdata->phy_data; 1362 1363 return phy_data->cur_mode; 1364 } 1365 1366 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1367 { 1368 struct axgbe_phy_data *phy_data = pdata->phy_data; 1369 1370 /* No switching if not 10GBase-T */ 1371 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1372 return axgbe_phy_cur_mode(pdata); 1373 1374 switch (axgbe_phy_cur_mode(pdata)) { 1375 case AXGBE_MODE_SGMII_100: 1376 case AXGBE_MODE_SGMII_1000: 1377 return AXGBE_MODE_KR; 1378 case AXGBE_MODE_KR: 1379 default: 1380 return AXGBE_MODE_SGMII_1000; 1381 } 1382 } 1383 1384 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1385 __rte_unused) 1386 { 1387 return AXGBE_MODE_KX_2500; 1388 } 1389 1390 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1391 { 1392 /* If we are in KR switch to KX, and vice-versa */ 1393 switch (axgbe_phy_cur_mode(pdata)) { 1394 case AXGBE_MODE_KX_1000: 1395 return AXGBE_MODE_KR; 1396 case AXGBE_MODE_KR: 1397 default: 1398 return AXGBE_MODE_KX_1000; 1399 } 1400 } 1401 1402 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1403 { 1404 struct axgbe_phy_data *phy_data = pdata->phy_data; 1405 1406 switch (phy_data->port_mode) { 1407 case AXGBE_PORT_MODE_BACKPLANE: 1408 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1409 return axgbe_phy_switch_bp_mode(pdata); 1410 case AXGBE_PORT_MODE_BACKPLANE_2500: 1411 return axgbe_phy_switch_bp_2500_mode(pdata); 1412 case AXGBE_PORT_MODE_1000BASE_T: 1413 case AXGBE_PORT_MODE_NBASE_T: 1414 case AXGBE_PORT_MODE_10GBASE_T: 1415 return axgbe_phy_switch_baset_mode(pdata); 1416 case AXGBE_PORT_MODE_1000BASE_X: 1417 case AXGBE_PORT_MODE_10GBASE_R: 1418 case AXGBE_PORT_MODE_SFP: 1419 /* No switching, so just return current mode */ 1420 return axgbe_phy_cur_mode(pdata); 1421 default: 1422 return AXGBE_MODE_UNKNOWN; 1423 } 1424 } 1425 1426 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1427 __rte_unused, 1428 int speed) 1429 { 1430 switch (speed) { 1431 case SPEED_1000: 1432 return AXGBE_MODE_X; 1433 case SPEED_10000: 1434 return AXGBE_MODE_KR; 1435 default: 1436 return AXGBE_MODE_UNKNOWN; 1437 } 1438 } 1439 1440 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1441 __rte_unused, 1442 int speed) 1443 { 1444 switch (speed) { 1445 case SPEED_100: 1446 return AXGBE_MODE_SGMII_100; 1447 case SPEED_1000: 1448 return AXGBE_MODE_SGMII_1000; 1449 case SPEED_10000: 1450 return AXGBE_MODE_KR; 1451 default: 1452 return AXGBE_MODE_UNKNOWN; 1453 } 1454 } 1455 1456 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1457 int speed) 1458 { 1459 switch (speed) { 1460 case SPEED_100: 1461 return AXGBE_MODE_SGMII_100; 1462 case SPEED_1000: 1463 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1464 return AXGBE_MODE_SGMII_1000; 1465 else 1466 return AXGBE_MODE_X; 1467 case SPEED_10000: 1468 case SPEED_UNKNOWN: 1469 return AXGBE_MODE_SFI; 1470 default: 1471 return AXGBE_MODE_UNKNOWN; 1472 } 1473 } 1474 1475 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1476 { 1477 switch (speed) { 1478 case SPEED_2500: 1479 return AXGBE_MODE_KX_2500; 1480 default: 1481 return AXGBE_MODE_UNKNOWN; 1482 } 1483 } 1484 1485 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1486 { 1487 switch (speed) { 1488 case SPEED_1000: 1489 return AXGBE_MODE_KX_1000; 1490 case SPEED_10000: 1491 return AXGBE_MODE_KR; 1492 default: 1493 return AXGBE_MODE_UNKNOWN; 1494 } 1495 } 1496 1497 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1498 int speed) 1499 { 1500 struct axgbe_phy_data *phy_data = pdata->phy_data; 1501 1502 switch (phy_data->port_mode) { 1503 case AXGBE_PORT_MODE_BACKPLANE: 1504 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1505 return axgbe_phy_get_bp_mode(speed); 1506 case AXGBE_PORT_MODE_BACKPLANE_2500: 1507 return axgbe_phy_get_bp_2500_mode(speed); 1508 case AXGBE_PORT_MODE_1000BASE_T: 1509 case AXGBE_PORT_MODE_NBASE_T: 1510 case AXGBE_PORT_MODE_10GBASE_T: 1511 return axgbe_phy_get_baset_mode(phy_data, speed); 1512 case AXGBE_PORT_MODE_1000BASE_X: 1513 case AXGBE_PORT_MODE_10GBASE_R: 1514 return axgbe_phy_get_basex_mode(phy_data, speed); 1515 case AXGBE_PORT_MODE_SFP: 1516 return axgbe_phy_get_sfp_mode(phy_data, speed); 1517 default: 1518 return AXGBE_MODE_UNKNOWN; 1519 } 1520 } 1521 1522 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1523 { 1524 switch (mode) { 1525 case AXGBE_MODE_KR: 1526 axgbe_phy_kr_mode(pdata); 1527 break; 1528 case AXGBE_MODE_SFI: 1529 axgbe_phy_sfi_mode(pdata); 1530 break; 1531 case AXGBE_MODE_KX_2500: 1532 axgbe_phy_kx_2500_mode(pdata); 1533 break; 1534 case AXGBE_MODE_SGMII_1000: 1535 axgbe_phy_sgmii_1000_mode(pdata); 1536 break; 1537 default: 1538 break; 1539 } 1540 } 1541 1542 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1543 enum axgbe_mode mode, u32 advert) 1544 { 1545 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1546 if (pdata->phy.advertising & advert) 1547 return true; 1548 } else { 1549 enum axgbe_mode cur_mode; 1550 1551 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1552 if (cur_mode == mode) 1553 return true; 1554 } 1555 1556 return false; 1557 } 1558 1559 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1560 enum axgbe_mode mode) 1561 { 1562 switch (mode) { 1563 case AXGBE_MODE_X: 1564 return axgbe_phy_check_mode(pdata, mode, 1565 ADVERTISED_1000baseT_Full); 1566 case AXGBE_MODE_KR: 1567 return axgbe_phy_check_mode(pdata, mode, 1568 ADVERTISED_10000baseT_Full); 1569 default: 1570 return false; 1571 } 1572 } 1573 1574 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1575 enum axgbe_mode mode) 1576 { 1577 switch (mode) { 1578 case AXGBE_MODE_SGMII_100: 1579 return axgbe_phy_check_mode(pdata, mode, 1580 ADVERTISED_100baseT_Full); 1581 case AXGBE_MODE_SGMII_1000: 1582 return axgbe_phy_check_mode(pdata, mode, 1583 ADVERTISED_1000baseT_Full); 1584 case AXGBE_MODE_KR: 1585 return axgbe_phy_check_mode(pdata, mode, 1586 ADVERTISED_10000baseT_Full); 1587 default: 1588 return false; 1589 } 1590 } 1591 1592 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1593 enum axgbe_mode mode) 1594 { 1595 struct axgbe_phy_data *phy_data = pdata->phy_data; 1596 1597 switch (mode) { 1598 case AXGBE_MODE_X: 1599 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1600 return false; 1601 return axgbe_phy_check_mode(pdata, mode, 1602 ADVERTISED_1000baseT_Full); 1603 case AXGBE_MODE_SGMII_100: 1604 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1605 return false; 1606 return axgbe_phy_check_mode(pdata, mode, 1607 ADVERTISED_100baseT_Full); 1608 case AXGBE_MODE_SGMII_1000: 1609 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1610 return false; 1611 return axgbe_phy_check_mode(pdata, mode, 1612 ADVERTISED_1000baseT_Full); 1613 case AXGBE_MODE_SFI: 1614 return axgbe_phy_check_mode(pdata, mode, 1615 ADVERTISED_10000baseT_Full); 1616 default: 1617 return false; 1618 } 1619 } 1620 1621 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1622 enum axgbe_mode mode) 1623 { 1624 switch (mode) { 1625 case AXGBE_MODE_KX_2500: 1626 return axgbe_phy_check_mode(pdata, mode, 1627 ADVERTISED_2500baseX_Full); 1628 default: 1629 return false; 1630 } 1631 } 1632 1633 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1634 enum axgbe_mode mode) 1635 { 1636 switch (mode) { 1637 case AXGBE_MODE_KX_1000: 1638 return axgbe_phy_check_mode(pdata, mode, 1639 ADVERTISED_1000baseKX_Full); 1640 case AXGBE_MODE_KR: 1641 return axgbe_phy_check_mode(pdata, mode, 1642 ADVERTISED_10000baseKR_Full); 1643 default: 1644 return false; 1645 } 1646 } 1647 1648 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1649 { 1650 struct axgbe_phy_data *phy_data = pdata->phy_data; 1651 1652 switch (phy_data->port_mode) { 1653 case AXGBE_PORT_MODE_BACKPLANE: 1654 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1655 return axgbe_phy_use_bp_mode(pdata, mode); 1656 case AXGBE_PORT_MODE_BACKPLANE_2500: 1657 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1658 case AXGBE_PORT_MODE_1000BASE_T: 1659 case AXGBE_PORT_MODE_NBASE_T: 1660 case AXGBE_PORT_MODE_10GBASE_T: 1661 return axgbe_phy_use_baset_mode(pdata, mode); 1662 case AXGBE_PORT_MODE_1000BASE_X: 1663 case AXGBE_PORT_MODE_10GBASE_R: 1664 return axgbe_phy_use_basex_mode(pdata, mode); 1665 case AXGBE_PORT_MODE_SFP: 1666 return axgbe_phy_use_sfp_mode(pdata, mode); 1667 default: 1668 return false; 1669 } 1670 } 1671 1672 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1673 { 1674 struct axgbe_phy_data *phy_data = pdata->phy_data; 1675 unsigned int reg; 1676 1677 *an_restart = 0; 1678 1679 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1680 /* Check SFP signals */ 1681 axgbe_phy_sfp_detect(pdata); 1682 1683 if (phy_data->sfp_changed) { 1684 *an_restart = 1; 1685 return 0; 1686 } 1687 1688 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1689 return 0; 1690 } 1691 1692 /* Link status is latched low, so read once to clear 1693 * and then read again to get current state 1694 */ 1695 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1696 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1697 if (reg & MDIO_STAT1_LSTATUS) 1698 return 1; 1699 1700 /* No link, attempt a receiver reset cycle */ 1701 if (phy_data->rrc_count++) { 1702 phy_data->rrc_count = 0; 1703 axgbe_phy_rrc(pdata); 1704 } 1705 1706 return 0; 1707 } 1708 1709 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1710 { 1711 struct axgbe_phy_data *phy_data = pdata->phy_data; 1712 unsigned int reg; 1713 1714 reg = XP_IOREAD(pdata, XP_PROP_3); 1715 1716 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1717 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 1718 1719 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 1720 1721 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 1722 GPIO_RX_LOS); 1723 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 1724 GPIO_TX_FAULT); 1725 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 1726 GPIO_MOD_ABS); 1727 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 1728 GPIO_RATE_SELECT); 1729 } 1730 1731 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1732 { 1733 struct axgbe_phy_data *phy_data = pdata->phy_data; 1734 unsigned int reg, mux_addr_hi, mux_addr_lo; 1735 1736 reg = XP_IOREAD(pdata, XP_PROP_4); 1737 1738 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 1739 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 1740 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1741 return; 1742 1743 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1744 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1745 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 1746 } 1747 1748 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1749 { 1750 axgbe_phy_sfp_comm_setup(pdata); 1751 axgbe_phy_sfp_gpio_setup(pdata); 1752 } 1753 1754 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1755 { 1756 if (!phy_data->redrv) 1757 return false; 1758 1759 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1760 return true; 1761 1762 switch (phy_data->redrv_model) { 1763 case AXGBE_PHY_REDRV_MODEL_4223: 1764 if (phy_data->redrv_lane > 3) 1765 return true; 1766 break; 1767 case AXGBE_PHY_REDRV_MODEL_4227: 1768 if (phy_data->redrv_lane > 1) 1769 return true; 1770 break; 1771 default: 1772 return true; 1773 } 1774 1775 return false; 1776 } 1777 1778 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1779 { 1780 struct axgbe_phy_data *phy_data = pdata->phy_data; 1781 unsigned int reg; 1782 1783 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1784 return 0; 1785 reg = XP_IOREAD(pdata, XP_PROP_3); 1786 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 1787 switch (phy_data->mdio_reset) { 1788 case AXGBE_MDIO_RESET_NONE: 1789 case AXGBE_MDIO_RESET_I2C_GPIO: 1790 case AXGBE_MDIO_RESET_INT_GPIO: 1791 break; 1792 default: 1793 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1794 phy_data->mdio_reset); 1795 return -EINVAL; 1796 } 1797 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1798 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1799 XP_GET_BITS(reg, XP_PROP_3, 1800 MDIO_RESET_I2C_ADDR); 1801 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1802 MDIO_RESET_I2C_GPIO); 1803 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1804 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1805 MDIO_RESET_INT_GPIO); 1806 } 1807 1808 return 0; 1809 } 1810 1811 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1812 { 1813 struct axgbe_phy_data *phy_data = pdata->phy_data; 1814 1815 switch (phy_data->port_mode) { 1816 case AXGBE_PORT_MODE_BACKPLANE: 1817 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1818 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1819 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1820 return false; 1821 break; 1822 case AXGBE_PORT_MODE_BACKPLANE_2500: 1823 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1824 return false; 1825 break; 1826 case AXGBE_PORT_MODE_1000BASE_T: 1827 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1828 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1829 return false; 1830 break; 1831 case AXGBE_PORT_MODE_1000BASE_X: 1832 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1833 return false; 1834 break; 1835 case AXGBE_PORT_MODE_NBASE_T: 1836 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1837 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1838 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1839 return false; 1840 break; 1841 case AXGBE_PORT_MODE_10GBASE_T: 1842 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1843 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1844 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1845 return false; 1846 break; 1847 case AXGBE_PORT_MODE_10GBASE_R: 1848 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1849 return false; 1850 break; 1851 case AXGBE_PORT_MODE_SFP: 1852 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1853 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1854 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1855 return false; 1856 break; 1857 default: 1858 break; 1859 } 1860 1861 return true; 1862 } 1863 1864 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1865 { 1866 struct axgbe_phy_data *phy_data = pdata->phy_data; 1867 1868 switch (phy_data->port_mode) { 1869 case AXGBE_PORT_MODE_BACKPLANE: 1870 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 1871 case AXGBE_PORT_MODE_BACKPLANE_2500: 1872 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1873 return false; 1874 break; 1875 case AXGBE_PORT_MODE_1000BASE_T: 1876 case AXGBE_PORT_MODE_1000BASE_X: 1877 case AXGBE_PORT_MODE_NBASE_T: 1878 case AXGBE_PORT_MODE_10GBASE_T: 1879 case AXGBE_PORT_MODE_10GBASE_R: 1880 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1881 return false; 1882 break; 1883 case AXGBE_PORT_MODE_SFP: 1884 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1885 return false; 1886 break; 1887 default: 1888 break; 1889 } 1890 1891 return true; 1892 } 1893 1894 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1895 { 1896 unsigned int reg; 1897 1898 reg = XP_IOREAD(pdata, XP_PROP_0); 1899 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 1900 return false; 1901 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 1902 return false; 1903 1904 return true; 1905 } 1906 1907 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1908 { 1909 struct axgbe_phy_data *phy_data = pdata->phy_data; 1910 1911 if (!pdata->vdata->an_cdr_workaround) 1912 return; 1913 1914 if (!phy_data->phy_cdr_notrack) 1915 return; 1916 1917 rte_delay_us(phy_data->phy_cdr_delay + 400); 1918 1919 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1920 AXGBE_PMA_CDR_TRACK_EN_MASK, 1921 AXGBE_PMA_CDR_TRACK_EN_ON); 1922 1923 phy_data->phy_cdr_notrack = 0; 1924 } 1925 1926 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1927 { 1928 struct axgbe_phy_data *phy_data = pdata->phy_data; 1929 1930 if (!pdata->vdata->an_cdr_workaround) 1931 return; 1932 1933 if (phy_data->phy_cdr_notrack) 1934 return; 1935 1936 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1937 AXGBE_PMA_CDR_TRACK_EN_MASK, 1938 AXGBE_PMA_CDR_TRACK_EN_OFF); 1939 1940 axgbe_phy_rrc(pdata); 1941 1942 phy_data->phy_cdr_notrack = 1; 1943 } 1944 1945 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1946 { 1947 if (!pdata->cdr_track_early) 1948 axgbe_phy_cdr_track(pdata); 1949 } 1950 1951 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1952 { 1953 if (pdata->cdr_track_early) 1954 axgbe_phy_cdr_track(pdata); 1955 } 1956 1957 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1958 { 1959 struct axgbe_phy_data *phy_data = pdata->phy_data; 1960 1961 switch (pdata->an_mode) { 1962 case AXGBE_AN_MODE_CL73: 1963 case AXGBE_AN_MODE_CL73_REDRV: 1964 if (phy_data->cur_mode != AXGBE_MODE_KR) 1965 break; 1966 1967 axgbe_phy_cdr_track(pdata); 1968 1969 switch (pdata->an_result) { 1970 case AXGBE_AN_READY: 1971 case AXGBE_AN_COMPLETE: 1972 break; 1973 default: 1974 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1975 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1976 break; 1977 } 1978 break; 1979 default: 1980 break; 1981 } 1982 } 1983 1984 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1985 { 1986 struct axgbe_phy_data *phy_data = pdata->phy_data; 1987 1988 switch (pdata->an_mode) { 1989 case AXGBE_AN_MODE_CL73: 1990 case AXGBE_AN_MODE_CL73_REDRV: 1991 if (phy_data->cur_mode != AXGBE_MODE_KR) 1992 break; 1993 1994 axgbe_phy_cdr_notrack(pdata); 1995 break; 1996 default: 1997 break; 1998 } 1999 } 2000 2001 static void axgbe_phy_stop(struct axgbe_port *pdata) 2002 { 2003 struct axgbe_phy_data *phy_data = pdata->phy_data; 2004 2005 /* Reset SFP data */ 2006 axgbe_phy_sfp_reset(phy_data); 2007 axgbe_phy_sfp_mod_absent(pdata); 2008 2009 /* Reset CDR support */ 2010 axgbe_phy_cdr_track(pdata); 2011 2012 /* Power off the PHY */ 2013 axgbe_phy_power_off(pdata); 2014 2015 /* Stop the I2C controller */ 2016 pdata->i2c_if.i2c_stop(pdata); 2017 } 2018 2019 static int axgbe_phy_start(struct axgbe_port *pdata) 2020 { 2021 struct axgbe_phy_data *phy_data = pdata->phy_data; 2022 int ret; 2023 2024 /* Start the I2C controller */ 2025 ret = pdata->i2c_if.i2c_start(pdata); 2026 if (ret) 2027 return ret; 2028 2029 /* Start in highest supported mode */ 2030 axgbe_phy_set_mode(pdata, phy_data->start_mode); 2031 2032 /* Reset CDR support */ 2033 axgbe_phy_cdr_track(pdata); 2034 2035 /* After starting the I2C controller, we can check for an SFP */ 2036 switch (phy_data->port_mode) { 2037 case AXGBE_PORT_MODE_SFP: 2038 axgbe_phy_sfp_detect(pdata); 2039 break; 2040 default: 2041 break; 2042 } 2043 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 2044 2045 return ret; 2046 } 2047 2048 static int axgbe_phy_reset(struct axgbe_port *pdata) 2049 { 2050 struct axgbe_phy_data *phy_data = pdata->phy_data; 2051 enum axgbe_mode cur_mode; 2052 2053 /* Reset by power cycling the PHY */ 2054 cur_mode = phy_data->cur_mode; 2055 axgbe_phy_power_off(pdata); 2056 /* First time reset is done with passed unknown mode*/ 2057 axgbe_phy_set_mode(pdata, cur_mode); 2058 return 0; 2059 } 2060 2061 static int axgbe_phy_init(struct axgbe_port *pdata) 2062 { 2063 struct axgbe_phy_data *phy_data; 2064 unsigned int reg; 2065 int ret; 2066 2067 /* Check if enabled */ 2068 if (!axgbe_phy_port_enabled(pdata)) { 2069 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2070 return -ENODEV; 2071 } 2072 2073 /* Initialize the I2C controller */ 2074 ret = pdata->i2c_if.i2c_init(pdata); 2075 if (ret) 2076 return ret; 2077 2078 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2079 if (!phy_data) { 2080 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2081 return -ENOMEM; 2082 } 2083 pdata->phy_data = phy_data; 2084 2085 reg = XP_IOREAD(pdata, XP_PROP_0); 2086 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2087 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2088 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2089 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2090 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2091 2092 reg = XP_IOREAD(pdata, XP_PROP_4); 2093 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2094 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2095 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2096 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2097 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2098 2099 /* Validate the connection requested */ 2100 if (axgbe_phy_conn_type_mismatch(pdata)) { 2101 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2102 phy_data->port_mode, phy_data->conn_type); 2103 return -EINVAL; 2104 } 2105 2106 /* Validate the mode requested */ 2107 if (axgbe_phy_port_mode_mismatch(pdata)) { 2108 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2109 phy_data->port_mode, phy_data->port_speeds); 2110 return -EINVAL; 2111 } 2112 2113 /* Check for and validate MDIO reset support */ 2114 ret = axgbe_phy_mdio_reset_setup(pdata); 2115 if (ret) 2116 return ret; 2117 2118 /* Validate the re-driver information */ 2119 if (axgbe_phy_redrv_error(phy_data)) { 2120 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2121 return -EINVAL; 2122 } 2123 pdata->kr_redrv = phy_data->redrv; 2124 2125 /* Indicate current mode is unknown */ 2126 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2127 2128 /* Initialize supported features */ 2129 pdata->phy.supported = 0; 2130 2131 switch (phy_data->port_mode) { 2132 /* Backplane support */ 2133 case AXGBE_PORT_MODE_BACKPLANE: 2134 pdata->phy.supported |= SUPPORTED_Autoneg; 2135 /* Fallthrough */ 2136 case AXGBE_PORT_MODE_BACKPLANE_NO_AUTONEG: 2137 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2138 pdata->phy.supported |= SUPPORTED_Backplane; 2139 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2140 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2141 phy_data->start_mode = AXGBE_MODE_KX_1000; 2142 } 2143 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2144 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2145 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2146 pdata->phy.supported |= 2147 SUPPORTED_10000baseR_FEC; 2148 phy_data->start_mode = AXGBE_MODE_KR; 2149 } 2150 2151 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2152 break; 2153 case AXGBE_PORT_MODE_BACKPLANE_2500: 2154 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2155 pdata->phy.supported |= SUPPORTED_Backplane; 2156 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2157 phy_data->start_mode = AXGBE_MODE_KX_2500; 2158 2159 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2160 break; 2161 2162 /* MDIO 1GBase-T support */ 2163 case AXGBE_PORT_MODE_1000BASE_T: 2164 pdata->phy.supported |= SUPPORTED_Autoneg; 2165 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2166 pdata->phy.supported |= SUPPORTED_TP; 2167 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2168 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2169 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2170 } 2171 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2172 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2173 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2174 } 2175 2176 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2177 break; 2178 2179 /* MDIO Base-X support */ 2180 case AXGBE_PORT_MODE_1000BASE_X: 2181 pdata->phy.supported |= SUPPORTED_Autoneg; 2182 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2183 pdata->phy.supported |= SUPPORTED_FIBRE; 2184 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2185 phy_data->start_mode = AXGBE_MODE_X; 2186 2187 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2188 break; 2189 2190 /* MDIO NBase-T support */ 2191 case AXGBE_PORT_MODE_NBASE_T: 2192 pdata->phy.supported |= SUPPORTED_Autoneg; 2193 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2194 pdata->phy.supported |= SUPPORTED_TP; 2195 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2196 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2197 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2198 } 2199 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2200 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2201 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2202 } 2203 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2204 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2205 phy_data->start_mode = AXGBE_MODE_KX_2500; 2206 } 2207 2208 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2209 break; 2210 2211 /* 10GBase-T support */ 2212 case AXGBE_PORT_MODE_10GBASE_T: 2213 pdata->phy.supported |= SUPPORTED_Autoneg; 2214 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2215 pdata->phy.supported |= SUPPORTED_TP; 2216 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2217 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2218 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2219 } 2220 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2221 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2222 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2223 } 2224 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2225 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2226 phy_data->start_mode = AXGBE_MODE_KR; 2227 } 2228 2229 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2230 break; 2231 2232 /* 10GBase-R support */ 2233 case AXGBE_PORT_MODE_10GBASE_R: 2234 pdata->phy.supported |= SUPPORTED_Autoneg; 2235 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2236 pdata->phy.supported |= SUPPORTED_TP; 2237 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2238 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2239 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2240 phy_data->start_mode = AXGBE_MODE_SFI; 2241 2242 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2243 break; 2244 2245 /* SFP support */ 2246 case AXGBE_PORT_MODE_SFP: 2247 pdata->phy.supported |= SUPPORTED_Autoneg; 2248 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2249 pdata->phy.supported |= SUPPORTED_TP; 2250 pdata->phy.supported |= SUPPORTED_FIBRE; 2251 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2252 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2253 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2254 } 2255 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2256 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2257 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2258 } 2259 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2260 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2261 phy_data->start_mode = AXGBE_MODE_SFI; 2262 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2263 pdata->phy.supported |= 2264 SUPPORTED_10000baseR_FEC; 2265 } 2266 2267 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2268 2269 axgbe_phy_sfp_setup(pdata); 2270 break; 2271 default: 2272 return -EINVAL; 2273 } 2274 2275 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2276 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2277 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2278 phy_data->phydev_mode); 2279 if (ret) { 2280 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2281 phy_data->mdio_addr, phy_data->phydev_mode); 2282 return -EINVAL; 2283 } 2284 } 2285 2286 if (phy_data->redrv && !phy_data->redrv_if) { 2287 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2288 AXGBE_MDIO_MODE_CL22); 2289 if (ret) { 2290 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2291 phy_data->redrv_addr); 2292 return -EINVAL; 2293 } 2294 } 2295 2296 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2297 return 0; 2298 } 2299 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2300 { 2301 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2302 2303 phy_impl->init = axgbe_phy_init; 2304 phy_impl->reset = axgbe_phy_reset; 2305 phy_impl->start = axgbe_phy_start; 2306 phy_impl->stop = axgbe_phy_stop; 2307 phy_impl->link_status = axgbe_phy_link_status; 2308 phy_impl->use_mode = axgbe_phy_use_mode; 2309 phy_impl->set_mode = axgbe_phy_set_mode; 2310 phy_impl->get_mode = axgbe_phy_get_mode; 2311 phy_impl->switch_mode = axgbe_phy_switch_mode; 2312 phy_impl->cur_mode = axgbe_phy_cur_mode; 2313 phy_impl->an_mode = axgbe_phy_an_mode; 2314 phy_impl->an_config = axgbe_phy_an_config; 2315 phy_impl->an_advertising = axgbe_phy_an_advertising; 2316 phy_impl->an_outcome = axgbe_phy_an_outcome; 2317 2318 phy_impl->an_pre = axgbe_phy_an_pre; 2319 phy_impl->an_post = axgbe_phy_an_post; 2320 2321 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2322 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2323 } 2324