1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. 3 * Copyright(c) 2018 Synopsys, Inc. All rights reserved. 4 */ 5 6 #include "axgbe_ethdev.h" 7 #include "axgbe_common.h" 8 #include "axgbe_phy.h" 9 10 #define AXGBE_PHY_PORT_SPEED_100 BIT(0) 11 #define AXGBE_PHY_PORT_SPEED_1000 BIT(1) 12 #define AXGBE_PHY_PORT_SPEED_2500 BIT(2) 13 #define AXGBE_PHY_PORT_SPEED_10000 BIT(3) 14 15 #define AXGBE_MUTEX_RELEASE 0x80000000 16 17 #define AXGBE_SFP_DIRECT 7 18 19 /* I2C target addresses */ 20 #define AXGBE_SFP_SERIAL_ID_ADDRESS 0x50 21 #define AXGBE_SFP_DIAG_INFO_ADDRESS 0x51 22 #define AXGBE_SFP_PHY_ADDRESS 0x56 23 #define AXGBE_GPIO_ADDRESS_PCA9555 0x20 24 25 /* SFP sideband signal indicators */ 26 #define AXGBE_GPIO_NO_TX_FAULT BIT(0) 27 #define AXGBE_GPIO_NO_RATE_SELECT BIT(1) 28 #define AXGBE_GPIO_NO_MOD_ABSENT BIT(2) 29 #define AXGBE_GPIO_NO_RX_LOS BIT(3) 30 31 /* Rate-change complete wait/retry count */ 32 #define AXGBE_RATECHANGE_COUNT 500 33 34 /* CDR delay values for KR support (in usec) */ 35 #define AXGBE_CDR_DELAY_INIT 10000 36 #define AXGBE_CDR_DELAY_INC 10000 37 #define AXGBE_CDR_DELAY_MAX 100000 38 39 enum axgbe_port_mode { 40 AXGBE_PORT_MODE_RSVD = 0, 41 AXGBE_PORT_MODE_BACKPLANE, 42 AXGBE_PORT_MODE_BACKPLANE_2500, 43 AXGBE_PORT_MODE_1000BASE_T, 44 AXGBE_PORT_MODE_1000BASE_X, 45 AXGBE_PORT_MODE_NBASE_T, 46 AXGBE_PORT_MODE_10GBASE_T, 47 AXGBE_PORT_MODE_10GBASE_R, 48 AXGBE_PORT_MODE_SFP, 49 AXGBE_PORT_MODE_MAX, 50 }; 51 52 enum axgbe_conn_type { 53 AXGBE_CONN_TYPE_NONE = 0, 54 AXGBE_CONN_TYPE_SFP, 55 AXGBE_CONN_TYPE_MDIO, 56 AXGBE_CONN_TYPE_RSVD1, 57 AXGBE_CONN_TYPE_BACKPLANE, 58 AXGBE_CONN_TYPE_MAX, 59 }; 60 61 /* SFP/SFP+ related definitions */ 62 enum axgbe_sfp_comm { 63 AXGBE_SFP_COMM_DIRECT = 0, 64 AXGBE_SFP_COMM_PCA9545, 65 }; 66 67 enum axgbe_sfp_cable { 68 AXGBE_SFP_CABLE_UNKNOWN = 0, 69 AXGBE_SFP_CABLE_ACTIVE, 70 AXGBE_SFP_CABLE_PASSIVE, 71 }; 72 73 enum axgbe_sfp_base { 74 AXGBE_SFP_BASE_UNKNOWN = 0, 75 AXGBE_SFP_BASE_1000_T, 76 AXGBE_SFP_BASE_1000_SX, 77 AXGBE_SFP_BASE_1000_LX, 78 AXGBE_SFP_BASE_1000_CX, 79 AXGBE_SFP_BASE_10000_SR, 80 AXGBE_SFP_BASE_10000_LR, 81 AXGBE_SFP_BASE_10000_LRM, 82 AXGBE_SFP_BASE_10000_ER, 83 AXGBE_SFP_BASE_10000_CR, 84 }; 85 86 enum axgbe_sfp_speed { 87 AXGBE_SFP_SPEED_UNKNOWN = 0, 88 AXGBE_SFP_SPEED_100_1000, 89 AXGBE_SFP_SPEED_1000, 90 AXGBE_SFP_SPEED_10000, 91 }; 92 93 /* SFP Serial ID Base ID values relative to an offset of 0 */ 94 #define AXGBE_SFP_BASE_ID 0 95 #define AXGBE_SFP_ID_SFP 0x03 96 97 #define AXGBE_SFP_BASE_EXT_ID 1 98 #define AXGBE_SFP_EXT_ID_SFP 0x04 99 100 #define AXGBE_SFP_BASE_10GBE_CC 3 101 #define AXGBE_SFP_BASE_10GBE_CC_SR BIT(4) 102 #define AXGBE_SFP_BASE_10GBE_CC_LR BIT(5) 103 #define AXGBE_SFP_BASE_10GBE_CC_LRM BIT(6) 104 #define AXGBE_SFP_BASE_10GBE_CC_ER BIT(7) 105 106 #define AXGBE_SFP_BASE_1GBE_CC 6 107 #define AXGBE_SFP_BASE_1GBE_CC_SX BIT(0) 108 #define AXGBE_SFP_BASE_1GBE_CC_LX BIT(1) 109 #define AXGBE_SFP_BASE_1GBE_CC_CX BIT(2) 110 #define AXGBE_SFP_BASE_1GBE_CC_T BIT(3) 111 112 #define AXGBE_SFP_BASE_CABLE 8 113 #define AXGBE_SFP_BASE_CABLE_PASSIVE BIT(2) 114 #define AXGBE_SFP_BASE_CABLE_ACTIVE BIT(3) 115 116 #define AXGBE_SFP_BASE_BR 12 117 #define AXGBE_SFP_BASE_BR_1GBE_MIN 0x0a 118 #define AXGBE_SFP_BASE_BR_1GBE_MAX 0x0d 119 #define AXGBE_SFP_BASE_BR_10GBE_MIN 0x64 120 #define AXGBE_SFP_BASE_BR_10GBE_MAX 0x68 121 122 #define AXGBE_SFP_BASE_CU_CABLE_LEN 18 123 124 #define AXGBE_SFP_BASE_VENDOR_NAME 20 125 #define AXGBE_SFP_BASE_VENDOR_NAME_LEN 16 126 #define AXGBE_SFP_BASE_VENDOR_PN 40 127 #define AXGBE_SFP_BASE_VENDOR_PN_LEN 16 128 #define AXGBE_SFP_BASE_VENDOR_REV 56 129 #define AXGBE_SFP_BASE_VENDOR_REV_LEN 4 130 131 #define AXGBE_SFP_BASE_CC 63 132 133 /* SFP Serial ID Extended ID values relative to an offset of 64 */ 134 #define AXGBE_SFP_BASE_VENDOR_SN 4 135 #define AXGBE_SFP_BASE_VENDOR_SN_LEN 16 136 137 #define AXGBE_SFP_EXTD_DIAG 28 138 #define AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE BIT(2) 139 140 #define AXGBE_SFP_EXTD_SFF_8472 30 141 142 #define AXGBE_SFP_EXTD_CC 31 143 144 struct axgbe_sfp_eeprom { 145 u8 base[64]; 146 u8 extd[32]; 147 u8 vendor[32]; 148 }; 149 150 #define AXGBE_BEL_FUSE_VENDOR "BEL-FUSE" 151 #define AXGBE_BEL_FUSE_PARTNO "1GBT-SFP06" 152 153 struct axgbe_sfp_ascii { 154 union { 155 char vendor[AXGBE_SFP_BASE_VENDOR_NAME_LEN + 1]; 156 char partno[AXGBE_SFP_BASE_VENDOR_PN_LEN + 1]; 157 char rev[AXGBE_SFP_BASE_VENDOR_REV_LEN + 1]; 158 char serno[AXGBE_SFP_BASE_VENDOR_SN_LEN + 1]; 159 } u; 160 }; 161 162 /* MDIO PHY reset types */ 163 enum axgbe_mdio_reset { 164 AXGBE_MDIO_RESET_NONE = 0, 165 AXGBE_MDIO_RESET_I2C_GPIO, 166 AXGBE_MDIO_RESET_INT_GPIO, 167 AXGBE_MDIO_RESET_MAX, 168 }; 169 170 /* Re-driver related definitions */ 171 enum axgbe_phy_redrv_if { 172 AXGBE_PHY_REDRV_IF_MDIO = 0, 173 AXGBE_PHY_REDRV_IF_I2C, 174 AXGBE_PHY_REDRV_IF_MAX, 175 }; 176 177 enum axgbe_phy_redrv_model { 178 AXGBE_PHY_REDRV_MODEL_4223 = 0, 179 AXGBE_PHY_REDRV_MODEL_4227, 180 AXGBE_PHY_REDRV_MODEL_MAX, 181 }; 182 183 enum axgbe_phy_redrv_mode { 184 AXGBE_PHY_REDRV_MODE_CX = 5, 185 AXGBE_PHY_REDRV_MODE_SR = 9, 186 }; 187 188 #define AXGBE_PHY_REDRV_MODE_REG 0x12b0 189 190 /* PHY related configuration information */ 191 struct axgbe_phy_data { 192 enum axgbe_port_mode port_mode; 193 194 unsigned int port_id; 195 196 unsigned int port_speeds; 197 198 enum axgbe_conn_type conn_type; 199 200 enum axgbe_mode cur_mode; 201 enum axgbe_mode start_mode; 202 203 unsigned int rrc_count; 204 205 unsigned int mdio_addr; 206 207 unsigned int comm_owned; 208 209 /* SFP Support */ 210 enum axgbe_sfp_comm sfp_comm; 211 unsigned int sfp_mux_address; 212 unsigned int sfp_mux_channel; 213 214 unsigned int sfp_gpio_address; 215 unsigned int sfp_gpio_mask; 216 unsigned int sfp_gpio_rx_los; 217 unsigned int sfp_gpio_tx_fault; 218 unsigned int sfp_gpio_mod_absent; 219 unsigned int sfp_gpio_rate_select; 220 221 unsigned int sfp_rx_los; 222 unsigned int sfp_tx_fault; 223 unsigned int sfp_mod_absent; 224 unsigned int sfp_diags; 225 unsigned int sfp_changed; 226 unsigned int sfp_phy_avail; 227 unsigned int sfp_cable_len; 228 enum axgbe_sfp_base sfp_base; 229 enum axgbe_sfp_cable sfp_cable; 230 enum axgbe_sfp_speed sfp_speed; 231 struct axgbe_sfp_eeprom sfp_eeprom; 232 233 /* External PHY support */ 234 enum axgbe_mdio_mode phydev_mode; 235 enum axgbe_mdio_reset mdio_reset; 236 unsigned int mdio_reset_addr; 237 unsigned int mdio_reset_gpio; 238 239 /* Re-driver support */ 240 unsigned int redrv; 241 unsigned int redrv_if; 242 unsigned int redrv_addr; 243 unsigned int redrv_lane; 244 unsigned int redrv_model; 245 246 /* KR AN support */ 247 unsigned int phy_cdr_notrack; 248 unsigned int phy_cdr_delay; 249 }; 250 251 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata); 252 253 static int axgbe_phy_i2c_xfer(struct axgbe_port *pdata, 254 struct axgbe_i2c_op *i2c_op) 255 { 256 struct axgbe_phy_data *phy_data = pdata->phy_data; 257 258 /* Be sure we own the bus */ 259 if (!phy_data->comm_owned) 260 return -EIO; 261 262 return pdata->i2c_if.i2c_xfer(pdata, i2c_op); 263 } 264 265 static int axgbe_phy_redrv_write(struct axgbe_port *pdata, unsigned int reg, 266 unsigned int val) 267 { 268 struct axgbe_phy_data *phy_data = pdata->phy_data; 269 struct axgbe_i2c_op i2c_op; 270 uint16_t *redrv_val; 271 u8 redrv_data[5], csum; 272 unsigned int i, retry; 273 int ret; 274 275 /* High byte of register contains read/write indicator */ 276 redrv_data[0] = ((reg >> 8) & 0xff) << 1; 277 redrv_data[1] = reg & 0xff; 278 redrv_val = (uint16_t *)&redrv_data[2]; 279 *redrv_val = rte_cpu_to_be_16(val); 280 281 /* Calculate 1 byte checksum */ 282 csum = 0; 283 for (i = 0; i < 4; i++) { 284 csum += redrv_data[i]; 285 if (redrv_data[i] > csum) 286 csum++; 287 } 288 redrv_data[4] = ~csum; 289 290 retry = 1; 291 again1: 292 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 293 i2c_op.target = phy_data->redrv_addr; 294 i2c_op.len = sizeof(redrv_data); 295 i2c_op.buf = redrv_data; 296 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 297 if (ret) { 298 if ((ret == -EAGAIN) && retry--) 299 goto again1; 300 301 return ret; 302 } 303 304 retry = 1; 305 again2: 306 i2c_op.cmd = AXGBE_I2C_CMD_READ; 307 i2c_op.target = phy_data->redrv_addr; 308 i2c_op.len = 1; 309 i2c_op.buf = redrv_data; 310 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 311 if (ret) { 312 if ((ret == -EAGAIN) && retry--) 313 goto again2; 314 315 return ret; 316 } 317 318 if (redrv_data[0] != 0xff) { 319 PMD_DRV_LOG(ERR, "Redriver write checksum error\n"); 320 ret = -EIO; 321 } 322 323 return ret; 324 } 325 326 static int axgbe_phy_i2c_read(struct axgbe_port *pdata, unsigned int target, 327 void *reg, unsigned int reg_len, 328 void *val, unsigned int val_len) 329 { 330 struct axgbe_i2c_op i2c_op; 331 int retry, ret; 332 333 retry = 1; 334 again1: 335 /* Set the specified register to read */ 336 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 337 i2c_op.target = target; 338 i2c_op.len = reg_len; 339 i2c_op.buf = reg; 340 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 341 if (ret) { 342 if ((ret == -EAGAIN) && retry--) 343 goto again1; 344 345 return ret; 346 } 347 348 retry = 1; 349 again2: 350 /* Read the specified register */ 351 i2c_op.cmd = AXGBE_I2C_CMD_READ; 352 i2c_op.target = target; 353 i2c_op.len = val_len; 354 i2c_op.buf = val; 355 ret = axgbe_phy_i2c_xfer(pdata, &i2c_op); 356 if ((ret == -EAGAIN) && retry--) 357 goto again2; 358 359 return ret; 360 } 361 362 static int axgbe_phy_sfp_put_mux(struct axgbe_port *pdata) 363 { 364 struct axgbe_phy_data *phy_data = pdata->phy_data; 365 struct axgbe_i2c_op i2c_op; 366 uint8_t mux_channel; 367 368 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 369 return 0; 370 371 /* Select no mux channels */ 372 mux_channel = 0; 373 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 374 i2c_op.target = phy_data->sfp_mux_address; 375 i2c_op.len = sizeof(mux_channel); 376 i2c_op.buf = &mux_channel; 377 378 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 379 } 380 381 static int axgbe_phy_sfp_get_mux(struct axgbe_port *pdata) 382 { 383 struct axgbe_phy_data *phy_data = pdata->phy_data; 384 struct axgbe_i2c_op i2c_op; 385 u8 mux_channel; 386 387 if (phy_data->sfp_comm == AXGBE_SFP_COMM_DIRECT) 388 return 0; 389 390 /* Select desired mux channel */ 391 mux_channel = 1 << phy_data->sfp_mux_channel; 392 i2c_op.cmd = AXGBE_I2C_CMD_WRITE; 393 i2c_op.target = phy_data->sfp_mux_address; 394 i2c_op.len = sizeof(mux_channel); 395 i2c_op.buf = &mux_channel; 396 397 return axgbe_phy_i2c_xfer(pdata, &i2c_op); 398 } 399 400 static void axgbe_phy_put_comm_ownership(struct axgbe_port *pdata) 401 { 402 struct axgbe_phy_data *phy_data = pdata->phy_data; 403 404 phy_data->comm_owned = 0; 405 406 pthread_mutex_unlock(&pdata->phy_mutex); 407 } 408 409 static int axgbe_phy_get_comm_ownership(struct axgbe_port *pdata) 410 { 411 struct axgbe_phy_data *phy_data = pdata->phy_data; 412 uint64_t timeout; 413 unsigned int mutex_id; 414 415 /* The I2C and MDIO/GPIO bus is multiplexed between multiple devices, 416 * the driver needs to take the software mutex and then the hardware 417 * mutexes before being able to use the busses. 418 */ 419 pthread_mutex_lock(&pdata->phy_mutex); 420 421 if (phy_data->comm_owned) 422 return 0; 423 424 /* Clear the mutexes */ 425 XP_IOWRITE(pdata, XP_I2C_MUTEX, AXGBE_MUTEX_RELEASE); 426 XP_IOWRITE(pdata, XP_MDIO_MUTEX, AXGBE_MUTEX_RELEASE); 427 428 /* Mutex formats are the same for I2C and MDIO/GPIO */ 429 mutex_id = 0; 430 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ID, phy_data->port_id); 431 XP_SET_BITS(mutex_id, XP_I2C_MUTEX, ACTIVE, 1); 432 433 timeout = rte_get_timer_cycles() + (rte_get_timer_hz() * 5); 434 while (time_before(rte_get_timer_cycles(), timeout)) { 435 /* Must be all zeroes in order to obtain the mutex */ 436 if (XP_IOREAD(pdata, XP_I2C_MUTEX) || 437 XP_IOREAD(pdata, XP_MDIO_MUTEX)) { 438 rte_delay_us(100); 439 continue; 440 } 441 442 /* Obtain the mutex */ 443 XP_IOWRITE(pdata, XP_I2C_MUTEX, mutex_id); 444 XP_IOWRITE(pdata, XP_MDIO_MUTEX, mutex_id); 445 446 phy_data->comm_owned = 1; 447 return 0; 448 } 449 450 pthread_mutex_unlock(&pdata->phy_mutex); 451 452 PMD_DRV_LOG(ERR, "unable to obtain hardware mutexes\n"); 453 454 return -ETIMEDOUT; 455 } 456 457 static void axgbe_phy_sfp_phy_settings(struct axgbe_port *pdata) 458 { 459 struct axgbe_phy_data *phy_data = pdata->phy_data; 460 461 if (phy_data->sfp_mod_absent) { 462 pdata->phy.speed = SPEED_UNKNOWN; 463 pdata->phy.duplex = DUPLEX_UNKNOWN; 464 pdata->phy.autoneg = AUTONEG_ENABLE; 465 pdata->phy.advertising = pdata->phy.supported; 466 } 467 468 pdata->phy.advertising &= ~ADVERTISED_Autoneg; 469 pdata->phy.advertising &= ~ADVERTISED_TP; 470 pdata->phy.advertising &= ~ADVERTISED_FIBRE; 471 pdata->phy.advertising &= ~ADVERTISED_100baseT_Full; 472 pdata->phy.advertising &= ~ADVERTISED_1000baseT_Full; 473 pdata->phy.advertising &= ~ADVERTISED_10000baseT_Full; 474 pdata->phy.advertising &= ~ADVERTISED_10000baseR_FEC; 475 476 switch (phy_data->sfp_base) { 477 case AXGBE_SFP_BASE_1000_T: 478 case AXGBE_SFP_BASE_1000_SX: 479 case AXGBE_SFP_BASE_1000_LX: 480 case AXGBE_SFP_BASE_1000_CX: 481 pdata->phy.speed = SPEED_UNKNOWN; 482 pdata->phy.duplex = DUPLEX_UNKNOWN; 483 pdata->phy.autoneg = AUTONEG_ENABLE; 484 pdata->phy.advertising |= ADVERTISED_Autoneg; 485 break; 486 case AXGBE_SFP_BASE_10000_SR: 487 case AXGBE_SFP_BASE_10000_LR: 488 case AXGBE_SFP_BASE_10000_LRM: 489 case AXGBE_SFP_BASE_10000_ER: 490 case AXGBE_SFP_BASE_10000_CR: 491 default: 492 pdata->phy.speed = SPEED_10000; 493 pdata->phy.duplex = DUPLEX_FULL; 494 pdata->phy.autoneg = AUTONEG_DISABLE; 495 break; 496 } 497 498 switch (phy_data->sfp_base) { 499 case AXGBE_SFP_BASE_1000_T: 500 case AXGBE_SFP_BASE_1000_CX: 501 case AXGBE_SFP_BASE_10000_CR: 502 pdata->phy.advertising |= ADVERTISED_TP; 503 break; 504 default: 505 pdata->phy.advertising |= ADVERTISED_FIBRE; 506 } 507 508 switch (phy_data->sfp_speed) { 509 case AXGBE_SFP_SPEED_100_1000: 510 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 511 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 512 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 513 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 514 break; 515 case AXGBE_SFP_SPEED_1000: 516 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 517 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 518 break; 519 case AXGBE_SFP_SPEED_10000: 520 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 521 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 522 break; 523 default: 524 /* Choose the fastest supported speed */ 525 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 526 pdata->phy.advertising |= ADVERTISED_10000baseT_Full; 527 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 528 pdata->phy.advertising |= ADVERTISED_1000baseT_Full; 529 else if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) 530 pdata->phy.advertising |= ADVERTISED_100baseT_Full; 531 } 532 } 533 534 static bool axgbe_phy_sfp_bit_rate(struct axgbe_sfp_eeprom *sfp_eeprom, 535 enum axgbe_sfp_speed sfp_speed) 536 { 537 u8 *sfp_base, min, max; 538 539 sfp_base = sfp_eeprom->base; 540 541 switch (sfp_speed) { 542 case AXGBE_SFP_SPEED_1000: 543 min = AXGBE_SFP_BASE_BR_1GBE_MIN; 544 max = AXGBE_SFP_BASE_BR_1GBE_MAX; 545 break; 546 case AXGBE_SFP_SPEED_10000: 547 min = AXGBE_SFP_BASE_BR_10GBE_MIN; 548 max = AXGBE_SFP_BASE_BR_10GBE_MAX; 549 break; 550 default: 551 return false; 552 } 553 554 return ((sfp_base[AXGBE_SFP_BASE_BR] >= min) && 555 (sfp_base[AXGBE_SFP_BASE_BR] <= max)); 556 } 557 558 static void axgbe_phy_sfp_external_phy(struct axgbe_port *pdata) 559 { 560 struct axgbe_phy_data *phy_data = pdata->phy_data; 561 562 if (!phy_data->sfp_changed) 563 return; 564 565 phy_data->sfp_phy_avail = 0; 566 567 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 568 return; 569 } 570 571 static bool axgbe_phy_belfuse_parse_quirks(struct axgbe_port *pdata) 572 { 573 struct axgbe_phy_data *phy_data = pdata->phy_data; 574 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 575 576 if (memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_NAME], 577 AXGBE_BEL_FUSE_VENDOR, strlen(AXGBE_BEL_FUSE_VENDOR))) 578 return false; 579 580 if (!memcmp(&sfp_eeprom->base[AXGBE_SFP_BASE_VENDOR_PN], 581 AXGBE_BEL_FUSE_PARTNO, strlen(AXGBE_BEL_FUSE_PARTNO))) { 582 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 583 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 584 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 585 return true; 586 } 587 588 return false; 589 } 590 591 static bool axgbe_phy_sfp_parse_quirks(struct axgbe_port *pdata) 592 { 593 if (axgbe_phy_belfuse_parse_quirks(pdata)) 594 return true; 595 596 return false; 597 } 598 599 static void axgbe_phy_sfp_parse_eeprom(struct axgbe_port *pdata) 600 { 601 struct axgbe_phy_data *phy_data = pdata->phy_data; 602 struct axgbe_sfp_eeprom *sfp_eeprom = &phy_data->sfp_eeprom; 603 uint8_t *sfp_base; 604 605 sfp_base = sfp_eeprom->base; 606 607 if (sfp_base[AXGBE_SFP_BASE_ID] != AXGBE_SFP_ID_SFP) 608 return; 609 610 if (sfp_base[AXGBE_SFP_BASE_EXT_ID] != AXGBE_SFP_EXT_ID_SFP) 611 return; 612 613 axgbe_phy_sfp_parse_quirks(pdata); 614 615 /* Assume ACTIVE cable unless told it is PASSIVE */ 616 if (sfp_base[AXGBE_SFP_BASE_CABLE] & AXGBE_SFP_BASE_CABLE_PASSIVE) { 617 phy_data->sfp_cable = AXGBE_SFP_CABLE_PASSIVE; 618 phy_data->sfp_cable_len = sfp_base[AXGBE_SFP_BASE_CU_CABLE_LEN]; 619 } else { 620 phy_data->sfp_cable = AXGBE_SFP_CABLE_ACTIVE; 621 } 622 623 /* Determine the type of SFP */ 624 if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_SR) 625 phy_data->sfp_base = AXGBE_SFP_BASE_10000_SR; 626 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_LR) 627 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LR; 628 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & 629 AXGBE_SFP_BASE_10GBE_CC_LRM) 630 phy_data->sfp_base = AXGBE_SFP_BASE_10000_LRM; 631 else if (sfp_base[AXGBE_SFP_BASE_10GBE_CC] & AXGBE_SFP_BASE_10GBE_CC_ER) 632 phy_data->sfp_base = AXGBE_SFP_BASE_10000_ER; 633 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_SX) 634 phy_data->sfp_base = AXGBE_SFP_BASE_1000_SX; 635 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_LX) 636 phy_data->sfp_base = AXGBE_SFP_BASE_1000_LX; 637 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_CX) 638 phy_data->sfp_base = AXGBE_SFP_BASE_1000_CX; 639 else if (sfp_base[AXGBE_SFP_BASE_1GBE_CC] & AXGBE_SFP_BASE_1GBE_CC_T) 640 phy_data->sfp_base = AXGBE_SFP_BASE_1000_T; 641 else if ((phy_data->sfp_cable == AXGBE_SFP_CABLE_PASSIVE) && 642 axgbe_phy_sfp_bit_rate(sfp_eeprom, AXGBE_SFP_SPEED_10000)) 643 phy_data->sfp_base = AXGBE_SFP_BASE_10000_CR; 644 645 switch (phy_data->sfp_base) { 646 case AXGBE_SFP_BASE_1000_T: 647 phy_data->sfp_speed = AXGBE_SFP_SPEED_100_1000; 648 break; 649 case AXGBE_SFP_BASE_1000_SX: 650 case AXGBE_SFP_BASE_1000_LX: 651 case AXGBE_SFP_BASE_1000_CX: 652 phy_data->sfp_speed = AXGBE_SFP_SPEED_1000; 653 break; 654 case AXGBE_SFP_BASE_10000_SR: 655 case AXGBE_SFP_BASE_10000_LR: 656 case AXGBE_SFP_BASE_10000_LRM: 657 case AXGBE_SFP_BASE_10000_ER: 658 case AXGBE_SFP_BASE_10000_CR: 659 phy_data->sfp_speed = AXGBE_SFP_SPEED_10000; 660 break; 661 default: 662 break; 663 } 664 } 665 666 static bool axgbe_phy_sfp_verify_eeprom(uint8_t cc_in, uint8_t *buf, 667 unsigned int len) 668 { 669 uint8_t cc; 670 671 for (cc = 0; len; buf++, len--) 672 cc += *buf; 673 674 return (cc == cc_in) ? true : false; 675 } 676 677 static int axgbe_phy_sfp_read_eeprom(struct axgbe_port *pdata) 678 { 679 struct axgbe_phy_data *phy_data = pdata->phy_data; 680 struct axgbe_sfp_eeprom sfp_eeprom; 681 uint8_t eeprom_addr; 682 int ret; 683 684 ret = axgbe_phy_sfp_get_mux(pdata); 685 if (ret) { 686 PMD_DRV_LOG(ERR, "I2C error setting SFP MUX\n"); 687 return ret; 688 } 689 690 /* Read the SFP serial ID eeprom */ 691 eeprom_addr = 0; 692 ret = axgbe_phy_i2c_read(pdata, AXGBE_SFP_SERIAL_ID_ADDRESS, 693 &eeprom_addr, sizeof(eeprom_addr), 694 &sfp_eeprom, sizeof(sfp_eeprom)); 695 if (ret) { 696 PMD_DRV_LOG(ERR, "I2C error reading SFP EEPROM\n"); 697 goto put; 698 } 699 700 /* Validate the contents read */ 701 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.base[AXGBE_SFP_BASE_CC], 702 sfp_eeprom.base, 703 sizeof(sfp_eeprom.base) - 1)) { 704 ret = -EINVAL; 705 goto put; 706 } 707 708 if (!axgbe_phy_sfp_verify_eeprom(sfp_eeprom.extd[AXGBE_SFP_EXTD_CC], 709 sfp_eeprom.extd, 710 sizeof(sfp_eeprom.extd) - 1)) { 711 ret = -EINVAL; 712 goto put; 713 } 714 715 /* Check for an added or changed SFP */ 716 if (memcmp(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom))) { 717 phy_data->sfp_changed = 1; 718 memcpy(&phy_data->sfp_eeprom, &sfp_eeprom, sizeof(sfp_eeprom)); 719 720 if (sfp_eeprom.extd[AXGBE_SFP_EXTD_SFF_8472]) { 721 uint8_t diag_type; 722 diag_type = sfp_eeprom.extd[AXGBE_SFP_EXTD_DIAG]; 723 724 if (!(diag_type & AXGBE_SFP_EXTD_DIAG_ADDR_CHANGE)) 725 phy_data->sfp_diags = 1; 726 } 727 } else { 728 phy_data->sfp_changed = 0; 729 } 730 731 put: 732 axgbe_phy_sfp_put_mux(pdata); 733 734 return ret; 735 } 736 737 static void axgbe_phy_sfp_signals(struct axgbe_port *pdata) 738 { 739 struct axgbe_phy_data *phy_data = pdata->phy_data; 740 unsigned int gpio_input; 741 u8 gpio_reg, gpio_ports[2]; 742 int ret; 743 744 /* Read the input port registers */ 745 gpio_reg = 0; 746 ret = axgbe_phy_i2c_read(pdata, phy_data->sfp_gpio_address, 747 &gpio_reg, sizeof(gpio_reg), 748 gpio_ports, sizeof(gpio_ports)); 749 if (ret) { 750 PMD_DRV_LOG(ERR, "I2C error reading SFP GPIOs\n"); 751 return; 752 } 753 754 gpio_input = (gpio_ports[1] << 8) | gpio_ports[0]; 755 756 if (phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_MOD_ABSENT) { 757 /* No GPIO, just assume the module is present for now */ 758 phy_data->sfp_mod_absent = 0; 759 } else { 760 if (!(gpio_input & (1 << phy_data->sfp_gpio_mod_absent))) 761 phy_data->sfp_mod_absent = 0; 762 } 763 764 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_RX_LOS) && 765 (gpio_input & (1 << phy_data->sfp_gpio_rx_los))) 766 phy_data->sfp_rx_los = 1; 767 768 if (!(phy_data->sfp_gpio_mask & AXGBE_GPIO_NO_TX_FAULT) && 769 (gpio_input & (1 << phy_data->sfp_gpio_tx_fault))) 770 phy_data->sfp_tx_fault = 1; 771 } 772 773 static void axgbe_phy_sfp_mod_absent(struct axgbe_port *pdata) 774 { 775 struct axgbe_phy_data *phy_data = pdata->phy_data; 776 777 phy_data->sfp_mod_absent = 1; 778 phy_data->sfp_phy_avail = 0; 779 memset(&phy_data->sfp_eeprom, 0, sizeof(phy_data->sfp_eeprom)); 780 } 781 782 static void axgbe_phy_sfp_reset(struct axgbe_phy_data *phy_data) 783 { 784 phy_data->sfp_rx_los = 0; 785 phy_data->sfp_tx_fault = 0; 786 phy_data->sfp_mod_absent = 1; 787 phy_data->sfp_diags = 0; 788 phy_data->sfp_base = AXGBE_SFP_BASE_UNKNOWN; 789 phy_data->sfp_cable = AXGBE_SFP_CABLE_UNKNOWN; 790 phy_data->sfp_speed = AXGBE_SFP_SPEED_UNKNOWN; 791 } 792 793 static const char *axgbe_base_as_string(enum axgbe_sfp_base sfp_base) 794 { 795 switch (sfp_base) { 796 case AXGBE_SFP_BASE_1000_T: 797 return "1G_T"; 798 case AXGBE_SFP_BASE_1000_SX: 799 return "1G_SX"; 800 case AXGBE_SFP_BASE_1000_LX: 801 return "1G_LX"; 802 case AXGBE_SFP_BASE_1000_CX: 803 return "1G_CX"; 804 case AXGBE_SFP_BASE_10000_SR: 805 return "10G_SR"; 806 case AXGBE_SFP_BASE_10000_LR: 807 return "10G_LR"; 808 case AXGBE_SFP_BASE_10000_LRM: 809 return "10G_LRM"; 810 case AXGBE_SFP_BASE_10000_ER: 811 return "10G_ER"; 812 case AXGBE_SFP_BASE_10000_CR: 813 return "10G_CR"; 814 default: 815 return "Unknown"; 816 } 817 } 818 819 static void axgbe_phy_sfp_detect(struct axgbe_port *pdata) 820 { 821 struct axgbe_phy_data *phy_data = pdata->phy_data; 822 int ret; 823 824 /* Reset the SFP signals and info */ 825 axgbe_phy_sfp_reset(phy_data); 826 827 ret = axgbe_phy_get_comm_ownership(pdata); 828 if (ret) 829 return; 830 831 /* Read the SFP signals and check for module presence */ 832 axgbe_phy_sfp_signals(pdata); 833 if (phy_data->sfp_mod_absent) { 834 axgbe_phy_sfp_mod_absent(pdata); 835 goto put; 836 } 837 838 ret = axgbe_phy_sfp_read_eeprom(pdata); 839 if (ret) { 840 /* Treat any error as if there isn't an SFP plugged in */ 841 axgbe_phy_sfp_reset(phy_data); 842 axgbe_phy_sfp_mod_absent(pdata); 843 goto put; 844 } 845 846 axgbe_phy_sfp_parse_eeprom(pdata); 847 axgbe_phy_sfp_external_phy(pdata); 848 849 PMD_DRV_LOG(DEBUG, "SFP Base: %s\n", 850 axgbe_base_as_string(phy_data->sfp_base)); 851 852 put: 853 axgbe_phy_sfp_phy_settings(pdata); 854 axgbe_phy_put_comm_ownership(pdata); 855 } 856 857 static void axgbe_phy_phydev_flowctrl(struct axgbe_port *pdata) 858 { 859 pdata->phy.tx_pause = 0; 860 pdata->phy.rx_pause = 0; 861 } 862 863 static enum axgbe_mode axgbe_phy_an73_redrv_outcome(struct axgbe_port *pdata) 864 { 865 struct axgbe_phy_data *phy_data = pdata->phy_data; 866 enum axgbe_mode mode; 867 unsigned int ad_reg, lp_reg; 868 869 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 870 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 871 872 /* Use external PHY to determine flow control */ 873 if (pdata->phy.pause_autoneg) 874 axgbe_phy_phydev_flowctrl(pdata); 875 876 /* Compare Advertisement and Link Partner register 2 */ 877 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 878 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 879 if (lp_reg & 0x80) 880 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 881 if (lp_reg & 0x20) 882 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 883 884 ad_reg &= lp_reg; 885 if (ad_reg & 0x80) { 886 switch (phy_data->port_mode) { 887 case AXGBE_PORT_MODE_BACKPLANE: 888 mode = AXGBE_MODE_KR; 889 break; 890 default: 891 mode = AXGBE_MODE_SFI; 892 break; 893 } 894 } else if (ad_reg & 0x20) { 895 switch (phy_data->port_mode) { 896 case AXGBE_PORT_MODE_BACKPLANE: 897 mode = AXGBE_MODE_KX_1000; 898 break; 899 case AXGBE_PORT_MODE_1000BASE_X: 900 mode = AXGBE_MODE_X; 901 break; 902 case AXGBE_PORT_MODE_SFP: 903 switch (phy_data->sfp_base) { 904 case AXGBE_SFP_BASE_1000_T: 905 mode = AXGBE_MODE_SGMII_1000; 906 break; 907 case AXGBE_SFP_BASE_1000_SX: 908 case AXGBE_SFP_BASE_1000_LX: 909 case AXGBE_SFP_BASE_1000_CX: 910 default: 911 mode = AXGBE_MODE_X; 912 break; 913 } 914 break; 915 default: 916 mode = AXGBE_MODE_SGMII_1000; 917 break; 918 } 919 } else { 920 mode = AXGBE_MODE_UNKNOWN; 921 } 922 923 /* Compare Advertisement and Link Partner register 3 */ 924 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 925 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 926 if (lp_reg & 0xc000) 927 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 928 929 return mode; 930 } 931 932 static enum axgbe_mode axgbe_phy_an73_outcome(struct axgbe_port *pdata) 933 { 934 enum axgbe_mode mode; 935 unsigned int ad_reg, lp_reg; 936 937 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 938 pdata->phy.lp_advertising |= ADVERTISED_Backplane; 939 940 /* Compare Advertisement and Link Partner register 1 */ 941 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE); 942 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA); 943 if (lp_reg & 0x400) 944 pdata->phy.lp_advertising |= ADVERTISED_Pause; 945 if (lp_reg & 0x800) 946 pdata->phy.lp_advertising |= ADVERTISED_Asym_Pause; 947 948 if (pdata->phy.pause_autoneg) { 949 /* Set flow control based on auto-negotiation result */ 950 pdata->phy.tx_pause = 0; 951 pdata->phy.rx_pause = 0; 952 953 if (ad_reg & lp_reg & 0x400) { 954 pdata->phy.tx_pause = 1; 955 pdata->phy.rx_pause = 1; 956 } else if (ad_reg & lp_reg & 0x800) { 957 if (ad_reg & 0x400) 958 pdata->phy.rx_pause = 1; 959 else if (lp_reg & 0x400) 960 pdata->phy.tx_pause = 1; 961 } 962 } 963 964 /* Compare Advertisement and Link Partner register 2 */ 965 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1); 966 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 1); 967 if (lp_reg & 0x80) 968 pdata->phy.lp_advertising |= ADVERTISED_10000baseKR_Full; 969 if (lp_reg & 0x20) 970 pdata->phy.lp_advertising |= ADVERTISED_1000baseKX_Full; 971 972 ad_reg &= lp_reg; 973 if (ad_reg & 0x80) 974 mode = AXGBE_MODE_KR; 975 else if (ad_reg & 0x20) 976 mode = AXGBE_MODE_KX_1000; 977 else 978 mode = AXGBE_MODE_UNKNOWN; 979 980 /* Compare Advertisement and Link Partner register 3 */ 981 ad_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2); 982 lp_reg = XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_LPA + 2); 983 if (lp_reg & 0xc000) 984 pdata->phy.lp_advertising |= ADVERTISED_10000baseR_FEC; 985 986 return mode; 987 } 988 989 static enum axgbe_mode axgbe_phy_an37_sgmii_outcome(struct axgbe_port *pdata) 990 { 991 enum axgbe_mode mode; 992 993 pdata->phy.lp_advertising |= ADVERTISED_Autoneg; 994 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 995 996 if (pdata->phy.pause_autoneg) 997 axgbe_phy_phydev_flowctrl(pdata); 998 999 switch (pdata->an_status & AXGBE_SGMII_AN_LINK_SPEED) { 1000 case AXGBE_SGMII_AN_LINK_SPEED_100: 1001 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1002 pdata->phy.lp_advertising |= ADVERTISED_100baseT_Full; 1003 mode = AXGBE_MODE_SGMII_100; 1004 } else { 1005 mode = AXGBE_MODE_UNKNOWN; 1006 } 1007 break; 1008 case AXGBE_SGMII_AN_LINK_SPEED_1000: 1009 if (pdata->an_status & AXGBE_SGMII_AN_LINK_DUPLEX) { 1010 pdata->phy.lp_advertising |= ADVERTISED_1000baseT_Full; 1011 mode = AXGBE_MODE_SGMII_1000; 1012 } else { 1013 /* Half-duplex not supported */ 1014 mode = AXGBE_MODE_UNKNOWN; 1015 } 1016 break; 1017 default: 1018 mode = AXGBE_MODE_UNKNOWN; 1019 break; 1020 } 1021 return mode; 1022 } 1023 1024 static enum axgbe_mode axgbe_phy_an_outcome(struct axgbe_port *pdata) 1025 { 1026 switch (pdata->an_mode) { 1027 case AXGBE_AN_MODE_CL73: 1028 return axgbe_phy_an73_outcome(pdata); 1029 case AXGBE_AN_MODE_CL73_REDRV: 1030 return axgbe_phy_an73_redrv_outcome(pdata); 1031 case AXGBE_AN_MODE_CL37: 1032 case AXGBE_AN_MODE_CL37_SGMII: 1033 return axgbe_phy_an37_sgmii_outcome(pdata); 1034 default: 1035 return AXGBE_MODE_UNKNOWN; 1036 } 1037 } 1038 1039 static unsigned int axgbe_phy_an_advertising(struct axgbe_port *pdata) 1040 { 1041 struct axgbe_phy_data *phy_data = pdata->phy_data; 1042 unsigned int advertising; 1043 1044 /* Without a re-driver, just return current advertising */ 1045 if (!phy_data->redrv) 1046 return pdata->phy.advertising; 1047 1048 /* With the KR re-driver we need to advertise a single speed */ 1049 advertising = pdata->phy.advertising; 1050 advertising &= ~ADVERTISED_1000baseKX_Full; 1051 advertising &= ~ADVERTISED_10000baseKR_Full; 1052 1053 switch (phy_data->port_mode) { 1054 case AXGBE_PORT_MODE_BACKPLANE: 1055 advertising |= ADVERTISED_10000baseKR_Full; 1056 break; 1057 case AXGBE_PORT_MODE_BACKPLANE_2500: 1058 advertising |= ADVERTISED_1000baseKX_Full; 1059 break; 1060 case AXGBE_PORT_MODE_1000BASE_T: 1061 case AXGBE_PORT_MODE_1000BASE_X: 1062 case AXGBE_PORT_MODE_NBASE_T: 1063 advertising |= ADVERTISED_1000baseKX_Full; 1064 break; 1065 case AXGBE_PORT_MODE_10GBASE_T: 1066 PMD_DRV_LOG(ERR, "10GBASE_T mode is not supported\n"); 1067 break; 1068 case AXGBE_PORT_MODE_10GBASE_R: 1069 advertising |= ADVERTISED_10000baseKR_Full; 1070 break; 1071 case AXGBE_PORT_MODE_SFP: 1072 switch (phy_data->sfp_base) { 1073 case AXGBE_SFP_BASE_1000_T: 1074 case AXGBE_SFP_BASE_1000_SX: 1075 case AXGBE_SFP_BASE_1000_LX: 1076 case AXGBE_SFP_BASE_1000_CX: 1077 advertising |= ADVERTISED_1000baseKX_Full; 1078 break; 1079 default: 1080 advertising |= ADVERTISED_10000baseKR_Full; 1081 break; 1082 } 1083 break; 1084 default: 1085 advertising |= ADVERTISED_10000baseKR_Full; 1086 break; 1087 } 1088 1089 return advertising; 1090 } 1091 1092 static int axgbe_phy_an_config(struct axgbe_port *pdata __rte_unused) 1093 { 1094 return 0; 1095 /* Dummy API since there is no case to support 1096 * external phy devices registered through kernel APIs 1097 */ 1098 } 1099 1100 static enum axgbe_an_mode axgbe_phy_an_sfp_mode(struct axgbe_phy_data *phy_data) 1101 { 1102 switch (phy_data->sfp_base) { 1103 case AXGBE_SFP_BASE_1000_T: 1104 return AXGBE_AN_MODE_CL37_SGMII; 1105 case AXGBE_SFP_BASE_1000_SX: 1106 case AXGBE_SFP_BASE_1000_LX: 1107 case AXGBE_SFP_BASE_1000_CX: 1108 return AXGBE_AN_MODE_CL37; 1109 default: 1110 return AXGBE_AN_MODE_NONE; 1111 } 1112 } 1113 1114 static enum axgbe_an_mode axgbe_phy_an_mode(struct axgbe_port *pdata) 1115 { 1116 struct axgbe_phy_data *phy_data = pdata->phy_data; 1117 1118 /* A KR re-driver will always require CL73 AN */ 1119 if (phy_data->redrv) 1120 return AXGBE_AN_MODE_CL73_REDRV; 1121 1122 switch (phy_data->port_mode) { 1123 case AXGBE_PORT_MODE_BACKPLANE: 1124 return AXGBE_AN_MODE_CL73; 1125 case AXGBE_PORT_MODE_BACKPLANE_2500: 1126 return AXGBE_AN_MODE_NONE; 1127 case AXGBE_PORT_MODE_1000BASE_T: 1128 return AXGBE_AN_MODE_CL37_SGMII; 1129 case AXGBE_PORT_MODE_1000BASE_X: 1130 return AXGBE_AN_MODE_CL37; 1131 case AXGBE_PORT_MODE_NBASE_T: 1132 return AXGBE_AN_MODE_CL37_SGMII; 1133 case AXGBE_PORT_MODE_10GBASE_T: 1134 return AXGBE_AN_MODE_CL73; 1135 case AXGBE_PORT_MODE_10GBASE_R: 1136 return AXGBE_AN_MODE_NONE; 1137 case AXGBE_PORT_MODE_SFP: 1138 return axgbe_phy_an_sfp_mode(phy_data); 1139 default: 1140 return AXGBE_AN_MODE_NONE; 1141 } 1142 } 1143 1144 static int axgbe_phy_set_redrv_mode_mdio(struct axgbe_port *pdata, 1145 enum axgbe_phy_redrv_mode mode) 1146 { 1147 struct axgbe_phy_data *phy_data = pdata->phy_data; 1148 u16 redrv_reg, redrv_val; 1149 1150 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1151 redrv_val = (u16)mode; 1152 1153 return pdata->hw_if.write_ext_mii_regs(pdata, phy_data->redrv_addr, 1154 redrv_reg, redrv_val); 1155 } 1156 1157 static int axgbe_phy_set_redrv_mode_i2c(struct axgbe_port *pdata, 1158 enum axgbe_phy_redrv_mode mode) 1159 { 1160 struct axgbe_phy_data *phy_data = pdata->phy_data; 1161 unsigned int redrv_reg; 1162 int ret; 1163 1164 /* Calculate the register to write */ 1165 redrv_reg = AXGBE_PHY_REDRV_MODE_REG + (phy_data->redrv_lane * 0x1000); 1166 1167 ret = axgbe_phy_redrv_write(pdata, redrv_reg, mode); 1168 1169 return ret; 1170 } 1171 1172 static void axgbe_phy_set_redrv_mode(struct axgbe_port *pdata) 1173 { 1174 struct axgbe_phy_data *phy_data = pdata->phy_data; 1175 enum axgbe_phy_redrv_mode mode; 1176 int ret; 1177 1178 if (!phy_data->redrv) 1179 return; 1180 1181 mode = AXGBE_PHY_REDRV_MODE_CX; 1182 if ((phy_data->port_mode == AXGBE_PORT_MODE_SFP) && 1183 (phy_data->sfp_base != AXGBE_SFP_BASE_1000_CX) && 1184 (phy_data->sfp_base != AXGBE_SFP_BASE_10000_CR)) 1185 mode = AXGBE_PHY_REDRV_MODE_SR; 1186 1187 ret = axgbe_phy_get_comm_ownership(pdata); 1188 if (ret) 1189 return; 1190 1191 if (phy_data->redrv_if) 1192 axgbe_phy_set_redrv_mode_i2c(pdata, mode); 1193 else 1194 axgbe_phy_set_redrv_mode_mdio(pdata, mode); 1195 1196 axgbe_phy_put_comm_ownership(pdata); 1197 } 1198 1199 static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable) 1200 { 1201 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0, 1202 XGBE_PMA_PLL_CTRL_MASK, 1203 enable ? XGBE_PMA_PLL_CTRL_SET 1204 : XGBE_PMA_PLL_CTRL_CLEAR); 1205 1206 /* Wait for command to complete */ 1207 rte_delay_us(150); 1208 } 1209 1210 static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata, 1211 unsigned int cmd, unsigned int sub_cmd) 1212 { 1213 unsigned int s0 = 0; 1214 unsigned int wait; 1215 /* Clear the PLL so that it helps in power down sequence */ 1216 axgbe_phy_pll_ctrl(pdata, false); 1217 1218 /* Log if a previous command did not complete */ 1219 if (XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1220 PMD_DRV_LOG(NOTICE, "firmware mailbox not ready for command\n"); 1221 1222 /* Construct the command */ 1223 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, COMMAND, cmd); 1224 XP_SET_BITS(s0, XP_DRIVER_SCRATCH_0, SUB_COMMAND, sub_cmd); 1225 1226 /* Issue the command */ 1227 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_0, s0); 1228 XP_IOWRITE(pdata, XP_DRIVER_SCRATCH_1, 0); 1229 XP_IOWRITE_BITS(pdata, XP_DRIVER_INT_REQ, REQUEST, 1); 1230 1231 /* Wait for command to complete */ 1232 wait = AXGBE_RATECHANGE_COUNT; 1233 while (wait--) { 1234 if (!XP_IOREAD_BITS(pdata, XP_DRIVER_INT_RO, STATUS)) 1235 goto reenable_pll; 1236 rte_delay_us(1500); 1237 } 1238 1239 reenable_pll: 1240 /* Re-enable the PLL control */ 1241 axgbe_phy_pll_ctrl(pdata, true); 1242 1243 PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n"); 1244 } 1245 1246 static void axgbe_phy_rrc(struct axgbe_port *pdata) 1247 { 1248 1249 1250 /* Receiver Reset Cycle */ 1251 axgbe_phy_perform_ratechange(pdata, 5, 0); 1252 1253 PMD_DRV_LOG(DEBUG, "receiver reset complete\n"); 1254 } 1255 1256 static void axgbe_phy_power_off(struct axgbe_port *pdata) 1257 { 1258 struct axgbe_phy_data *phy_data = pdata->phy_data; 1259 1260 /* Power off */ 1261 axgbe_phy_perform_ratechange(pdata, 0, 0); 1262 1263 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 1264 1265 PMD_DRV_LOG(DEBUG, "phy powered off\n"); 1266 } 1267 1268 static void axgbe_phy_sfi_mode(struct axgbe_port *pdata) 1269 { 1270 struct axgbe_phy_data *phy_data = pdata->phy_data; 1271 1272 axgbe_phy_set_redrv_mode(pdata); 1273 1274 /* 10G/SFI */ 1275 if (phy_data->sfp_cable != AXGBE_SFP_CABLE_PASSIVE) { 1276 axgbe_phy_perform_ratechange(pdata, 3, 0); 1277 } else { 1278 if (phy_data->sfp_cable_len <= 1) 1279 axgbe_phy_perform_ratechange(pdata, 3, 1); 1280 else if (phy_data->sfp_cable_len <= 3) 1281 axgbe_phy_perform_ratechange(pdata, 3, 2); 1282 else 1283 axgbe_phy_perform_ratechange(pdata, 3, 3); 1284 } 1285 1286 phy_data->cur_mode = AXGBE_MODE_SFI; 1287 1288 PMD_DRV_LOG(DEBUG, "10GbE SFI mode set\n"); 1289 } 1290 1291 static void axgbe_phy_kr_mode(struct axgbe_port *pdata) 1292 { 1293 struct axgbe_phy_data *phy_data = pdata->phy_data; 1294 1295 axgbe_phy_set_redrv_mode(pdata); 1296 1297 /* 10G/KR */ 1298 axgbe_phy_perform_ratechange(pdata, 4, 0); 1299 phy_data->cur_mode = AXGBE_MODE_KR; 1300 1301 PMD_DRV_LOG(DEBUG, "10GbE KR mode set\n"); 1302 } 1303 1304 static void axgbe_phy_kx_2500_mode(struct axgbe_port *pdata) 1305 { 1306 struct axgbe_phy_data *phy_data = pdata->phy_data; 1307 1308 axgbe_phy_set_redrv_mode(pdata); 1309 1310 /* 2.5G/KX */ 1311 axgbe_phy_perform_ratechange(pdata, 2, 0); 1312 phy_data->cur_mode = AXGBE_MODE_KX_2500; 1313 } 1314 1315 static void axgbe_phy_sgmii_1000_mode(struct axgbe_port *pdata) 1316 { 1317 struct axgbe_phy_data *phy_data = pdata->phy_data; 1318 1319 axgbe_phy_set_redrv_mode(pdata); 1320 1321 /* 1G/SGMII */ 1322 axgbe_phy_perform_ratechange(pdata, 1, 2); 1323 1324 phy_data->cur_mode = AXGBE_MODE_SGMII_1000; 1325 } 1326 1327 static enum axgbe_mode axgbe_phy_cur_mode(struct axgbe_port *pdata) 1328 { 1329 struct axgbe_phy_data *phy_data = pdata->phy_data; 1330 1331 return phy_data->cur_mode; 1332 } 1333 1334 static enum axgbe_mode axgbe_phy_switch_baset_mode(struct axgbe_port *pdata) 1335 { 1336 struct axgbe_phy_data *phy_data = pdata->phy_data; 1337 1338 /* No switching if not 10GBase-T */ 1339 if (phy_data->port_mode != AXGBE_PORT_MODE_10GBASE_T) 1340 return axgbe_phy_cur_mode(pdata); 1341 1342 switch (axgbe_phy_cur_mode(pdata)) { 1343 case AXGBE_MODE_SGMII_100: 1344 case AXGBE_MODE_SGMII_1000: 1345 return AXGBE_MODE_KR; 1346 case AXGBE_MODE_KR: 1347 default: 1348 return AXGBE_MODE_SGMII_1000; 1349 } 1350 } 1351 1352 static enum axgbe_mode axgbe_phy_switch_bp_2500_mode(struct axgbe_port *pdata 1353 __rte_unused) 1354 { 1355 return AXGBE_MODE_KX_2500; 1356 } 1357 1358 static enum axgbe_mode axgbe_phy_switch_bp_mode(struct axgbe_port *pdata) 1359 { 1360 /* If we are in KR switch to KX, and vice-versa */ 1361 switch (axgbe_phy_cur_mode(pdata)) { 1362 case AXGBE_MODE_KX_1000: 1363 return AXGBE_MODE_KR; 1364 case AXGBE_MODE_KR: 1365 default: 1366 return AXGBE_MODE_KX_1000; 1367 } 1368 } 1369 1370 static enum axgbe_mode axgbe_phy_switch_mode(struct axgbe_port *pdata) 1371 { 1372 struct axgbe_phy_data *phy_data = pdata->phy_data; 1373 1374 switch (phy_data->port_mode) { 1375 case AXGBE_PORT_MODE_BACKPLANE: 1376 return axgbe_phy_switch_bp_mode(pdata); 1377 case AXGBE_PORT_MODE_BACKPLANE_2500: 1378 return axgbe_phy_switch_bp_2500_mode(pdata); 1379 case AXGBE_PORT_MODE_1000BASE_T: 1380 case AXGBE_PORT_MODE_NBASE_T: 1381 case AXGBE_PORT_MODE_10GBASE_T: 1382 return axgbe_phy_switch_baset_mode(pdata); 1383 case AXGBE_PORT_MODE_1000BASE_X: 1384 case AXGBE_PORT_MODE_10GBASE_R: 1385 case AXGBE_PORT_MODE_SFP: 1386 /* No switching, so just return current mode */ 1387 return axgbe_phy_cur_mode(pdata); 1388 default: 1389 return AXGBE_MODE_UNKNOWN; 1390 } 1391 } 1392 1393 static enum axgbe_mode axgbe_phy_get_basex_mode(struct axgbe_phy_data *phy_data 1394 __rte_unused, 1395 int speed) 1396 { 1397 switch (speed) { 1398 case SPEED_1000: 1399 return AXGBE_MODE_X; 1400 case SPEED_10000: 1401 return AXGBE_MODE_KR; 1402 default: 1403 return AXGBE_MODE_UNKNOWN; 1404 } 1405 } 1406 1407 static enum axgbe_mode axgbe_phy_get_baset_mode(struct axgbe_phy_data *phy_data 1408 __rte_unused, 1409 int speed) 1410 { 1411 switch (speed) { 1412 case SPEED_100: 1413 return AXGBE_MODE_SGMII_100; 1414 case SPEED_1000: 1415 return AXGBE_MODE_SGMII_1000; 1416 case SPEED_10000: 1417 return AXGBE_MODE_KR; 1418 default: 1419 return AXGBE_MODE_UNKNOWN; 1420 } 1421 } 1422 1423 static enum axgbe_mode axgbe_phy_get_sfp_mode(struct axgbe_phy_data *phy_data, 1424 int speed) 1425 { 1426 switch (speed) { 1427 case SPEED_100: 1428 return AXGBE_MODE_SGMII_100; 1429 case SPEED_1000: 1430 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1431 return AXGBE_MODE_SGMII_1000; 1432 else 1433 return AXGBE_MODE_X; 1434 case SPEED_10000: 1435 case SPEED_UNKNOWN: 1436 return AXGBE_MODE_SFI; 1437 default: 1438 return AXGBE_MODE_UNKNOWN; 1439 } 1440 } 1441 1442 static enum axgbe_mode axgbe_phy_get_bp_2500_mode(int speed) 1443 { 1444 switch (speed) { 1445 case SPEED_2500: 1446 return AXGBE_MODE_KX_2500; 1447 default: 1448 return AXGBE_MODE_UNKNOWN; 1449 } 1450 } 1451 1452 static enum axgbe_mode axgbe_phy_get_bp_mode(int speed) 1453 { 1454 switch (speed) { 1455 case SPEED_1000: 1456 return AXGBE_MODE_KX_1000; 1457 case SPEED_10000: 1458 return AXGBE_MODE_KR; 1459 default: 1460 return AXGBE_MODE_UNKNOWN; 1461 } 1462 } 1463 1464 static enum axgbe_mode axgbe_phy_get_mode(struct axgbe_port *pdata, 1465 int speed) 1466 { 1467 struct axgbe_phy_data *phy_data = pdata->phy_data; 1468 1469 switch (phy_data->port_mode) { 1470 case AXGBE_PORT_MODE_BACKPLANE: 1471 return axgbe_phy_get_bp_mode(speed); 1472 case AXGBE_PORT_MODE_BACKPLANE_2500: 1473 return axgbe_phy_get_bp_2500_mode(speed); 1474 case AXGBE_PORT_MODE_1000BASE_T: 1475 case AXGBE_PORT_MODE_NBASE_T: 1476 case AXGBE_PORT_MODE_10GBASE_T: 1477 return axgbe_phy_get_baset_mode(phy_data, speed); 1478 case AXGBE_PORT_MODE_1000BASE_X: 1479 case AXGBE_PORT_MODE_10GBASE_R: 1480 return axgbe_phy_get_basex_mode(phy_data, speed); 1481 case AXGBE_PORT_MODE_SFP: 1482 return axgbe_phy_get_sfp_mode(phy_data, speed); 1483 default: 1484 return AXGBE_MODE_UNKNOWN; 1485 } 1486 } 1487 1488 static void axgbe_phy_set_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1489 { 1490 switch (mode) { 1491 case AXGBE_MODE_KR: 1492 axgbe_phy_kr_mode(pdata); 1493 break; 1494 case AXGBE_MODE_SFI: 1495 axgbe_phy_sfi_mode(pdata); 1496 break; 1497 case AXGBE_MODE_KX_2500: 1498 axgbe_phy_kx_2500_mode(pdata); 1499 break; 1500 case AXGBE_MODE_SGMII_1000: 1501 axgbe_phy_sgmii_1000_mode(pdata); 1502 break; 1503 default: 1504 break; 1505 } 1506 } 1507 1508 static bool axgbe_phy_check_mode(struct axgbe_port *pdata, 1509 enum axgbe_mode mode, u32 advert) 1510 { 1511 if (pdata->phy.autoneg == AUTONEG_ENABLE) { 1512 if (pdata->phy.advertising & advert) 1513 return true; 1514 } else { 1515 enum axgbe_mode cur_mode; 1516 1517 cur_mode = axgbe_phy_get_mode(pdata, pdata->phy.speed); 1518 if (cur_mode == mode) 1519 return true; 1520 } 1521 1522 return false; 1523 } 1524 1525 static bool axgbe_phy_use_basex_mode(struct axgbe_port *pdata, 1526 enum axgbe_mode mode) 1527 { 1528 switch (mode) { 1529 case AXGBE_MODE_X: 1530 return axgbe_phy_check_mode(pdata, mode, 1531 ADVERTISED_1000baseT_Full); 1532 case AXGBE_MODE_KR: 1533 return axgbe_phy_check_mode(pdata, mode, 1534 ADVERTISED_10000baseT_Full); 1535 default: 1536 return false; 1537 } 1538 } 1539 1540 static bool axgbe_phy_use_baset_mode(struct axgbe_port *pdata, 1541 enum axgbe_mode mode) 1542 { 1543 switch (mode) { 1544 case AXGBE_MODE_SGMII_100: 1545 return axgbe_phy_check_mode(pdata, mode, 1546 ADVERTISED_100baseT_Full); 1547 case AXGBE_MODE_SGMII_1000: 1548 return axgbe_phy_check_mode(pdata, mode, 1549 ADVERTISED_1000baseT_Full); 1550 case AXGBE_MODE_KR: 1551 return axgbe_phy_check_mode(pdata, mode, 1552 ADVERTISED_10000baseT_Full); 1553 default: 1554 return false; 1555 } 1556 } 1557 1558 static bool axgbe_phy_use_sfp_mode(struct axgbe_port *pdata, 1559 enum axgbe_mode mode) 1560 { 1561 struct axgbe_phy_data *phy_data = pdata->phy_data; 1562 1563 switch (mode) { 1564 case AXGBE_MODE_X: 1565 if (phy_data->sfp_base == AXGBE_SFP_BASE_1000_T) 1566 return false; 1567 return axgbe_phy_check_mode(pdata, mode, 1568 ADVERTISED_1000baseT_Full); 1569 case AXGBE_MODE_SGMII_100: 1570 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1571 return false; 1572 return axgbe_phy_check_mode(pdata, mode, 1573 ADVERTISED_100baseT_Full); 1574 case AXGBE_MODE_SGMII_1000: 1575 if (phy_data->sfp_base != AXGBE_SFP_BASE_1000_T) 1576 return false; 1577 return axgbe_phy_check_mode(pdata, mode, 1578 ADVERTISED_1000baseT_Full); 1579 case AXGBE_MODE_SFI: 1580 return axgbe_phy_check_mode(pdata, mode, 1581 ADVERTISED_10000baseT_Full); 1582 default: 1583 return false; 1584 } 1585 } 1586 1587 static bool axgbe_phy_use_bp_2500_mode(struct axgbe_port *pdata, 1588 enum axgbe_mode mode) 1589 { 1590 switch (mode) { 1591 case AXGBE_MODE_KX_2500: 1592 return axgbe_phy_check_mode(pdata, mode, 1593 ADVERTISED_2500baseX_Full); 1594 default: 1595 return false; 1596 } 1597 } 1598 1599 static bool axgbe_phy_use_bp_mode(struct axgbe_port *pdata, 1600 enum axgbe_mode mode) 1601 { 1602 switch (mode) { 1603 case AXGBE_MODE_KX_1000: 1604 return axgbe_phy_check_mode(pdata, mode, 1605 ADVERTISED_1000baseKX_Full); 1606 case AXGBE_MODE_KR: 1607 return axgbe_phy_check_mode(pdata, mode, 1608 ADVERTISED_10000baseKR_Full); 1609 default: 1610 return false; 1611 } 1612 } 1613 1614 static bool axgbe_phy_use_mode(struct axgbe_port *pdata, enum axgbe_mode mode) 1615 { 1616 struct axgbe_phy_data *phy_data = pdata->phy_data; 1617 1618 switch (phy_data->port_mode) { 1619 case AXGBE_PORT_MODE_BACKPLANE: 1620 return axgbe_phy_use_bp_mode(pdata, mode); 1621 case AXGBE_PORT_MODE_BACKPLANE_2500: 1622 return axgbe_phy_use_bp_2500_mode(pdata, mode); 1623 case AXGBE_PORT_MODE_1000BASE_T: 1624 case AXGBE_PORT_MODE_NBASE_T: 1625 case AXGBE_PORT_MODE_10GBASE_T: 1626 return axgbe_phy_use_baset_mode(pdata, mode); 1627 case AXGBE_PORT_MODE_1000BASE_X: 1628 case AXGBE_PORT_MODE_10GBASE_R: 1629 return axgbe_phy_use_basex_mode(pdata, mode); 1630 case AXGBE_PORT_MODE_SFP: 1631 return axgbe_phy_use_sfp_mode(pdata, mode); 1632 default: 1633 return false; 1634 } 1635 } 1636 1637 static int axgbe_phy_link_status(struct axgbe_port *pdata, int *an_restart) 1638 { 1639 struct axgbe_phy_data *phy_data = pdata->phy_data; 1640 unsigned int reg; 1641 1642 *an_restart = 0; 1643 1644 if (phy_data->port_mode == AXGBE_PORT_MODE_SFP) { 1645 /* Check SFP signals */ 1646 axgbe_phy_sfp_detect(pdata); 1647 1648 if (phy_data->sfp_changed) { 1649 *an_restart = 1; 1650 return 0; 1651 } 1652 1653 if (phy_data->sfp_mod_absent || phy_data->sfp_rx_los) 1654 return 0; 1655 } 1656 1657 /* Link status is latched low, so read once to clear 1658 * and then read again to get current state 1659 */ 1660 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1661 reg = XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1); 1662 if (reg & MDIO_STAT1_LSTATUS) 1663 return 1; 1664 1665 /* No link, attempt a receiver reset cycle */ 1666 if (phy_data->rrc_count++) { 1667 phy_data->rrc_count = 0; 1668 axgbe_phy_rrc(pdata); 1669 } 1670 1671 return 0; 1672 } 1673 1674 static void axgbe_phy_sfp_gpio_setup(struct axgbe_port *pdata) 1675 { 1676 struct axgbe_phy_data *phy_data = pdata->phy_data; 1677 unsigned int reg; 1678 1679 reg = XP_IOREAD(pdata, XP_PROP_3); 1680 1681 phy_data->sfp_gpio_address = AXGBE_GPIO_ADDRESS_PCA9555 + 1682 XP_GET_BITS(reg, XP_PROP_3, GPIO_ADDR); 1683 1684 phy_data->sfp_gpio_mask = XP_GET_BITS(reg, XP_PROP_3, GPIO_MASK); 1685 1686 phy_data->sfp_gpio_rx_los = XP_GET_BITS(reg, XP_PROP_3, 1687 GPIO_RX_LOS); 1688 phy_data->sfp_gpio_tx_fault = XP_GET_BITS(reg, XP_PROP_3, 1689 GPIO_TX_FAULT); 1690 phy_data->sfp_gpio_mod_absent = XP_GET_BITS(reg, XP_PROP_3, 1691 GPIO_MOD_ABS); 1692 phy_data->sfp_gpio_rate_select = XP_GET_BITS(reg, XP_PROP_3, 1693 GPIO_RATE_SELECT); 1694 } 1695 1696 static void axgbe_phy_sfp_comm_setup(struct axgbe_port *pdata) 1697 { 1698 struct axgbe_phy_data *phy_data = pdata->phy_data; 1699 unsigned int reg, mux_addr_hi, mux_addr_lo; 1700 1701 reg = XP_IOREAD(pdata, XP_PROP_4); 1702 1703 mux_addr_hi = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_HI); 1704 mux_addr_lo = XP_GET_BITS(reg, XP_PROP_4, MUX_ADDR_LO); 1705 if (mux_addr_lo == AXGBE_SFP_DIRECT) 1706 return; 1707 1708 phy_data->sfp_comm = AXGBE_SFP_COMM_PCA9545; 1709 phy_data->sfp_mux_address = (mux_addr_hi << 2) + mux_addr_lo; 1710 phy_data->sfp_mux_channel = XP_GET_BITS(reg, XP_PROP_4, MUX_CHAN); 1711 } 1712 1713 static void axgbe_phy_sfp_setup(struct axgbe_port *pdata) 1714 { 1715 axgbe_phy_sfp_comm_setup(pdata); 1716 axgbe_phy_sfp_gpio_setup(pdata); 1717 } 1718 1719 static bool axgbe_phy_redrv_error(struct axgbe_phy_data *phy_data) 1720 { 1721 if (!phy_data->redrv) 1722 return false; 1723 1724 if (phy_data->redrv_if >= AXGBE_PHY_REDRV_IF_MAX) 1725 return true; 1726 1727 switch (phy_data->redrv_model) { 1728 case AXGBE_PHY_REDRV_MODEL_4223: 1729 if (phy_data->redrv_lane > 3) 1730 return true; 1731 break; 1732 case AXGBE_PHY_REDRV_MODEL_4227: 1733 if (phy_data->redrv_lane > 1) 1734 return true; 1735 break; 1736 default: 1737 return true; 1738 } 1739 1740 return false; 1741 } 1742 1743 static int axgbe_phy_mdio_reset_setup(struct axgbe_port *pdata) 1744 { 1745 struct axgbe_phy_data *phy_data = pdata->phy_data; 1746 unsigned int reg; 1747 1748 if (phy_data->conn_type != AXGBE_CONN_TYPE_MDIO) 1749 return 0; 1750 reg = XP_IOREAD(pdata, XP_PROP_3); 1751 phy_data->mdio_reset = XP_GET_BITS(reg, XP_PROP_3, MDIO_RESET); 1752 switch (phy_data->mdio_reset) { 1753 case AXGBE_MDIO_RESET_NONE: 1754 case AXGBE_MDIO_RESET_I2C_GPIO: 1755 case AXGBE_MDIO_RESET_INT_GPIO: 1756 break; 1757 default: 1758 PMD_DRV_LOG(ERR, "unsupported MDIO reset (%#x)\n", 1759 phy_data->mdio_reset); 1760 return -EINVAL; 1761 } 1762 if (phy_data->mdio_reset == AXGBE_MDIO_RESET_I2C_GPIO) { 1763 phy_data->mdio_reset_addr = AXGBE_GPIO_ADDRESS_PCA9555 + 1764 XP_GET_BITS(reg, XP_PROP_3, 1765 MDIO_RESET_I2C_ADDR); 1766 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1767 MDIO_RESET_I2C_GPIO); 1768 } else if (phy_data->mdio_reset == AXGBE_MDIO_RESET_INT_GPIO) { 1769 phy_data->mdio_reset_gpio = XP_GET_BITS(reg, XP_PROP_3, 1770 MDIO_RESET_INT_GPIO); 1771 } 1772 1773 return 0; 1774 } 1775 1776 static bool axgbe_phy_port_mode_mismatch(struct axgbe_port *pdata) 1777 { 1778 struct axgbe_phy_data *phy_data = pdata->phy_data; 1779 1780 switch (phy_data->port_mode) { 1781 case AXGBE_PORT_MODE_BACKPLANE: 1782 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1783 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1784 return false; 1785 break; 1786 case AXGBE_PORT_MODE_BACKPLANE_2500: 1787 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) 1788 return false; 1789 break; 1790 case AXGBE_PORT_MODE_1000BASE_T: 1791 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1792 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000)) 1793 return false; 1794 break; 1795 case AXGBE_PORT_MODE_1000BASE_X: 1796 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) 1797 return false; 1798 break; 1799 case AXGBE_PORT_MODE_NBASE_T: 1800 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1801 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1802 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500)) 1803 return false; 1804 break; 1805 case AXGBE_PORT_MODE_10GBASE_T: 1806 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1807 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1808 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1809 return false; 1810 break; 1811 case AXGBE_PORT_MODE_10GBASE_R: 1812 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) 1813 return false; 1814 break; 1815 case AXGBE_PORT_MODE_SFP: 1816 if ((phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) || 1817 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) || 1818 (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000)) 1819 return false; 1820 break; 1821 default: 1822 break; 1823 } 1824 1825 return true; 1826 } 1827 1828 static bool axgbe_phy_conn_type_mismatch(struct axgbe_port *pdata) 1829 { 1830 struct axgbe_phy_data *phy_data = pdata->phy_data; 1831 1832 switch (phy_data->port_mode) { 1833 case AXGBE_PORT_MODE_BACKPLANE: 1834 case AXGBE_PORT_MODE_BACKPLANE_2500: 1835 if (phy_data->conn_type == AXGBE_CONN_TYPE_BACKPLANE) 1836 return false; 1837 break; 1838 case AXGBE_PORT_MODE_1000BASE_T: 1839 case AXGBE_PORT_MODE_1000BASE_X: 1840 case AXGBE_PORT_MODE_NBASE_T: 1841 case AXGBE_PORT_MODE_10GBASE_T: 1842 case AXGBE_PORT_MODE_10GBASE_R: 1843 if (phy_data->conn_type == AXGBE_CONN_TYPE_MDIO) 1844 return false; 1845 break; 1846 case AXGBE_PORT_MODE_SFP: 1847 if (phy_data->conn_type == AXGBE_CONN_TYPE_SFP) 1848 return false; 1849 break; 1850 default: 1851 break; 1852 } 1853 1854 return true; 1855 } 1856 1857 static bool axgbe_phy_port_enabled(struct axgbe_port *pdata) 1858 { 1859 unsigned int reg; 1860 1861 reg = XP_IOREAD(pdata, XP_PROP_0); 1862 if (!XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS)) 1863 return false; 1864 if (!XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE)) 1865 return false; 1866 1867 return true; 1868 } 1869 1870 static void axgbe_phy_cdr_track(struct axgbe_port *pdata) 1871 { 1872 struct axgbe_phy_data *phy_data = pdata->phy_data; 1873 1874 if (!pdata->vdata->an_cdr_workaround) 1875 return; 1876 1877 if (!phy_data->phy_cdr_notrack) 1878 return; 1879 1880 rte_delay_us(phy_data->phy_cdr_delay + 400); 1881 1882 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1883 AXGBE_PMA_CDR_TRACK_EN_MASK, 1884 AXGBE_PMA_CDR_TRACK_EN_ON); 1885 1886 phy_data->phy_cdr_notrack = 0; 1887 } 1888 1889 static void axgbe_phy_cdr_notrack(struct axgbe_port *pdata) 1890 { 1891 struct axgbe_phy_data *phy_data = pdata->phy_data; 1892 1893 if (!pdata->vdata->an_cdr_workaround) 1894 return; 1895 1896 if (phy_data->phy_cdr_notrack) 1897 return; 1898 1899 XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_CDR_CONTROL, 1900 AXGBE_PMA_CDR_TRACK_EN_MASK, 1901 AXGBE_PMA_CDR_TRACK_EN_OFF); 1902 1903 axgbe_phy_rrc(pdata); 1904 1905 phy_data->phy_cdr_notrack = 1; 1906 } 1907 1908 static void axgbe_phy_kr_training_post(struct axgbe_port *pdata) 1909 { 1910 if (!pdata->cdr_track_early) 1911 axgbe_phy_cdr_track(pdata); 1912 } 1913 1914 static void axgbe_phy_kr_training_pre(struct axgbe_port *pdata) 1915 { 1916 if (pdata->cdr_track_early) 1917 axgbe_phy_cdr_track(pdata); 1918 } 1919 1920 static void axgbe_phy_an_post(struct axgbe_port *pdata) 1921 { 1922 struct axgbe_phy_data *phy_data = pdata->phy_data; 1923 1924 switch (pdata->an_mode) { 1925 case AXGBE_AN_MODE_CL73: 1926 case AXGBE_AN_MODE_CL73_REDRV: 1927 if (phy_data->cur_mode != AXGBE_MODE_KR) 1928 break; 1929 1930 axgbe_phy_cdr_track(pdata); 1931 1932 switch (pdata->an_result) { 1933 case AXGBE_AN_READY: 1934 case AXGBE_AN_COMPLETE: 1935 break; 1936 default: 1937 if (phy_data->phy_cdr_delay < AXGBE_CDR_DELAY_MAX) 1938 phy_data->phy_cdr_delay += AXGBE_CDR_DELAY_INC; 1939 break; 1940 } 1941 break; 1942 default: 1943 break; 1944 } 1945 } 1946 1947 static void axgbe_phy_an_pre(struct axgbe_port *pdata) 1948 { 1949 struct axgbe_phy_data *phy_data = pdata->phy_data; 1950 1951 switch (pdata->an_mode) { 1952 case AXGBE_AN_MODE_CL73: 1953 case AXGBE_AN_MODE_CL73_REDRV: 1954 if (phy_data->cur_mode != AXGBE_MODE_KR) 1955 break; 1956 1957 axgbe_phy_cdr_notrack(pdata); 1958 break; 1959 default: 1960 break; 1961 } 1962 } 1963 1964 static void axgbe_phy_stop(struct axgbe_port *pdata) 1965 { 1966 struct axgbe_phy_data *phy_data = pdata->phy_data; 1967 1968 /* Reset SFP data */ 1969 axgbe_phy_sfp_reset(phy_data); 1970 axgbe_phy_sfp_mod_absent(pdata); 1971 1972 /* Reset CDR support */ 1973 axgbe_phy_cdr_track(pdata); 1974 1975 /* Power off the PHY */ 1976 axgbe_phy_power_off(pdata); 1977 1978 /* Stop the I2C controller */ 1979 pdata->i2c_if.i2c_stop(pdata); 1980 } 1981 1982 static int axgbe_phy_start(struct axgbe_port *pdata) 1983 { 1984 struct axgbe_phy_data *phy_data = pdata->phy_data; 1985 int ret; 1986 1987 /* Start the I2C controller */ 1988 ret = pdata->i2c_if.i2c_start(pdata); 1989 if (ret) 1990 return ret; 1991 1992 /* Start in highest supported mode */ 1993 axgbe_phy_set_mode(pdata, phy_data->start_mode); 1994 1995 /* Reset CDR support */ 1996 axgbe_phy_cdr_track(pdata); 1997 1998 /* After starting the I2C controller, we can check for an SFP */ 1999 switch (phy_data->port_mode) { 2000 case AXGBE_PORT_MODE_SFP: 2001 axgbe_phy_sfp_detect(pdata); 2002 break; 2003 default: 2004 break; 2005 } 2006 pdata->phy.advertising &= axgbe_phy_an_advertising(pdata); 2007 2008 return ret; 2009 } 2010 2011 static int axgbe_phy_reset(struct axgbe_port *pdata) 2012 { 2013 struct axgbe_phy_data *phy_data = pdata->phy_data; 2014 enum axgbe_mode cur_mode; 2015 2016 /* Reset by power cycling the PHY */ 2017 cur_mode = phy_data->cur_mode; 2018 axgbe_phy_power_off(pdata); 2019 /* First time reset is done with passed unknown mode*/ 2020 axgbe_phy_set_mode(pdata, cur_mode); 2021 return 0; 2022 } 2023 2024 static int axgbe_phy_init(struct axgbe_port *pdata) 2025 { 2026 struct axgbe_phy_data *phy_data; 2027 unsigned int reg; 2028 int ret; 2029 2030 /* Check if enabled */ 2031 if (!axgbe_phy_port_enabled(pdata)) { 2032 PMD_DRV_LOG(ERR, "device is not enabled\n"); 2033 return -ENODEV; 2034 } 2035 2036 /* Initialize the I2C controller */ 2037 ret = pdata->i2c_if.i2c_init(pdata); 2038 if (ret) 2039 return ret; 2040 2041 phy_data = rte_zmalloc("phy_data memory", sizeof(*phy_data), 0); 2042 if (!phy_data) { 2043 PMD_DRV_LOG(ERR, "phy_data allocation failed\n"); 2044 return -ENOMEM; 2045 } 2046 pdata->phy_data = phy_data; 2047 2048 reg = XP_IOREAD(pdata, XP_PROP_0); 2049 phy_data->port_mode = XP_GET_BITS(reg, XP_PROP_0, PORT_MODE); 2050 phy_data->port_id = XP_GET_BITS(reg, XP_PROP_0, PORT_ID); 2051 phy_data->port_speeds = XP_GET_BITS(reg, XP_PROP_0, PORT_SPEEDS); 2052 phy_data->conn_type = XP_GET_BITS(reg, XP_PROP_0, CONN_TYPE); 2053 phy_data->mdio_addr = XP_GET_BITS(reg, XP_PROP_0, MDIO_ADDR); 2054 2055 reg = XP_IOREAD(pdata, XP_PROP_4); 2056 phy_data->redrv = XP_GET_BITS(reg, XP_PROP_4, REDRV_PRESENT); 2057 phy_data->redrv_if = XP_GET_BITS(reg, XP_PROP_4, REDRV_IF); 2058 phy_data->redrv_addr = XP_GET_BITS(reg, XP_PROP_4, REDRV_ADDR); 2059 phy_data->redrv_lane = XP_GET_BITS(reg, XP_PROP_4, REDRV_LANE); 2060 phy_data->redrv_model = XP_GET_BITS(reg, XP_PROP_4, REDRV_MODEL); 2061 2062 /* Validate the connection requested */ 2063 if (axgbe_phy_conn_type_mismatch(pdata)) { 2064 PMD_DRV_LOG(ERR, "phy mode/connection mismatch (%#x/%#x)\n", 2065 phy_data->port_mode, phy_data->conn_type); 2066 return -EINVAL; 2067 } 2068 2069 /* Validate the mode requested */ 2070 if (axgbe_phy_port_mode_mismatch(pdata)) { 2071 PMD_DRV_LOG(ERR, "phy mode/speed mismatch (%#x/%#x)\n", 2072 phy_data->port_mode, phy_data->port_speeds); 2073 return -EINVAL; 2074 } 2075 2076 /* Check for and validate MDIO reset support */ 2077 ret = axgbe_phy_mdio_reset_setup(pdata); 2078 if (ret) 2079 return ret; 2080 2081 /* Validate the re-driver information */ 2082 if (axgbe_phy_redrv_error(phy_data)) { 2083 PMD_DRV_LOG(ERR, "phy re-driver settings error\n"); 2084 return -EINVAL; 2085 } 2086 pdata->kr_redrv = phy_data->redrv; 2087 2088 /* Indicate current mode is unknown */ 2089 phy_data->cur_mode = AXGBE_MODE_UNKNOWN; 2090 2091 /* Initialize supported features */ 2092 pdata->phy.supported = 0; 2093 2094 switch (phy_data->port_mode) { 2095 /* Backplane support */ 2096 case AXGBE_PORT_MODE_BACKPLANE: 2097 pdata->phy.supported |= SUPPORTED_Autoneg; 2098 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2099 pdata->phy.supported |= SUPPORTED_Backplane; 2100 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2101 pdata->phy.supported |= SUPPORTED_1000baseKX_Full; 2102 phy_data->start_mode = AXGBE_MODE_KX_1000; 2103 } 2104 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2105 pdata->phy.supported |= SUPPORTED_10000baseKR_Full; 2106 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2107 pdata->phy.supported |= 2108 SUPPORTED_10000baseR_FEC; 2109 phy_data->start_mode = AXGBE_MODE_KR; 2110 } 2111 2112 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2113 break; 2114 case AXGBE_PORT_MODE_BACKPLANE_2500: 2115 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2116 pdata->phy.supported |= SUPPORTED_Backplane; 2117 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2118 phy_data->start_mode = AXGBE_MODE_KX_2500; 2119 2120 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2121 break; 2122 2123 /* MDIO 1GBase-T support */ 2124 case AXGBE_PORT_MODE_1000BASE_T: 2125 pdata->phy.supported |= SUPPORTED_Autoneg; 2126 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2127 pdata->phy.supported |= SUPPORTED_TP; 2128 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2129 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2130 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2131 } 2132 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2133 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2134 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2135 } 2136 2137 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2138 break; 2139 2140 /* MDIO Base-X support */ 2141 case AXGBE_PORT_MODE_1000BASE_X: 2142 pdata->phy.supported |= SUPPORTED_Autoneg; 2143 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2144 pdata->phy.supported |= SUPPORTED_FIBRE; 2145 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2146 phy_data->start_mode = AXGBE_MODE_X; 2147 2148 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2149 break; 2150 2151 /* MDIO NBase-T support */ 2152 case AXGBE_PORT_MODE_NBASE_T: 2153 pdata->phy.supported |= SUPPORTED_Autoneg; 2154 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2155 pdata->phy.supported |= SUPPORTED_TP; 2156 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2157 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2158 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2159 } 2160 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2161 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2162 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2163 } 2164 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_2500) { 2165 pdata->phy.supported |= SUPPORTED_2500baseX_Full; 2166 phy_data->start_mode = AXGBE_MODE_KX_2500; 2167 } 2168 2169 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL45; 2170 break; 2171 2172 /* 10GBase-T support */ 2173 case AXGBE_PORT_MODE_10GBASE_T: 2174 pdata->phy.supported |= SUPPORTED_Autoneg; 2175 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2176 pdata->phy.supported |= SUPPORTED_TP; 2177 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2178 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2179 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2180 } 2181 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2182 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2183 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2184 } 2185 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2186 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2187 phy_data->start_mode = AXGBE_MODE_KR; 2188 } 2189 2190 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2191 break; 2192 2193 /* 10GBase-R support */ 2194 case AXGBE_PORT_MODE_10GBASE_R: 2195 pdata->phy.supported |= SUPPORTED_Autoneg; 2196 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2197 pdata->phy.supported |= SUPPORTED_TP; 2198 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2199 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2200 pdata->phy.supported |= SUPPORTED_10000baseR_FEC; 2201 phy_data->start_mode = AXGBE_MODE_SFI; 2202 2203 phy_data->phydev_mode = AXGBE_MDIO_MODE_NONE; 2204 break; 2205 2206 /* SFP support */ 2207 case AXGBE_PORT_MODE_SFP: 2208 pdata->phy.supported |= SUPPORTED_Autoneg; 2209 pdata->phy.supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause; 2210 pdata->phy.supported |= SUPPORTED_TP; 2211 pdata->phy.supported |= SUPPORTED_FIBRE; 2212 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_100) { 2213 pdata->phy.supported |= SUPPORTED_100baseT_Full; 2214 phy_data->start_mode = AXGBE_MODE_SGMII_100; 2215 } 2216 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_1000) { 2217 pdata->phy.supported |= SUPPORTED_1000baseT_Full; 2218 phy_data->start_mode = AXGBE_MODE_SGMII_1000; 2219 } 2220 if (phy_data->port_speeds & AXGBE_PHY_PORT_SPEED_10000) { 2221 pdata->phy.supported |= SUPPORTED_10000baseT_Full; 2222 phy_data->start_mode = AXGBE_MODE_SFI; 2223 if (pdata->fec_ability & MDIO_PMA_10GBR_FECABLE_ABLE) 2224 pdata->phy.supported |= 2225 SUPPORTED_10000baseR_FEC; 2226 } 2227 2228 phy_data->phydev_mode = AXGBE_MDIO_MODE_CL22; 2229 2230 axgbe_phy_sfp_setup(pdata); 2231 break; 2232 default: 2233 return -EINVAL; 2234 } 2235 2236 if ((phy_data->conn_type & AXGBE_CONN_TYPE_MDIO) && 2237 (phy_data->phydev_mode != AXGBE_MDIO_MODE_NONE)) { 2238 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->mdio_addr, 2239 phy_data->phydev_mode); 2240 if (ret) { 2241 PMD_DRV_LOG(ERR, "mdio port/clause not compatible (%d/%u)\n", 2242 phy_data->mdio_addr, phy_data->phydev_mode); 2243 return -EINVAL; 2244 } 2245 } 2246 2247 if (phy_data->redrv && !phy_data->redrv_if) { 2248 ret = pdata->hw_if.set_ext_mii_mode(pdata, phy_data->redrv_addr, 2249 AXGBE_MDIO_MODE_CL22); 2250 if (ret) { 2251 PMD_DRV_LOG(ERR, "redriver mdio port not compatible (%u)\n", 2252 phy_data->redrv_addr); 2253 return -EINVAL; 2254 } 2255 } 2256 2257 phy_data->phy_cdr_delay = AXGBE_CDR_DELAY_INIT; 2258 return 0; 2259 } 2260 void axgbe_init_function_ptrs_phy_v2(struct axgbe_phy_if *phy_if) 2261 { 2262 struct axgbe_phy_impl_if *phy_impl = &phy_if->phy_impl; 2263 2264 phy_impl->init = axgbe_phy_init; 2265 phy_impl->reset = axgbe_phy_reset; 2266 phy_impl->start = axgbe_phy_start; 2267 phy_impl->stop = axgbe_phy_stop; 2268 phy_impl->link_status = axgbe_phy_link_status; 2269 phy_impl->use_mode = axgbe_phy_use_mode; 2270 phy_impl->set_mode = axgbe_phy_set_mode; 2271 phy_impl->get_mode = axgbe_phy_get_mode; 2272 phy_impl->switch_mode = axgbe_phy_switch_mode; 2273 phy_impl->cur_mode = axgbe_phy_cur_mode; 2274 phy_impl->an_mode = axgbe_phy_an_mode; 2275 phy_impl->an_config = axgbe_phy_an_config; 2276 phy_impl->an_advertising = axgbe_phy_an_advertising; 2277 phy_impl->an_outcome = axgbe_phy_an_outcome; 2278 2279 phy_impl->an_pre = axgbe_phy_an_pre; 2280 phy_impl->an_post = axgbe_phy_an_post; 2281 2282 phy_impl->kr_training_pre = axgbe_phy_kr_training_pre; 2283 phy_impl->kr_training_post = axgbe_phy_kr_training_post; 2284 } 2285